Intel-XE Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: Matthew Auld <matthew.auld@intel.com>
To: "Lin, Shuicheng" <shuicheng.lin@intel.com>,
	"intel-xe@lists.freedesktop.org" <intel-xe@lists.freedesktop.org>
Cc: "Ghimiray, Himal Prasad" <himal.prasad.ghimiray@intel.com>,
	"Jahagirdar, Akshata" <akshata.jahagirdar@intel.com>,
	"Roper, Matthew D" <matthew.d.roper@intel.com>,
	"stable@vger.kernel.org" <stable@vger.kernel.org>
Subject: Re: [PATCH v2] drm/xe/vram: fix ccs offset calculation
Date: Mon, 16 Sep 2024 09:32:40 +0100	[thread overview]
Message-ID: <b6b402ca-243c-4d0d-af54-b20ac39b9ee9@intel.com> (raw)
In-Reply-To: <DM4PR11MB5456F540B3D043C896C4773EEA662@DM4PR11MB5456.namprd11.prod.outlook.com>

On 15/09/2024 00:29, Lin, Shuicheng wrote:
>>> Spec says SW is expected to round up to the nearest 128K, if not
>>> already aligned for the CC unit view of CCS. We are seeing the assert
>>> sometimes pop on BMG to tell us that there is a hole between GSM and
>>> CCS, as well as popping other asserts with having a vram size with
>>> strange alignment, which is likely caused by misaligned offset here.
>>>
>>> BSpec: 68023
>>> Fixes: b5c2ca0372dc ("drm/xe/xe2hpg: Determine flat ccs offset for
>>> vram")
>>> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
>>> Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
>>> Cc: Akshata Jahagirdar <akshata.jahagirdar@intel.com>
>>> Cc: Shuicheng Lin <shuicheng.lin@intel.com>
>>> Cc: Matt Roper <matthew.d.roper@intel.com>
>>> Cc: <stable@vger.kernel.org> # v6.10+
>>> ---
>>>   drivers/gpu/drm/xe/xe_vram.c | 1 +
>>>   1 file changed, 1 insertion(+)
>>>
>>> diff --git a/drivers/gpu/drm/xe/xe_vram.c
>>> b/drivers/gpu/drm/xe/xe_vram.c index
>>> 7e765b1499b1..8e65cb4cc477 100644
>>> --- a/drivers/gpu/drm/xe/xe_vram.c
>>> +++ b/drivers/gpu/drm/xe/xe_vram.c
>>> @@ -181,6 +181,7 @@ static inline u64 get_flat_ccs_offset(struct xe_gt
>>> *gt, u64
>>> tile_size)
>>>
>>>   		offset = offset_hi << 32; /* HW view bits 39:32 */
>>>   		offset |= offset_lo << 6; /* HW view bits 31:6 */
>>> +		offset = round_up(offset, SZ_128K); /* SW must round up to
>>> nearest
>>> +128K */
>>>   		offset *= num_enabled; /* convert to SW view */
> f> >
>>>   		/* We don't expect any holes */
>>> --
>>> 2.46.0
>>
>> The patch works in my platform.
>> Tested-by: Shuicheng Lin <shuicheng.lin@intel.com>
> The round up should be applied to the SW address. So, the right sequence should be as below:
>    		offset *= num_enabled; /* convert to SW view */
> +		offset = round_up(offset, SZ_128K); /* SW must round up to nearest +128K */
> 
> I applied the patch manually and didn't notice the sequence difference. With upper sequence, the patch could fix the misaligned offset issue.

Ok, will move this. Thanks for testing.

      reply	other threads:[~2024-09-16  8:32 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-09-13 12:00 [PATCH v2] drm/xe/vram: fix ccs offset calculation Matthew Auld
2024-09-13 12:35 ` Andi Shyti
2024-09-13 12:40   ` Matthew Auld
2024-09-13 12:44   ` Ghimiray, Himal Prasad
2024-09-13 13:54 ` ✓ CI.Patch_applied: success for drm/xe/vram: fix ccs offset calculation (rev2) Patchwork
2024-09-13 13:54 ` ✓ CI.checkpatch: " Patchwork
2024-09-13 14:00 ` ✓ CI.KUnit: " Patchwork
2024-09-13 14:23 ` ✓ CI.Build: " Patchwork
2024-09-13 14:28 ` ✓ CI.Hooks: " Patchwork
2024-09-13 14:41 ` ✓ CI.checksparse: " Patchwork
2024-09-13 15:10 ` ✓ CI.BAT: " Patchwork
2024-09-13 22:36 ` [PATCH v2] drm/xe/vram: fix ccs offset calculation Lucas De Marchi
2024-09-16  8:38   ` Matthew Auld
2024-09-14  5:40 ` ✗ CI.FULL: failure for drm/xe/vram: fix ccs offset calculation (rev2) Patchwork
2024-09-14 23:05 ` [PATCH v2] drm/xe/vram: fix ccs offset calculation Lin, Shuicheng
2024-09-14 23:29   ` Lin, Shuicheng
2024-09-16  8:32     ` Matthew Auld [this message]

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=b6b402ca-243c-4d0d-af54-b20ac39b9ee9@intel.com \
    --to=matthew.auld@intel.com \
    --cc=akshata.jahagirdar@intel.com \
    --cc=himal.prasad.ghimiray@intel.com \
    --cc=intel-xe@lists.freedesktop.org \
    --cc=matthew.d.roper@intel.com \
    --cc=shuicheng.lin@intel.com \
    --cc=stable@vger.kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox