[PATCH 0/9] drm/i915/wm: Watermark/SAGV fixes/cleanups/etc

[PATCH 0/9] drm/i915/wm: Watermark/SAGV fixes/cleanups/etc

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Bunch of work around watermarks and SAGV. A few fixes, some
refactoring, and finish off by relaxing the SAGV requirements
on pre-icl hardware.

Ville Syrjälä (9):
  drm/i915/wm: Reject SAGV consistently when block_time_us==0
  drm/i915/wm: Don't compute separate SAGV watermarks for RKL
  drm/i915/wm: Consolidate SAGV pipe active/interlace checks to common
    code
  drm/i915/wm: Verify the correct plane DDB entry
  drm/i915/wm: Extract skl_wm_level_verify()
  drm/i915/wm: Extract skl_ddb_entry_verify()
  drm/i915/wm: Verify 'ddb_y' as well as 'ddb'
  drm/i915/wm: Reduce copy-pasta in skl_print_plane_wm_changes()
  drm/i915/wm: Allow SAGV with multiple pipes on pre-icl

 drivers/gpu/drm/i915/display/intel_bw.c       |  40 ---
 .../drm/i915/display/intel_display_device.h   |   1 +
 drivers/gpu/drm/i915/display/skl_watermark.c  | 292 +++++++-----------
 3 files changed, 117 insertions(+), 216 deletions(-)

-- 
2.52.0

[PATCH 1/9] drm/i915/wm: Reject SAGV consistently when block_time_us==0

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We have three ways for the platform to indicate that
SAGV is not supported:
- pcode returns zero block time
- pcode returns only a single QGV point (icl+)
- pcode rejects the SAGV enable/disable command (pre-icl)

We don't currently consider all those factors when computing
pipe_sagv_reject, meaning we might still try to enable
SAGV when we should not.

I think one plausible scenario is when pcode returns a
zero block time, and all the pipes are disabled. In
that case intel_crtc_can_enable_sagv() will return true
for all pipes, and thus we might try to enable SAGV
despite pcode indicating that it's not supported.

Make sure pipe_sagv_reject will consistently reject
SAGV when our cached block time is zero. That will cover
all the aforementioned mechanisms by which SAGV can be
disabled.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index d45b3bcc6ef0..09988f46e083 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -308,9 +308,6 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
 	enum plane_id plane_id;
 	int max_level = INT_MAX;
 
-	if (!intel_has_sagv(display))
-		return false;
-
 	if (!crtc_state->hw.active)
 		return true;
 
@@ -377,6 +374,9 @@ bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 
+	if (!display->sagv.block_time_us)
+		return false;
+
 	if (!display->params.enable_sagv)
 		return false;
 
-- 
2.52.0

Re: [PATCH 1/9] drm/i915/wm: Reject SAGV consistently when block_time_us==0

[Govindapillai, Vinod]

On Tue, 2026-03-24 at 15:48 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> We have three ways for the platform to indicate that
> SAGV is not supported:
> - pcode returns zero block time
> - pcode returns only a single QGV point (icl+)
> - pcode rejects the SAGV enable/disable command (pre-icl)
> 
> We don't currently consider all those factors when computing
> pipe_sagv_reject, meaning we might still try to enable
> SAGV when we should not.
> 
> I think one plausible scenario is when pcode returns a
> zero block time, and all the pipes are disabled. In
> that case intel_crtc_can_enable_sagv() will return true
> for all pipes, and thus we might try to enable SAGV
> despite pcode indicating that it's not supported.
> 
> Make sure pipe_sagv_reject will consistently reject
> SAGV when our cached block time is zero. That will cover
> all the aforementioned mechanisms by which SAGV can be
> disabled.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/skl_watermark.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 

Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>

> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> b/drivers/gpu/drm/i915/display/skl_watermark.c
> index d45b3bcc6ef0..09988f46e083 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -308,9 +308,6 @@ static bool skl_crtc_can_enable_sagv(const struct
> intel_crtc_state *crtc_state)
>  	enum plane_id plane_id;
>  	int max_level = INT_MAX;
>  
> -	if (!intel_has_sagv(display))
> -		return false;
> -
>  	if (!crtc_state->hw.active)
>  		return true;
>  
> @@ -377,6 +374,9 @@ bool intel_crtc_can_enable_sagv(const struct
> intel_crtc_state *crtc_state)
>  {
>  	struct intel_display *display =
> to_intel_display(crtc_state);
>  
> +	if (!display->sagv.block_time_us)
> +		return false;
> +
>  	if (!display->params.enable_sagv)
>  		return false;
>  

[PATCH 2/9] drm/i915/wm: Don't compute separate SAGV watermarks for RKL

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

RKL is supposed to use the old SKL/ICL method for determining
whether the watermarks tolerate SAGV or not, not the TGL+ method.
Make it so.

BSpec: 49325
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 .../gpu/drm/i915/display/intel_display_device.h   |  1 +
 drivers/gpu/drm/i915/display/skl_watermark.c      | 15 ++++++++-------
 2 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 1170ac346615..074e3ba8fb77 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -200,6 +200,7 @@ struct intel_display_platforms {
 #define HAS_PSR_TRANS_PUSH_FRAME_CHANGE(__display)	(DISPLAY_VER(__display) >= 20)
 #define HAS_SAGV(__display)		(DISPLAY_VER(__display) >= 9 && \
 					 !(__display)->platform.broxton && !(__display)->platform.geminilake)
+#define HAS_SAGV_WM(__display)		(DISPLAY_VER(__display) >= 12 && !(__display)->platform.rocketlake)
 #define HAS_TRANSCODER(__display, trans)	((DISPLAY_RUNTIME_INFO(__display)->cpu_transcoder_mask & \
 						  BIT(trans)) != 0)
 #define HAS_UNCOMPRESSED_JOINER(__display)	(DISPLAY_VER(__display) >= 13)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 09988f46e083..bcdca1b99fe4 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -388,7 +388,7 @@ bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
 	if (crtc_state->inherited)
 		return false;
 
-	if (DISPLAY_VER(display) >= 12)
+	if (HAS_SAGV_WM(display))
 		return tgl_crtc_can_enable_sagv(crtc_state);
 	else
 		return skl_crtc_can_enable_sagv(crtc_state);
@@ -1939,7 +1939,7 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
 	result->enable = true;
 	result->auto_min_alloc_wm_enable = xe3_auto_min_alloc_capable(plane, level);
 
-	if (DISPLAY_VER(display) < 12 && display->sagv.block_time_us)
+	if (!HAS_SAGV_WM(display) && display->sagv.block_time_us)
 		result->can_sagv = latency >= display->sagv.block_time_us;
 }
 
@@ -2065,7 +2065,7 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
 	skl_compute_transition_wm(display, &wm->trans_wm,
 				  &wm->wm[0], &wm_params);
 
-	if (DISPLAY_VER(display) >= 12) {
+	if (HAS_SAGV_WM(display)) {
 		tgl_compute_sagv_wm(crtc_state, plane, &wm_params, wm);
 
 		skl_compute_transition_wm(display, &wm->sagv.trans_wm,
@@ -2324,7 +2324,7 @@ static int skl_wm_check_vblank(struct intel_crtc_state *crtc_state)
 		}
 	}
 
-	if (DISPLAY_VER(display) >= 12 &&
+	if (HAS_SAGV_WM(display) &&
 	    display->sagv.block_time_us &&
 	    skl_prefill_vblank_too_short(&ctx, crtc_state,
 					 display->sagv.block_time_us)) {
@@ -2997,8 +2997,9 @@ skl_compute_wm(struct intel_atomic_state *state)
 		 * other crtcs can't be allowed to use the more optimal
 		 * normal (ie. non-SAGV) watermarks.
 		 */
-		pipe_wm->use_sagv_wm = !HAS_HW_SAGV_WM(display) &&
-			DISPLAY_VER(display) >= 12 &&
+		pipe_wm->use_sagv_wm =
+			HAS_SAGV_WM(display) &&
+			!HAS_HW_SAGV_WM(display) &&
 			intel_crtc_can_enable_sagv(new_crtc_state);
 
 		ret = skl_wm_add_affected_planes(state, crtc);
@@ -3064,7 +3065,7 @@ static void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
 				val = intel_de_read(display, CUR_WM_SAGV_TRANS(pipe));
 
 			skl_wm_level_from_reg_val(display, val, &wm->sagv.trans_wm);
-		} else if (DISPLAY_VER(display) >= 12) {
+		} else if (HAS_SAGV_WM(display)) {
 			wm->sagv.wm0 = wm->wm[0];
 			wm->sagv.trans_wm = wm->trans_wm;
 		}
-- 
2.52.0

Re: [PATCH 2/9] drm/i915/wm: Don't compute separate SAGV watermarks for RKL

[Govindapillai, Vinod]

On Tue, 2026-03-24 at 15:48 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> RKL is supposed to use the old SKL/ICL method for determining
> whether the watermarks tolerate SAGV or not, not the TGL+ method.
> Make it so.
> 
> BSpec: 49325
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  .../gpu/drm/i915/display/intel_display_device.h   |  1 +
>  drivers/gpu/drm/i915/display/skl_watermark.c      | 15 ++++++++-----
> --
>  2 files changed, 9 insertions(+), 7 deletions(-)
> 

Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>

> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
> b/drivers/gpu/drm/i915/display/intel_display_device.h
> index 1170ac346615..074e3ba8fb77 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -200,6 +200,7 @@ struct intel_display_platforms {
>  #define
> HAS_PSR_TRANS_PUSH_FRAME_CHANGE(__display)	(DISPLAY_VER(__display) >=20)
>  #define HAS_SAGV(__display)		(DISPLAY_VER(__display) >= 9
> && \
>  					 !(__display)-
> >platform.broxton && !(__display)->platform.geminilake)
> +#define HAS_SAGV_WM(__display)		(DISPLAY_VER(__display) >=
> 12 && !(__display)->platform.rocketlake)
>  #define HAS_TRANSCODER(__display,
> trans)	((DISPLAY_RUNTIME_INFO(__display)->cpu_transcoder_mask & \
>  						  BIT(trans)) != 0)
>  #define
> HAS_UNCOMPRESSED_JOINER(__display)	(DISPLAY_VER(__display) >= 13)
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 09988f46e083..bcdca1b99fe4 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -388,7 +388,7 @@ bool intel_crtc_can_enable_sagv(const struct
> intel_crtc_state *crtc_state)
>  	if (crtc_state->inherited)
>  		return false;
>  
> -	if (DISPLAY_VER(display) >= 12)
> +	if (HAS_SAGV_WM(display))
>  		return tgl_crtc_can_enable_sagv(crtc_state);
>  	else
>  		return skl_crtc_can_enable_sagv(crtc_state);
> @@ -1939,7 +1939,7 @@ static void skl_compute_plane_wm(const struct
> intel_crtc_state *crtc_state,
>  	result->enable = true;
>  	result->auto_min_alloc_wm_enable =
> xe3_auto_min_alloc_capable(plane, level);
>  
> -	if (DISPLAY_VER(display) < 12 && display-
> >sagv.block_time_us)
> +	if (!HAS_SAGV_WM(display) && display->sagv.block_time_us)
>  		result->can_sagv = latency >= display-
> >sagv.block_time_us;
>  }
>  
> @@ -2065,7 +2065,7 @@ static int skl_build_plane_wm_single(struct
> intel_crtc_state *crtc_state,
>  	skl_compute_transition_wm(display, &wm->trans_wm,
>  				  &wm->wm[0], &wm_params);
>  
> -	if (DISPLAY_VER(display) >= 12) {
> +	if (HAS_SAGV_WM(display)) {
>  		tgl_compute_sagv_wm(crtc_state, plane, &wm_params,
> wm);
>  
>  		skl_compute_transition_wm(display, &wm-
> >sagv.trans_wm,
> @@ -2324,7 +2324,7 @@ static int skl_wm_check_vblank(struct
> intel_crtc_state *crtc_state)
>  		}
>  	}
>  
> -	if (DISPLAY_VER(display) >= 12 &&
> +	if (HAS_SAGV_WM(display) &&
>  	    display->sagv.block_time_us &&
>  	    skl_prefill_vblank_too_short(&ctx, crtc_state,
>  					 display-
> >sagv.block_time_us)) {
> @@ -2997,8 +2997,9 @@ skl_compute_wm(struct intel_atomic_state
> *state)
>  		 * other crtcs can't be allowed to use the more
> optimal
>  		 * normal (ie. non-SAGV) watermarks.
>  		 */
> -		pipe_wm->use_sagv_wm = !HAS_HW_SAGV_WM(display) &&
> -			DISPLAY_VER(display) >= 12 &&
> +		pipe_wm->use_sagv_wm =
> +			HAS_SAGV_WM(display) &&
> +			!HAS_HW_SAGV_WM(display) &&
>  			intel_crtc_can_enable_sagv(new_crtc_state);
>  
>  		ret = skl_wm_add_affected_planes(state, crtc);
> @@ -3064,7 +3065,7 @@ static void skl_pipe_wm_get_hw_state(struct
> intel_crtc *crtc,
>  				val = intel_de_read(display,
> CUR_WM_SAGV_TRANS(pipe));
>  
>  			skl_wm_level_from_reg_val(display, val, &wm-
> >sagv.trans_wm);
> -		} else if (DISPLAY_VER(display) >= 12) {
> +		} else if (HAS_SAGV_WM(display)) {
>  			wm->sagv.wm0 = wm->wm[0];
>  			wm->sagv.trans_wm = wm->trans_wm;
>  		}

[PATCH 3/9] drm/i915/wm: Consolidate SAGV pipe active/interlace checks to common code

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

There are no differences between the platforms when
considering whether SAGV can be used when the pipe is
inactive or using an interlaced mode. Consolidate the
checks to common code.

Note that we weren't even checking for interlaced modes
on TGL+, but since we've previously soft defeatured
interlaced modes on TGL+ that was more or less fine.
The hardware does still have the capability though,
and in case we ever decide to resurrect it having the
check seems like a good idea.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 15 ++++++---------
 1 file changed, 6 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index bcdca1b99fe4..e37fde9f765d 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -308,12 +308,6 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
 	enum plane_id plane_id;
 	int max_level = INT_MAX;
 
-	if (!crtc_state->hw.active)
-		return true;
-
-	if (crtc_state->hw.pipe_mode.flags & DRM_MODE_FLAG_INTERLACE)
-		return false;
-
 	for_each_plane_id_on_crtc(crtc, plane_id) {
 		const struct skl_plane_wm *wm =
 			&crtc_state->wm.skl.optimal.planes[plane_id];
@@ -356,9 +350,6 @@ static bool tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum plane_id plane_id;
 
-	if (!crtc_state->hw.active)
-		return true;
-
 	for_each_plane_id_on_crtc(crtc, plane_id) {
 		const struct skl_plane_wm *wm =
 			&crtc_state->wm.skl.optimal.planes[plane_id];
@@ -388,6 +379,12 @@ bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
 	if (crtc_state->inherited)
 		return false;
 
+	if (!crtc_state->hw.active)
+		return true;
+
+	if (crtc_state->hw.pipe_mode.flags & DRM_MODE_FLAG_INTERLACE)
+		return false;
+
 	if (HAS_SAGV_WM(display))
 		return tgl_crtc_can_enable_sagv(crtc_state);
 	else
-- 
2.52.0

Re: [PATCH 3/9] drm/i915/wm: Consolidate SAGV pipe active/interlace checks to common code

[Govindapillai, Vinod]

On Tue, 2026-03-24 at 15:48 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> There are no differences between the platforms when
> considering whether SAGV can be used when the pipe is
> inactive or using an interlaced mode. Consolidate the
> checks to common code.
> 
> Note that we weren't even checking for interlaced modes
> on TGL+, but since we've previously soft defeatured
> interlaced modes on TGL+ that was more or less fine.
> The hardware does still have the capability though,
> and in case we ever decide to resurrect it having the
> check seems like a good idea.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/skl_watermark.c | 15 ++++++---------
>  1 file changed, 6 insertions(+), 9 deletions(-)
> 

Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>

> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> b/drivers/gpu/drm/i915/display/skl_watermark.c
> index bcdca1b99fe4..e37fde9f765d 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -308,12 +308,6 @@ static bool skl_crtc_can_enable_sagv(const
> struct intel_crtc_state *crtc_state)
>  	enum plane_id plane_id;
>  	int max_level = INT_MAX;
>  
> -	if (!crtc_state->hw.active)
> -		return true;
> -
> -	if (crtc_state->hw.pipe_mode.flags &
> DRM_MODE_FLAG_INTERLACE)
> -		return false;
> -
>  	for_each_plane_id_on_crtc(crtc, plane_id) {
>  		const struct skl_plane_wm *wm =
>  			&crtc_state-
> >wm.skl.optimal.planes[plane_id];
> @@ -356,9 +350,6 @@ static bool tgl_crtc_can_enable_sagv(const struct
> intel_crtc_state *crtc_state)
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state-
> >uapi.crtc);
>  	enum plane_id plane_id;
>  
> -	if (!crtc_state->hw.active)
> -		return true;
> -
>  	for_each_plane_id_on_crtc(crtc, plane_id) {
>  		const struct skl_plane_wm *wm =
>  			&crtc_state-
> >wm.skl.optimal.planes[plane_id];
> @@ -388,6 +379,12 @@ bool intel_crtc_can_enable_sagv(const struct
> intel_crtc_state *crtc_state)
>  	if (crtc_state->inherited)
>  		return false;
>  
> +	if (!crtc_state->hw.active)
> +		return true;
> +
> +	if (crtc_state->hw.pipe_mode.flags &
> DRM_MODE_FLAG_INTERLACE)
> +		return false;
> +
>  	if (HAS_SAGV_WM(display))
>  		return tgl_crtc_can_enable_sagv(crtc_state);
>  	else

[PATCH 4/9] drm/i915/wm: Verify the correct plane DDB entry

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Actually verify the DDB entry for the plane we're looking
at instead of always verifying the cursor DDB.

Fixes: 7d4561722c3b ("drm/i915: Tweak plane ddb allocation tracking")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index e37fde9f765d..cbc03938442d 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -4026,8 +4026,8 @@ void intel_wm_state_verify(struct intel_atomic_state *state,
 		}
 
 		/* DDB */
-		hw_ddb_entry = &hw->ddb[PLANE_CURSOR];
-		sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb[PLANE_CURSOR];
+		hw_ddb_entry = &hw->ddb[plane->id];
+		sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb[plane->id];
 
 		if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
 			drm_err(display->drm,
-- 
2.52.0

Re: [PATCH 4/9] drm/i915/wm: Verify the correct plane DDB entry

[Govindapillai, Vinod]

On Tue, 2026-03-24 at 15:48 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Actually verify the DDB entry for the plane we're looking
> at instead of always verifying the cursor DDB.
> 
> Fixes: 7d4561722c3b ("drm/i915: Tweak plane ddb allocation tracking")
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/skl_watermark.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 

Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>

> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> b/drivers/gpu/drm/i915/display/skl_watermark.c
> index e37fde9f765d..cbc03938442d 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -4026,8 +4026,8 @@ void intel_wm_state_verify(struct
> intel_atomic_state *state,
>  		}
>  
>  		/* DDB */
> -		hw_ddb_entry = &hw->ddb[PLANE_CURSOR];
> -		sw_ddb_entry = &new_crtc_state-
> >wm.skl.plane_ddb[PLANE_CURSOR];
> +		hw_ddb_entry = &hw->ddb[plane->id];
> +		sw_ddb_entry = &new_crtc_state-
> >wm.skl.plane_ddb[plane->id];
>  
>  		if (!skl_ddb_entry_equal(hw_ddb_entry,
> sw_ddb_entry)) {
>  			drm_err(display->drm,

[PATCH 5/9] drm/i915/wm: Extract skl_wm_level_verify()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reduce duplicated code by extracting the code to
verify a single WM level to a common function.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 94 ++++++++------------
 1 file changed, 36 insertions(+), 58 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index cbc03938442d..3e323e434bfb 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3917,6 +3917,23 @@ void skl_wm_plane_disable_noatomic(struct intel_crtc *crtc,
 	       sizeof(crtc_state->wm.skl.optimal.planes[plane->id]));
 }
 
+static void skl_wm_level_verify(struct intel_plane *plane,
+				const char *wm_name,
+				const struct skl_wm_level *hw_wm_level,
+				const struct skl_wm_level *sw_wm_level)
+{
+	struct intel_display *display = to_intel_display(plane);
+
+	if (skl_wm_level_equals(hw_wm_level, sw_wm_level))
+		return;
+
+	drm_err(display->drm,
+		"[PLANE:%d:%s] mismatch in %s (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
+		plane->base.base.id, plane->base.name, wm_name,
+		sw_wm_level->enable, sw_wm_level->blocks, sw_wm_level->lines,
+		hw_wm_level->enable, hw_wm_level->blocks, hw_wm_level->lines);
+}
+
 void intel_wm_state_verify(struct intel_atomic_state *state,
 			   struct intel_crtc *crtc)
 {
@@ -3956,73 +3973,34 @@ void intel_wm_state_verify(struct intel_atomic_state *state,
 			hw_enabled_slices);
 
 	for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
+		const struct skl_plane_wm *hw_plane_wm =
+			&hw->wm.planes[plane->id];
+		const struct skl_plane_wm *sw_plane_wm =
+			&sw_wm->planes[plane->id];
 		const struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
-		const struct skl_wm_level *hw_wm_level, *sw_wm_level;
 
-		/* Watermarks */
 		for (level = 0; level < display->wm.num_levels; level++) {
-			hw_wm_level = &hw->wm.planes[plane->id].wm[level];
-			sw_wm_level = skl_plane_wm_level(sw_wm, plane->id, level);
+			char wm_name[16];
 
-			if (skl_wm_level_equals(hw_wm_level, sw_wm_level))
-				continue;
+			snprintf(wm_name, sizeof(wm_name), "WM%d", level);
 
-			drm_err(display->drm,
-				"[PLANE:%d:%s] mismatch in WM%d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
-				plane->base.base.id, plane->base.name, level,
-				sw_wm_level->enable,
-				sw_wm_level->blocks,
-				sw_wm_level->lines,
-				hw_wm_level->enable,
-				hw_wm_level->blocks,
-				hw_wm_level->lines);
+			skl_wm_level_verify(plane, wm_name,
+					    &hw_plane_wm->wm[level],
+					    skl_plane_wm_level(sw_wm, plane->id, level));
 		}
 
-		hw_wm_level = &hw->wm.planes[plane->id].trans_wm;
-		sw_wm_level = skl_plane_trans_wm(sw_wm, plane->id);
+		skl_wm_level_verify(plane, "trans WM",
+				    &hw_plane_wm->trans_wm,
+				    skl_plane_trans_wm(sw_wm, plane->id));
 
-		if (!skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
-			drm_err(display->drm,
-				"[PLANE:%d:%s] mismatch in trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
-				plane->base.base.id, plane->base.name,
-				sw_wm_level->enable,
-				sw_wm_level->blocks,
-				sw_wm_level->lines,
-				hw_wm_level->enable,
-				hw_wm_level->blocks,
-				hw_wm_level->lines);
-		}
-
-		hw_wm_level = &hw->wm.planes[plane->id].sagv.wm0;
-		sw_wm_level = &sw_wm->planes[plane->id].sagv.wm0;
-
-		if (HAS_HW_SAGV_WM(display) &&
-		    !skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
-			drm_err(display->drm,
-				"[PLANE:%d:%s] mismatch in SAGV WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
-				plane->base.base.id, plane->base.name,
-				sw_wm_level->enable,
-				sw_wm_level->blocks,
-				sw_wm_level->lines,
-				hw_wm_level->enable,
-				hw_wm_level->blocks,
-				hw_wm_level->lines);
-		}
-
-		hw_wm_level = &hw->wm.planes[plane->id].sagv.trans_wm;
-		sw_wm_level = &sw_wm->planes[plane->id].sagv.trans_wm;
+		if (HAS_HW_SAGV_WM(display)) {
+			skl_wm_level_verify(plane, "SAGV WM",
+					    &hw_plane_wm->sagv.wm0,
+					    &sw_plane_wm->sagv.wm0);
 
-		if (HAS_HW_SAGV_WM(display) &&
-		    !skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
-			drm_err(display->drm,
-				"[PLANE:%d:%s] mismatch in SAGV trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
-				plane->base.base.id, plane->base.name,
-				sw_wm_level->enable,
-				sw_wm_level->blocks,
-				sw_wm_level->lines,
-				hw_wm_level->enable,
-				hw_wm_level->blocks,
-				hw_wm_level->lines);
+			skl_wm_level_verify(plane, "SAGV trans WM",
+					    &hw_plane_wm->sagv.trans_wm,
+					    &sw_plane_wm->sagv.trans_wm);
 		}
 
 		/* DDB */
-- 
2.52.0

Re: [PATCH 5/9] drm/i915/wm: Extract skl_wm_level_verify()

[Govindapillai, Vinod]

On Tue, 2026-03-24 at 15:48 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Reduce duplicated code by extracting the code to
> verify a single WM level to a common function.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/skl_watermark.c | 94 ++++++++----------
> --
>  1 file changed, 36 insertions(+), 58 deletions(-)
> 

Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>

> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> b/drivers/gpu/drm/i915/display/skl_watermark.c
> index cbc03938442d..3e323e434bfb 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -3917,6 +3917,23 @@ void skl_wm_plane_disable_noatomic(struct
> intel_crtc *crtc,
>  	       sizeof(crtc_state->wm.skl.optimal.planes[plane-
> >id]));
>  }
>  
> +static void skl_wm_level_verify(struct intel_plane *plane,
> +				const char *wm_name,
> +				const struct skl_wm_level
> *hw_wm_level,
> +				const struct skl_wm_level
> *sw_wm_level)
> +{
> +	struct intel_display *display = to_intel_display(plane);
> +
> +	if (skl_wm_level_equals(hw_wm_level, sw_wm_level))
> +		return;
> +
> +	drm_err(display->drm,
> +		"[PLANE:%d:%s] mismatch in %s (expected e=%d b=%u
> l=%u, got e=%d b=%u l=%u)\n",
> +		plane->base.base.id, plane->base.name, wm_name,
> +		sw_wm_level->enable, sw_wm_level->blocks,
> sw_wm_level->lines,
> +		hw_wm_level->enable, hw_wm_level->blocks,
> hw_wm_level->lines);
> +}
> +
>  void intel_wm_state_verify(struct intel_atomic_state *state,
>  			   struct intel_crtc *crtc)
>  {
> @@ -3956,73 +3973,34 @@ void intel_wm_state_verify(struct
> intel_atomic_state *state,
>  			hw_enabled_slices);
>  
>  	for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
> +		const struct skl_plane_wm *hw_plane_wm =
> +			&hw->wm.planes[plane->id];
> +		const struct skl_plane_wm *sw_plane_wm =
> +			&sw_wm->planes[plane->id];
>  		const struct skl_ddb_entry *hw_ddb_entry,
> *sw_ddb_entry;
> -		const struct skl_wm_level *hw_wm_level,
> *sw_wm_level;
>  
> -		/* Watermarks */
>  		for (level = 0; level < display->wm.num_levels;
> level++) {
> -			hw_wm_level = &hw->wm.planes[plane-
> >id].wm[level];
> -			sw_wm_level = skl_plane_wm_level(sw_wm,
> plane->id, level);
> +			char wm_name[16];
>  
> -			if (skl_wm_level_equals(hw_wm_level,
> sw_wm_level))
> -				continue;
> +			snprintf(wm_name, sizeof(wm_name), "WM%d",
> level);
>  
> -			drm_err(display->drm,
> -				"[PLANE:%d:%s] mismatch in WM%d
> (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
> -				plane->base.base.id, plane-
> >base.name, level,
> -				sw_wm_level->enable,
> -				sw_wm_level->blocks,
> -				sw_wm_level->lines,
> -				hw_wm_level->enable,
> -				hw_wm_level->blocks,
> -				hw_wm_level->lines);
> +			skl_wm_level_verify(plane, wm_name,
> +					    &hw_plane_wm->wm[level],
> +					   
> skl_plane_wm_level(sw_wm, plane->id, level));
>  		}
>  
> -		hw_wm_level = &hw->wm.planes[plane->id].trans_wm;
> -		sw_wm_level = skl_plane_trans_wm(sw_wm, plane->id);
> +		skl_wm_level_verify(plane, "trans WM",
> +				    &hw_plane_wm->trans_wm,
> +				    skl_plane_trans_wm(sw_wm, plane-
> >id));
>  
> -		if (!skl_wm_level_equals(hw_wm_level, sw_wm_level))
> {
> -			drm_err(display->drm,
> -				"[PLANE:%d:%s] mismatch in trans WM
> (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
> -				plane->base.base.id, plane-
> >base.name,
> -				sw_wm_level->enable,
> -				sw_wm_level->blocks,
> -				sw_wm_level->lines,
> -				hw_wm_level->enable,
> -				hw_wm_level->blocks,
> -				hw_wm_level->lines);
> -		}
> -
> -		hw_wm_level = &hw->wm.planes[plane->id].sagv.wm0;
> -		sw_wm_level = &sw_wm->planes[plane->id].sagv.wm0;
> -
> -		if (HAS_HW_SAGV_WM(display) &&
> -		    !skl_wm_level_equals(hw_wm_level, sw_wm_level))
> {
> -			drm_err(display->drm,
> -				"[PLANE:%d:%s] mismatch in SAGV WM
> (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
> -				plane->base.base.id, plane-
> >base.name,
> -				sw_wm_level->enable,
> -				sw_wm_level->blocks,
> -				sw_wm_level->lines,
> -				hw_wm_level->enable,
> -				hw_wm_level->blocks,
> -				hw_wm_level->lines);
> -		}
> -
> -		hw_wm_level = &hw->wm.planes[plane-
> >id].sagv.trans_wm;
> -		sw_wm_level = &sw_wm->planes[plane-
> >id].sagv.trans_wm;
> +		if (HAS_HW_SAGV_WM(display)) {
> +			skl_wm_level_verify(plane, "SAGV WM",
> +					    &hw_plane_wm->sagv.wm0,
> +					    &sw_plane_wm->sagv.wm0);
>  
> -		if (HAS_HW_SAGV_WM(display) &&
> -		    !skl_wm_level_equals(hw_wm_level, sw_wm_level))
> {
> -			drm_err(display->drm,
> -				"[PLANE:%d:%s] mismatch in SAGV
> trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
> -				plane->base.base.id, plane-
> >base.name,
> -				sw_wm_level->enable,
> -				sw_wm_level->blocks,
> -				sw_wm_level->lines,
> -				hw_wm_level->enable,
> -				hw_wm_level->blocks,
> -				hw_wm_level->lines);
> +			skl_wm_level_verify(plane, "SAGV trans WM",
> +					    &hw_plane_wm-
> >sagv.trans_wm,
> +					    &sw_plane_wm-
> >sagv.trans_wm);
>  		}
>  
>  		/* DDB */

[PATCH 6/9] drm/i915/wm: Extract skl_ddb_entry_verify()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Extract the DDB entry verification to a helper function.
We'll have another caller soon.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 32 ++++++++++++--------
 1 file changed, 20 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 3e323e434bfb..17faf090a154 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3934,6 +3934,23 @@ static void skl_wm_level_verify(struct intel_plane *plane,
 		hw_wm_level->enable, hw_wm_level->blocks, hw_wm_level->lines);
 }
 
+static void skl_ddb_entry_verify(struct intel_plane *plane,
+				 const char *ddb_name,
+				 const struct skl_ddb_entry *hw_ddb_entry,
+				 const struct skl_ddb_entry *sw_ddb_entry)
+{
+	struct intel_display *display = to_intel_display(plane);
+
+	if (skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry))
+		return;
+
+	drm_err(display->drm,
+		"[PLANE:%d:%s] mismatch in %s (expected (%u,%u), found (%u,%u))\n",
+		plane->base.base.id, plane->base.name, ddb_name,
+		sw_ddb_entry->start, sw_ddb_entry->end,
+		hw_ddb_entry->start, hw_ddb_entry->end);
+}
+
 void intel_wm_state_verify(struct intel_atomic_state *state,
 			   struct intel_crtc *crtc)
 {
@@ -3977,7 +3994,6 @@ void intel_wm_state_verify(struct intel_atomic_state *state,
 			&hw->wm.planes[plane->id];
 		const struct skl_plane_wm *sw_plane_wm =
 			&sw_wm->planes[plane->id];
-		const struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
 
 		for (level = 0; level < display->wm.num_levels; level++) {
 			char wm_name[16];
@@ -4003,17 +4019,9 @@ void intel_wm_state_verify(struct intel_atomic_state *state,
 					    &sw_plane_wm->sagv.trans_wm);
 		}
 
-		/* DDB */
-		hw_ddb_entry = &hw->ddb[plane->id];
-		sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb[plane->id];
-
-		if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
-			drm_err(display->drm,
-				"[PLANE:%d:%s] mismatch in DDB (expected (%u,%u), found (%u,%u))\n",
-				plane->base.base.id, plane->base.name,
-				sw_ddb_entry->start, sw_ddb_entry->end,
-				hw_ddb_entry->start, hw_ddb_entry->end);
-		}
+		skl_ddb_entry_verify(plane, "DDB",
+				     &hw->ddb[plane->id],
+				     &new_crtc_state->wm.skl.plane_ddb[plane->id]);
 	}
 
 	kfree(hw);
-- 
2.52.0

Re: [PATCH 6/9] drm/i915/wm: Extract skl_ddb_entry_verify()

[Govindapillai, Vinod]

On Tue, 2026-03-24 at 15:48 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Extract the DDB entry verification to a helper function.
> We'll have another caller soon.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/skl_watermark.c | 32 ++++++++++++------
> --
>  1 file changed, 20 insertions(+), 12 deletions(-)
> 

Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>

> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 3e323e434bfb..17faf090a154 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -3934,6 +3934,23 @@ static void skl_wm_level_verify(struct
> intel_plane *plane,
>  		hw_wm_level->enable, hw_wm_level->blocks,
> hw_wm_level->lines);
>  }
>  
> +static void skl_ddb_entry_verify(struct intel_plane *plane,
> +				 const char *ddb_name,
> +				 const struct skl_ddb_entry
> *hw_ddb_entry,
> +				 const struct skl_ddb_entry
> *sw_ddb_entry)
> +{
> +	struct intel_display *display = to_intel_display(plane);
> +
> +	if (skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry))
> +		return;
> +
> +	drm_err(display->drm,
> +		"[PLANE:%d:%s] mismatch in %s (expected (%u,%u),
> found (%u,%u))\n",
> +		plane->base.base.id, plane->base.name, ddb_name,
> +		sw_ddb_entry->start, sw_ddb_entry->end,
> +		hw_ddb_entry->start, hw_ddb_entry->end);
> +}
> +
>  void intel_wm_state_verify(struct intel_atomic_state *state,
>  			   struct intel_crtc *crtc)
>  {
> @@ -3977,7 +3994,6 @@ void intel_wm_state_verify(struct
> intel_atomic_state *state,
>  			&hw->wm.planes[plane->id];
>  		const struct skl_plane_wm *sw_plane_wm =
>  			&sw_wm->planes[plane->id];
> -		const struct skl_ddb_entry *hw_ddb_entry,
> *sw_ddb_entry;
>  
>  		for (level = 0; level < display->wm.num_levels;
> level++) {
>  			char wm_name[16];
> @@ -4003,17 +4019,9 @@ void intel_wm_state_verify(struct
> intel_atomic_state *state,
>  					    &sw_plane_wm-
> >sagv.trans_wm);
>  		}
>  
> -		/* DDB */
> -		hw_ddb_entry = &hw->ddb[plane->id];
> -		sw_ddb_entry = &new_crtc_state-
> >wm.skl.plane_ddb[plane->id];
> -
> -		if (!skl_ddb_entry_equal(hw_ddb_entry,
> sw_ddb_entry)) {
> -			drm_err(display->drm,
> -				"[PLANE:%d:%s] mismatch in DDB
> (expected (%u,%u), found (%u,%u))\n",
> -				plane->base.base.id, plane-
> >base.name,
> -				sw_ddb_entry->start, sw_ddb_entry-
> >end,
> -				hw_ddb_entry->start, hw_ddb_entry-
> >end);
> -		}
> +		skl_ddb_entry_verify(plane, "DDB",
> +				     &hw->ddb[plane->id],
> +				     &new_crtc_state-
> >wm.skl.plane_ddb[plane->id]);
>  	}
>  
>  	kfree(hw);

[PATCH 7/9] drm/i915/wm: Verify 'ddb_y' as well as 'ddb'

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Verify the pre-icl NV12 Y color plane DDB entry. Thus far
we've only verified the RGB/UV DDB entry.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 17faf090a154..1d932c37d768 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -4022,6 +4022,10 @@ void intel_wm_state_verify(struct intel_atomic_state *state,
 		skl_ddb_entry_verify(plane, "DDB",
 				     &hw->ddb[plane->id],
 				     &new_crtc_state->wm.skl.plane_ddb[plane->id]);
+
+		skl_ddb_entry_verify(plane, "DDB Y",
+				     &hw->ddb_y[plane->id],
+				     &new_crtc_state->wm.skl.plane_ddb_y[plane->id]);
 	}
 
 	kfree(hw);
-- 
2.52.0

Re: [PATCH 7/9] drm/i915/wm: Verify 'ddb_y' as well as 'ddb'

[Govindapillai, Vinod]

On Tue, 2026-03-24 at 15:48 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Verify the pre-icl NV12 Y color plane DDB entry. Thus far
> we've only verified the RGB/UV DDB entry.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/skl_watermark.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 

Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>

> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 17faf090a154..1d932c37d768 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -4022,6 +4022,10 @@ void intel_wm_state_verify(struct
> intel_atomic_state *state,
>  		skl_ddb_entry_verify(plane, "DDB",
>  				     &hw->ddb[plane->id],
>  				     &new_crtc_state-
> >wm.skl.plane_ddb[plane->id]);
> +
> +		skl_ddb_entry_verify(plane, "DDB Y",
> +				     &hw->ddb_y[plane->id],
> +				     &new_crtc_state-
> >wm.skl.plane_ddb_y[plane->id]);
>  	}
>  
>  	kfree(hw);

[PATCH 8/9] drm/i915/wm: Reduce copy-pasta in skl_print_plane_wm_changes()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

skl_print_plane_wm_changes() is rather ugly with the copy-pasted
massive printk arguments. Reduce the duplication a bit by defining
a few FMT/ARG macros. Still ugly, but perhaps a bit less fragile.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 128 ++++++-------------
 1 file changed, 40 insertions(+), 88 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 1d932c37d768..4bffa27ce02c 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -2613,6 +2613,26 @@ skl_print_plane_ddb_changes(struct intel_plane *plane,
 		    skl_ddb_entry_size(old), skl_ddb_entry_size(new));
 }
 
+#define PLANE_WM_EN_FMT "%cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm"
+#define PLANE_WM_EN_ARGS(__wm) \
+	enast((__wm)->wm[0].enable), enast((__wm)->wm[1].enable), \
+	enast((__wm)->wm[2].enable), enast((__wm)->wm[3].enable), \
+	enast((__wm)->wm[4].enable), enast((__wm)->wm[5].enable), \
+	enast((__wm)->wm[6].enable), enast((__wm)->wm[7].enable), \
+	enast((__wm)->trans_wm.enable), \
+	enast((__wm)->sagv.wm0.enable), \
+	enast((__wm)->sagv.trans_wm.enable)
+
+#define PLANE_WM_FMT "%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"
+#define PLANE_WM_ARGS(__wm, __field) \
+	(__wm)->wm[0].__field, (__wm)->wm[1].__field, \
+	(__wm)->wm[2].__field, (__wm)->wm[3].__field, \
+	(__wm)->wm[4].__field, (__wm)->wm[5].__field, \
+	(__wm)->wm[6].__field, (__wm)->wm[7].__field, \
+	(__wm)->trans_wm.__field, \
+	(__wm)->sagv.wm0.__field, \
+	(__wm)->sagv.trans_wm.__field
+
 static noinline_for_stack void
 skl_print_plane_wm_changes(struct intel_plane *plane,
 			   const struct skl_plane_wm *old_wm,
@@ -2621,112 +2641,44 @@ skl_print_plane_wm_changes(struct intel_plane *plane,
 	struct intel_display *display = to_intel_display(plane);
 
 	drm_dbg_kms(display->drm,
-		    "[PLANE:%d:%s]      level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm"
-		    " -> %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm\n",
+		    "[PLANE:%d:%s]      level " PLANE_WM_EN_FMT " -> " PLANE_WM_EN_FMT "\n",
 		    plane->base.base.id, plane->base.name,
-		    enast(old_wm->wm[0].enable), enast(old_wm->wm[1].enable),
-		    enast(old_wm->wm[2].enable), enast(old_wm->wm[3].enable),
-		    enast(old_wm->wm[4].enable), enast(old_wm->wm[5].enable),
-		    enast(old_wm->wm[6].enable), enast(old_wm->wm[7].enable),
-		    enast(old_wm->trans_wm.enable),
-		    enast(old_wm->sagv.wm0.enable),
-		    enast(old_wm->sagv.trans_wm.enable),
-		    enast(new_wm->wm[0].enable), enast(new_wm->wm[1].enable),
-		    enast(new_wm->wm[2].enable), enast(new_wm->wm[3].enable),
-		    enast(new_wm->wm[4].enable), enast(new_wm->wm[5].enable),
-		    enast(new_wm->wm[6].enable), enast(new_wm->wm[7].enable),
-		    enast(new_wm->trans_wm.enable),
-		    enast(new_wm->sagv.wm0.enable),
-		    enast(new_wm->sagv.trans_wm.enable));
+		    PLANE_WM_EN_ARGS(old_wm),
+		    PLANE_WM_EN_ARGS(new_wm));
 
 	drm_dbg_kms(display->drm,
-		    "[PLANE:%d:%s]      lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d"
-		      " -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d\n",
+		    "[PLANE:%d:%s]      lines " PLANE_WM_FMT " -> " PLANE_WM_FMT "\n",
 		    plane->base.base.id, plane->base.name,
-		    enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].lines,
-		    enast(old_wm->wm[1].ignore_lines), old_wm->wm[1].lines,
-		    enast(old_wm->wm[2].ignore_lines), old_wm->wm[2].lines,
-		    enast(old_wm->wm[3].ignore_lines), old_wm->wm[3].lines,
-		    enast(old_wm->wm[4].ignore_lines), old_wm->wm[4].lines,
-		    enast(old_wm->wm[5].ignore_lines), old_wm->wm[5].lines,
-		    enast(old_wm->wm[6].ignore_lines), old_wm->wm[6].lines,
-		    enast(old_wm->wm[7].ignore_lines), old_wm->wm[7].lines,
-		    enast(old_wm->trans_wm.ignore_lines), old_wm->trans_wm.lines,
-		    enast(old_wm->sagv.wm0.ignore_lines), old_wm->sagv.wm0.lines,
-		    enast(old_wm->sagv.trans_wm.ignore_lines), old_wm->sagv.trans_wm.lines,
-		    enast(new_wm->wm[0].ignore_lines), new_wm->wm[0].lines,
-		    enast(new_wm->wm[1].ignore_lines), new_wm->wm[1].lines,
-		    enast(new_wm->wm[2].ignore_lines), new_wm->wm[2].lines,
-		    enast(new_wm->wm[3].ignore_lines), new_wm->wm[3].lines,
-		    enast(new_wm->wm[4].ignore_lines), new_wm->wm[4].lines,
-		    enast(new_wm->wm[5].ignore_lines), new_wm->wm[5].lines,
-		    enast(new_wm->wm[6].ignore_lines), new_wm->wm[6].lines,
-		    enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].lines,
-		    enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.lines,
-		    enast(new_wm->sagv.wm0.ignore_lines), new_wm->sagv.wm0.lines,
-		    enast(new_wm->sagv.trans_wm.ignore_lines), new_wm->sagv.trans_wm.lines);
+		    PLANE_WM_ARGS(old_wm, lines),
+		    PLANE_WM_ARGS(new_wm, lines));
 
 	drm_dbg_kms(display->drm,
-		    "[PLANE:%d:%s]     blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"
-		    " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n",
+		    "[PLANE:%d:%s]     blocks " PLANE_WM_FMT " -> " PLANE_WM_FMT "\n",
 		    plane->base.base.id, plane->base.name,
-		    old_wm->wm[0].blocks, old_wm->wm[1].blocks,
-		    old_wm->wm[2].blocks, old_wm->wm[3].blocks,
-		    old_wm->wm[4].blocks, old_wm->wm[5].blocks,
-		    old_wm->wm[6].blocks, old_wm->wm[7].blocks,
-		    old_wm->trans_wm.blocks,
-		    old_wm->sagv.wm0.blocks,
-		    old_wm->sagv.trans_wm.blocks,
-		    new_wm->wm[0].blocks, new_wm->wm[1].blocks,
-		    new_wm->wm[2].blocks, new_wm->wm[3].blocks,
-		    new_wm->wm[4].blocks, new_wm->wm[5].blocks,
-		    new_wm->wm[6].blocks, new_wm->wm[7].blocks,
-		    new_wm->trans_wm.blocks,
-		    new_wm->sagv.wm0.blocks,
-		    new_wm->sagv.trans_wm.blocks);
+		    PLANE_WM_ARGS(old_wm, blocks),
+		    PLANE_WM_ARGS(new_wm, blocks));
 
 	drm_dbg_kms(display->drm,
-		    "[PLANE:%d:%s]    min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"
-		    " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n",
+		    "[PLANE:%d:%s]    min_ddb " PLANE_WM_FMT " -> " PLANE_WM_FMT "\n",
 		    plane->base.base.id, plane->base.name,
-		    old_wm->wm[0].min_ddb_alloc, old_wm->wm[1].min_ddb_alloc,
-		    old_wm->wm[2].min_ddb_alloc, old_wm->wm[3].min_ddb_alloc,
-		    old_wm->wm[4].min_ddb_alloc, old_wm->wm[5].min_ddb_alloc,
-		    old_wm->wm[6].min_ddb_alloc, old_wm->wm[7].min_ddb_alloc,
-		    old_wm->trans_wm.min_ddb_alloc,
-		    old_wm->sagv.wm0.min_ddb_alloc,
-		    old_wm->sagv.trans_wm.min_ddb_alloc,
-		    new_wm->wm[0].min_ddb_alloc, new_wm->wm[1].min_ddb_alloc,
-		    new_wm->wm[2].min_ddb_alloc, new_wm->wm[3].min_ddb_alloc,
-		    new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc,
-		    new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc,
-		    new_wm->trans_wm.min_ddb_alloc,
-		    new_wm->sagv.wm0.min_ddb_alloc,
-		    new_wm->sagv.trans_wm.min_ddb_alloc);
+		    PLANE_WM_ARGS(old_wm, min_ddb_alloc),
+		    PLANE_WM_ARGS(new_wm, min_ddb_alloc));
 
 	if (DISPLAY_VER(display) >= 11)
 		return;
 
 	drm_dbg_kms(display->drm,
-		    "[PLANE:%d:%s] min_ddb_uv %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"
-		    " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n",
+		    "[PLANE:%d:%s] min_ddb_uv " PLANE_WM_FMT " -> " PLANE_WM_FMT "\n",
 		    plane->base.base.id, plane->base.name,
-		    old_wm->wm[0].min_ddb_alloc_uv, old_wm->wm[1].min_ddb_alloc_uv,
-		    old_wm->wm[2].min_ddb_alloc_uv, old_wm->wm[3].min_ddb_alloc_uv,
-		    old_wm->wm[4].min_ddb_alloc_uv, old_wm->wm[5].min_ddb_alloc_uv,
-		    old_wm->wm[6].min_ddb_alloc_uv, old_wm->wm[7].min_ddb_alloc_uv,
-		    old_wm->trans_wm.min_ddb_alloc_uv,
-		    old_wm->sagv.wm0.min_ddb_alloc_uv,
-		    old_wm->sagv.trans_wm.min_ddb_alloc_uv,
-		    new_wm->wm[0].min_ddb_alloc_uv, new_wm->wm[1].min_ddb_alloc_uv,
-		    new_wm->wm[2].min_ddb_alloc_uv, new_wm->wm[3].min_ddb_alloc_uv,
-		    new_wm->wm[4].min_ddb_alloc_uv, new_wm->wm[5].min_ddb_alloc_uv,
-		    new_wm->wm[6].min_ddb_alloc_uv, new_wm->wm[7].min_ddb_alloc_uv,
-		    new_wm->trans_wm.min_ddb_alloc_uv,
-		    new_wm->sagv.wm0.min_ddb_alloc_uv,
-		    new_wm->sagv.trans_wm.min_ddb_alloc_uv);
+		    PLANE_WM_ARGS(old_wm, min_ddb_alloc_uv),
+		    PLANE_WM_ARGS(new_wm, min_ddb_alloc_uv));
 }
 
+#undef PLANE_WM_EN_FMT
+#undef PLANE_WM_EN_ARGS
+#undef PLANE_WM_FMT
+#undef PLANE_WM_ARGS
+
 static void
 skl_print_wm_changes(struct intel_atomic_state *state)
 {
-- 
2.52.0

Re: [PATCH 8/9] drm/i915/wm: Reduce copy-pasta in skl_print_plane_wm_changes()

[Govindapillai, Vinod]

On Tue, 2026-03-24 at 15:48 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> skl_print_plane_wm_changes() is rather ugly with the copy-pasted
> massive printk arguments. Reduce the duplication a bit by defining
> a few FMT/ARG macros. Still ugly, but perhaps a bit less fragile.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/skl_watermark.c | 128 ++++++-----------
> --
>  1 file changed, 40 insertions(+), 88 deletions(-)
> 

Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>

> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 1d932c37d768..4bffa27ce02c 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -2613,6 +2613,26 @@ skl_print_plane_ddb_changes(struct intel_plane
> *plane,
>  		    skl_ddb_entry_size(old),
> skl_ddb_entry_size(new));
>  }
>  
> +#define PLANE_WM_EN_FMT
> "%cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm"
> +#define PLANE_WM_EN_ARGS(__wm) \
> +	enast((__wm)->wm[0].enable), enast((__wm)->wm[1].enable), \
> +	enast((__wm)->wm[2].enable), enast((__wm)->wm[3].enable), \
> +	enast((__wm)->wm[4].enable), enast((__wm)->wm[5].enable), \
> +	enast((__wm)->wm[6].enable), enast((__wm)->wm[7].enable), \
> +	enast((__wm)->trans_wm.enable), \
> +	enast((__wm)->sagv.wm0.enable), \
> +	enast((__wm)->sagv.trans_wm.enable)
> +
> +#define PLANE_WM_FMT "%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"
> +#define PLANE_WM_ARGS(__wm, __field) \
> +	(__wm)->wm[0].__field, (__wm)->wm[1].__field, \
> +	(__wm)->wm[2].__field, (__wm)->wm[3].__field, \
> +	(__wm)->wm[4].__field, (__wm)->wm[5].__field, \
> +	(__wm)->wm[6].__field, (__wm)->wm[7].__field, \
> +	(__wm)->trans_wm.__field, \
> +	(__wm)->sagv.wm0.__field, \
> +	(__wm)->sagv.trans_wm.__field
> +
>  static noinline_for_stack void
>  skl_print_plane_wm_changes(struct intel_plane *plane,
>  			   const struct skl_plane_wm *old_wm,
> @@ -2621,112 +2641,44 @@ skl_print_plane_wm_changes(struct
> intel_plane *plane,
>  	struct intel_display *display = to_intel_display(plane);
>  
>  	drm_dbg_kms(display->drm,
> -		    "[PLANE:%d:%s]      level
> %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm"
> -		    " ->
> %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm\n"
> ,
> +		    "[PLANE:%d:%s]      level " PLANE_WM_EN_FMT " ->
> " PLANE_WM_EN_FMT "\n",
>  		    plane->base.base.id, plane->base.name,
> -		    enast(old_wm->wm[0].enable), enast(old_wm-
> >wm[1].enable),
> -		    enast(old_wm->wm[2].enable), enast(old_wm-
> >wm[3].enable),
> -		    enast(old_wm->wm[4].enable), enast(old_wm-
> >wm[5].enable),
> -		    enast(old_wm->wm[6].enable), enast(old_wm-
> >wm[7].enable),
> -		    enast(old_wm->trans_wm.enable),
> -		    enast(old_wm->sagv.wm0.enable),
> -		    enast(old_wm->sagv.trans_wm.enable),
> -		    enast(new_wm->wm[0].enable), enast(new_wm-
> >wm[1].enable),
> -		    enast(new_wm->wm[2].enable), enast(new_wm-
> >wm[3].enable),
> -		    enast(new_wm->wm[4].enable), enast(new_wm-
> >wm[5].enable),
> -		    enast(new_wm->wm[6].enable), enast(new_wm-
> >wm[7].enable),
> -		    enast(new_wm->trans_wm.enable),
> -		    enast(new_wm->sagv.wm0.enable),
> -		    enast(new_wm->sagv.trans_wm.enable));
> +		    PLANE_WM_EN_ARGS(old_wm),
> +		    PLANE_WM_EN_ARGS(new_wm));
>  
>  	drm_dbg_kms(display->drm,
> -		    "[PLANE:%d:%s]      lines
> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d"
> -		      " ->
> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d\n",
> +		    "[PLANE:%d:%s]      lines " PLANE_WM_FMT " -> "
> PLANE_WM_FMT "\n",
>  		    plane->base.base.id, plane->base.name,
> -		    enast(old_wm->wm[0].ignore_lines), old_wm-
> >wm[0].lines,
> -		    enast(old_wm->wm[1].ignore_lines), old_wm-
> >wm[1].lines,
> -		    enast(old_wm->wm[2].ignore_lines), old_wm-
> >wm[2].lines,
> -		    enast(old_wm->wm[3].ignore_lines), old_wm-
> >wm[3].lines,
> -		    enast(old_wm->wm[4].ignore_lines), old_wm-
> >wm[4].lines,
> -		    enast(old_wm->wm[5].ignore_lines), old_wm-
> >wm[5].lines,
> -		    enast(old_wm->wm[6].ignore_lines), old_wm-
> >wm[6].lines,
> -		    enast(old_wm->wm[7].ignore_lines), old_wm-
> >wm[7].lines,
> -		    enast(old_wm->trans_wm.ignore_lines), old_wm-
> >trans_wm.lines,
> -		    enast(old_wm->sagv.wm0.ignore_lines), old_wm-
> >sagv.wm0.lines,
> -		    enast(old_wm->sagv.trans_wm.ignore_lines),
> old_wm->sagv.trans_wm.lines,
> -		    enast(new_wm->wm[0].ignore_lines), new_wm-
> >wm[0].lines,
> -		    enast(new_wm->wm[1].ignore_lines), new_wm-
> >wm[1].lines,
> -		    enast(new_wm->wm[2].ignore_lines), new_wm-
> >wm[2].lines,
> -		    enast(new_wm->wm[3].ignore_lines), new_wm-
> >wm[3].lines,
> -		    enast(new_wm->wm[4].ignore_lines), new_wm-
> >wm[4].lines,
> -		    enast(new_wm->wm[5].ignore_lines), new_wm-
> >wm[5].lines,
> -		    enast(new_wm->wm[6].ignore_lines), new_wm-
> >wm[6].lines,
> -		    enast(new_wm->wm[7].ignore_lines), new_wm-
> >wm[7].lines,
> -		    enast(new_wm->trans_wm.ignore_lines), new_wm-
> >trans_wm.lines,
> -		    enast(new_wm->sagv.wm0.ignore_lines), new_wm-
> >sagv.wm0.lines,
> -		    enast(new_wm->sagv.trans_wm.ignore_lines),
> new_wm->sagv.trans_wm.lines);
> +		    PLANE_WM_ARGS(old_wm, lines),
> +		    PLANE_WM_ARGS(new_wm, lines));
>  
>  	drm_dbg_kms(display->drm,
> -		    "[PLANE:%d:%s]     blocks
> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"
> -		    " ->
> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n",
> +		    "[PLANE:%d:%s]     blocks " PLANE_WM_FMT " -> "
> PLANE_WM_FMT "\n",
>  		    plane->base.base.id, plane->base.name,
> -		    old_wm->wm[0].blocks, old_wm->wm[1].blocks,
> -		    old_wm->wm[2].blocks, old_wm->wm[3].blocks,
> -		    old_wm->wm[4].blocks, old_wm->wm[5].blocks,
> -		    old_wm->wm[6].blocks, old_wm->wm[7].blocks,
> -		    old_wm->trans_wm.blocks,
> -		    old_wm->sagv.wm0.blocks,
> -		    old_wm->sagv.trans_wm.blocks,
> -		    new_wm->wm[0].blocks, new_wm->wm[1].blocks,
> -		    new_wm->wm[2].blocks, new_wm->wm[3].blocks,
> -		    new_wm->wm[4].blocks, new_wm->wm[5].blocks,
> -		    new_wm->wm[6].blocks, new_wm->wm[7].blocks,
> -		    new_wm->trans_wm.blocks,
> -		    new_wm->sagv.wm0.blocks,
> -		    new_wm->sagv.trans_wm.blocks);
> +		    PLANE_WM_ARGS(old_wm, blocks),
> +		    PLANE_WM_ARGS(new_wm, blocks));
>  
>  	drm_dbg_kms(display->drm,
> -		    "[PLANE:%d:%s]    min_ddb
> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"
> -		    " ->
> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n",
> +		    "[PLANE:%d:%s]    min_ddb " PLANE_WM_FMT " -> "
> PLANE_WM_FMT "\n",
>  		    plane->base.base.id, plane->base.name,
> -		    old_wm->wm[0].min_ddb_alloc, old_wm-
> >wm[1].min_ddb_alloc,
> -		    old_wm->wm[2].min_ddb_alloc, old_wm-
> >wm[3].min_ddb_alloc,
> -		    old_wm->wm[4].min_ddb_alloc, old_wm-
> >wm[5].min_ddb_alloc,
> -		    old_wm->wm[6].min_ddb_alloc, old_wm-
> >wm[7].min_ddb_alloc,
> -		    old_wm->trans_wm.min_ddb_alloc,
> -		    old_wm->sagv.wm0.min_ddb_alloc,
> -		    old_wm->sagv.trans_wm.min_ddb_alloc,
> -		    new_wm->wm[0].min_ddb_alloc, new_wm-
> >wm[1].min_ddb_alloc,
> -		    new_wm->wm[2].min_ddb_alloc, new_wm-
> >wm[3].min_ddb_alloc,
> -		    new_wm->wm[4].min_ddb_alloc, new_wm-
> >wm[5].min_ddb_alloc,
> -		    new_wm->wm[6].min_ddb_alloc, new_wm-
> >wm[7].min_ddb_alloc,
> -		    new_wm->trans_wm.min_ddb_alloc,
> -		    new_wm->sagv.wm0.min_ddb_alloc,
> -		    new_wm->sagv.trans_wm.min_ddb_alloc);
> +		    PLANE_WM_ARGS(old_wm, min_ddb_alloc),
> +		    PLANE_WM_ARGS(new_wm, min_ddb_alloc));
>  
>  	if (DISPLAY_VER(display) >= 11)
>  		return;
>  
>  	drm_dbg_kms(display->drm,
> -		    "[PLANE:%d:%s] min_ddb_uv
> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"
> -		    " ->
> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n",
> +		    "[PLANE:%d:%s] min_ddb_uv " PLANE_WM_FMT " -> "
> PLANE_WM_FMT "\n",
>  		    plane->base.base.id, plane->base.name,
> -		    old_wm->wm[0].min_ddb_alloc_uv, old_wm-
> >wm[1].min_ddb_alloc_uv,
> -		    old_wm->wm[2].min_ddb_alloc_uv, old_wm-
> >wm[3].min_ddb_alloc_uv,
> -		    old_wm->wm[4].min_ddb_alloc_uv, old_wm-
> >wm[5].min_ddb_alloc_uv,
> -		    old_wm->wm[6].min_ddb_alloc_uv, old_wm-
> >wm[7].min_ddb_alloc_uv,
> -		    old_wm->trans_wm.min_ddb_alloc_uv,
> -		    old_wm->sagv.wm0.min_ddb_alloc_uv,
> -		    old_wm->sagv.trans_wm.min_ddb_alloc_uv,
> -		    new_wm->wm[0].min_ddb_alloc_uv, new_wm-
> >wm[1].min_ddb_alloc_uv,
> -		    new_wm->wm[2].min_ddb_alloc_uv, new_wm-
> >wm[3].min_ddb_alloc_uv,
> -		    new_wm->wm[4].min_ddb_alloc_uv, new_wm-
> >wm[5].min_ddb_alloc_uv,
> -		    new_wm->wm[6].min_ddb_alloc_uv, new_wm-
> >wm[7].min_ddb_alloc_uv,
> -		    new_wm->trans_wm.min_ddb_alloc_uv,
> -		    new_wm->sagv.wm0.min_ddb_alloc_uv,
> -		    new_wm->sagv.trans_wm.min_ddb_alloc_uv);
> +		    PLANE_WM_ARGS(old_wm, min_ddb_alloc_uv),
> +		    PLANE_WM_ARGS(new_wm, min_ddb_alloc_uv));
>  }
>  
> +#undef PLANE_WM_EN_FMT
> +#undef PLANE_WM_EN_ARGS
> +#undef PLANE_WM_FMT
> +#undef PLANE_WM_ARGS
> +
>  static void
>  skl_print_wm_changes(struct intel_atomic_state *state)
>  {

[PATCH 9/9] drm/i915/wm: Allow SAGV with multiple pipes on pre-icl

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

There was never any documented reason for limiting SAGV to
single active pipe configuration on pre-icl. Allow SAGV
with multiple active pipes.

At least my CFL NUC seems happy with this when using
multiple displays. The machine actually has working
SAGV because the memory clock can be observed changing
via SA_PERF_STATUS/mchbar:0x5918.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 40 -------------------------
 1 file changed, 40 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 07b4531a4376..bf7683ddcb67 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -28,9 +28,6 @@ struct intel_bw_state {
 	 */
 	u8 pipe_sagv_reject;
 
-	/* bitmask of active pipes */
-	u8 active_pipes;
-
 	/*
 	 * From MTL onwards, to lock a QGV point, punit expects the peak BW of
 	 * the selected QGV point as the parameter in multiples of 100MB/s
@@ -1265,31 +1262,6 @@ static int intel_bw_check_data_rate(struct intel_atomic_state *state, bool *chan
 	return 0;
 }
 
-static int intel_bw_modeset_checks(struct intel_atomic_state *state)
-{
-	const struct intel_bw_state *old_bw_state;
-	struct intel_bw_state *new_bw_state;
-	int ret;
-
-	if (!intel_any_crtc_active_changed(state))
-		return 0;
-
-	new_bw_state = intel_atomic_get_bw_state(state);
-	if (IS_ERR(new_bw_state))
-		return PTR_ERR(new_bw_state);
-
-	old_bw_state = intel_atomic_get_old_bw_state(state);
-
-	new_bw_state->active_pipes =
-		intel_calc_active_pipes(state, old_bw_state->active_pipes);
-
-	ret = intel_atomic_lock_global_state(&new_bw_state->base);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
 static int intel_bw_check_sagv_mask(struct intel_atomic_state *state)
 {
 	struct intel_display *display = to_intel_display(state);
@@ -1346,10 +1318,6 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
 	if (DISPLAY_VER(display) < 9)
 		return 0;
 
-	ret = intel_bw_modeset_checks(state);
-	if (ret)
-		return ret;
-
 	ret = intel_bw_check_sagv_mask(state);
 	if (ret)
 		return ret;
@@ -1410,7 +1378,6 @@ void intel_bw_update_hw_state(struct intel_display *display)
 	if (DISPLAY_VER(display) < 9)
 		return;
 
-	bw_state->active_pipes = 0;
 	bw_state->pipe_sagv_reject = 0;
 
 	for_each_intel_crtc(display->drm, crtc) {
@@ -1418,9 +1385,6 @@ void intel_bw_update_hw_state(struct intel_display *display)
 			to_intel_crtc_state(crtc->base.state);
 		enum pipe pipe = crtc->pipe;
 
-		if (crtc_state->hw.active)
-			bw_state->active_pipes |= BIT(pipe);
-
 		if (DISPLAY_VER(display) >= 11)
 			intel_bw_crtc_update(bw_state, crtc_state);
 
@@ -1504,10 +1468,6 @@ bool intel_bw_pmdemand_needs_update(struct intel_atomic_state *state)
 bool intel_bw_can_enable_sagv(struct intel_display *display,
 			      const struct intel_bw_state *bw_state)
 {
-	if (DISPLAY_VER(display) < 11 &&
-	    bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
-		return false;
-
 	return bw_state->pipe_sagv_reject == 0;
 }
 
-- 
2.52.0

Re: [PATCH 9/9] drm/i915/wm: Allow SAGV with multiple pipes on pre-icl

[Govindapillai, Vinod]

On Tue, 2026-03-24 at 15:48 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> There was never any documented reason for limiting SAGV to
> single active pipe configuration on pre-icl. Allow SAGV
> with multiple active pipes.
> 
> At least my CFL NUC seems happy with this when using
> multiple displays. The machine actually has working
> SAGV because the memory clock can be observed changing
> via SA_PERF_STATUS/mchbar:0x5918.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bw.c | 40 -----------------------
> --
>  1 file changed, 40 deletions(-)
> 

Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>

> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index 07b4531a4376..bf7683ddcb67 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -28,9 +28,6 @@ struct intel_bw_state {
>  	 */
>  	u8 pipe_sagv_reject;
>  
> -	/* bitmask of active pipes */
> -	u8 active_pipes;
> -
>  	/*
>  	 * From MTL onwards, to lock a QGV point, punit expects the
> peak BW of
>  	 * the selected QGV point as the parameter in multiples of
> 100MB/s
> @@ -1265,31 +1262,6 @@ static int intel_bw_check_data_rate(struct
> intel_atomic_state *state, bool *chan
>  	return 0;
>  }
>  
> -static int intel_bw_modeset_checks(struct intel_atomic_state *state)
> -{
> -	const struct intel_bw_state *old_bw_state;
> -	struct intel_bw_state *new_bw_state;
> -	int ret;
> -
> -	if (!intel_any_crtc_active_changed(state))
> -		return 0;
> -
> -	new_bw_state = intel_atomic_get_bw_state(state);
> -	if (IS_ERR(new_bw_state))
> -		return PTR_ERR(new_bw_state);
> -
> -	old_bw_state = intel_atomic_get_old_bw_state(state);
> -
> -	new_bw_state->active_pipes =
> -		intel_calc_active_pipes(state, old_bw_state-
> >active_pipes);
> -
> -	ret = intel_atomic_lock_global_state(&new_bw_state->base);
> -	if (ret)
> -		return ret;
> -
> -	return 0;
> -}
> -
>  static int intel_bw_check_sagv_mask(struct intel_atomic_state
> *state)
>  {
>  	struct intel_display *display = to_intel_display(state);
> @@ -1346,10 +1318,6 @@ int intel_bw_atomic_check(struct
> intel_atomic_state *state)
>  	if (DISPLAY_VER(display) < 9)
>  		return 0;
>  
> -	ret = intel_bw_modeset_checks(state);
> -	if (ret)
> -		return ret;
> -
>  	ret = intel_bw_check_sagv_mask(state);
>  	if (ret)
>  		return ret;
> @@ -1410,7 +1378,6 @@ void intel_bw_update_hw_state(struct
> intel_display *display)
>  	if (DISPLAY_VER(display) < 9)
>  		return;
>  
> -	bw_state->active_pipes = 0;
>  	bw_state->pipe_sagv_reject = 0;
>  
>  	for_each_intel_crtc(display->drm, crtc) {
> @@ -1418,9 +1385,6 @@ void intel_bw_update_hw_state(struct
> intel_display *display)
>  			to_intel_crtc_state(crtc->base.state);
>  		enum pipe pipe = crtc->pipe;
>  
> -		if (crtc_state->hw.active)
> -			bw_state->active_pipes |= BIT(pipe);
> -
>  		if (DISPLAY_VER(display) >= 11)
>  			intel_bw_crtc_update(bw_state, crtc_state);
>  
> @@ -1504,10 +1468,6 @@ bool intel_bw_pmdemand_needs_update(struct
> intel_atomic_state *state)
>  bool intel_bw_can_enable_sagv(struct intel_display *display,
>  			      const struct intel_bw_state *bw_state)
>  {
> -	if (DISPLAY_VER(display) < 11 &&
> -	    bw_state->active_pipes && !is_power_of_2(bw_state-
> >active_pipes))
> -		return false;
> -
>  	return bw_state->pipe_sagv_reject == 0;
>  }
>  

✗ CI.checkpatch: warning for drm/i915/wm: Watermark/SAGV fixes/cleanups/etc

[Patchwork]

== Series Details ==

Series: drm/i915/wm: Watermark/SAGV fixes/cleanups/etc
URL   : https://patchwork.freedesktop.org/series/163783/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
1f57ba1afceae32108bd24770069f764d940a0e4
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 27adaeaea14b2b145e3f56da54c7682080580654
Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
Date:   Tue Mar 24 15:48:43 2026 +0200

    drm/i915/wm: Allow SAGV with multiple pipes on pre-icl
    
    There was never any documented reason for limiting SAGV to
    single active pipe configuration on pre-icl. Allow SAGV
    with multiple active pipes.
    
    At least my CFL NUC seems happy with this when using
    multiple displays. The machine actually has working
    SAGV because the memory clock can be observed changing
    via SA_PERF_STATUS/mchbar:0x5918.
    
    Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+ /mt/dim checkpatch 3a61374eb191c4ab83fbbcc569bb3f82a5d68819 drm-intel
c2d67d7533b2 drm/i915/wm: Reject SAGV consistently when block_time_us==0
a9f9af560708 drm/i915/wm: Don't compute separate SAGV watermarks for RKL
-:24: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#24: FILE: drivers/gpu/drm/i915/display/intel_display_device.h:203:
+#define HAS_SAGV_WM(__display)		(DISPLAY_VER(__display) >= 12 && !(__display)->platform.rocketlake)

-:24: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__display' - possible side-effects?
#24: FILE: drivers/gpu/drm/i915/display/intel_display_device.h:203:
+#define HAS_SAGV_WM(__display)		(DISPLAY_VER(__display) >= 12 && !(__display)->platform.rocketlake)

total: 0 errors, 1 warnings, 1 checks, 58 lines checked
af9bde3ce05c drm/i915/wm: Consolidate SAGV pipe active/interlace checks to common code
0262717f3680 drm/i915/wm: Verify the correct plane DDB entry
38b174170dd9 drm/i915/wm: Extract skl_wm_level_verify()
677129410b71 drm/i915/wm: Extract skl_ddb_entry_verify()
d24aee566334 drm/i915/wm: Verify 'ddb_y' as well as 'ddb'
b6fe7d92b13a drm/i915/wm: Reduce copy-pasta in skl_print_plane_wm_changes()
-:25: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#25: FILE: drivers/gpu/drm/i915/display/skl_watermark.c:2617:
+#define PLANE_WM_EN_ARGS(__wm) \
+	enast((__wm)->wm[0].enable), enast((__wm)->wm[1].enable), \
+	enast((__wm)->wm[2].enable), enast((__wm)->wm[3].enable), \
+	enast((__wm)->wm[4].enable), enast((__wm)->wm[5].enable), \
+	enast((__wm)->wm[6].enable), enast((__wm)->wm[7].enable), \
+	enast((__wm)->trans_wm.enable), \
+	enast((__wm)->sagv.wm0.enable), \
+	enast((__wm)->sagv.trans_wm.enable)

BUT SEE:

   do {} while (0) advice is over-stated in a few situations:

   The more obvious case is macros, like MODULE_PARM_DESC, invoked at
   file-scope, where C disallows code (it must be in functions).  See
   $exceptions if you have one to add by name.

   More troublesome is declarative macros used at top of new scope,
   like DECLARE_PER_CPU.  These might just compile with a do-while-0
   wrapper, but would be incorrect.  Most of these are handled by
   detecting struct,union,etc declaration primitives in $exceptions.

   Theres also macros called inside an if (block), which "return" an
   expression.  These cannot do-while, and need a ({}) wrapper.

   Enjoy this qualification while we work to improve our heuristics.

-:25: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__wm' - possible side-effects?
#25: FILE: drivers/gpu/drm/i915/display/skl_watermark.c:2617:
+#define PLANE_WM_EN_ARGS(__wm) \
+	enast((__wm)->wm[0].enable), enast((__wm)->wm[1].enable), \
+	enast((__wm)->wm[2].enable), enast((__wm)->wm[3].enable), \
+	enast((__wm)->wm[4].enable), enast((__wm)->wm[5].enable), \
+	enast((__wm)->wm[6].enable), enast((__wm)->wm[7].enable), \
+	enast((__wm)->trans_wm.enable), \
+	enast((__wm)->sagv.wm0.enable), \
+	enast((__wm)->sagv.trans_wm.enable)

-:35: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#35: FILE: drivers/gpu/drm/i915/display/skl_watermark.c:2627:
+#define PLANE_WM_ARGS(__wm, __field) \
+	(__wm)->wm[0].__field, (__wm)->wm[1].__field, \
+	(__wm)->wm[2].__field, (__wm)->wm[3].__field, \
+	(__wm)->wm[4].__field, (__wm)->wm[5].__field, \
+	(__wm)->wm[6].__field, (__wm)->wm[7].__field, \
+	(__wm)->trans_wm.__field, \
+	(__wm)->sagv.wm0.__field, \
+	(__wm)->sagv.trans_wm.__field

BUT SEE:

   do {} while (0) advice is over-stated in a few situations:

   The more obvious case is macros, like MODULE_PARM_DESC, invoked at
   file-scope, where C disallows code (it must be in functions).  See
   $exceptions if you have one to add by name.

   More troublesome is declarative macros used at top of new scope,
   like DECLARE_PER_CPU.  These might just compile with a do-while-0
   wrapper, but would be incorrect.  Most of these are handled by
   detecting struct,union,etc declaration primitives in $exceptions.

   Theres also macros called inside an if (block), which "return" an
   expression.  These cannot do-while, and need a ({}) wrapper.

   Enjoy this qualification while we work to improve our heuristics.

-:35: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__wm' - possible side-effects?
#35: FILE: drivers/gpu/drm/i915/display/skl_watermark.c:2627:
+#define PLANE_WM_ARGS(__wm, __field) \
+	(__wm)->wm[0].__field, (__wm)->wm[1].__field, \
+	(__wm)->wm[2].__field, (__wm)->wm[3].__field, \
+	(__wm)->wm[4].__field, (__wm)->wm[5].__field, \
+	(__wm)->wm[6].__field, (__wm)->wm[7].__field, \
+	(__wm)->trans_wm.__field, \
+	(__wm)->sagv.wm0.__field, \
+	(__wm)->sagv.trans_wm.__field

-:35: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__field' - possible side-effects?
#35: FILE: drivers/gpu/drm/i915/display/skl_watermark.c:2627:
+#define PLANE_WM_ARGS(__wm, __field) \
+	(__wm)->wm[0].__field, (__wm)->wm[1].__field, \
+	(__wm)->wm[2].__field, (__wm)->wm[3].__field, \
+	(__wm)->wm[4].__field, (__wm)->wm[5].__field, \
+	(__wm)->wm[6].__field, (__wm)->wm[7].__field, \
+	(__wm)->trans_wm.__field, \
+	(__wm)->sagv.wm0.__field, \
+	(__wm)->sagv.trans_wm.__field

total: 2 errors, 0 warnings, 3 checks, 158 lines checked
27adaeaea14b drm/i915/wm: Allow SAGV with multiple pipes on pre-icl

✓ CI.KUnit: success for drm/i915/wm: Watermark/SAGV fixes/cleanups/etc

[Patchwork]

== Series Details ==

Series: drm/i915/wm: Watermark/SAGV fixes/cleanups/etc
URL   : https://patchwork.freedesktop.org/series/163783/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[13:58:58] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[13:59:02] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[13:59:34] Starting KUnit Kernel (1/1)...
[13:59:34] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[13:59:34] ================== guc_buf (11 subtests) ===================
[13:59:34] [PASSED] test_smallest
[13:59:34] [PASSED] test_largest
[13:59:34] [PASSED] test_granular
[13:59:34] [PASSED] test_unique
[13:59:34] [PASSED] test_overlap
[13:59:34] [PASSED] test_reusable
[13:59:35] [PASSED] test_too_big
[13:59:35] [PASSED] test_flush
[13:59:35] [PASSED] test_lookup
[13:59:35] [PASSED] test_data
[13:59:35] [PASSED] test_class
[13:59:35] ===================== [PASSED] guc_buf =====================
[13:59:35] =================== guc_dbm (7 subtests) ===================
[13:59:35] [PASSED] test_empty
[13:59:35] [PASSED] test_default
[13:59:35] ======================== test_size  ========================
[13:59:35] [PASSED] 4
[13:59:35] [PASSED] 8
[13:59:35] [PASSED] 32
[13:59:35] [PASSED] 256
[13:59:35] ==================== [PASSED] test_size ====================
[13:59:35] ======================= test_reuse  ========================
[13:59:35] [PASSED] 4
[13:59:35] [PASSED] 8
[13:59:35] [PASSED] 32
[13:59:35] [PASSED] 256
[13:59:35] =================== [PASSED] test_reuse ====================
[13:59:35] =================== test_range_overlap  ====================
[13:59:35] [PASSED] 4
[13:59:35] [PASSED] 8
[13:59:35] [PASSED] 32
[13:59:35] [PASSED] 256
[13:59:35] =============== [PASSED] test_range_overlap ================
[13:59:35] =================== test_range_compact  ====================
[13:59:35] [PASSED] 4
[13:59:35] [PASSED] 8
[13:59:35] [PASSED] 32
[13:59:35] [PASSED] 256
[13:59:35] =============== [PASSED] test_range_compact ================
[13:59:35] ==================== test_range_spare  =====================
[13:59:35] [PASSED] 4
[13:59:35] [PASSED] 8
[13:59:35] [PASSED] 32
[13:59:35] [PASSED] 256
[13:59:35] ================ [PASSED] test_range_spare =================
[13:59:35] ===================== [PASSED] guc_dbm =====================
[13:59:35] =================== guc_idm (6 subtests) ===================
[13:59:35] [PASSED] bad_init
[13:59:35] [PASSED] no_init
[13:59:35] [PASSED] init_fini
[13:59:35] [PASSED] check_used
[13:59:35] [PASSED] check_quota
[13:59:35] [PASSED] check_all
[13:59:35] ===================== [PASSED] guc_idm =====================
[13:59:35] ================== no_relay (3 subtests) ===================
[13:59:35] [PASSED] xe_drops_guc2pf_if_not_ready
[13:59:35] [PASSED] xe_drops_guc2vf_if_not_ready
[13:59:35] [PASSED] xe_rejects_send_if_not_ready
[13:59:35] ==================== [PASSED] no_relay =====================
[13:59:35] ================== pf_relay (14 subtests) ==================
[13:59:35] [PASSED] pf_rejects_guc2pf_too_short
[13:59:35] [PASSED] pf_rejects_guc2pf_too_long
[13:59:35] [PASSED] pf_rejects_guc2pf_no_payload
[13:59:35] [PASSED] pf_fails_no_payload
[13:59:35] [PASSED] pf_fails_bad_origin
[13:59:35] [PASSED] pf_fails_bad_type
[13:59:35] [PASSED] pf_txn_reports_error
[13:59:35] [PASSED] pf_txn_sends_pf2guc
[13:59:35] [PASSED] pf_sends_pf2guc
[13:59:35] [SKIPPED] pf_loopback_nop
[13:59:35] [SKIPPED] pf_loopback_echo
[13:59:35] [SKIPPED] pf_loopback_fail
[13:59:35] [SKIPPED] pf_loopback_busy
[13:59:35] [SKIPPED] pf_loopback_retry
[13:59:35] ==================== [PASSED] pf_relay =====================
[13:59:35] ================== vf_relay (3 subtests) ===================
[13:59:35] [PASSED] vf_rejects_guc2vf_too_short
[13:59:35] [PASSED] vf_rejects_guc2vf_too_long
[13:59:35] [PASSED] vf_rejects_guc2vf_no_payload
[13:59:35] ==================== [PASSED] vf_relay =====================
[13:59:35] ================ pf_gt_config (9 subtests) =================
[13:59:35] [PASSED] fair_contexts_1vf
[13:59:35] [PASSED] fair_doorbells_1vf
[13:59:35] [PASSED] fair_ggtt_1vf
[13:59:35] ====================== fair_vram_1vf  ======================
[13:59:35] [PASSED] 3.50 GiB
[13:59:35] [PASSED] 11.5 GiB
[13:59:35] [PASSED] 15.5 GiB
[13:59:35] [PASSED] 31.5 GiB
[13:59:35] [PASSED] 63.5 GiB
[13:59:35] [PASSED] 1.91 GiB
[13:59:35] ================== [PASSED] fair_vram_1vf ==================
[13:59:35] ================ fair_vram_1vf_admin_only  =================
[13:59:35] [PASSED] 3.50 GiB
[13:59:35] [PASSED] 11.5 GiB
[13:59:35] [PASSED] 15.5 GiB
[13:59:35] [PASSED] 31.5 GiB
[13:59:35] [PASSED] 63.5 GiB
[13:59:35] [PASSED] 1.91 GiB
[13:59:35] ============ [PASSED] fair_vram_1vf_admin_only =============
[13:59:35] ====================== fair_contexts  ======================
[13:59:35] [PASSED] 1 VF
[13:59:35] [PASSED] 2 VFs
[13:59:35] [PASSED] 3 VFs
[13:59:35] [PASSED] 4 VFs
[13:59:35] [PASSED] 5 VFs
[13:59:35] [PASSED] 6 VFs
[13:59:35] [PASSED] 7 VFs
[13:59:35] [PASSED] 8 VFs
[13:59:35] [PASSED] 9 VFs
[13:59:35] [PASSED] 10 VFs
[13:59:35] [PASSED] 11 VFs
[13:59:35] [PASSED] 12 VFs
[13:59:35] [PASSED] 13 VFs
[13:59:35] [PASSED] 14 VFs
[13:59:35] [PASSED] 15 VFs
[13:59:35] [PASSED] 16 VFs
[13:59:35] [PASSED] 17 VFs
[13:59:35] [PASSED] 18 VFs
[13:59:35] [PASSED] 19 VFs
[13:59:35] [PASSED] 20 VFs
[13:59:35] [PASSED] 21 VFs
[13:59:35] [PASSED] 22 VFs
[13:59:35] [PASSED] 23 VFs
[13:59:35] [PASSED] 24 VFs
[13:59:35] [PASSED] 25 VFs
[13:59:35] [PASSED] 26 VFs
[13:59:35] [PASSED] 27 VFs
[13:59:35] [PASSED] 28 VFs
[13:59:35] [PASSED] 29 VFs
[13:59:35] [PASSED] 30 VFs
[13:59:35] [PASSED] 31 VFs
[13:59:35] [PASSED] 32 VFs
[13:59:35] [PASSED] 33 VFs
[13:59:35] [PASSED] 34 VFs
[13:59:35] [PASSED] 35 VFs
[13:59:35] [PASSED] 36 VFs
[13:59:35] [PASSED] 37 VFs
[13:59:35] [PASSED] 38 VFs
[13:59:35] [PASSED] 39 VFs
[13:59:35] [PASSED] 40 VFs
[13:59:35] [PASSED] 41 VFs
[13:59:35] [PASSED] 42 VFs
[13:59:35] [PASSED] 43 VFs
[13:59:35] [PASSED] 44 VFs
[13:59:35] [PASSED] 45 VFs
[13:59:35] [PASSED] 46 VFs
[13:59:35] [PASSED] 47 VFs
[13:59:35] [PASSED] 48 VFs
[13:59:35] [PASSED] 49 VFs
[13:59:35] [PASSED] 50 VFs
[13:59:35] [PASSED] 51 VFs
[13:59:35] [PASSED] 52 VFs
[13:59:35] [PASSED] 53 VFs
[13:59:35] [PASSED] 54 VFs
[13:59:35] [PASSED] 55 VFs
[13:59:35] [PASSED] 56 VFs
[13:59:35] [PASSED] 57 VFs
[13:59:35] [PASSED] 58 VFs
[13:59:35] [PASSED] 59 VFs
[13:59:35] [PASSED] 60 VFs
[13:59:35] [PASSED] 61 VFs
[13:59:35] [PASSED] 62 VFs
[13:59:35] [PASSED] 63 VFs
[13:59:35] ================== [PASSED] fair_contexts ==================
[13:59:35] ===================== fair_doorbells  ======================
[13:59:35] [PASSED] 1 VF
[13:59:35] [PASSED] 2 VFs
[13:59:35] [PASSED] 3 VFs
[13:59:35] [PASSED] 4 VFs
[13:59:35] [PASSED] 5 VFs
[13:59:35] [PASSED] 6 VFs
[13:59:35] [PASSED] 7 VFs
[13:59:35] [PASSED] 8 VFs
[13:59:35] [PASSED] 9 VFs
[13:59:35] [PASSED] 10 VFs
[13:59:35] [PASSED] 11 VFs
[13:59:35] [PASSED] 12 VFs
[13:59:35] [PASSED] 13 VFs
[13:59:35] [PASSED] 14 VFs
[13:59:35] [PASSED] 15 VFs
[13:59:35] [PASSED] 16 VFs
[13:59:35] [PASSED] 17 VFs
[13:59:35] [PASSED] 18 VFs
[13:59:35] [PASSED] 19 VFs
[13:59:35] [PASSED] 20 VFs
[13:59:35] [PASSED] 21 VFs
[13:59:35] [PASSED] 22 VFs
[13:59:35] [PASSED] 23 VFs
[13:59:35] [PASSED] 24 VFs
[13:59:35] [PASSED] 25 VFs
[13:59:35] [PASSED] 26 VFs
[13:59:35] [PASSED] 27 VFs
[13:59:35] [PASSED] 28 VFs
[13:59:35] [PASSED] 29 VFs
[13:59:35] [PASSED] 30 VFs
[13:59:35] [PASSED] 31 VFs
[13:59:35] [PASSED] 32 VFs
[13:59:35] [PASSED] 33 VFs
[13:59:35] [PASSED] 34 VFs
[13:59:35] [PASSED] 35 VFs
[13:59:35] [PASSED] 36 VFs
[13:59:35] [PASSED] 37 VFs
[13:59:35] [PASSED] 38 VFs
[13:59:35] [PASSED] 39 VFs
[13:59:35] [PASSED] 40 VFs
[13:59:35] [PASSED] 41 VFs
[13:59:35] [PASSED] 42 VFs
[13:59:35] [PASSED] 43 VFs
[13:59:35] [PASSED] 44 VFs
[13:59:35] [PASSED] 45 VFs
[13:59:35] [PASSED] 46 VFs
[13:59:35] [PASSED] 47 VFs
[13:59:35] [PASSED] 48 VFs
[13:59:35] [PASSED] 49 VFs
[13:59:35] [PASSED] 50 VFs
[13:59:35] [PASSED] 51 VFs
[13:59:35] [PASSED] 52 VFs
[13:59:35] [PASSED] 53 VFs
[13:59:35] [PASSED] 54 VFs
[13:59:35] [PASSED] 55 VFs
[13:59:35] [PASSED] 56 VFs
[13:59:35] [PASSED] 57 VFs
[13:59:35] [PASSED] 58 VFs
[13:59:35] [PASSED] 59 VFs
[13:59:35] [PASSED] 60 VFs
[13:59:35] [PASSED] 61 VFs
[13:59:35] [PASSED] 62 VFs
[13:59:35] [PASSED] 63 VFs
[13:59:35] ================= [PASSED] fair_doorbells ==================
[13:59:35] ======================== fair_ggtt  ========================
[13:59:35] [PASSED] 1 VF
[13:59:35] [PASSED] 2 VFs
[13:59:35] [PASSED] 3 VFs
[13:59:35] [PASSED] 4 VFs
[13:59:35] [PASSED] 5 VFs
[13:59:35] [PASSED] 6 VFs
[13:59:35] [PASSED] 7 VFs
[13:59:35] [PASSED] 8 VFs
[13:59:35] [PASSED] 9 VFs
[13:59:35] [PASSED] 10 VFs
[13:59:35] [PASSED] 11 VFs
[13:59:35] [PASSED] 12 VFs
[13:59:35] [PASSED] 13 VFs
[13:59:35] [PASSED] 14 VFs
[13:59:35] [PASSED] 15 VFs
[13:59:35] [PASSED] 16 VFs
[13:59:35] [PASSED] 17 VFs
[13:59:35] [PASSED] 18 VFs
[13:59:35] [PASSED] 19 VFs
[13:59:35] [PASSED] 20 VFs
[13:59:35] [PASSED] 21 VFs
[13:59:35] [PASSED] 22 VFs
[13:59:35] [PASSED] 23 VFs
[13:59:35] [PASSED] 24 VFs
[13:59:35] [PASSED] 25 VFs
[13:59:35] [PASSED] 26 VFs
[13:59:35] [PASSED] 27 VFs
[13:59:35] [PASSED] 28 VFs
[13:59:35] [PASSED] 29 VFs
[13:59:35] [PASSED] 30 VFs
[13:59:35] [PASSED] 31 VFs
[13:59:35] [PASSED] 32 VFs
[13:59:35] [PASSED] 33 VFs
[13:59:35] [PASSED] 34 VFs
[13:59:35] [PASSED] 35 VFs
[13:59:35] [PASSED] 36 VFs
[13:59:35] [PASSED] 37 VFs
[13:59:35] [PASSED] 38 VFs
[13:59:35] [PASSED] 39 VFs
[13:59:35] [PASSED] 40 VFs
[13:59:35] [PASSED] 41 VFs
[13:59:35] [PASSED] 42 VFs
[13:59:35] [PASSED] 43 VFs
[13:59:35] [PASSED] 44 VFs
[13:59:35] [PASSED] 45 VFs
[13:59:35] [PASSED] 46 VFs
[13:59:35] [PASSED] 47 VFs
[13:59:35] [PASSED] 48 VFs
[13:59:35] [PASSED] 49 VFs
[13:59:35] [PASSED] 50 VFs
[13:59:35] [PASSED] 51 VFs
[13:59:35] [PASSED] 52 VFs
[13:59:35] [PASSED] 53 VFs
[13:59:35] [PASSED] 54 VFs
[13:59:35] [PASSED] 55 VFs
[13:59:35] [PASSED] 56 VFs
[13:59:35] [PASSED] 57 VFs
[13:59:35] [PASSED] 58 VFs
[13:59:35] [PASSED] 59 VFs
[13:59:35] [PASSED] 60 VFs
[13:59:35] [PASSED] 61 VFs
[13:59:35] [PASSED] 62 VFs
[13:59:35] [PASSED] 63 VFs
[13:59:35] ==================== [PASSED] fair_ggtt ====================
[13:59:35] ======================== fair_vram  ========================
[13:59:35] [PASSED] 1 VF
[13:59:35] [PASSED] 2 VFs
[13:59:35] [PASSED] 3 VFs
[13:59:35] [PASSED] 4 VFs
[13:59:35] [PASSED] 5 VFs
[13:59:35] [PASSED] 6 VFs
[13:59:35] [PASSED] 7 VFs
[13:59:35] [PASSED] 8 VFs
[13:59:35] [PASSED] 9 VFs
[13:59:35] [PASSED] 10 VFs
[13:59:35] [PASSED] 11 VFs
[13:59:35] [PASSED] 12 VFs
[13:59:35] [PASSED] 13 VFs
[13:59:35] [PASSED] 14 VFs
[13:59:35] [PASSED] 15 VFs
[13:59:35] [PASSED] 16 VFs
[13:59:35] [PASSED] 17 VFs
[13:59:35] [PASSED] 18 VFs
[13:59:35] [PASSED] 19 VFs
[13:59:35] [PASSED] 20 VFs
[13:59:35] [PASSED] 21 VFs
[13:59:35] [PASSED] 22 VFs
[13:59:35] [PASSED] 23 VFs
[13:59:35] [PASSED] 24 VFs
[13:59:35] [PASSED] 25 VFs
[13:59:35] [PASSED] 26 VFs
[13:59:35] [PASSED] 27 VFs
[13:59:35] [PASSED] 28 VFs
[13:59:35] [PASSED] 29 VFs
[13:59:35] [PASSED] 30 VFs
[13:59:35] [PASSED] 31 VFs
[13:59:35] [PASSED] 32 VFs
[13:59:35] [PASSED] 33 VFs
[13:59:35] [PASSED] 34 VFs
[13:59:35] [PASSED] 35 VFs
[13:59:35] [PASSED] 36 VFs
[13:59:35] [PASSED] 37 VFs
[13:59:35] [PASSED] 38 VFs
[13:59:35] [PASSED] 39 VFs
[13:59:35] [PASSED] 40 VFs
[13:59:35] [PASSED] 41 VFs
[13:59:35] [PASSED] 42 VFs
[13:59:35] [PASSED] 43 VFs
[13:59:35] [PASSED] 44 VFs
[13:59:35] [PASSED] 45 VFs
[13:59:35] [PASSED] 46 VFs
[13:59:35] [PASSED] 47 VFs
[13:59:35] [PASSED] 48 VFs
[13:59:35] [PASSED] 49 VFs
[13:59:35] [PASSED] 50 VFs
[13:59:35] [PASSED] 51 VFs
[13:59:35] [PASSED] 52 VFs
[13:59:35] [PASSED] 53 VFs
[13:59:35] [PASSED] 54 VFs
[13:59:35] [PASSED] 55 VFs
[13:59:35] [PASSED] 56 VFs
[13:59:35] [PASSED] 57 VFs
[13:59:35] [PASSED] 58 VFs
[13:59:35] [PASSED] 59 VFs
[13:59:35] [PASSED] 60 VFs
[13:59:35] [PASSED] 61 VFs
[13:59:35] [PASSED] 62 VFs
[13:59:35] [PASSED] 63 VFs
[13:59:35] ==================== [PASSED] fair_vram ====================
[13:59:35] ================== [PASSED] pf_gt_config ===================
[13:59:35] ===================== lmtt (1 subtest) =====================
[13:59:35] ======================== test_ops  =========================
[13:59:35] [PASSED] 2-level
[13:59:35] [PASSED] multi-level
[13:59:35] ==================== [PASSED] test_ops =====================
[13:59:35] ====================== [PASSED] lmtt =======================
[13:59:35] ================= pf_service (11 subtests) =================
[13:59:35] [PASSED] pf_negotiate_any
[13:59:35] [PASSED] pf_negotiate_base_match
[13:59:35] [PASSED] pf_negotiate_base_newer
[13:59:35] [PASSED] pf_negotiate_base_next
[13:59:35] [SKIPPED] pf_negotiate_base_older
[13:59:35] [PASSED] pf_negotiate_base_prev
[13:59:35] [PASSED] pf_negotiate_latest_match
[13:59:35] [PASSED] pf_negotiate_latest_newer
[13:59:35] [PASSED] pf_negotiate_latest_next
[13:59:35] [SKIPPED] pf_negotiate_latest_older
[13:59:35] [SKIPPED] pf_negotiate_latest_prev
[13:59:35] =================== [PASSED] pf_service ====================
[13:59:35] ================= xe_guc_g2g (2 subtests) ==================
[13:59:35] ============== xe_live_guc_g2g_kunit_default  ==============
[13:59:35] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[13:59:35] ============== xe_live_guc_g2g_kunit_allmem  ===============
[13:59:35] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[13:59:35] =================== [SKIPPED] xe_guc_g2g ===================
[13:59:35] =================== xe_mocs (2 subtests) ===================
[13:59:35] ================ xe_live_mocs_kernel_kunit  ================
[13:59:35] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[13:59:35] ================ xe_live_mocs_reset_kunit  =================
[13:59:35] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[13:59:35] ==================== [SKIPPED] xe_mocs =====================
[13:59:35] ================= xe_migrate (2 subtests) ==================
[13:59:35] ================= xe_migrate_sanity_kunit  =================
[13:59:35] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[13:59:35] ================== xe_validate_ccs_kunit  ==================
[13:59:35] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[13:59:35] =================== [SKIPPED] xe_migrate ===================
[13:59:35] ================== xe_dma_buf (1 subtest) ==================
[13:59:35] ==================== xe_dma_buf_kunit  =====================
[13:59:35] ================ [SKIPPED] xe_dma_buf_kunit ================
[13:59:35] =================== [SKIPPED] xe_dma_buf ===================
[13:59:35] ================= xe_bo_shrink (1 subtest) =================
[13:59:35] =================== xe_bo_shrink_kunit  ====================
[13:59:35] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[13:59:35] ================== [SKIPPED] xe_bo_shrink ==================
[13:59:35] ==================== xe_bo (2 subtests) ====================
[13:59:35] ================== xe_ccs_migrate_kunit  ===================
[13:59:35] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[13:59:35] ==================== xe_bo_evict_kunit  ====================
[13:59:35] =============== [SKIPPED] xe_bo_evict_kunit ================
[13:59:35] ===================== [SKIPPED] xe_bo ======================
[13:59:35] ==================== args (13 subtests) ====================
[13:59:35] [PASSED] count_args_test
[13:59:35] [PASSED] call_args_example
[13:59:35] [PASSED] call_args_test
[13:59:35] [PASSED] drop_first_arg_example
[13:59:35] [PASSED] drop_first_arg_test
[13:59:35] [PASSED] first_arg_example
[13:59:35] [PASSED] first_arg_test
[13:59:35] [PASSED] last_arg_example
[13:59:35] [PASSED] last_arg_test
[13:59:35] [PASSED] pick_arg_example
[13:59:35] [PASSED] if_args_example
[13:59:35] [PASSED] if_args_test
[13:59:35] [PASSED] sep_comma_example
[13:59:35] ====================== [PASSED] args =======================
[13:59:35] =================== xe_pci (3 subtests) ====================
[13:59:35] ==================== check_graphics_ip  ====================
[13:59:35] [PASSED] 12.00 Xe_LP
[13:59:35] [PASSED] 12.10 Xe_LP+
[13:59:35] [PASSED] 12.55 Xe_HPG
[13:59:35] [PASSED] 12.60 Xe_HPC
[13:59:35] [PASSED] 12.70 Xe_LPG
[13:59:35] [PASSED] 12.71 Xe_LPG
[13:59:35] [PASSED] 12.74 Xe_LPG+
[13:59:35] [PASSED] 20.01 Xe2_HPG
[13:59:35] [PASSED] 20.02 Xe2_HPG
[13:59:35] [PASSED] 20.04 Xe2_LPG
[13:59:35] [PASSED] 30.00 Xe3_LPG
[13:59:35] [PASSED] 30.01 Xe3_LPG
[13:59:35] [PASSED] 30.03 Xe3_LPG
[13:59:35] [PASSED] 30.04 Xe3_LPG
[13:59:35] [PASSED] 30.05 Xe3_LPG
[13:59:35] [PASSED] 35.10 Xe3p_LPG
[13:59:35] [PASSED] 35.11 Xe3p_XPC
[13:59:35] ================ [PASSED] check_graphics_ip ================
[13:59:35] ===================== check_media_ip  ======================
[13:59:35] [PASSED] 12.00 Xe_M
[13:59:35] [PASSED] 12.55 Xe_HPM
[13:59:35] [PASSED] 13.00 Xe_LPM+
[13:59:35] [PASSED] 13.01 Xe2_HPM
[13:59:35] [PASSED] 20.00 Xe2_LPM
[13:59:35] [PASSED] 30.00 Xe3_LPM
[13:59:35] [PASSED] 30.02 Xe3_LPM
[13:59:35] [PASSED] 35.00 Xe3p_LPM
[13:59:35] [PASSED] 35.03 Xe3p_HPM
[13:59:35] ================= [PASSED] check_media_ip ==================
[13:59:35] =================== check_platform_desc  ===================
[13:59:35] [PASSED] 0x9A60 (TIGERLAKE)
[13:59:35] [PASSED] 0x9A68 (TIGERLAKE)
[13:59:35] [PASSED] 0x9A70 (TIGERLAKE)
[13:59:35] [PASSED] 0x9A40 (TIGERLAKE)
[13:59:35] [PASSED] 0x9A49 (TIGERLAKE)
[13:59:35] [PASSED] 0x9A59 (TIGERLAKE)
[13:59:35] [PASSED] 0x9A78 (TIGERLAKE)
[13:59:35] [PASSED] 0x9AC0 (TIGERLAKE)
[13:59:35] [PASSED] 0x9AC9 (TIGERLAKE)
[13:59:35] [PASSED] 0x9AD9 (TIGERLAKE)
[13:59:35] [PASSED] 0x9AF8 (TIGERLAKE)
[13:59:35] [PASSED] 0x4C80 (ROCKETLAKE)
[13:59:35] [PASSED] 0x4C8A (ROCKETLAKE)
[13:59:35] [PASSED] 0x4C8B (ROCKETLAKE)
[13:59:35] [PASSED] 0x4C8C (ROCKETLAKE)
[13:59:35] [PASSED] 0x4C90 (ROCKETLAKE)
[13:59:35] [PASSED] 0x4C9A (ROCKETLAKE)
[13:59:35] [PASSED] 0x4680 (ALDERLAKE_S)
[13:59:35] [PASSED] 0x4682 (ALDERLAKE_S)
[13:59:35] [PASSED] 0x4688 (ALDERLAKE_S)
[13:59:35] [PASSED] 0x468A (ALDERLAKE_S)
[13:59:35] [PASSED] 0x468B (ALDERLAKE_S)
[13:59:35] [PASSED] 0x4690 (ALDERLAKE_S)
[13:59:35] [PASSED] 0x4692 (ALDERLAKE_S)
[13:59:35] [PASSED] 0x4693 (ALDERLAKE_S)
[13:59:35] [PASSED] 0x46A0 (ALDERLAKE_P)
[13:59:35] [PASSED] 0x46A1 (ALDERLAKE_P)
[13:59:35] [PASSED] 0x46A2 (ALDERLAKE_P)
[13:59:35] [PASSED] 0x46A3 (ALDERLAKE_P)
[13:59:35] [PASSED] 0x46A6 (ALDERLAKE_P)
[13:59:35] [PASSED] 0x46A8 (ALDERLAKE_P)
[13:59:35] [PASSED] 0x46AA (ALDERLAKE_P)
[13:59:35] [PASSED] 0x462A (ALDERLAKE_P)
[13:59:35] [PASSED] 0x4626 (ALDERLAKE_P)
[13:59:35] [PASSED] 0x4628 (ALDERLAKE_P)
[13:59:35] [PASSED] 0x46B0 (ALDERLAKE_P)
[13:59:35] [PASSED] 0x46B1 (ALDERLAKE_P)
[13:59:35] [PASSED] 0x46B2 (ALDERLAKE_P)
[13:59:35] [PASSED] 0x46B3 (ALDERLAKE_P)
[13:59:35] [PASSED] 0x46C0 (ALDERLAKE_P)
[13:59:35] [PASSED] 0x46C1 (ALDERLAKE_P)
[13:59:35] [PASSED] 0x46C2 (ALDERLAKE_P)
[13:59:35] [PASSED] 0x46C3 (ALDERLAKE_P)
[13:59:35] [PASSED] 0x46D0 (ALDERLAKE_N)
[13:59:35] [PASSED] 0x46D1 (ALDERLAKE_N)
[13:59:35] [PASSED] 0x46D2 (ALDERLAKE_N)
[13:59:35] [PASSED] 0x46D3 (ALDERLAKE_N)
[13:59:35] [PASSED] 0x46D4 (ALDERLAKE_N)
[13:59:35] [PASSED] 0xA721 (ALDERLAKE_P)
[13:59:35] [PASSED] 0xA7A1 (ALDERLAKE_P)
[13:59:35] [PASSED] 0xA7A9 (ALDERLAKE_P)
[13:59:35] [PASSED] 0xA7AC (ALDERLAKE_P)
[13:59:35] [PASSED] 0xA7AD (ALDERLAKE_P)
[13:59:35] [PASSED] 0xA720 (ALDERLAKE_P)
[13:59:35] [PASSED] 0xA7A0 (ALDERLAKE_P)
[13:59:35] [PASSED] 0xA7A8 (ALDERLAKE_P)
[13:59:35] [PASSED] 0xA7AA (ALDERLAKE_P)
[13:59:35] [PASSED] 0xA7AB (ALDERLAKE_P)
[13:59:35] [PASSED] 0xA780 (ALDERLAKE_S)
[13:59:35] [PASSED] 0xA781 (ALDERLAKE_S)
[13:59:35] [PASSED] 0xA782 (ALDERLAKE_S)
[13:59:35] [PASSED] 0xA783 (ALDERLAKE_S)
[13:59:35] [PASSED] 0xA788 (ALDERLAKE_S)
[13:59:35] [PASSED] 0xA789 (ALDERLAKE_S)
[13:59:35] [PASSED] 0xA78A (ALDERLAKE_S)
[13:59:35] [PASSED] 0xA78B (ALDERLAKE_S)
[13:59:35] [PASSED] 0x4905 (DG1)
[13:59:35] [PASSED] 0x4906 (DG1)
[13:59:35] [PASSED] 0x4907 (DG1)
[13:59:35] [PASSED] 0x4908 (DG1)
[13:59:35] [PASSED] 0x4909 (DG1)
[13:59:35] [PASSED] 0x56C0 (DG2)
[13:59:35] [PASSED] 0x56C2 (DG2)
[13:59:35] [PASSED] 0x56C1 (DG2)
[13:59:35] [PASSED] 0x7D51 (METEORLAKE)
[13:59:35] [PASSED] 0x7DD1 (METEORLAKE)
[13:59:35] [PASSED] 0x7D41 (METEORLAKE)
[13:59:35] [PASSED] 0x7D67 (METEORLAKE)
[13:59:35] [PASSED] 0xB640 (METEORLAKE)
[13:59:35] [PASSED] 0x56A0 (DG2)
[13:59:35] [PASSED] 0x56A1 (DG2)
[13:59:35] [PASSED] 0x56A2 (DG2)
[13:59:35] [PASSED] 0x56BE (DG2)
[13:59:35] [PASSED] 0x56BF (DG2)
[13:59:35] [PASSED] 0x5690 (DG2)
[13:59:35] [PASSED] 0x5691 (DG2)
[13:59:35] [PASSED] 0x5692 (DG2)
[13:59:35] [PASSED] 0x56A5 (DG2)
[13:59:35] [PASSED] 0x56A6 (DG2)
[13:59:35] [PASSED] 0x56B0 (DG2)
[13:59:35] [PASSED] 0x56B1 (DG2)
[13:59:35] [PASSED] 0x56BA (DG2)
[13:59:35] [PASSED] 0x56BB (DG2)
[13:59:35] [PASSED] 0x56BC (DG2)
[13:59:35] [PASSED] 0x56BD (DG2)
[13:59:35] [PASSED] 0x5693 (DG2)
[13:59:35] [PASSED] 0x5694 (DG2)
[13:59:35] [PASSED] 0x5695 (DG2)
[13:59:35] [PASSED] 0x56A3 (DG2)
[13:59:35] [PASSED] 0x56A4 (DG2)
[13:59:35] [PASSED] 0x56B2 (DG2)
[13:59:35] [PASSED] 0x56B3 (DG2)
[13:59:35] [PASSED] 0x5696 (DG2)
[13:59:35] [PASSED] 0x5697 (DG2)
[13:59:35] [PASSED] 0xB69 (PVC)
[13:59:35] [PASSED] 0xB6E (PVC)
[13:59:35] [PASSED] 0xBD4 (PVC)
[13:59:35] [PASSED] 0xBD5 (PVC)
[13:59:35] [PASSED] 0xBD6 (PVC)
[13:59:35] [PASSED] 0xBD7 (PVC)
[13:59:35] [PASSED] 0xBD8 (PVC)
[13:59:35] [PASSED] 0xBD9 (PVC)
[13:59:35] [PASSED] 0xBDA (PVC)
[13:59:35] [PASSED] 0xBDB (PVC)
[13:59:35] [PASSED] 0xBE0 (PVC)
[13:59:35] [PASSED] 0xBE1 (PVC)
[13:59:35] [PASSED] 0xBE5 (PVC)
[13:59:35] [PASSED] 0x7D40 (METEORLAKE)
[13:59:35] [PASSED] 0x7D45 (METEORLAKE)
[13:59:35] [PASSED] 0x7D55 (METEORLAKE)
[13:59:35] [PASSED] 0x7D60 (METEORLAKE)
[13:59:35] [PASSED] 0x7DD5 (METEORLAKE)
[13:59:35] [PASSED] 0x6420 (LUNARLAKE)
[13:59:35] [PASSED] 0x64A0 (LUNARLAKE)
[13:59:35] [PASSED] 0x64B0 (LUNARLAKE)
[13:59:35] [PASSED] 0xE202 (BATTLEMAGE)
[13:59:35] [PASSED] 0xE209 (BATTLEMAGE)
[13:59:35] [PASSED] 0xE20B (BATTLEMAGE)
[13:59:35] [PASSED] 0xE20C (BATTLEMAGE)
[13:59:35] [PASSED] 0xE20D (BATTLEMAGE)
[13:59:35] [PASSED] 0xE210 (BATTLEMAGE)
[13:59:35] [PASSED] 0xE211 (BATTLEMAGE)
[13:59:35] [PASSED] 0xE212 (BATTLEMAGE)
[13:59:35] [PASSED] 0xE216 (BATTLEMAGE)
[13:59:35] [PASSED] 0xE220 (BATTLEMAGE)
[13:59:35] [PASSED] 0xE221 (BATTLEMAGE)
[13:59:35] [PASSED] 0xE222 (BATTLEMAGE)
[13:59:35] [PASSED] 0xE223 (BATTLEMAGE)
[13:59:35] [PASSED] 0xB080 (PANTHERLAKE)
[13:59:35] [PASSED] 0xB081 (PANTHERLAKE)
[13:59:35] [PASSED] 0xB082 (PANTHERLAKE)
[13:59:35] [PASSED] 0xB083 (PANTHERLAKE)
[13:59:35] [PASSED] 0xB084 (PANTHERLAKE)
[13:59:35] [PASSED] 0xB085 (PANTHERLAKE)
[13:59:35] [PASSED] 0xB086 (PANTHERLAKE)
[13:59:35] [PASSED] 0xB087 (PANTHERLAKE)
[13:59:35] [PASSED] 0xB08F (PANTHERLAKE)
[13:59:35] [PASSED] 0xB090 (PANTHERLAKE)
[13:59:35] [PASSED] 0xB0A0 (PANTHERLAKE)
[13:59:35] [PASSED] 0xB0B0 (PANTHERLAKE)
[13:59:35] [PASSED] 0xFD80 (PANTHERLAKE)
[13:59:35] [PASSED] 0xFD81 (PANTHERLAKE)
[13:59:35] [PASSED] 0xD740 (NOVALAKE_S)
[13:59:35] [PASSED] 0xD741 (NOVALAKE_S)
[13:59:35] [PASSED] 0xD742 (NOVALAKE_S)
[13:59:35] [PASSED] 0xD743 (NOVALAKE_S)
[13:59:35] [PASSED] 0xD744 (NOVALAKE_S)
[13:59:35] [PASSED] 0xD745 (NOVALAKE_S)
[13:59:35] [PASSED] 0x674C (CRESCENTISLAND)
[13:59:35] [PASSED] 0xD750 (NOVALAKE_P)
[13:59:35] [PASSED] 0xD751 (NOVALAKE_P)
[13:59:35] [PASSED] 0xD752 (NOVALAKE_P)
[13:59:35] [PASSED] 0xD753 (NOVALAKE_P)
[13:59:35] [PASSED] 0xD754 (NOVALAKE_P)
[13:59:35] [PASSED] 0xD755 (NOVALAKE_P)
[13:59:35] [PASSED] 0xD756 (NOVALAKE_P)
[13:59:35] [PASSED] 0xD757 (NOVALAKE_P)
[13:59:35] [PASSED] 0xD75F (NOVALAKE_P)
[13:59:35] =============== [PASSED] check_platform_desc ===============
[13:59:35] ===================== [PASSED] xe_pci ======================
[13:59:35] =================== xe_rtp (2 subtests) ====================
[13:59:35] =============== xe_rtp_process_to_sr_tests  ================
[13:59:35] [PASSED] coalesce-same-reg
[13:59:35] [PASSED] no-match-no-add
[13:59:35] [PASSED] match-or
[13:59:35] [PASSED] match-or-xfail
[13:59:35] [PASSED] no-match-no-add-multiple-rules
[13:59:35] [PASSED] two-regs-two-entries
[13:59:35] [PASSED] clr-one-set-other
[13:59:35] [PASSED] set-field
[13:59:35] [PASSED] conflict-duplicate
stty: 'standard input': Inappropriate ioctl for device
[13:59:35] [PASSED] conflict-not-disjoint
[13:59:35] [PASSED] conflict-reg-type
[13:59:35] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[13:59:35] ================== xe_rtp_process_tests  ===================
[13:59:35] [PASSED] active1
[13:59:35] [PASSED] active2
[13:59:35] [PASSED] active-inactive
[13:59:35] [PASSED] inactive-active
[13:59:35] [PASSED] inactive-1st_or_active-inactive
[13:59:35] [PASSED] inactive-2nd_or_active-inactive
[13:59:35] [PASSED] inactive-last_or_active-inactive
[13:59:35] [PASSED] inactive-no_or_active-inactive
[13:59:35] ============== [PASSED] xe_rtp_process_tests ===============
[13:59:35] ===================== [PASSED] xe_rtp ======================
[13:59:35] ==================== xe_wa (1 subtest) =====================
[13:59:35] ======================== xe_wa_gt  =========================
[13:59:35] [PASSED] TIGERLAKE B0
[13:59:35] [PASSED] DG1 A0
[13:59:35] [PASSED] DG1 B0
[13:59:35] [PASSED] ALDERLAKE_S A0
[13:59:35] [PASSED] ALDERLAKE_S B0
[13:59:35] [PASSED] ALDERLAKE_S C0
[13:59:35] [PASSED] ALDERLAKE_S D0
[13:59:35] [PASSED] ALDERLAKE_P A0
[13:59:35] [PASSED] ALDERLAKE_P B0
[13:59:35] [PASSED] ALDERLAKE_P C0
[13:59:35] [PASSED] ALDERLAKE_S RPLS D0
[13:59:35] [PASSED] ALDERLAKE_P RPLU E0
[13:59:35] [PASSED] DG2 G10 C0
[13:59:35] [PASSED] DG2 G11 B1
[13:59:35] [PASSED] DG2 G12 A1
[13:59:35] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[13:59:35] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[13:59:35] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[13:59:35] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[13:59:35] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[13:59:35] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[13:59:35] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[13:59:35] ==================== [PASSED] xe_wa_gt =====================
[13:59:35] ====================== [PASSED] xe_wa ======================
[13:59:35] ============================================================
[13:59:35] Testing complete. Ran 597 tests: passed: 579, skipped: 18
[13:59:35] Elapsed time: 36.742s total, 4.334s configuring, 31.791s building, 0.603s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[13:59:35] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[13:59:37] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[14:00:02] Starting KUnit Kernel (1/1)...
[14:00:02] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[14:00:02] ============ drm_test_pick_cmdline (2 subtests) ============
[14:00:02] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[14:00:02] =============== drm_test_pick_cmdline_named  ===============
[14:00:02] [PASSED] NTSC
[14:00:02] [PASSED] NTSC-J
[14:00:02] [PASSED] PAL
[14:00:02] [PASSED] PAL-M
[14:00:02] =========== [PASSED] drm_test_pick_cmdline_named ===========
[14:00:02] ============== [PASSED] drm_test_pick_cmdline ==============
[14:00:02] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[14:00:02] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[14:00:02] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[14:00:02] =========== drm_validate_clone_mode (2 subtests) ===========
[14:00:02] ============== drm_test_check_in_clone_mode  ===============
[14:00:02] [PASSED] in_clone_mode
[14:00:02] [PASSED] not_in_clone_mode
[14:00:02] ========== [PASSED] drm_test_check_in_clone_mode ===========
[14:00:02] =============== drm_test_check_valid_clones  ===============
[14:00:02] [PASSED] not_in_clone_mode
[14:00:02] [PASSED] valid_clone
[14:00:02] [PASSED] invalid_clone
[14:00:02] =========== [PASSED] drm_test_check_valid_clones ===========
[14:00:02] ============= [PASSED] drm_validate_clone_mode =============
[14:00:02] ============= drm_validate_modeset (1 subtest) =============
[14:00:02] [PASSED] drm_test_check_connector_changed_modeset
[14:00:02] ============== [PASSED] drm_validate_modeset ===============
[14:00:02] ====== drm_test_bridge_get_current_state (2 subtests) ======
[14:00:02] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[14:00:02] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[14:00:02] ======== [PASSED] drm_test_bridge_get_current_state ========
[14:00:02] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[14:00:02] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[14:00:02] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[14:00:02] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[14:00:02] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[14:00:02] ============== drm_bridge_alloc (2 subtests) ===============
[14:00:02] [PASSED] drm_test_drm_bridge_alloc_basic
[14:00:02] [PASSED] drm_test_drm_bridge_alloc_get_put
[14:00:02] ================ [PASSED] drm_bridge_alloc =================
[14:00:02] ============= drm_cmdline_parser (40 subtests) =============
[14:00:02] [PASSED] drm_test_cmdline_force_d_only
[14:00:02] [PASSED] drm_test_cmdline_force_D_only_dvi
[14:00:02] [PASSED] drm_test_cmdline_force_D_only_hdmi
[14:00:02] [PASSED] drm_test_cmdline_force_D_only_not_digital
[14:00:02] [PASSED] drm_test_cmdline_force_e_only
[14:00:02] [PASSED] drm_test_cmdline_res
[14:00:02] [PASSED] drm_test_cmdline_res_vesa
[14:00:02] [PASSED] drm_test_cmdline_res_vesa_rblank
[14:00:02] [PASSED] drm_test_cmdline_res_rblank
[14:00:02] [PASSED] drm_test_cmdline_res_bpp
[14:00:02] [PASSED] drm_test_cmdline_res_refresh
[14:00:02] [PASSED] drm_test_cmdline_res_bpp_refresh
[14:00:02] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[14:00:02] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[14:00:02] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[14:00:02] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[14:00:02] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[14:00:02] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[14:00:02] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[14:00:02] [PASSED] drm_test_cmdline_res_margins_force_on
[14:00:02] [PASSED] drm_test_cmdline_res_vesa_margins
[14:00:02] [PASSED] drm_test_cmdline_name
[14:00:02] [PASSED] drm_test_cmdline_name_bpp
[14:00:02] [PASSED] drm_test_cmdline_name_option
[14:00:02] [PASSED] drm_test_cmdline_name_bpp_option
[14:00:02] [PASSED] drm_test_cmdline_rotate_0
[14:00:02] [PASSED] drm_test_cmdline_rotate_90
[14:00:02] [PASSED] drm_test_cmdline_rotate_180
[14:00:02] [PASSED] drm_test_cmdline_rotate_270
[14:00:02] [PASSED] drm_test_cmdline_hmirror
[14:00:02] [PASSED] drm_test_cmdline_vmirror
[14:00:02] [PASSED] drm_test_cmdline_margin_options
[14:00:02] [PASSED] drm_test_cmdline_multiple_options
[14:00:02] [PASSED] drm_test_cmdline_bpp_extra_and_option
[14:00:02] [PASSED] drm_test_cmdline_extra_and_option
[14:00:02] [PASSED] drm_test_cmdline_freestanding_options
[14:00:02] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[14:00:02] [PASSED] drm_test_cmdline_panel_orientation
[14:00:02] ================ drm_test_cmdline_invalid  =================
[14:00:02] [PASSED] margin_only
[14:00:02] [PASSED] interlace_only
[14:00:02] [PASSED] res_missing_x
[14:00:02] [PASSED] res_missing_y
[14:00:02] [PASSED] res_bad_y
[14:00:02] [PASSED] res_missing_y_bpp
[14:00:02] [PASSED] res_bad_bpp
[14:00:02] [PASSED] res_bad_refresh
[14:00:02] [PASSED] res_bpp_refresh_force_on_off
[14:00:02] [PASSED] res_invalid_mode
[14:00:02] [PASSED] res_bpp_wrong_place_mode
[14:00:02] [PASSED] name_bpp_refresh
[14:00:02] [PASSED] name_refresh
[14:00:02] [PASSED] name_refresh_wrong_mode
[14:00:02] [PASSED] name_refresh_invalid_mode
[14:00:02] [PASSED] rotate_multiple
[14:00:02] [PASSED] rotate_invalid_val
[14:00:02] [PASSED] rotate_truncated
[14:00:02] [PASSED] invalid_option
[14:00:02] [PASSED] invalid_tv_option
[14:00:02] [PASSED] truncated_tv_option
[14:00:02] ============ [PASSED] drm_test_cmdline_invalid =============
[14:00:02] =============== drm_test_cmdline_tv_options  ===============
[14:00:02] [PASSED] NTSC
[14:00:02] [PASSED] NTSC_443
[14:00:02] [PASSED] NTSC_J
[14:00:02] [PASSED] PAL
[14:00:02] [PASSED] PAL_M
[14:00:02] [PASSED] PAL_N
[14:00:02] [PASSED] SECAM
[14:00:02] [PASSED] MONO_525
[14:00:02] [PASSED] MONO_625
[14:00:02] =========== [PASSED] drm_test_cmdline_tv_options ===========
[14:00:02] =============== [PASSED] drm_cmdline_parser ================
[14:00:02] ========== drmm_connector_hdmi_init (20 subtests) ==========
[14:00:02] [PASSED] drm_test_connector_hdmi_init_valid
[14:00:02] [PASSED] drm_test_connector_hdmi_init_bpc_8
[14:00:02] [PASSED] drm_test_connector_hdmi_init_bpc_10
[14:00:02] [PASSED] drm_test_connector_hdmi_init_bpc_12
[14:00:02] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[14:00:02] [PASSED] drm_test_connector_hdmi_init_bpc_null
[14:00:02] [PASSED] drm_test_connector_hdmi_init_formats_empty
[14:00:02] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[14:00:02] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[14:00:02] [PASSED] supported_formats=0x9 yuv420_allowed=1
[14:00:02] [PASSED] supported_formats=0x9 yuv420_allowed=0
[14:00:02] [PASSED] supported_formats=0x5 yuv420_allowed=1
[14:00:02] [PASSED] supported_formats=0x5 yuv420_allowed=0
[14:00:02] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[14:00:02] [PASSED] drm_test_connector_hdmi_init_null_ddc
[14:00:02] [PASSED] drm_test_connector_hdmi_init_null_product
[14:00:02] [PASSED] drm_test_connector_hdmi_init_null_vendor
[14:00:02] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[14:00:02] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[14:00:02] [PASSED] drm_test_connector_hdmi_init_product_valid
[14:00:02] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[14:00:02] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[14:00:02] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[14:00:02] ========= drm_test_connector_hdmi_init_type_valid  =========
[14:00:02] [PASSED] HDMI-A
[14:00:02] [PASSED] HDMI-B
[14:00:02] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[14:00:02] ======== drm_test_connector_hdmi_init_type_invalid  ========
[14:00:02] [PASSED] Unknown
[14:00:02] [PASSED] VGA
[14:00:02] [PASSED] DVI-I
[14:00:02] [PASSED] DVI-D
[14:00:02] [PASSED] DVI-A
[14:00:02] [PASSED] Composite
[14:00:02] [PASSED] SVIDEO
[14:00:02] [PASSED] LVDS
[14:00:02] [PASSED] Component
[14:00:02] [PASSED] DIN
[14:00:02] [PASSED] DP
[14:00:02] [PASSED] TV
[14:00:02] [PASSED] eDP
[14:00:02] [PASSED] Virtual
[14:00:02] [PASSED] DSI
[14:00:02] [PASSED] DPI
[14:00:02] [PASSED] Writeback
[14:00:02] [PASSED] SPI
[14:00:02] [PASSED] USB
[14:00:02] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[14:00:02] ============ [PASSED] drmm_connector_hdmi_init =============
[14:00:02] ============= drmm_connector_init (3 subtests) =============
[14:00:02] [PASSED] drm_test_drmm_connector_init
[14:00:02] [PASSED] drm_test_drmm_connector_init_null_ddc
[14:00:02] ========= drm_test_drmm_connector_init_type_valid  =========
[14:00:02] [PASSED] Unknown
[14:00:02] [PASSED] VGA
[14:00:02] [PASSED] DVI-I
[14:00:02] [PASSED] DVI-D
[14:00:02] [PASSED] DVI-A
[14:00:02] [PASSED] Composite
[14:00:02] [PASSED] SVIDEO
[14:00:02] [PASSED] LVDS
[14:00:02] [PASSED] Component
[14:00:02] [PASSED] DIN
[14:00:02] [PASSED] DP
[14:00:02] [PASSED] HDMI-A
[14:00:02] [PASSED] HDMI-B
[14:00:02] [PASSED] TV
[14:00:02] [PASSED] eDP
[14:00:02] [PASSED] Virtual
[14:00:02] [PASSED] DSI
[14:00:02] [PASSED] DPI
[14:00:02] [PASSED] Writeback
[14:00:02] [PASSED] SPI
[14:00:02] [PASSED] USB
[14:00:02] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[14:00:02] =============== [PASSED] drmm_connector_init ===============
[14:00:02] ========= drm_connector_dynamic_init (6 subtests) ==========
[14:00:02] [PASSED] drm_test_drm_connector_dynamic_init
[14:00:02] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[14:00:02] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[14:00:02] [PASSED] drm_test_drm_connector_dynamic_init_properties
[14:00:02] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[14:00:02] [PASSED] Unknown
[14:00:02] [PASSED] VGA
[14:00:02] [PASSED] DVI-I
[14:00:02] [PASSED] DVI-D
[14:00:02] [PASSED] DVI-A
[14:00:02] [PASSED] Composite
[14:00:02] [PASSED] SVIDEO
[14:00:02] [PASSED] LVDS
[14:00:02] [PASSED] Component
[14:00:02] [PASSED] DIN
[14:00:02] [PASSED] DP
[14:00:02] [PASSED] HDMI-A
[14:00:02] [PASSED] HDMI-B
[14:00:02] [PASSED] TV
[14:00:02] [PASSED] eDP
[14:00:02] [PASSED] Virtual
[14:00:02] [PASSED] DSI
[14:00:02] [PASSED] DPI
[14:00:02] [PASSED] Writeback
[14:00:02] [PASSED] SPI
[14:00:02] [PASSED] USB
[14:00:02] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[14:00:02] ======== drm_test_drm_connector_dynamic_init_name  =========
[14:00:02] [PASSED] Unknown
[14:00:02] [PASSED] VGA
[14:00:02] [PASSED] DVI-I
[14:00:02] [PASSED] DVI-D
[14:00:02] [PASSED] DVI-A
[14:00:02] [PASSED] Composite
[14:00:02] [PASSED] SVIDEO
[14:00:02] [PASSED] LVDS
[14:00:02] [PASSED] Component
[14:00:02] [PASSED] DIN
[14:00:02] [PASSED] DP
[14:00:02] [PASSED] HDMI-A
[14:00:02] [PASSED] HDMI-B
[14:00:02] [PASSED] TV
[14:00:02] [PASSED] eDP
[14:00:02] [PASSED] Virtual
[14:00:02] [PASSED] DSI
[14:00:02] [PASSED] DPI
[14:00:02] [PASSED] Writeback
[14:00:02] [PASSED] SPI
[14:00:02] [PASSED] USB
[14:00:02] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[14:00:02] =========== [PASSED] drm_connector_dynamic_init ============
[14:00:02] ==== drm_connector_dynamic_register_early (4 subtests) =====
[14:00:02] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[14:00:02] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[14:00:02] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[14:00:02] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[14:00:02] ====== [PASSED] drm_connector_dynamic_register_early =======
[14:00:02] ======= drm_connector_dynamic_register (7 subtests) ========
[14:00:02] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[14:00:02] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[14:00:02] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[14:00:02] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[14:00:02] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[14:00:02] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[14:00:02] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[14:00:02] ========= [PASSED] drm_connector_dynamic_register ==========
[14:00:02] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[14:00:02] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[14:00:02] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[14:00:02] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[14:00:02] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[14:00:02] ========== drm_test_get_tv_mode_from_name_valid  ===========
[14:00:02] [PASSED] NTSC
[14:00:02] [PASSED] NTSC-443
[14:00:02] [PASSED] NTSC-J
[14:00:02] [PASSED] PAL
[14:00:02] [PASSED] PAL-M
[14:00:02] [PASSED] PAL-N
[14:00:02] [PASSED] SECAM
[14:00:02] [PASSED] Mono
[14:00:02] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[14:00:02] [PASSED] drm_test_get_tv_mode_from_name_truncated
[14:00:02] ============ [PASSED] drm_get_tv_mode_from_name ============
[14:00:02] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[14:00:02] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[14:00:02] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[14:00:02] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[14:00:02] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[14:00:02] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[14:00:02] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[14:00:02] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[14:00:02] [PASSED] VIC 96
[14:00:02] [PASSED] VIC 97
[14:00:02] [PASSED] VIC 101
[14:00:02] [PASSED] VIC 102
[14:00:02] [PASSED] VIC 106
[14:00:02] [PASSED] VIC 107
[14:00:02] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[14:00:02] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[14:00:02] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[14:00:02] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[14:00:02] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[14:00:02] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[14:00:02] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[14:00:02] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[14:00:02] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[14:00:02] [PASSED] Automatic
[14:00:02] [PASSED] Full
[14:00:02] [PASSED] Limited 16:235
[14:00:02] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[14:00:02] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[14:00:02] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[14:00:02] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[14:00:02] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[14:00:02] [PASSED] RGB
[14:00:02] [PASSED] YUV 4:2:0
[14:00:02] [PASSED] YUV 4:2:2
[14:00:02] [PASSED] YUV 4:4:4
[14:00:02] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[14:00:02] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[14:00:02] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[14:00:02] ============= drm_damage_helper (21 subtests) ==============
[14:00:02] [PASSED] drm_test_damage_iter_no_damage
[14:00:02] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[14:00:02] [PASSED] drm_test_damage_iter_no_damage_src_moved
[14:00:02] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[14:00:02] [PASSED] drm_test_damage_iter_no_damage_not_visible
[14:00:02] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[14:00:02] [PASSED] drm_test_damage_iter_no_damage_no_fb
[14:00:02] [PASSED] drm_test_damage_iter_simple_damage
[14:00:02] [PASSED] drm_test_damage_iter_single_damage
[14:00:02] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[14:00:02] [PASSED] drm_test_damage_iter_single_damage_outside_src
[14:00:02] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[14:00:02] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[14:00:02] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[14:00:02] [PASSED] drm_test_damage_iter_single_damage_src_moved
[14:00:02] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[14:00:02] [PASSED] drm_test_damage_iter_damage
[14:00:02] [PASSED] drm_test_damage_iter_damage_one_intersect
[14:00:02] [PASSED] drm_test_damage_iter_damage_one_outside
[14:00:02] [PASSED] drm_test_damage_iter_damage_src_moved
[14:00:02] [PASSED] drm_test_damage_iter_damage_not_visible
[14:00:02] ================ [PASSED] drm_damage_helper ================
[14:00:02] ============== drm_dp_mst_helper (3 subtests) ==============
[14:00:02] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[14:00:02] [PASSED] Clock 154000 BPP 30 DSC disabled
[14:00:02] [PASSED] Clock 234000 BPP 30 DSC disabled
[14:00:02] [PASSED] Clock 297000 BPP 24 DSC disabled
[14:00:02] [PASSED] Clock 332880 BPP 24 DSC enabled
[14:00:02] [PASSED] Clock 324540 BPP 24 DSC enabled
[14:00:02] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[14:00:02] ============== drm_test_dp_mst_calc_pbn_div  ===============
[14:00:02] [PASSED] Link rate 2000000 lane count 4
[14:00:02] [PASSED] Link rate 2000000 lane count 2
[14:00:02] [PASSED] Link rate 2000000 lane count 1
[14:00:02] [PASSED] Link rate 1350000 lane count 4
[14:00:02] [PASSED] Link rate 1350000 lane count 2
[14:00:02] [PASSED] Link rate 1350000 lane count 1
[14:00:02] [PASSED] Link rate 1000000 lane count 4
[14:00:02] [PASSED] Link rate 1000000 lane count 2
[14:00:02] [PASSED] Link rate 1000000 lane count 1
[14:00:02] [PASSED] Link rate 810000 lane count 4
[14:00:02] [PASSED] Link rate 810000 lane count 2
[14:00:02] [PASSED] Link rate 810000 lane count 1
[14:00:02] [PASSED] Link rate 540000 lane count 4
[14:00:02] [PASSED] Link rate 540000 lane count 2
[14:00:02] [PASSED] Link rate 540000 lane count 1
[14:00:02] [PASSED] Link rate 270000 lane count 4
[14:00:02] [PASSED] Link rate 270000 lane count 2
[14:00:02] [PASSED] Link rate 270000 lane count 1
[14:00:02] [PASSED] Link rate 162000 lane count 4
[14:00:02] [PASSED] Link rate 162000 lane count 2
[14:00:02] [PASSED] Link rate 162000 lane count 1
[14:00:02] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[14:00:02] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[14:00:02] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[14:00:02] [PASSED] DP_POWER_UP_PHY with port number
[14:00:02] [PASSED] DP_POWER_DOWN_PHY with port number
[14:00:02] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[14:00:02] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[14:00:02] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[14:00:02] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[14:00:02] [PASSED] DP_QUERY_PAYLOAD with port number
[14:00:02] [PASSED] DP_QUERY_PAYLOAD with VCPI
[14:00:02] [PASSED] DP_REMOTE_DPCD_READ with port number
[14:00:02] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[14:00:02] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[14:00:02] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[14:00:02] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[14:00:02] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[14:00:02] [PASSED] DP_REMOTE_I2C_READ with port number
[14:00:02] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[14:00:02] [PASSED] DP_REMOTE_I2C_READ with transactions array
[14:00:02] [PASSED] DP_REMOTE_I2C_WRITE with port number
[14:00:02] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[14:00:02] [PASSED] DP_REMOTE_I2C_WRITE with data array
[14:00:02] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[14:00:02] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[14:00:02] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[14:00:02] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[14:00:02] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[14:00:02] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[14:00:02] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[14:00:02] ================ [PASSED] drm_dp_mst_helper ================
[14:00:02] ================== drm_exec (7 subtests) ===================
[14:00:02] [PASSED] sanitycheck
[14:00:02] [PASSED] test_lock
[14:00:02] [PASSED] test_lock_unlock
[14:00:02] [PASSED] test_duplicates
[14:00:02] [PASSED] test_prepare
[14:00:02] [PASSED] test_prepare_array
[14:00:02] [PASSED] test_multiple_loops
[14:00:02] ==================== [PASSED] drm_exec =====================
[14:00:02] =========== drm_format_helper_test (17 subtests) ===========
[14:00:02] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[14:00:02] [PASSED] single_pixel_source_buffer
[14:00:02] [PASSED] single_pixel_clip_rectangle
[14:00:02] [PASSED] well_known_colors
[14:00:02] [PASSED] destination_pitch
[14:00:02] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[14:00:02] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[14:00:02] [PASSED] single_pixel_source_buffer
[14:00:02] [PASSED] single_pixel_clip_rectangle
[14:00:02] [PASSED] well_known_colors
[14:00:02] [PASSED] destination_pitch
[14:00:02] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[14:00:02] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[14:00:02] [PASSED] single_pixel_source_buffer
[14:00:02] [PASSED] single_pixel_clip_rectangle
[14:00:02] [PASSED] well_known_colors
[14:00:02] [PASSED] destination_pitch
[14:00:02] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[14:00:02] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[14:00:02] [PASSED] single_pixel_source_buffer
[14:00:02] [PASSED] single_pixel_clip_rectangle
[14:00:02] [PASSED] well_known_colors
[14:00:02] [PASSED] destination_pitch
[14:00:02] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[14:00:02] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[14:00:02] [PASSED] single_pixel_source_buffer
[14:00:02] [PASSED] single_pixel_clip_rectangle
[14:00:02] [PASSED] well_known_colors
[14:00:02] [PASSED] destination_pitch
[14:00:02] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[14:00:02] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[14:00:02] [PASSED] single_pixel_source_buffer
[14:00:02] [PASSED] single_pixel_clip_rectangle
[14:00:02] [PASSED] well_known_colors
[14:00:02] [PASSED] destination_pitch
[14:00:02] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[14:00:02] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[14:00:02] [PASSED] single_pixel_source_buffer
[14:00:02] [PASSED] single_pixel_clip_rectangle
[14:00:02] [PASSED] well_known_colors
[14:00:02] [PASSED] destination_pitch
[14:00:02] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[14:00:02] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[14:00:02] [PASSED] single_pixel_source_buffer
[14:00:02] [PASSED] single_pixel_clip_rectangle
[14:00:02] [PASSED] well_known_colors
[14:00:02] [PASSED] destination_pitch
[14:00:02] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[14:00:02] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[14:00:02] [PASSED] single_pixel_source_buffer
[14:00:02] [PASSED] single_pixel_clip_rectangle
[14:00:02] [PASSED] well_known_colors
[14:00:02] [PASSED] destination_pitch
[14:00:02] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[14:00:02] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[14:00:02] [PASSED] single_pixel_source_buffer
[14:00:02] [PASSED] single_pixel_clip_rectangle
[14:00:02] [PASSED] well_known_colors
[14:00:02] [PASSED] destination_pitch
[14:00:02] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[14:00:02] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[14:00:02] [PASSED] single_pixel_source_buffer
[14:00:02] [PASSED] single_pixel_clip_rectangle
[14:00:02] [PASSED] well_known_colors
[14:00:02] [PASSED] destination_pitch
[14:00:02] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[14:00:02] ============== drm_test_fb_xrgb8888_to_mono  ===============
[14:00:02] [PASSED] single_pixel_source_buffer
[14:00:02] [PASSED] single_pixel_clip_rectangle
[14:00:02] [PASSED] well_known_colors
[14:00:02] [PASSED] destination_pitch
[14:00:02] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[14:00:02] ==================== drm_test_fb_swab  =====================
[14:00:02] [PASSED] single_pixel_source_buffer
[14:00:02] [PASSED] single_pixel_clip_rectangle
[14:00:02] [PASSED] well_known_colors
[14:00:02] [PASSED] destination_pitch
[14:00:02] ================ [PASSED] drm_test_fb_swab =================
[14:00:02] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[14:00:02] [PASSED] single_pixel_source_buffer
[14:00:02] [PASSED] single_pixel_clip_rectangle
[14:00:02] [PASSED] well_known_colors
[14:00:02] [PASSED] destination_pitch
[14:00:02] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[14:00:02] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[14:00:02] [PASSED] single_pixel_source_buffer
[14:00:02] [PASSED] single_pixel_clip_rectangle
[14:00:02] [PASSED] well_known_colors
[14:00:02] [PASSED] destination_pitch
[14:00:02] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[14:00:02] ================= drm_test_fb_clip_offset  =================
[14:00:02] [PASSED] pass through
[14:00:02] [PASSED] horizontal offset
[14:00:02] [PASSED] vertical offset
[14:00:02] [PASSED] horizontal and vertical offset
[14:00:02] [PASSED] horizontal offset (custom pitch)
[14:00:02] [PASSED] vertical offset (custom pitch)
[14:00:02] [PASSED] horizontal and vertical offset (custom pitch)
[14:00:02] ============= [PASSED] drm_test_fb_clip_offset =============
[14:00:02] =================== drm_test_fb_memcpy  ====================
[14:00:02] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[14:00:02] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[14:00:02] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[14:00:02] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[14:00:02] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[14:00:02] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[14:00:02] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[14:00:02] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[14:00:02] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[14:00:02] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[14:00:02] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[14:00:02] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[14:00:02] =============== [PASSED] drm_test_fb_memcpy ================
[14:00:02] ============= [PASSED] drm_format_helper_test ==============
[14:00:02] ================= drm_format (18 subtests) =================
[14:00:02] [PASSED] drm_test_format_block_width_invalid
[14:00:02] [PASSED] drm_test_format_block_width_one_plane
[14:00:02] [PASSED] drm_test_format_block_width_two_plane
[14:00:02] [PASSED] drm_test_format_block_width_three_plane
[14:00:02] [PASSED] drm_test_format_block_width_tiled
[14:00:02] [PASSED] drm_test_format_block_height_invalid
[14:00:02] [PASSED] drm_test_format_block_height_one_plane
[14:00:02] [PASSED] drm_test_format_block_height_two_plane
[14:00:02] [PASSED] drm_test_format_block_height_three_plane
[14:00:02] [PASSED] drm_test_format_block_height_tiled
[14:00:02] [PASSED] drm_test_format_min_pitch_invalid
[14:00:02] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[14:00:02] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[14:00:02] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[14:00:02] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[14:00:02] [PASSED] drm_test_format_min_pitch_two_plane
[14:00:02] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[14:00:02] [PASSED] drm_test_format_min_pitch_tiled
[14:00:02] =================== [PASSED] drm_format ====================
[14:00:02] ============== drm_framebuffer (10 subtests) ===============
[14:00:02] ========== drm_test_framebuffer_check_src_coords  ==========
[14:00:02] [PASSED] Success: source fits into fb
[14:00:02] [PASSED] Fail: overflowing fb with x-axis coordinate
[14:00:02] [PASSED] Fail: overflowing fb with y-axis coordinate
[14:00:02] [PASSED] Fail: overflowing fb with source width
[14:00:02] [PASSED] Fail: overflowing fb with source height
[14:00:02] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[14:00:02] [PASSED] drm_test_framebuffer_cleanup
[14:00:02] =============== drm_test_framebuffer_create  ===============
[14:00:02] [PASSED] ABGR8888 normal sizes
[14:00:02] [PASSED] ABGR8888 max sizes
[14:00:02] [PASSED] ABGR8888 pitch greater than min required
[14:00:02] [PASSED] ABGR8888 pitch less than min required
[14:00:02] [PASSED] ABGR8888 Invalid width
[14:00:02] [PASSED] ABGR8888 Invalid buffer handle
[14:00:02] [PASSED] No pixel format
[14:00:02] [PASSED] ABGR8888 Width 0
[14:00:02] [PASSED] ABGR8888 Height 0
[14:00:02] [PASSED] ABGR8888 Out of bound height * pitch combination
[14:00:02] [PASSED] ABGR8888 Large buffer offset
[14:00:02] [PASSED] ABGR8888 Buffer offset for inexistent plane
[14:00:02] [PASSED] ABGR8888 Invalid flag
[14:00:02] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[14:00:02] [PASSED] ABGR8888 Valid buffer modifier
[14:00:02] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[14:00:02] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[14:00:02] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[14:00:02] [PASSED] NV12 Normal sizes
[14:00:02] [PASSED] NV12 Max sizes
[14:00:02] [PASSED] NV12 Invalid pitch
[14:00:02] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[14:00:02] [PASSED] NV12 different  modifier per-plane
[14:00:02] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[14:00:02] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[14:00:02] [PASSED] NV12 Modifier for inexistent plane
[14:00:02] [PASSED] NV12 Handle for inexistent plane
[14:00:02] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[14:00:02] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[14:00:02] [PASSED] YVU420 Normal sizes
[14:00:02] [PASSED] YVU420 Max sizes
[14:00:02] [PASSED] YVU420 Invalid pitch
[14:00:02] [PASSED] YVU420 Different pitches
[14:00:02] [PASSED] YVU420 Different buffer offsets/pitches
[14:00:02] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[14:00:02] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[14:00:02] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[14:00:02] [PASSED] YVU420 Valid modifier
[14:00:02] [PASSED] YVU420 Different modifiers per plane
[14:00:02] [PASSED] YVU420 Modifier for inexistent plane
[14:00:02] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[14:00:02] [PASSED] X0L2 Normal sizes
[14:00:02] [PASSED] X0L2 Max sizes
[14:00:02] [PASSED] X0L2 Invalid pitch
[14:00:02] [PASSED] X0L2 Pitch greater than minimum required
[14:00:02] [PASSED] X0L2 Handle for inexistent plane
[14:00:02] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[14:00:02] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[14:00:02] [PASSED] X0L2 Valid modifier
[14:00:02] [PASSED] X0L2 Modifier for inexistent plane
[14:00:02] =========== [PASSED] drm_test_framebuffer_create ===========
[14:00:02] [PASSED] drm_test_framebuffer_free
[14:00:02] [PASSED] drm_test_framebuffer_init
[14:00:02] [PASSED] drm_test_framebuffer_init_bad_format
[14:00:02] [PASSED] drm_test_framebuffer_init_dev_mismatch
[14:00:02] [PASSED] drm_test_framebuffer_lookup
[14:00:02] [PASSED] drm_test_framebuffer_lookup_inexistent
[14:00:02] [PASSED] drm_test_framebuffer_modifiers_not_supported
[14:00:02] ================= [PASSED] drm_framebuffer =================
[14:00:02] ================ drm_gem_shmem (8 subtests) ================
[14:00:02] [PASSED] drm_gem_shmem_test_obj_create
[14:00:02] [PASSED] drm_gem_shmem_test_obj_create_private
[14:00:02] [PASSED] drm_gem_shmem_test_pin_pages
[14:00:02] [PASSED] drm_gem_shmem_test_vmap
[14:00:02] [PASSED] drm_gem_shmem_test_get_sg_table
[14:00:02] [PASSED] drm_gem_shmem_test_get_pages_sgt
[14:00:02] [PASSED] drm_gem_shmem_test_madvise
[14:00:02] [PASSED] drm_gem_shmem_test_purge
[14:00:02] ================== [PASSED] drm_gem_shmem ==================
[14:00:02] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[14:00:02] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[14:00:02] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[14:00:02] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[14:00:02] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[14:00:02] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[14:00:02] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[14:00:02] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[14:00:02] [PASSED] Automatic
[14:00:02] [PASSED] Full
[14:00:02] [PASSED] Limited 16:235
[14:00:02] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[14:00:02] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[14:00:02] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[14:00:02] [PASSED] drm_test_check_disable_connector
[14:00:02] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[14:00:02] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[14:00:02] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[14:00:02] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[14:00:02] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[14:00:02] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[14:00:02] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[14:00:02] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[14:00:02] [PASSED] drm_test_check_output_bpc_dvi
[14:00:02] [PASSED] drm_test_check_output_bpc_format_vic_1
[14:00:02] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[14:00:02] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[14:00:02] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[14:00:02] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[14:00:02] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[14:00:02] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[14:00:02] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[14:00:02] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[14:00:02] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[14:00:02] [PASSED] drm_test_check_broadcast_rgb_value
[14:00:02] [PASSED] drm_test_check_bpc_8_value
[14:00:02] [PASSED] drm_test_check_bpc_10_value
[14:00:02] [PASSED] drm_test_check_bpc_12_value
[14:00:02] [PASSED] drm_test_check_format_value
[14:00:02] [PASSED] drm_test_check_tmds_char_value
[14:00:02] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[14:00:02] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[14:00:02] [PASSED] drm_test_check_mode_valid
[14:00:02] [PASSED] drm_test_check_mode_valid_reject
[14:00:02] [PASSED] drm_test_check_mode_valid_reject_rate
[14:00:02] [PASSED] drm_test_check_mode_valid_reject_max_clock
[14:00:02] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[14:00:02] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[14:00:02] [PASSED] drm_test_check_infoframes
[14:00:02] [PASSED] drm_test_check_reject_avi_infoframe
[14:00:02] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[14:00:02] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[14:00:02] [PASSED] drm_test_check_reject_audio_infoframe
[14:00:02] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[14:00:02] ================= drm_managed (2 subtests) =================
[14:00:02] [PASSED] drm_test_managed_release_action
[14:00:02] [PASSED] drm_test_managed_run_action
[14:00:02] =================== [PASSED] drm_managed ===================
[14:00:02] =================== drm_mm (6 subtests) ====================
[14:00:02] [PASSED] drm_test_mm_init
[14:00:02] [PASSED] drm_test_mm_debug
[14:00:02] [PASSED] drm_test_mm_align32
[14:00:02] [PASSED] drm_test_mm_align64
[14:00:02] [PASSED] drm_test_mm_lowest
[14:00:02] [PASSED] drm_test_mm_highest
[14:00:02] ===================== [PASSED] drm_mm ======================
[14:00:02] ============= drm_modes_analog_tv (5 subtests) =============
[14:00:02] [PASSED] drm_test_modes_analog_tv_mono_576i
[14:00:02] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[14:00:02] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[14:00:02] [PASSED] drm_test_modes_analog_tv_pal_576i
[14:00:02] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[14:00:02] =============== [PASSED] drm_modes_analog_tv ===============
[14:00:02] ============== drm_plane_helper (2 subtests) ===============
[14:00:02] =============== drm_test_check_plane_state  ================
[14:00:02] [PASSED] clipping_simple
[14:00:02] [PASSED] clipping_rotate_reflect
[14:00:02] [PASSED] positioning_simple
[14:00:02] [PASSED] upscaling
[14:00:02] [PASSED] downscaling
[14:00:02] [PASSED] rounding1
[14:00:02] [PASSED] rounding2
[14:00:02] [PASSED] rounding3
[14:00:02] [PASSED] rounding4
[14:00:02] =========== [PASSED] drm_test_check_plane_state ============
[14:00:02] =========== drm_test_check_invalid_plane_state  ============
[14:00:02] [PASSED] positioning_invalid
[14:00:02] [PASSED] upscaling_invalid
[14:00:02] [PASSED] downscaling_invalid
[14:00:02] ======= [PASSED] drm_test_check_invalid_plane_state ========
[14:00:02] ================ [PASSED] drm_plane_helper =================
[14:00:02] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[14:00:02] ====== drm_test_connector_helper_tv_get_modes_check  =======
[14:00:02] [PASSED] None
[14:00:02] [PASSED] PAL
[14:00:02] [PASSED] NTSC
[14:00:02] [PASSED] Both, NTSC Default
[14:00:02] [PASSED] Both, PAL Default
[14:00:02] [PASSED] Both, NTSC Default, with PAL on command-line
[14:00:02] [PASSED] Both, PAL Default, with NTSC on command-line
[14:00:02] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[14:00:02] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[14:00:02] ================== drm_rect (9 subtests) ===================
[14:00:02] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[14:00:02] [PASSED] drm_test_rect_clip_scaled_not_clipped
[14:00:02] [PASSED] drm_test_rect_clip_scaled_clipped
[14:00:02] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[14:00:02] ================= drm_test_rect_intersect  =================
[14:00:02] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[14:00:02] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[14:00:02] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[14:00:02] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[14:00:02] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[14:00:02] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[14:00:02] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[14:00:02] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[14:00:02] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[14:00:02] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[14:00:02] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[14:00:02] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[14:00:02] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[14:00:02] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[14:00:02] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[14:00:02] ============= [PASSED] drm_test_rect_intersect =============
[14:00:02] ================ drm_test_rect_calc_hscale  ================
[14:00:02] [PASSED] normal use
[14:00:02] [PASSED] out of max range
[14:00:02] [PASSED] out of min range
[14:00:02] [PASSED] zero dst
[14:00:02] [PASSED] negative src
[14:00:02] [PASSED] negative dst
[14:00:02] ============ [PASSED] drm_test_rect_calc_hscale ============
[14:00:02] ================ drm_test_rect_calc_vscale  ================
[14:00:02] [PASSED] normal use
[14:00:02] [PASSED] out of max range
[14:00:02] [PASSED] out of min range
[14:00:02] [PASSED] zero dst
[14:00:02] [PASSED] negative src
[14:00:02] [PASSED] negative dst
stty: 'standard input': Inappropriate ioctl for device
[14:00:02] ============ [PASSED] drm_test_rect_calc_vscale ============
[14:00:02] ================== drm_test_rect_rotate  ===================
[14:00:02] [PASSED] reflect-x
[14:00:02] [PASSED] reflect-y
[14:00:02] [PASSED] rotate-0
[14:00:02] [PASSED] rotate-90
[14:00:02] [PASSED] rotate-180
[14:00:02] [PASSED] rotate-270
[14:00:02] ============== [PASSED] drm_test_rect_rotate ===============
[14:00:02] ================ drm_test_rect_rotate_inv  =================
[14:00:02] [PASSED] reflect-x
[14:00:02] [PASSED] reflect-y
[14:00:02] [PASSED] rotate-0
[14:00:02] [PASSED] rotate-90
[14:00:02] [PASSED] rotate-180
[14:00:02] [PASSED] rotate-270
[14:00:02] ============ [PASSED] drm_test_rect_rotate_inv =============
[14:00:02] ==================== [PASSED] drm_rect =====================
[14:00:02] ============ drm_sysfb_modeset_test (1 subtest) ============
[14:00:02] ============ drm_test_sysfb_build_fourcc_list  =============
[14:00:02] [PASSED] no native formats
[14:00:02] [PASSED] XRGB8888 as native format
[14:00:02] [PASSED] remove duplicates
[14:00:02] [PASSED] convert alpha formats
[14:00:02] [PASSED] random formats
[14:00:02] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[14:00:02] ============= [PASSED] drm_sysfb_modeset_test ==============
[14:00:02] ================== drm_fixp (2 subtests) ===================
[14:00:02] [PASSED] drm_test_int2fixp
[14:00:02] [PASSED] drm_test_sm2fixp
[14:00:02] ==================== [PASSED] drm_fixp =====================
[14:00:02] ============================================================
[14:00:02] Testing complete. Ran 621 tests: passed: 621
[14:00:02] Elapsed time: 27.154s total, 1.804s configuring, 25.183s building, 0.120s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[14:00:02] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[14:00:04] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[14:00:13] Starting KUnit Kernel (1/1)...
[14:00:13] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[14:00:13] ================= ttm_device (5 subtests) ==================
[14:00:13] [PASSED] ttm_device_init_basic
[14:00:13] [PASSED] ttm_device_init_multiple
[14:00:13] [PASSED] ttm_device_fini_basic
[14:00:13] [PASSED] ttm_device_init_no_vma_man
[14:00:13] ================== ttm_device_init_pools  ==================
[14:00:13] [PASSED] No DMA allocations, no DMA32 required
[14:00:13] [PASSED] DMA allocations, DMA32 required
[14:00:13] [PASSED] No DMA allocations, DMA32 required
[14:00:13] [PASSED] DMA allocations, no DMA32 required
[14:00:13] ============== [PASSED] ttm_device_init_pools ==============
[14:00:13] =================== [PASSED] ttm_device ====================
[14:00:13] ================== ttm_pool (8 subtests) ===================
[14:00:13] ================== ttm_pool_alloc_basic  ===================
[14:00:13] [PASSED] One page
[14:00:13] [PASSED] More than one page
[14:00:13] [PASSED] Above the allocation limit
[14:00:13] [PASSED] One page, with coherent DMA mappings enabled
[14:00:13] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[14:00:13] ============== [PASSED] ttm_pool_alloc_basic ===============
[14:00:13] ============== ttm_pool_alloc_basic_dma_addr  ==============
[14:00:13] [PASSED] One page
[14:00:13] [PASSED] More than one page
[14:00:13] [PASSED] Above the allocation limit
[14:00:13] [PASSED] One page, with coherent DMA mappings enabled
[14:00:13] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[14:00:13] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[14:00:13] [PASSED] ttm_pool_alloc_order_caching_match
[14:00:13] [PASSED] ttm_pool_alloc_caching_mismatch
[14:00:13] [PASSED] ttm_pool_alloc_order_mismatch
[14:00:13] [PASSED] ttm_pool_free_dma_alloc
[14:00:13] [PASSED] ttm_pool_free_no_dma_alloc
[14:00:13] [PASSED] ttm_pool_fini_basic
[14:00:13] ==================== [PASSED] ttm_pool =====================
[14:00:13] ================ ttm_resource (8 subtests) =================
[14:00:13] ================= ttm_resource_init_basic  =================
[14:00:13] [PASSED] Init resource in TTM_PL_SYSTEM
[14:00:13] [PASSED] Init resource in TTM_PL_VRAM
[14:00:13] [PASSED] Init resource in a private placement
[14:00:13] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[14:00:13] ============= [PASSED] ttm_resource_init_basic =============
[14:00:13] [PASSED] ttm_resource_init_pinned
[14:00:13] [PASSED] ttm_resource_fini_basic
[14:00:13] [PASSED] ttm_resource_manager_init_basic
[14:00:13] [PASSED] ttm_resource_manager_usage_basic
[14:00:13] [PASSED] ttm_resource_manager_set_used_basic
[14:00:13] [PASSED] ttm_sys_man_alloc_basic
[14:00:13] [PASSED] ttm_sys_man_free_basic
[14:00:13] ================== [PASSED] ttm_resource ===================
[14:00:13] =================== ttm_tt (15 subtests) ===================
[14:00:13] ==================== ttm_tt_init_basic  ====================
[14:00:13] [PASSED] Page-aligned size
[14:00:13] [PASSED] Extra pages requested
[14:00:13] ================ [PASSED] ttm_tt_init_basic ================
[14:00:13] [PASSED] ttm_tt_init_misaligned
[14:00:13] [PASSED] ttm_tt_fini_basic
[14:00:13] [PASSED] ttm_tt_fini_sg
[14:00:13] [PASSED] ttm_tt_fini_shmem
[14:00:13] [PASSED] ttm_tt_create_basic
[14:00:13] [PASSED] ttm_tt_create_invalid_bo_type
[14:00:13] [PASSED] ttm_tt_create_ttm_exists
[14:00:13] [PASSED] ttm_tt_create_failed
[14:00:13] [PASSED] ttm_tt_destroy_basic
[14:00:13] [PASSED] ttm_tt_populate_null_ttm
[14:00:13] [PASSED] ttm_tt_populate_populated_ttm
[14:00:13] [PASSED] ttm_tt_unpopulate_basic
[14:00:13] [PASSED] ttm_tt_unpopulate_empty_ttm
[14:00:13] [PASSED] ttm_tt_swapin_basic
[14:00:13] ===================== [PASSED] ttm_tt ======================
[14:00:13] =================== ttm_bo (14 subtests) ===================
[14:00:13] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[14:00:13] [PASSED] Cannot be interrupted and sleeps
[14:00:13] [PASSED] Cannot be interrupted, locks straight away
[14:00:13] [PASSED] Can be interrupted, sleeps
[14:00:13] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[14:00:13] [PASSED] ttm_bo_reserve_locked_no_sleep
[14:00:13] [PASSED] ttm_bo_reserve_no_wait_ticket
[14:00:13] [PASSED] ttm_bo_reserve_double_resv
[14:00:13] [PASSED] ttm_bo_reserve_interrupted
[14:00:13] [PASSED] ttm_bo_reserve_deadlock
[14:00:13] [PASSED] ttm_bo_unreserve_basic
[14:00:13] [PASSED] ttm_bo_unreserve_pinned
[14:00:13] [PASSED] ttm_bo_unreserve_bulk
[14:00:13] [PASSED] ttm_bo_fini_basic
[14:00:13] [PASSED] ttm_bo_fini_shared_resv
[14:00:13] [PASSED] ttm_bo_pin_basic
[14:00:13] [PASSED] ttm_bo_pin_unpin_resource
[14:00:13] [PASSED] ttm_bo_multiple_pin_one_unpin
[14:00:13] ===================== [PASSED] ttm_bo ======================
[14:00:13] ============== ttm_bo_validate (22 subtests) ===============
[14:00:13] ============== ttm_bo_init_reserved_sys_man  ===============
[14:00:13] [PASSED] Buffer object for userspace
[14:00:13] [PASSED] Kernel buffer object
[14:00:13] [PASSED] Shared buffer object
[14:00:13] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[14:00:13] ============== ttm_bo_init_reserved_mock_man  ==============
[14:00:13] [PASSED] Buffer object for userspace
[14:00:13] [PASSED] Kernel buffer object
[14:00:13] [PASSED] Shared buffer object
[14:00:13] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[14:00:13] [PASSED] ttm_bo_init_reserved_resv
[14:00:13] ================== ttm_bo_validate_basic  ==================
[14:00:13] [PASSED] Buffer object for userspace
[14:00:13] [PASSED] Kernel buffer object
[14:00:13] [PASSED] Shared buffer object
[14:00:13] ============== [PASSED] ttm_bo_validate_basic ==============
[14:00:13] [PASSED] ttm_bo_validate_invalid_placement
[14:00:13] ============= ttm_bo_validate_same_placement  ==============
[14:00:13] [PASSED] System manager
[14:00:13] [PASSED] VRAM manager
[14:00:13] ========= [PASSED] ttm_bo_validate_same_placement ==========
[14:00:13] [PASSED] ttm_bo_validate_failed_alloc
[14:00:13] [PASSED] ttm_bo_validate_pinned
[14:00:13] [PASSED] ttm_bo_validate_busy_placement
[14:00:13] ================ ttm_bo_validate_multihop  =================
[14:00:13] [PASSED] Buffer object for userspace
[14:00:13] [PASSED] Kernel buffer object
[14:00:13] [PASSED] Shared buffer object
[14:00:13] ============ [PASSED] ttm_bo_validate_multihop =============
[14:00:13] ========== ttm_bo_validate_no_placement_signaled  ==========
[14:00:13] [PASSED] Buffer object in system domain, no page vector
[14:00:13] [PASSED] Buffer object in system domain with an existing page vector
[14:00:13] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[14:00:13] ======== ttm_bo_validate_no_placement_not_signaled  ========
[14:00:13] [PASSED] Buffer object for userspace
[14:00:13] [PASSED] Kernel buffer object
[14:00:13] [PASSED] Shared buffer object
[14:00:13] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[14:00:13] [PASSED] ttm_bo_validate_move_fence_signaled
[14:00:14] ========= ttm_bo_validate_move_fence_not_signaled  =========
[14:00:14] [PASSED] Waits for GPU
[14:00:14] [PASSED] Tries to lock straight away
[14:00:14] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[14:00:14] [PASSED] ttm_bo_validate_swapout
[14:00:14] [PASSED] ttm_bo_validate_happy_evict
[14:00:14] [PASSED] ttm_bo_validate_all_pinned_evict
[14:00:14] [PASSED] ttm_bo_validate_allowed_only_evict
[14:00:14] [PASSED] ttm_bo_validate_deleted_evict
[14:00:14] [PASSED] ttm_bo_validate_busy_domain_evict
[14:00:14] [PASSED] ttm_bo_validate_evict_gutting
[14:00:14] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[14:00:14] ================= [PASSED] ttm_bo_validate =================
[14:00:14] ============================================================
[14:00:14] Testing complete. Ran 102 tests: passed: 102
[14:00:14] Elapsed time: 11.346s total, 1.674s configuring, 9.456s building, 0.181s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for drm/i915/wm: Watermark/SAGV fixes/cleanups/etc

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 2199 bytes --]

== Series Details ==

Series: drm/i915/wm: Watermark/SAGV fixes/cleanups/etc
URL   : https://patchwork.freedesktop.org/series/163783/
State : success

== Summary ==

CI Bug Log - changes from xe-4771-cc83f6d4f072e6c0a7033e5391d651b0f7c9fa0f_BAT -> xe-pw-163783v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (14 -> 14)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-163783v1_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@sriov_basic@enable-vfs-autoprobe-on:
    - bat-bmg-2:          [PASS][1] -> [DMESG-WARN][2] ([Intel XE#7433]) +3 other tests dmesg-warn
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4771-cc83f6d4f072e6c0a7033e5391d651b0f7c9fa0f/bat-bmg-2/igt@sriov_basic@enable-vfs-autoprobe-on.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163783v1/bat-bmg-2/igt@sriov_basic@enable-vfs-autoprobe-on.html
    - bat-bmg-1:          [PASS][3] -> [DMESG-WARN][4] ([Intel XE#7433]) +3 other tests dmesg-warn
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4771-cc83f6d4f072e6c0a7033e5391d651b0f7c9fa0f/bat-bmg-1/igt@sriov_basic@enable-vfs-autoprobe-on.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163783v1/bat-bmg-1/igt@sriov_basic@enable-vfs-autoprobe-on.html

  * igt@xe_module_load@load:
    - bat-bmg-3:          [PASS][5] -> [DMESG-WARN][6] ([Intel XE#7433])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4771-cc83f6d4f072e6c0a7033e5391d651b0f7c9fa0f/bat-bmg-3/igt@xe_module_load@load.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163783v1/bat-bmg-3/igt@xe_module_load@load.html

  
  [Intel XE#7433]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7433


Build changes
-------------

  * Linux: xe-4771-cc83f6d4f072e6c0a7033e5391d651b0f7c9fa0f -> xe-pw-163783v1

  IGT_8822: 8822
  xe-4771-cc83f6d4f072e6c0a7033e5391d651b0f7c9fa0f: cc83f6d4f072e6c0a7033e5391d651b0f7c9fa0f
  xe-pw-163783v1: 163783v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163783v1/index.html

[-- Attachment #2: Type: text/html, Size: 2951 bytes --]

✓ Xe.CI.FULL: success for drm/i915/wm: Watermark/SAGV fixes/cleanups/etc

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 8626 bytes --]

== Series Details ==

Series: drm/i915/wm: Watermark/SAGV fixes/cleanups/etc
URL   : https://patchwork.freedesktop.org/series/163783/
State : success

== Summary ==

CI Bug Log - changes from xe-4771-cc83f6d4f072e6c0a7033e5391d651b0f7c9fa0f_FULL -> xe-pw-163783v1_FULL
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-163783v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@xe_module_load@load:
    - shard-bmg:          ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) -> ([DMESG-WARN][26], [DMESG-WARN][27], [DMESG-WARN][28], [DMESG-WARN][29], [DMESG-WARN][30], [DMESG-WARN][31], [DMESG-WARN][32], [DMESG-WARN][33], [DMESG-WARN][34], [DMESG-WARN][35], [DMESG-WARN][36], [DMESG-WARN][37], [DMESG-WARN][38], [DMESG-WARN][39], [DMESG-WARN][40], [DMESG-WARN][41], [DMESG-WARN][42], [DMESG-WARN][43], [DMESG-WARN][44], [DMESG-WARN][45], [DMESG-WARN][46], [DMESG-WARN][47], [DMESG-WARN][48], [DMESG-WARN][49], [DMESG-WARN][50]) ([Intel XE#7433])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4771-cc83f6d4f072e6c0a7033e5391d651b0f7c9fa0f/shard-bmg-7/igt@xe_module_load@load.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4771-cc83f6d4f072e6c0a7033e5391d651b0f7c9fa0f/shard-bmg-4/igt@xe_module_load@load.html
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4771-cc83f6d4f072e6c0a7033e5391d651b0f7c9fa0f/shard-bmg-2/igt@xe_module_load@load.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4771-cc83f6d4f072e6c0a7033e5391d651b0f7c9fa0f/shard-bmg-4/igt@xe_module_load@load.html
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4771-cc83f6d4f072e6c0a7033e5391d651b0f7c9fa0f/shard-bmg-5/igt@xe_module_load@load.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4771-cc83f6d4f072e6c0a7033e5391d651b0f7c9fa0f/shard-bmg-3/igt@xe_module_load@load.html
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4771-cc83f6d4f072e6c0a7033e5391d651b0f7c9fa0f/shard-bmg-9/igt@xe_module_load@load.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4771-cc83f6d4f072e6c0a7033e5391d651b0f7c9fa0f/shard-bmg-3/igt@xe_module_load@load.html
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4771-cc83f6d4f072e6c0a7033e5391d651b0f7c9fa0f/shard-bmg-8/igt@xe_module_load@load.html
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4771-cc83f6d4f072e6c0a7033e5391d651b0f7c9fa0f/shard-bmg-9/igt@xe_module_load@load.html
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4771-cc83f6d4f072e6c0a7033e5391d651b0f7c9fa0f/shard-bmg-8/igt@xe_module_load@load.html
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4771-cc83f6d4f072e6c0a7033e5391d651b0f7c9fa0f/shard-bmg-9/igt@xe_module_load@load.html
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4771-cc83f6d4f072e6c0a7033e5391d651b0f7c9fa0f/shard-bmg-2/igt@xe_module_load@load.html
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4771-cc83f6d4f072e6c0a7033e5391d651b0f7c9fa0f/shard-bmg-10/igt@xe_module_load@load.html
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4771-cc83f6d4f072e6c0a7033e5391d651b0f7c9fa0f/shard-bmg-10/igt@xe_module_load@load.html
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4771-cc83f6d4f072e6c0a7033e5391d651b0f7c9fa0f/shard-bmg-10/igt@xe_module_load@load.html
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4771-cc83f6d4f072e6c0a7033e5391d651b0f7c9fa0f/shard-bmg-1/igt@xe_module_load@load.html
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4771-cc83f6d4f072e6c0a7033e5391d651b0f7c9fa0f/shard-bmg-3/igt@xe_module_load@load.html
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4771-cc83f6d4f072e6c0a7033e5391d651b0f7c9fa0f/shard-bmg-7/igt@xe_module_load@load.html
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4771-cc83f6d4f072e6c0a7033e5391d651b0f7c9fa0f/shard-bmg-6/igt@xe_module_load@load.html
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4771-cc83f6d4f072e6c0a7033e5391d651b0f7c9fa0f/shard-bmg-6/igt@xe_module_load@load.html
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4771-cc83f6d4f072e6c0a7033e5391d651b0f7c9fa0f/shard-bmg-4/igt@xe_module_load@load.html
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4771-cc83f6d4f072e6c0a7033e5391d651b0f7c9fa0f/shard-bmg-1/igt@xe_module_load@load.html
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4771-cc83f6d4f072e6c0a7033e5391d651b0f7c9fa0f/shard-bmg-5/igt@xe_module_load@load.html
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4771-cc83f6d4f072e6c0a7033e5391d651b0f7c9fa0f/shard-bmg-7/igt@xe_module_load@load.html
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163783v1/shard-bmg-5/igt@xe_module_load@load.html
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163783v1/shard-bmg-4/igt@xe_module_load@load.html
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163783v1/shard-bmg-4/igt@xe_module_load@load.html
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163783v1/shard-bmg-5/igt@xe_module_load@load.html
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163783v1/shard-bmg-10/igt@xe_module_load@load.html
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163783v1/shard-bmg-10/igt@xe_module_load@load.html
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163783v1/shard-bmg-8/igt@xe_module_load@load.html
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163783v1/shard-bmg-8/igt@xe_module_load@load.html
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163783v1/shard-bmg-10/igt@xe_module_load@load.html
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163783v1/shard-bmg-1/igt@xe_module_load@load.html
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163783v1/shard-bmg-1/igt@xe_module_load@load.html
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163783v1/shard-bmg-1/igt@xe_module_load@load.html
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163783v1/shard-bmg-7/igt@xe_module_load@load.html
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163783v1/shard-bmg-7/igt@xe_module_load@load.html
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163783v1/shard-bmg-7/igt@xe_module_load@load.html
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163783v1/shard-bmg-9/igt@xe_module_load@load.html
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163783v1/shard-bmg-9/igt@xe_module_load@load.html
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163783v1/shard-bmg-9/igt@xe_module_load@load.html
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163783v1/shard-bmg-2/igt@xe_module_load@load.html
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163783v1/shard-bmg-2/igt@xe_module_load@load.html
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163783v1/shard-bmg-3/igt@xe_module_load@load.html
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163783v1/shard-bmg-3/igt@xe_module_load@load.html
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163783v1/shard-bmg-3/igt@xe_module_load@load.html
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163783v1/shard-bmg-6/igt@xe_module_load@load.html
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163783v1/shard-bmg-6/igt@xe_module_load@load.html

  
#### Possible fixes ####

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-lnl:          [FAIL][51] ([Intel XE#301]) -> [PASS][52] +1 other test pass
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4771-cc83f6d4f072e6c0a7033e5391d651b0f7c9fa0f/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163783v1/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#7433]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7433


Build changes
-------------

  * Linux: xe-4771-cc83f6d4f072e6c0a7033e5391d651b0f7c9fa0f -> xe-pw-163783v1

  IGT_8822: 8822
  xe-4771-cc83f6d4f072e6c0a7033e5391d651b0f7c9fa0f: cc83f6d4f072e6c0a7033e5391d651b0f7c9fa0f
  xe-pw-163783v1: 163783v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163783v1/index.html

[-- Attachment #2: Type: text/html, Size: 9233 bytes --]