Re: [PATCH v6] drm/xe/migrate: Revamp PAT index selection for migrate PTEs

[Matthew Auld <matthew.auld@intel.com>]

On 10/07/2026 09:30, Sanjay Yadav wrote:
> Improve PAT index selection logic in xe_migrate.c to avoid unnecessary
> coherency overhead when host-side memory is uncached. Previously,
> we defaulted to XE_CACHE_WB, which enforces 2-way coherency and may
> trigger cacheline pulls from CPU even when host-side memory is never
> dirty.
> 
> This change introduces xe_migrate_pat_index() to choose the appropriate
> PAT index based on the actual TTM caching mode of the buffer object
> being mapped. For iGPUs with WC host mappings, we now prefer
> XE_CACHE_NONE to skip coherency snoops. For compressed PTEs on newer
> platforms, we select XE_CACHE_NONE_COMPRESSION.
> 
> This avoids unnecessary cache traffic for uncached host mappings.
> 
> v6: (sashiko)
> - Only apply the BO's host-side caching for system-memory PTEs.
> 
> v5: (Matt A)
> - Simplify emit_pte() to derive caching from res->bo directly, removing
>    the separate bo parameter
> - Leave changes in __xe_migrate_update_pgtables() and
>    build_pt_update_batch_sram()
> - Fix comment about page-walker coherency in xe_migrate_pat_index()
> 
> v4:
> - Keep xe_migrate_prepare_vm() on XE_CACHE_WB since page tables require
>    page-walker coherency.
> - Pass BO into emit_pte() and select PAT attributes from the BO's TTM
>    caching mode.
> 
> Assisted-by: GitHub Copilot:claude-opus-4.8
> Signed-off-by: Sanjay Yadav <sanjay.kumar.yadav@intel.com>
> Suggested-by: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>