* [PATCH] drm/ttm: WIP limit the TTM pool to 32bit CPUs
@ 2025-08-06 13:28 Christian König
2025-08-06 13:58 ` ✗ CI.checkpatch: warning for " Patchwork
` (6 more replies)
0 siblings, 7 replies; 14+ messages in thread
From: Christian König @ 2025-08-06 13:28 UTC (permalink / raw)
To: dri-devel, intel-gfx, intel-xe; +Cc: airlied, thomas.hellstrom, matthew.brost
On some old x86 systems we had the problem that changing the caching flags
of system memory requires changing the global MTRR/PAT tables.
But on any modern x86 system (CPUs introduced rughly after 2004) we
actually don't need that any more and can update the caching flags
directly in the PTEs of the CPU mapping. It was just never disabled
because of the fear of regressions.
We already use the PTE flags for encryption on x86 64bit for quite a while
and all other supported platforms (Sparc, PowerPC, ARM, MIPS, LONGARCH)
have never done anything different either.
So disable the page pool completely for 64bit systems and just insert a
clflush to be on the safe side so that we never return memory with dirty
cache lines.
Testing on a Ryzen 5 and 7 shows that this has absolutely no performance
impact and of hand the AMD CI can't find a problem either.
Let's see what the i915 and XE CI systems say to that.
Signed-off-by: Christian König <christian.koenig@amd.com>
---
drivers/gpu/drm/ttm/ttm_pool.c | 16 +++++++++++-----
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_pool.c b/drivers/gpu/drm/ttm/ttm_pool.c
index baf27c70a419..7487eac29398 100644
--- a/drivers/gpu/drm/ttm/ttm_pool.c
+++ b/drivers/gpu/drm/ttm/ttm_pool.c
@@ -38,7 +38,7 @@
#include <linux/highmem.h>
#include <linux/sched/mm.h>
-#ifdef CONFIG_X86
+#ifdef CONFIG_X86_32
#include <asm/set_memory.h>
#endif
@@ -46,6 +46,7 @@
#include <drm/ttm/ttm_pool.h>
#include <drm/ttm/ttm_tt.h>
#include <drm/ttm/ttm_bo.h>
+#include <drm/drm_cache.h>
#include "ttm_module.h"
@@ -192,7 +193,7 @@ static void ttm_pool_free_page(struct ttm_pool *pool, enum ttm_caching caching,
struct ttm_pool_dma *dma;
void *vaddr;
-#ifdef CONFIG_X86
+#ifdef CONFIG_X86_32
/* We don't care that set_pages_wb is inefficient here. This is only
* used when we have to shrink and CPU overhead is irrelevant then.
*/
@@ -218,7 +219,7 @@ static void ttm_pool_free_page(struct ttm_pool *pool, enum ttm_caching caching,
/* Apply any cpu-caching deferred during page allocation */
static int ttm_pool_apply_caching(struct ttm_pool_alloc_state *alloc)
{
-#ifdef CONFIG_X86
+#ifdef CONFIG_X86_32
unsigned int num_pages = alloc->pages - alloc->caching_divide;
if (!num_pages)
@@ -232,6 +233,11 @@ static int ttm_pool_apply_caching(struct ttm_pool_alloc_state *alloc)
case ttm_uncached:
return set_pages_array_uc(alloc->caching_divide, num_pages);
}
+
+#elif defined(CONFIG_X86_64)
+ unsigned int num_pages = alloc->pages - alloc->caching_divide;
+
+ drm_clflush_pages(alloc->caching_divide, num_pages);
#endif
alloc->caching_divide = alloc->pages;
return 0;
@@ -342,7 +348,7 @@ static struct ttm_pool_type *ttm_pool_select_type(struct ttm_pool *pool,
if (pool->use_dma_alloc)
return &pool->caching[caching].orders[order];
-#ifdef CONFIG_X86
+#ifdef CONFIG_X86_32
switch (caching) {
case ttm_write_combined:
if (pool->nid != NUMA_NO_NODE)
@@ -980,7 +986,7 @@ long ttm_pool_backup(struct ttm_pool *pool, struct ttm_tt *tt,
pool->use_dma_alloc || ttm_tt_is_backed_up(tt))
return -EBUSY;
-#ifdef CONFIG_X86
+#ifdef CONFIG_X86_32
/* Anything returned to the system needs to be cached. */
if (tt->caching != ttm_cached)
set_pages_array_wb(tt->pages, tt->num_pages);
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* ✗ CI.checkpatch: warning for drm/ttm: WIP limit the TTM pool to 32bit CPUs
2025-08-06 13:28 [PATCH] drm/ttm: WIP limit the TTM pool to 32bit CPUs Christian König
@ 2025-08-06 13:58 ` Patchwork
2025-08-06 14:00 ` ✓ CI.KUnit: success " Patchwork
` (5 subsequent siblings)
6 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2025-08-06 13:58 UTC (permalink / raw)
To: Christian König; +Cc: intel-xe
== Series Details ==
Series: drm/ttm: WIP limit the TTM pool to 32bit CPUs
URL : https://patchwork.freedesktop.org/series/152588/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
c298eac5978c38dcc62a70c0d73c91765e7cc296
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 6fd3754e5533e725f9e19b96f5f30524ca8858f5
Author: Christian König <ckoenig.leichtzumerken@gmail.com>
Date: Wed Aug 6 15:28:38 2025 +0200
drm/ttm: WIP limit the TTM pool to 32bit CPUs
On some old x86 systems we had the problem that changing the caching flags
of system memory requires changing the global MTRR/PAT tables.
But on any modern x86 system (CPUs introduced rughly after 2004) we
actually don't need that any more and can update the caching flags
directly in the PTEs of the CPU mapping. It was just never disabled
because of the fear of regressions.
We already use the PTE flags for encryption on x86 64bit for quite a while
and all other supported platforms (Sparc, PowerPC, ARM, MIPS, LONGARCH)
have never done anything different either.
So disable the page pool completely for 64bit systems and just insert a
clflush to be on the safe side so that we never return memory with dirty
cache lines.
Testing on a Ryzen 5 and 7 shows that this has absolutely no performance
impact and of hand the AMD CI can't find a problem either.
Let's see what the i915 and XE CI systems say to that.
Signed-off-by: Christian König <christian.koenig@amd.com>
+ /mt/dim checkpatch 886b8d8ef3839f604e3e7f6187ac6c46eb21b802 drm-intel
6fd3754e5533 drm/ttm: WIP limit the TTM pool to 32bit CPUs
-:100: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: "Christian König" <ckoenig.leichtzumerken@gmail.com>' != 'Signed-off-by: Christian König <christian.koenig@amd.com>'
total: 0 errors, 1 warnings, 0 checks, 58 lines checked
^ permalink raw reply [flat|nested] 14+ messages in thread
* ✓ CI.KUnit: success for drm/ttm: WIP limit the TTM pool to 32bit CPUs
2025-08-06 13:28 [PATCH] drm/ttm: WIP limit the TTM pool to 32bit CPUs Christian König
2025-08-06 13:58 ` ✗ CI.checkpatch: warning for " Patchwork
@ 2025-08-06 14:00 ` Patchwork
2025-08-06 15:07 ` ✗ Xe.CI.BAT: failure " Patchwork
` (4 subsequent siblings)
6 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2025-08-06 14:00 UTC (permalink / raw)
To: Christian König; +Cc: intel-xe
== Series Details ==
Series: drm/ttm: WIP limit the TTM pool to 32bit CPUs
URL : https://patchwork.freedesktop.org/series/152588/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[13:59:03] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[13:59:07] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[13:59:41] Starting KUnit Kernel (1/1)...
[13:59:41] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[13:59:41] ================== guc_buf (11 subtests) ===================
[13:59:41] [PASSED] test_smallest
[13:59:41] [PASSED] test_largest
[13:59:41] [PASSED] test_granular
[13:59:41] [PASSED] test_unique
[13:59:41] [PASSED] test_overlap
[13:59:41] [PASSED] test_reusable
[13:59:41] [PASSED] test_too_big
[13:59:41] [PASSED] test_flush
[13:59:41] [PASSED] test_lookup
[13:59:41] [PASSED] test_data
[13:59:41] [PASSED] test_class
[13:59:41] ===================== [PASSED] guc_buf =====================
[13:59:41] =================== guc_dbm (7 subtests) ===================
[13:59:41] [PASSED] test_empty
[13:59:41] [PASSED] test_default
[13:59:41] ======================== test_size ========================
[13:59:41] [PASSED] 4
[13:59:41] [PASSED] 8
[13:59:41] [PASSED] 32
[13:59:41] [PASSED] 256
[13:59:41] ==================== [PASSED] test_size ====================
[13:59:41] ======================= test_reuse ========================
[13:59:41] [PASSED] 4
[13:59:41] [PASSED] 8
[13:59:41] [PASSED] 32
[13:59:41] [PASSED] 256
[13:59:41] =================== [PASSED] test_reuse ====================
[13:59:41] =================== test_range_overlap ====================
[13:59:41] [PASSED] 4
[13:59:41] [PASSED] 8
[13:59:41] [PASSED] 32
[13:59:41] [PASSED] 256
[13:59:41] =============== [PASSED] test_range_overlap ================
[13:59:41] =================== test_range_compact ====================
[13:59:41] [PASSED] 4
[13:59:41] [PASSED] 8
[13:59:41] [PASSED] 32
[13:59:41] [PASSED] 256
[13:59:41] =============== [PASSED] test_range_compact ================
[13:59:41] ==================== test_range_spare =====================
[13:59:41] [PASSED] 4
[13:59:41] [PASSED] 8
[13:59:41] [PASSED] 32
[13:59:41] [PASSED] 256
[13:59:41] ================ [PASSED] test_range_spare =================
[13:59:41] ===================== [PASSED] guc_dbm =====================
[13:59:41] =================== guc_idm (6 subtests) ===================
[13:59:41] [PASSED] bad_init
[13:59:41] [PASSED] no_init
[13:59:41] [PASSED] init_fini
[13:59:41] [PASSED] check_used
[13:59:41] [PASSED] check_quota
[13:59:41] [PASSED] check_all
[13:59:41] ===================== [PASSED] guc_idm =====================
[13:59:41] ================== no_relay (3 subtests) ===================
[13:59:41] [PASSED] xe_drops_guc2pf_if_not_ready
[13:59:41] [PASSED] xe_drops_guc2vf_if_not_ready
[13:59:41] [PASSED] xe_rejects_send_if_not_ready
[13:59:41] ==================== [PASSED] no_relay =====================
[13:59:41] ================== pf_relay (14 subtests) ==================
[13:59:41] [PASSED] pf_rejects_guc2pf_too_short
[13:59:41] [PASSED] pf_rejects_guc2pf_too_long
[13:59:41] [PASSED] pf_rejects_guc2pf_no_payload
[13:59:41] [PASSED] pf_fails_no_payload
[13:59:41] [PASSED] pf_fails_bad_origin
[13:59:41] [PASSED] pf_fails_bad_type
[13:59:41] [PASSED] pf_txn_reports_error
[13:59:41] [PASSED] pf_txn_sends_pf2guc
[13:59:41] [PASSED] pf_sends_pf2guc
[13:59:41] [SKIPPED] pf_loopback_nop
[13:59:41] [SKIPPED] pf_loopback_echo
[13:59:41] [SKIPPED] pf_loopback_fail
[13:59:41] [SKIPPED] pf_loopback_busy
[13:59:41] [SKIPPED] pf_loopback_retry
[13:59:41] ==================== [PASSED] pf_relay =====================
[13:59:41] ================== vf_relay (3 subtests) ===================
[13:59:41] [PASSED] vf_rejects_guc2vf_too_short
[13:59:41] [PASSED] vf_rejects_guc2vf_too_long
[13:59:41] [PASSED] vf_rejects_guc2vf_no_payload
[13:59:41] ==================== [PASSED] vf_relay =====================
[13:59:41] ===================== lmtt (1 subtest) =====================
[13:59:41] ======================== test_ops =========================
[13:59:41] [PASSED] 2-level
[13:59:41] [PASSED] multi-level
[13:59:41] ==================== [PASSED] test_ops =====================
[13:59:41] ====================== [PASSED] lmtt =======================
[13:59:41] ================= pf_service (11 subtests) =================
[13:59:41] [PASSED] pf_negotiate_any
[13:59:41] [PASSED] pf_negotiate_base_match
[13:59:41] [PASSED] pf_negotiate_base_newer
[13:59:41] [PASSED] pf_negotiate_base_next
[13:59:41] [SKIPPED] pf_negotiate_base_older
[13:59:41] [PASSED] pf_negotiate_base_prev
[13:59:41] [PASSED] pf_negotiate_latest_match
[13:59:41] [PASSED] pf_negotiate_latest_newer
[13:59:41] [PASSED] pf_negotiate_latest_next
[13:59:41] [SKIPPED] pf_negotiate_latest_older
[13:59:41] [SKIPPED] pf_negotiate_latest_prev
[13:59:41] =================== [PASSED] pf_service ====================
[13:59:41] =================== xe_mocs (2 subtests) ===================
[13:59:41] ================ xe_live_mocs_kernel_kunit ================
[13:59:41] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[13:59:41] ================ xe_live_mocs_reset_kunit =================
[13:59:41] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[13:59:41] ==================== [SKIPPED] xe_mocs =====================
[13:59:41] ================= xe_migrate (2 subtests) ==================
[13:59:41] ================= xe_migrate_sanity_kunit =================
[13:59:41] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[13:59:41] ================== xe_validate_ccs_kunit ==================
[13:59:41] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[13:59:41] =================== [SKIPPED] xe_migrate ===================
[13:59:41] ================== xe_dma_buf (1 subtest) ==================
[13:59:41] ==================== xe_dma_buf_kunit =====================
[13:59:41] ================ [SKIPPED] xe_dma_buf_kunit ================
[13:59:41] =================== [SKIPPED] xe_dma_buf ===================
[13:59:41] ================= xe_bo_shrink (1 subtest) =================
[13:59:41] =================== xe_bo_shrink_kunit ====================
[13:59:41] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[13:59:41] ================== [SKIPPED] xe_bo_shrink ==================
[13:59:41] ==================== xe_bo (2 subtests) ====================
[13:59:41] ================== xe_ccs_migrate_kunit ===================
[13:59:41] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[13:59:41] ==================== xe_bo_evict_kunit ====================
[13:59:41] =============== [SKIPPED] xe_bo_evict_kunit ================
[13:59:41] ===================== [SKIPPED] xe_bo ======================
[13:59:41] ==================== args (11 subtests) ====================
[13:59:41] [PASSED] count_args_test
[13:59:41] [PASSED] call_args_example
[13:59:41] [PASSED] call_args_test
[13:59:41] [PASSED] drop_first_arg_example
[13:59:41] [PASSED] drop_first_arg_test
[13:59:41] [PASSED] first_arg_example
[13:59:41] [PASSED] first_arg_test
[13:59:41] [PASSED] last_arg_example
[13:59:41] [PASSED] last_arg_test
[13:59:41] [PASSED] pick_arg_example
[13:59:41] [PASSED] sep_comma_example
[13:59:41] ====================== [PASSED] args =======================
[13:59:41] =================== xe_pci (3 subtests) ====================
[13:59:41] ==================== check_graphics_ip ====================
[13:59:41] [PASSED] 12.70 Xe_LPG
[13:59:41] [PASSED] 12.71 Xe_LPG
[13:59:41] [PASSED] 12.74 Xe_LPG+
[13:59:41] [PASSED] 20.01 Xe2_HPG
[13:59:41] [PASSED] 20.02 Xe2_HPG
[13:59:41] [PASSED] 20.04 Xe2_LPG
[13:59:41] [PASSED] 30.00 Xe3_LPG
[13:59:41] [PASSED] 30.01 Xe3_LPG
[13:59:41] [PASSED] 30.03 Xe3_LPG
[13:59:41] ================ [PASSED] check_graphics_ip ================
[13:59:41] ===================== check_media_ip ======================
[13:59:41] [PASSED] 13.00 Xe_LPM+
[13:59:41] [PASSED] 13.01 Xe2_HPM
[13:59:41] [PASSED] 20.00 Xe2_LPM
[13:59:41] [PASSED] 30.00 Xe3_LPM
[13:59:41] [PASSED] 30.02 Xe3_LPM
[13:59:41] ================= [PASSED] check_media_ip ==================
[13:59:41] ================= check_platform_gt_count =================
[13:59:41] [PASSED] 0x9A60 (TIGERLAKE)
[13:59:41] [PASSED] 0x9A68 (TIGERLAKE)
[13:59:41] [PASSED] 0x9A70 (TIGERLAKE)
[13:59:41] [PASSED] 0x9A40 (TIGERLAKE)
[13:59:41] [PASSED] 0x9A49 (TIGERLAKE)
[13:59:41] [PASSED] 0x9A59 (TIGERLAKE)
[13:59:41] [PASSED] 0x9A78 (TIGERLAKE)
[13:59:41] [PASSED] 0x9AC0 (TIGERLAKE)
[13:59:41] [PASSED] 0x9AC9 (TIGERLAKE)
[13:59:41] [PASSED] 0x9AD9 (TIGERLAKE)
[13:59:41] [PASSED] 0x9AF8 (TIGERLAKE)
[13:59:41] [PASSED] 0x4C80 (ROCKETLAKE)
[13:59:41] [PASSED] 0x4C8A (ROCKETLAKE)
[13:59:41] [PASSED] 0x4C8B (ROCKETLAKE)
[13:59:41] [PASSED] 0x4C8C (ROCKETLAKE)
[13:59:41] [PASSED] 0x4C90 (ROCKETLAKE)
[13:59:41] [PASSED] 0x4C9A (ROCKETLAKE)
[13:59:41] [PASSED] 0x4680 (ALDERLAKE_S)
[13:59:41] [PASSED] 0x4682 (ALDERLAKE_S)
[13:59:41] [PASSED] 0x4688 (ALDERLAKE_S)
[13:59:41] [PASSED] 0x468A (ALDERLAKE_S)
[13:59:41] [PASSED] 0x468B (ALDERLAKE_S)
[13:59:41] [PASSED] 0x4690 (ALDERLAKE_S)
[13:59:41] [PASSED] 0x4692 (ALDERLAKE_S)
[13:59:41] [PASSED] 0x4693 (ALDERLAKE_S)
[13:59:41] [PASSED] 0x46A0 (ALDERLAKE_P)
[13:59:41] [PASSED] 0x46A1 (ALDERLAKE_P)
[13:59:41] [PASSED] 0x46A2 (ALDERLAKE_P)
[13:59:41] [PASSED] 0x46A3 (ALDERLAKE_P)
[13:59:41] [PASSED] 0x46A6 (ALDERLAKE_P)
[13:59:41] [PASSED] 0x46A8 (ALDERLAKE_P)
[13:59:41] [PASSED] 0x46AA (ALDERLAKE_P)
[13:59:41] [PASSED] 0x462A (ALDERLAKE_P)
[13:59:41] [PASSED] 0x4626 (ALDERLAKE_P)
[13:59:41] [PASSED] 0x4628 (ALDERLAKE_P)
[13:59:41] [PASSED] 0x46B0 (ALDERLAKE_P)
[13:59:41] [PASSED] 0x46B1 (ALDERLAKE_P)
[13:59:41] [PASSED] 0x46B2 (ALDERLAKE_P)
[13:59:41] [PASSED] 0x46B3 (ALDERLAKE_P)
[13:59:41] [PASSED] 0x46C0 (ALDERLAKE_P)
[13:59:41] [PASSED] 0x46C1 (ALDERLAKE_P)
[13:59:41] [PASSED] 0x46C2 (ALDERLAKE_P)
[13:59:41] [PASSED] 0x46C3 (ALDERLAKE_P)
[13:59:41] [PASSED] 0x46D0 (ALDERLAKE_N)
[13:59:41] [PASSED] 0x46D1 (ALDERLAKE_N)
[13:59:41] [PASSED] 0x46D2 (ALDERLAKE_N)
[13:59:41] [PASSED] 0x46D3 (ALDERLAKE_N)
[13:59:41] [PASSED] 0x46D4 (ALDERLAKE_N)
[13:59:41] [PASSED] 0xA721 (ALDERLAKE_P)
[13:59:41] [PASSED] 0xA7A1 (ALDERLAKE_P)
[13:59:41] [PASSED] 0xA7A9 (ALDERLAKE_P)
[13:59:41] [PASSED] 0xA7AC (ALDERLAKE_P)
[13:59:41] [PASSED] 0xA7AD (ALDERLAKE_P)
[13:59:41] [PASSED] 0xA720 (ALDERLAKE_P)
[13:59:41] [PASSED] 0xA7A0 (ALDERLAKE_P)
[13:59:41] [PASSED] 0xA7A8 (ALDERLAKE_P)
[13:59:41] [PASSED] 0xA7AA (ALDERLAKE_P)
[13:59:41] [PASSED] 0xA7AB (ALDERLAKE_P)
[13:59:41] [PASSED] 0xA780 (ALDERLAKE_S)
[13:59:41] [PASSED] 0xA781 (ALDERLAKE_S)
[13:59:41] [PASSED] 0xA782 (ALDERLAKE_S)
[13:59:41] [PASSED] 0xA783 (ALDERLAKE_S)
[13:59:41] [PASSED] 0xA788 (ALDERLAKE_S)
[13:59:41] [PASSED] 0xA789 (ALDERLAKE_S)
[13:59:41] [PASSED] 0xA78A (ALDERLAKE_S)
[13:59:41] [PASSED] 0xA78B (ALDERLAKE_S)
[13:59:41] [PASSED] 0x4905 (DG1)
[13:59:41] [PASSED] 0x4906 (DG1)
[13:59:41] [PASSED] 0x4907 (DG1)
[13:59:41] [PASSED] 0x4908 (DG1)
[13:59:41] [PASSED] 0x4909 (DG1)
[13:59:41] [PASSED] 0x56C0 (DG2)
[13:59:41] [PASSED] 0x56C2 (DG2)
[13:59:41] [PASSED] 0x56C1 (DG2)
[13:59:41] [PASSED] 0x7D51 (METEORLAKE)
[13:59:41] [PASSED] 0x7DD1 (METEORLAKE)
[13:59:41] [PASSED] 0x7D41 (METEORLAKE)
[13:59:41] [PASSED] 0x7D67 (METEORLAKE)
[13:59:41] [PASSED] 0xB640 (METEORLAKE)
[13:59:41] [PASSED] 0x56A0 (DG2)
[13:59:41] [PASSED] 0x56A1 (DG2)
[13:59:41] [PASSED] 0x56A2 (DG2)
[13:59:41] [PASSED] 0x56BE (DG2)
[13:59:41] [PASSED] 0x56BF (DG2)
[13:59:41] [PASSED] 0x5690 (DG2)
[13:59:41] [PASSED] 0x5691 (DG2)
[13:59:41] [PASSED] 0x5692 (DG2)
[13:59:41] [PASSED] 0x56A5 (DG2)
[13:59:41] [PASSED] 0x56A6 (DG2)
[13:59:41] [PASSED] 0x56B0 (DG2)
[13:59:41] [PASSED] 0x56B1 (DG2)
[13:59:41] [PASSED] 0x56BA (DG2)
[13:59:41] [PASSED] 0x56BB (DG2)
[13:59:41] [PASSED] 0x56BC (DG2)
[13:59:41] [PASSED] 0x56BD (DG2)
[13:59:41] [PASSED] 0x5693 (DG2)
[13:59:41] [PASSED] 0x5694 (DG2)
[13:59:41] [PASSED] 0x5695 (DG2)
[13:59:41] [PASSED] 0x56A3 (DG2)
[13:59:41] [PASSED] 0x56A4 (DG2)
[13:59:41] [PASSED] 0x56B2 (DG2)
[13:59:41] [PASSED] 0x56B3 (DG2)
[13:59:41] [PASSED] 0x5696 (DG2)
[13:59:41] [PASSED] 0x5697 (DG2)
[13:59:41] [PASSED] 0xB69 (PVC)
[13:59:41] [PASSED] 0xB6E (PVC)
[13:59:41] [PASSED] 0xBD4 (PVC)
[13:59:41] [PASSED] 0xBD5 (PVC)
[13:59:41] [PASSED] 0xBD6 (PVC)
[13:59:41] [PASSED] 0xBD7 (PVC)
[13:59:41] [PASSED] 0xBD8 (PVC)
[13:59:41] [PASSED] 0xBD9 (PVC)
[13:59:41] [PASSED] 0xBDA (PVC)
[13:59:41] [PASSED] 0xBDB (PVC)
[13:59:41] [PASSED] 0xBE0 (PVC)
[13:59:41] [PASSED] 0xBE1 (PVC)
[13:59:41] [PASSED] 0xBE5 (PVC)
[13:59:41] [PASSED] 0x7D40 (METEORLAKE)
[13:59:41] [PASSED] 0x7D45 (METEORLAKE)
[13:59:41] [PASSED] 0x7D55 (METEORLAKE)
[13:59:41] [PASSED] 0x7D60 (METEORLAKE)
[13:59:41] [PASSED] 0x7DD5 (METEORLAKE)
[13:59:41] [PASSED] 0x6420 (LUNARLAKE)
[13:59:41] [PASSED] 0x64A0 (LUNARLAKE)
[13:59:41] [PASSED] 0x64B0 (LUNARLAKE)
[13:59:41] [PASSED] 0xE202 (BATTLEMAGE)
[13:59:41] [PASSED] 0xE209 (BATTLEMAGE)
[13:59:41] [PASSED] 0xE20B (BATTLEMAGE)
[13:59:41] [PASSED] 0xE20C (BATTLEMAGE)
[13:59:41] [PASSED] 0xE20D (BATTLEMAGE)
[13:59:41] [PASSED] 0xE210 (BATTLEMAGE)
[13:59:41] [PASSED] 0xE211 (BATTLEMAGE)
[13:59:41] [PASSED] 0xE212 (BATTLEMAGE)
[13:59:41] [PASSED] 0xE216 (BATTLEMAGE)
[13:59:41] [PASSED] 0xE220 (BATTLEMAGE)
[13:59:41] [PASSED] 0xE221 (BATTLEMAGE)
[13:59:41] [PASSED] 0xE222 (BATTLEMAGE)
[13:59:41] [PASSED] 0xE223 (BATTLEMAGE)
[13:59:41] [PASSED] 0xB080 (PANTHERLAKE)
[13:59:41] [PASSED] 0xB081 (PANTHERLAKE)
[13:59:41] [PASSED] 0xB082 (PANTHERLAKE)
[13:59:41] [PASSED] 0xB083 (PANTHERLAKE)
[13:59:41] [PASSED] 0xB084 (PANTHERLAKE)
[13:59:41] [PASSED] 0xB085 (PANTHERLAKE)
[13:59:41] [PASSED] 0xB086 (PANTHERLAKE)
[13:59:41] [PASSED] 0xB087 (PANTHERLAKE)
[13:59:41] [PASSED] 0xB08F (PANTHERLAKE)
[13:59:41] [PASSED] 0xB090 (PANTHERLAKE)
[13:59:41] [PASSED] 0xB0A0 (PANTHERLAKE)
[13:59:41] [PASSED] 0xB0B0 (PANTHERLAKE)
[13:59:41] [PASSED] 0xFD80 (PANTHERLAKE)
[13:59:41] [PASSED] 0xFD81 (PANTHERLAKE)
[13:59:41] ============= [PASSED] check_platform_gt_count =============
[13:59:41] ===================== [PASSED] xe_pci ======================
[13:59:41] =================== xe_rtp (2 subtests) ====================
[13:59:41] =============== xe_rtp_process_to_sr_tests ================
[13:59:41] [PASSED] coalesce-same-reg
[13:59:41] [PASSED] no-match-no-add
[13:59:41] [PASSED] match-or
[13:59:41] [PASSED] match-or-xfail
[13:59:41] [PASSED] no-match-no-add-multiple-rules
[13:59:41] [PASSED] two-regs-two-entries
[13:59:41] [PASSED] clr-one-set-other
[13:59:41] [PASSED] set-field
[13:59:41] [PASSED] conflict-duplicate
[13:59:41] [PASSED] conflict-not-disjoint
[13:59:41] [PASSED] conflict-reg-type
[13:59:41] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[13:59:41] ================== xe_rtp_process_tests ===================
[13:59:41] [PASSED] active1
[13:59:41] [PASSED] active2
[13:59:41] [PASSED] active-inactive
[13:59:41] [PASSED] inactive-active
[13:59:41] [PASSED] inactive-1st_or_active-inactive
[13:59:41] [PASSED] inactive-2nd_or_active-inactive
[13:59:41] [PASSED] inactive-last_or_active-inactive
[13:59:41] [PASSED] inactive-no_or_active-inactive
[13:59:41] ============== [PASSED] xe_rtp_process_tests ===============
[13:59:41] ===================== [PASSED] xe_rtp ======================
[13:59:41] ==================== xe_wa (1 subtest) =====================
[13:59:41] ======================== xe_wa_gt =========================
[13:59:41] [PASSED] TIGERLAKE (B0)
[13:59:41] [PASSED] DG1 (A0)
[13:59:41] [PASSED] DG1 (B0)
[13:59:41] [PASSED] ALDERLAKE_S (A0)
[13:59:41] [PASSED] ALDERLAKE_S (B0)
[13:59:41] [PASSED] ALDERLAKE_S (C0)
[13:59:41] [PASSED] ALDERLAKE_S (D0)
[13:59:41] [PASSED] ALDERLAKE_P (A0)
[13:59:41] [PASSED] ALDERLAKE_P (B0)
[13:59:41] [PASSED] ALDERLAKE_P (C0)
[13:59:41] [PASSED] ALDERLAKE_S_RPLS (D0)
[13:59:41] [PASSED] ALDERLAKE_P_RPLU (E0)
[13:59:41] [PASSED] DG2_G10 (C0)
[13:59:41] [PASSED] DG2_G11 (B1)
[13:59:41] [PASSED] DG2_G12 (A1)
[13:59:41] [PASSED] METEORLAKE (g:A0, m:A0)
[13:59:41] [PASSED] METEORLAKE (g:A0, m:A0)
[13:59:41] [PASSED] METEORLAKE (g:A0, m:A0)
[13:59:41] [PASSED] LUNARLAKE (g:A0, m:A0)
[13:59:41] [PASSED] LUNARLAKE (g:B0, m:A0)
stty: 'standard input': Inappropriate ioctl for device
[13:59:41] [PASSED] BATTLEMAGE (g:A0, m:A1)
[13:59:41] ==================== [PASSED] xe_wa_gt =====================
[13:59:41] ====================== [PASSED] xe_wa ======================
[13:59:41] ============================================================
[13:59:41] Testing complete. Ran 297 tests: passed: 281, skipped: 16
[13:59:41] Elapsed time: 38.217s total, 4.210s configuring, 33.641s building, 0.334s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[13:59:42] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[13:59:43] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[14:00:09] Starting KUnit Kernel (1/1)...
[14:00:09] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[14:00:09] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[14:00:09] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[14:00:09] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[14:00:09] =========== drm_validate_clone_mode (2 subtests) ===========
[14:00:09] ============== drm_test_check_in_clone_mode ===============
[14:00:09] [PASSED] in_clone_mode
[14:00:09] [PASSED] not_in_clone_mode
[14:00:09] ========== [PASSED] drm_test_check_in_clone_mode ===========
[14:00:09] =============== drm_test_check_valid_clones ===============
[14:00:09] [PASSED] not_in_clone_mode
[14:00:09] [PASSED] valid_clone
[14:00:09] [PASSED] invalid_clone
[14:00:09] =========== [PASSED] drm_test_check_valid_clones ===========
[14:00:09] ============= [PASSED] drm_validate_clone_mode =============
[14:00:09] ============= drm_validate_modeset (1 subtest) =============
[14:00:09] [PASSED] drm_test_check_connector_changed_modeset
[14:00:09] ============== [PASSED] drm_validate_modeset ===============
[14:00:09] ====== drm_test_bridge_get_current_state (2 subtests) ======
[14:00:09] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[14:00:09] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[14:00:09] ======== [PASSED] drm_test_bridge_get_current_state ========
[14:00:09] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[14:00:09] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[14:00:09] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[14:00:09] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[14:00:09] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[14:00:09] ============== drm_bridge_alloc (2 subtests) ===============
[14:00:09] [PASSED] drm_test_drm_bridge_alloc_basic
[14:00:09] [PASSED] drm_test_drm_bridge_alloc_get_put
[14:00:09] ================ [PASSED] drm_bridge_alloc =================
[14:00:09] ================== drm_buddy (7 subtests) ==================
[14:00:09] [PASSED] drm_test_buddy_alloc_limit
[14:00:09] [PASSED] drm_test_buddy_alloc_optimistic
[14:00:09] [PASSED] drm_test_buddy_alloc_pessimistic
[14:00:09] [PASSED] drm_test_buddy_alloc_pathological
[14:00:09] [PASSED] drm_test_buddy_alloc_contiguous
[14:00:09] [PASSED] drm_test_buddy_alloc_clear
[14:00:09] [PASSED] drm_test_buddy_alloc_range_bias
[14:00:09] ==================== [PASSED] drm_buddy ====================
[14:00:09] ============= drm_cmdline_parser (40 subtests) =============
[14:00:09] [PASSED] drm_test_cmdline_force_d_only
[14:00:09] [PASSED] drm_test_cmdline_force_D_only_dvi
[14:00:09] [PASSED] drm_test_cmdline_force_D_only_hdmi
[14:00:09] [PASSED] drm_test_cmdline_force_D_only_not_digital
[14:00:09] [PASSED] drm_test_cmdline_force_e_only
[14:00:09] [PASSED] drm_test_cmdline_res
[14:00:09] [PASSED] drm_test_cmdline_res_vesa
[14:00:09] [PASSED] drm_test_cmdline_res_vesa_rblank
[14:00:09] [PASSED] drm_test_cmdline_res_rblank
[14:00:09] [PASSED] drm_test_cmdline_res_bpp
[14:00:09] [PASSED] drm_test_cmdline_res_refresh
[14:00:09] [PASSED] drm_test_cmdline_res_bpp_refresh
[14:00:09] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[14:00:09] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[14:00:09] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[14:00:09] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[14:00:09] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[14:00:09] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[14:00:09] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[14:00:09] [PASSED] drm_test_cmdline_res_margins_force_on
[14:00:09] [PASSED] drm_test_cmdline_res_vesa_margins
[14:00:09] [PASSED] drm_test_cmdline_name
[14:00:09] [PASSED] drm_test_cmdline_name_bpp
[14:00:09] [PASSED] drm_test_cmdline_name_option
[14:00:09] [PASSED] drm_test_cmdline_name_bpp_option
[14:00:09] [PASSED] drm_test_cmdline_rotate_0
[14:00:09] [PASSED] drm_test_cmdline_rotate_90
[14:00:09] [PASSED] drm_test_cmdline_rotate_180
[14:00:09] [PASSED] drm_test_cmdline_rotate_270
[14:00:09] [PASSED] drm_test_cmdline_hmirror
[14:00:09] [PASSED] drm_test_cmdline_vmirror
[14:00:09] [PASSED] drm_test_cmdline_margin_options
[14:00:09] [PASSED] drm_test_cmdline_multiple_options
[14:00:09] [PASSED] drm_test_cmdline_bpp_extra_and_option
[14:00:09] [PASSED] drm_test_cmdline_extra_and_option
[14:00:09] [PASSED] drm_test_cmdline_freestanding_options
[14:00:09] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[14:00:09] [PASSED] drm_test_cmdline_panel_orientation
[14:00:09] ================ drm_test_cmdline_invalid =================
[14:00:09] [PASSED] margin_only
[14:00:09] [PASSED] interlace_only
[14:00:09] [PASSED] res_missing_x
[14:00:09] [PASSED] res_missing_y
[14:00:09] [PASSED] res_bad_y
[14:00:09] [PASSED] res_missing_y_bpp
[14:00:09] [PASSED] res_bad_bpp
[14:00:09] [PASSED] res_bad_refresh
[14:00:09] [PASSED] res_bpp_refresh_force_on_off
[14:00:09] [PASSED] res_invalid_mode
[14:00:09] [PASSED] res_bpp_wrong_place_mode
[14:00:09] [PASSED] name_bpp_refresh
[14:00:09] [PASSED] name_refresh
[14:00:09] [PASSED] name_refresh_wrong_mode
[14:00:09] [PASSED] name_refresh_invalid_mode
[14:00:09] [PASSED] rotate_multiple
[14:00:09] [PASSED] rotate_invalid_val
[14:00:09] [PASSED] rotate_truncated
[14:00:09] [PASSED] invalid_option
[14:00:09] [PASSED] invalid_tv_option
[14:00:09] [PASSED] truncated_tv_option
[14:00:09] ============ [PASSED] drm_test_cmdline_invalid =============
[14:00:09] =============== drm_test_cmdline_tv_options ===============
[14:00:09] [PASSED] NTSC
[14:00:09] [PASSED] NTSC_443
[14:00:09] [PASSED] NTSC_J
[14:00:09] [PASSED] PAL
[14:00:09] [PASSED] PAL_M
[14:00:09] [PASSED] PAL_N
[14:00:09] [PASSED] SECAM
[14:00:09] [PASSED] MONO_525
[14:00:09] [PASSED] MONO_625
[14:00:09] =========== [PASSED] drm_test_cmdline_tv_options ===========
[14:00:09] =============== [PASSED] drm_cmdline_parser ================
[14:00:09] ========== drmm_connector_hdmi_init (20 subtests) ==========
[14:00:09] [PASSED] drm_test_connector_hdmi_init_valid
[14:00:09] [PASSED] drm_test_connector_hdmi_init_bpc_8
[14:00:09] [PASSED] drm_test_connector_hdmi_init_bpc_10
[14:00:09] [PASSED] drm_test_connector_hdmi_init_bpc_12
[14:00:09] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[14:00:09] [PASSED] drm_test_connector_hdmi_init_bpc_null
[14:00:09] [PASSED] drm_test_connector_hdmi_init_formats_empty
[14:00:09] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[14:00:09] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[14:00:09] [PASSED] supported_formats=0x9 yuv420_allowed=1
[14:00:09] [PASSED] supported_formats=0x9 yuv420_allowed=0
[14:00:09] [PASSED] supported_formats=0x3 yuv420_allowed=1
[14:00:09] [PASSED] supported_formats=0x3 yuv420_allowed=0
[14:00:09] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[14:00:09] [PASSED] drm_test_connector_hdmi_init_null_ddc
[14:00:09] [PASSED] drm_test_connector_hdmi_init_null_product
[14:00:09] [PASSED] drm_test_connector_hdmi_init_null_vendor
[14:00:09] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[14:00:09] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[14:00:09] [PASSED] drm_test_connector_hdmi_init_product_valid
[14:00:09] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[14:00:09] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[14:00:09] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[14:00:09] ========= drm_test_connector_hdmi_init_type_valid =========
[14:00:09] [PASSED] HDMI-A
[14:00:09] [PASSED] HDMI-B
[14:00:09] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[14:00:09] ======== drm_test_connector_hdmi_init_type_invalid ========
[14:00:09] [PASSED] Unknown
[14:00:09] [PASSED] VGA
[14:00:09] [PASSED] DVI-I
[14:00:09] [PASSED] DVI-D
[14:00:09] [PASSED] DVI-A
[14:00:09] [PASSED] Composite
[14:00:09] [PASSED] SVIDEO
[14:00:09] [PASSED] LVDS
[14:00:09] [PASSED] Component
[14:00:09] [PASSED] DIN
[14:00:09] [PASSED] DP
[14:00:09] [PASSED] TV
[14:00:09] [PASSED] eDP
[14:00:09] [PASSED] Virtual
[14:00:09] [PASSED] DSI
[14:00:09] [PASSED] DPI
[14:00:09] [PASSED] Writeback
[14:00:09] [PASSED] SPI
[14:00:09] [PASSED] USB
[14:00:09] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[14:00:09] ============ [PASSED] drmm_connector_hdmi_init =============
[14:00:09] ============= drmm_connector_init (3 subtests) =============
[14:00:09] [PASSED] drm_test_drmm_connector_init
[14:00:09] [PASSED] drm_test_drmm_connector_init_null_ddc
[14:00:09] ========= drm_test_drmm_connector_init_type_valid =========
[14:00:09] [PASSED] Unknown
[14:00:09] [PASSED] VGA
[14:00:09] [PASSED] DVI-I
[14:00:09] [PASSED] DVI-D
[14:00:09] [PASSED] DVI-A
[14:00:09] [PASSED] Composite
[14:00:09] [PASSED] SVIDEO
[14:00:09] [PASSED] LVDS
[14:00:09] [PASSED] Component
[14:00:09] [PASSED] DIN
[14:00:09] [PASSED] DP
[14:00:09] [PASSED] HDMI-A
[14:00:09] [PASSED] HDMI-B
[14:00:09] [PASSED] TV
[14:00:09] [PASSED] eDP
[14:00:09] [PASSED] Virtual
[14:00:09] [PASSED] DSI
[14:00:09] [PASSED] DPI
[14:00:09] [PASSED] Writeback
[14:00:09] [PASSED] SPI
[14:00:09] [PASSED] USB
[14:00:09] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[14:00:09] =============== [PASSED] drmm_connector_init ===============
[14:00:09] ========= drm_connector_dynamic_init (6 subtests) ==========
[14:00:09] [PASSED] drm_test_drm_connector_dynamic_init
[14:00:09] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[14:00:09] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[14:00:09] [PASSED] drm_test_drm_connector_dynamic_init_properties
[14:00:09] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[14:00:09] [PASSED] Unknown
[14:00:09] [PASSED] VGA
[14:00:09] [PASSED] DVI-I
[14:00:09] [PASSED] DVI-D
[14:00:09] [PASSED] DVI-A
[14:00:09] [PASSED] Composite
[14:00:09] [PASSED] SVIDEO
[14:00:09] [PASSED] LVDS
[14:00:09] [PASSED] Component
[14:00:09] [PASSED] DIN
[14:00:09] [PASSED] DP
[14:00:09] [PASSED] HDMI-A
[14:00:09] [PASSED] HDMI-B
[14:00:09] [PASSED] TV
[14:00:09] [PASSED] eDP
[14:00:09] [PASSED] Virtual
[14:00:09] [PASSED] DSI
[14:00:09] [PASSED] DPI
[14:00:09] [PASSED] Writeback
[14:00:09] [PASSED] SPI
[14:00:09] [PASSED] USB
[14:00:09] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[14:00:09] ======== drm_test_drm_connector_dynamic_init_name =========
[14:00:09] [PASSED] Unknown
[14:00:09] [PASSED] VGA
[14:00:09] [PASSED] DVI-I
[14:00:09] [PASSED] DVI-D
[14:00:09] [PASSED] DVI-A
[14:00:09] [PASSED] Composite
[14:00:09] [PASSED] SVIDEO
[14:00:09] [PASSED] LVDS
[14:00:09] [PASSED] Component
[14:00:09] [PASSED] DIN
[14:00:09] [PASSED] DP
[14:00:09] [PASSED] HDMI-A
[14:00:09] [PASSED] HDMI-B
[14:00:09] [PASSED] TV
[14:00:09] [PASSED] eDP
[14:00:09] [PASSED] Virtual
[14:00:09] [PASSED] DSI
[14:00:09] [PASSED] DPI
[14:00:09] [PASSED] Writeback
[14:00:09] [PASSED] SPI
[14:00:09] [PASSED] USB
[14:00:09] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[14:00:09] =========== [PASSED] drm_connector_dynamic_init ============
[14:00:09] ==== drm_connector_dynamic_register_early (4 subtests) =====
[14:00:09] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[14:00:09] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[14:00:09] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[14:00:09] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[14:00:09] ====== [PASSED] drm_connector_dynamic_register_early =======
[14:00:09] ======= drm_connector_dynamic_register (7 subtests) ========
[14:00:09] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[14:00:09] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[14:00:09] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[14:00:09] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[14:00:09] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[14:00:09] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[14:00:09] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[14:00:09] ========= [PASSED] drm_connector_dynamic_register ==========
[14:00:09] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[14:00:09] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[14:00:09] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[14:00:09] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[14:00:09] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[14:00:09] ========== drm_test_get_tv_mode_from_name_valid ===========
[14:00:09] [PASSED] NTSC
[14:00:09] [PASSED] NTSC-443
[14:00:09] [PASSED] NTSC-J
[14:00:09] [PASSED] PAL
[14:00:09] [PASSED] PAL-M
[14:00:09] [PASSED] PAL-N
[14:00:09] [PASSED] SECAM
[14:00:09] [PASSED] Mono
[14:00:09] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[14:00:09] [PASSED] drm_test_get_tv_mode_from_name_truncated
[14:00:09] ============ [PASSED] drm_get_tv_mode_from_name ============
[14:00:09] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[14:00:09] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[14:00:09] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[14:00:09] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[14:00:09] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[14:00:09] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[14:00:09] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[14:00:09] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[14:00:09] [PASSED] VIC 96
[14:00:09] [PASSED] VIC 97
[14:00:09] [PASSED] VIC 101
[14:00:09] [PASSED] VIC 102
[14:00:09] [PASSED] VIC 106
[14:00:09] [PASSED] VIC 107
[14:00:09] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[14:00:09] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[14:00:09] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[14:00:09] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[14:00:09] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[14:00:09] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[14:00:09] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[14:00:09] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[14:00:09] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[14:00:09] [PASSED] Automatic
[14:00:09] [PASSED] Full
[14:00:09] [PASSED] Limited 16:235
[14:00:09] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[14:00:09] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[14:00:09] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[14:00:09] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[14:00:09] === drm_test_drm_hdmi_connector_get_output_format_name ====
[14:00:09] [PASSED] RGB
[14:00:09] [PASSED] YUV 4:2:0
[14:00:09] [PASSED] YUV 4:2:2
[14:00:09] [PASSED] YUV 4:4:4
[14:00:09] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[14:00:09] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[14:00:09] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[14:00:09] ============= drm_damage_helper (21 subtests) ==============
[14:00:09] [PASSED] drm_test_damage_iter_no_damage
[14:00:09] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[14:00:09] [PASSED] drm_test_damage_iter_no_damage_src_moved
[14:00:09] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[14:00:09] [PASSED] drm_test_damage_iter_no_damage_not_visible
[14:00:09] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[14:00:09] [PASSED] drm_test_damage_iter_no_damage_no_fb
[14:00:09] [PASSED] drm_test_damage_iter_simple_damage
[14:00:09] [PASSED] drm_test_damage_iter_single_damage
[14:00:09] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[14:00:09] [PASSED] drm_test_damage_iter_single_damage_outside_src
[14:00:09] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[14:00:09] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[14:00:09] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[14:00:09] [PASSED] drm_test_damage_iter_single_damage_src_moved
[14:00:09] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[14:00:09] [PASSED] drm_test_damage_iter_damage
[14:00:09] [PASSED] drm_test_damage_iter_damage_one_intersect
[14:00:09] [PASSED] drm_test_damage_iter_damage_one_outside
[14:00:09] [PASSED] drm_test_damage_iter_damage_src_moved
[14:00:09] [PASSED] drm_test_damage_iter_damage_not_visible
[14:00:09] ================ [PASSED] drm_damage_helper ================
[14:00:09] ============== drm_dp_mst_helper (3 subtests) ==============
[14:00:09] ============== drm_test_dp_mst_calc_pbn_mode ==============
[14:00:09] [PASSED] Clock 154000 BPP 30 DSC disabled
[14:00:09] [PASSED] Clock 234000 BPP 30 DSC disabled
[14:00:09] [PASSED] Clock 297000 BPP 24 DSC disabled
[14:00:09] [PASSED] Clock 332880 BPP 24 DSC enabled
[14:00:09] [PASSED] Clock 324540 BPP 24 DSC enabled
[14:00:09] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[14:00:09] ============== drm_test_dp_mst_calc_pbn_div ===============
[14:00:09] [PASSED] Link rate 2000000 lane count 4
[14:00:09] [PASSED] Link rate 2000000 lane count 2
[14:00:09] [PASSED] Link rate 2000000 lane count 1
[14:00:09] [PASSED] Link rate 1350000 lane count 4
[14:00:09] [PASSED] Link rate 1350000 lane count 2
[14:00:09] [PASSED] Link rate 1350000 lane count 1
[14:00:09] [PASSED] Link rate 1000000 lane count 4
[14:00:09] [PASSED] Link rate 1000000 lane count 2
[14:00:09] [PASSED] Link rate 1000000 lane count 1
[14:00:09] [PASSED] Link rate 810000 lane count 4
[14:00:09] [PASSED] Link rate 810000 lane count 2
[14:00:09] [PASSED] Link rate 810000 lane count 1
[14:00:09] [PASSED] Link rate 540000 lane count 4
[14:00:09] [PASSED] Link rate 540000 lane count 2
[14:00:09] [PASSED] Link rate 540000 lane count 1
[14:00:09] [PASSED] Link rate 270000 lane count 4
[14:00:09] [PASSED] Link rate 270000 lane count 2
[14:00:09] [PASSED] Link rate 270000 lane count 1
[14:00:09] [PASSED] Link rate 162000 lane count 4
[14:00:09] [PASSED] Link rate 162000 lane count 2
[14:00:09] [PASSED] Link rate 162000 lane count 1
[14:00:09] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[14:00:09] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[14:00:09] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[14:00:09] [PASSED] DP_POWER_UP_PHY with port number
[14:00:09] [PASSED] DP_POWER_DOWN_PHY with port number
[14:00:09] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[14:00:09] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[14:00:09] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[14:00:09] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[14:00:09] [PASSED] DP_QUERY_PAYLOAD with port number
[14:00:09] [PASSED] DP_QUERY_PAYLOAD with VCPI
[14:00:09] [PASSED] DP_REMOTE_DPCD_READ with port number
[14:00:09] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[14:00:09] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[14:00:09] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[14:00:09] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[14:00:09] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[14:00:09] [PASSED] DP_REMOTE_I2C_READ with port number
[14:00:09] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[14:00:09] [PASSED] DP_REMOTE_I2C_READ with transactions array
[14:00:09] [PASSED] DP_REMOTE_I2C_WRITE with port number
[14:00:09] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[14:00:09] [PASSED] DP_REMOTE_I2C_WRITE with data array
[14:00:09] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[14:00:09] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[14:00:09] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[14:00:09] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[14:00:09] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[14:00:09] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[14:00:09] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[14:00:09] ================ [PASSED] drm_dp_mst_helper ================
[14:00:09] ================== drm_exec (7 subtests) ===================
[14:00:09] [PASSED] sanitycheck
[14:00:09] [PASSED] test_lock
[14:00:09] [PASSED] test_lock_unlock
[14:00:09] [PASSED] test_duplicates
[14:00:09] [PASSED] test_prepare
[14:00:09] [PASSED] test_prepare_array
[14:00:09] [PASSED] test_multiple_loops
[14:00:09] ==================== [PASSED] drm_exec =====================
[14:00:09] =========== drm_format_helper_test (17 subtests) ===========
[14:00:09] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[14:00:09] [PASSED] single_pixel_source_buffer
[14:00:09] [PASSED] single_pixel_clip_rectangle
[14:00:09] [PASSED] well_known_colors
[14:00:09] [PASSED] destination_pitch
[14:00:09] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[14:00:09] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[14:00:09] [PASSED] single_pixel_source_buffer
[14:00:09] [PASSED] single_pixel_clip_rectangle
[14:00:09] [PASSED] well_known_colors
[14:00:09] [PASSED] destination_pitch
[14:00:09] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[14:00:09] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[14:00:09] [PASSED] single_pixel_source_buffer
[14:00:09] [PASSED] single_pixel_clip_rectangle
[14:00:09] [PASSED] well_known_colors
[14:00:09] [PASSED] destination_pitch
[14:00:09] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[14:00:09] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[14:00:09] [PASSED] single_pixel_source_buffer
[14:00:09] [PASSED] single_pixel_clip_rectangle
[14:00:09] [PASSED] well_known_colors
[14:00:09] [PASSED] destination_pitch
[14:00:09] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[14:00:09] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[14:00:09] [PASSED] single_pixel_source_buffer
[14:00:09] [PASSED] single_pixel_clip_rectangle
[14:00:09] [PASSED] well_known_colors
[14:00:09] [PASSED] destination_pitch
[14:00:09] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[14:00:09] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[14:00:09] [PASSED] single_pixel_source_buffer
[14:00:09] [PASSED] single_pixel_clip_rectangle
[14:00:09] [PASSED] well_known_colors
[14:00:09] [PASSED] destination_pitch
[14:00:09] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[14:00:09] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[14:00:09] [PASSED] single_pixel_source_buffer
[14:00:09] [PASSED] single_pixel_clip_rectangle
[14:00:09] [PASSED] well_known_colors
[14:00:09] [PASSED] destination_pitch
[14:00:09] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[14:00:09] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[14:00:09] [PASSED] single_pixel_source_buffer
[14:00:09] [PASSED] single_pixel_clip_rectangle
[14:00:09] [PASSED] well_known_colors
[14:00:09] [PASSED] destination_pitch
[14:00:09] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[14:00:09] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[14:00:09] [PASSED] single_pixel_source_buffer
[14:00:09] [PASSED] single_pixel_clip_rectangle
[14:00:09] [PASSED] well_known_colors
[14:00:09] [PASSED] destination_pitch
[14:00:09] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[14:00:09] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[14:00:09] [PASSED] single_pixel_source_buffer
[14:00:09] [PASSED] single_pixel_clip_rectangle
[14:00:09] [PASSED] well_known_colors
[14:00:09] [PASSED] destination_pitch
[14:00:09] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[14:00:09] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[14:00:09] [PASSED] single_pixel_source_buffer
[14:00:09] [PASSED] single_pixel_clip_rectangle
[14:00:09] [PASSED] well_known_colors
[14:00:09] [PASSED] destination_pitch
[14:00:09] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[14:00:09] ============== drm_test_fb_xrgb8888_to_mono ===============
[14:00:09] [PASSED] single_pixel_source_buffer
[14:00:09] [PASSED] single_pixel_clip_rectangle
[14:00:09] [PASSED] well_known_colors
[14:00:09] [PASSED] destination_pitch
[14:00:09] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[14:00:09] ==================== drm_test_fb_swab =====================
[14:00:09] [PASSED] single_pixel_source_buffer
[14:00:09] [PASSED] single_pixel_clip_rectangle
[14:00:09] [PASSED] well_known_colors
[14:00:09] [PASSED] destination_pitch
[14:00:09] ================ [PASSED] drm_test_fb_swab =================
[14:00:09] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[14:00:09] [PASSED] single_pixel_source_buffer
[14:00:09] [PASSED] single_pixel_clip_rectangle
[14:00:09] [PASSED] well_known_colors
[14:00:09] [PASSED] destination_pitch
[14:00:09] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[14:00:09] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[14:00:09] [PASSED] single_pixel_source_buffer
[14:00:09] [PASSED] single_pixel_clip_rectangle
[14:00:09] [PASSED] well_known_colors
[14:00:09] [PASSED] destination_pitch
[14:00:09] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[14:00:09] ================= drm_test_fb_clip_offset =================
[14:00:09] [PASSED] pass through
[14:00:09] [PASSED] horizontal offset
[14:00:09] [PASSED] vertical offset
[14:00:09] [PASSED] horizontal and vertical offset
[14:00:09] [PASSED] horizontal offset (custom pitch)
[14:00:09] [PASSED] vertical offset (custom pitch)
[14:00:09] [PASSED] horizontal and vertical offset (custom pitch)
[14:00:09] ============= [PASSED] drm_test_fb_clip_offset =============
[14:00:09] =================== drm_test_fb_memcpy ====================
[14:00:09] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[14:00:09] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[14:00:09] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[14:00:09] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[14:00:09] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[14:00:09] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[14:00:09] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[14:00:09] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[14:00:09] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[14:00:09] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[14:00:09] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[14:00:09] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[14:00:09] =============== [PASSED] drm_test_fb_memcpy ================
[14:00:09] ============= [PASSED] drm_format_helper_test ==============
[14:00:09] ================= drm_format (18 subtests) =================
[14:00:09] [PASSED] drm_test_format_block_width_invalid
[14:00:09] [PASSED] drm_test_format_block_width_one_plane
[14:00:09] [PASSED] drm_test_format_block_width_two_plane
[14:00:09] [PASSED] drm_test_format_block_width_three_plane
[14:00:09] [PASSED] drm_test_format_block_width_tiled
[14:00:09] [PASSED] drm_test_format_block_height_invalid
[14:00:09] [PASSED] drm_test_format_block_height_one_plane
[14:00:09] [PASSED] drm_test_format_block_height_two_plane
[14:00:09] [PASSED] drm_test_format_block_height_three_plane
[14:00:09] [PASSED] drm_test_format_block_height_tiled
[14:00:09] [PASSED] drm_test_format_min_pitch_invalid
[14:00:09] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[14:00:09] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[14:00:09] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[14:00:09] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[14:00:09] [PASSED] drm_test_format_min_pitch_two_plane
[14:00:09] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[14:00:09] [PASSED] drm_test_format_min_pitch_tiled
[14:00:09] =================== [PASSED] drm_format ====================
[14:00:09] ============== drm_framebuffer (10 subtests) ===============
[14:00:09] ========== drm_test_framebuffer_check_src_coords ==========
[14:00:09] [PASSED] Success: source fits into fb
[14:00:09] [PASSED] Fail: overflowing fb with x-axis coordinate
[14:00:09] [PASSED] Fail: overflowing fb with y-axis coordinate
[14:00:09] [PASSED] Fail: overflowing fb with source width
[14:00:09] [PASSED] Fail: overflowing fb with source height
[14:00:09] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[14:00:09] [PASSED] drm_test_framebuffer_cleanup
[14:00:09] =============== drm_test_framebuffer_create ===============
[14:00:09] [PASSED] ABGR8888 normal sizes
[14:00:09] [PASSED] ABGR8888 max sizes
[14:00:09] [PASSED] ABGR8888 pitch greater than min required
[14:00:09] [PASSED] ABGR8888 pitch less than min required
[14:00:09] [PASSED] ABGR8888 Invalid width
[14:00:09] [PASSED] ABGR8888 Invalid buffer handle
[14:00:09] [PASSED] No pixel format
[14:00:09] [PASSED] ABGR8888 Width 0
[14:00:09] [PASSED] ABGR8888 Height 0
[14:00:09] [PASSED] ABGR8888 Out of bound height * pitch combination
[14:00:09] [PASSED] ABGR8888 Large buffer offset
[14:00:09] [PASSED] ABGR8888 Buffer offset for inexistent plane
[14:00:09] [PASSED] ABGR8888 Invalid flag
[14:00:09] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[14:00:09] [PASSED] ABGR8888 Valid buffer modifier
[14:00:09] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[14:00:09] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[14:00:09] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[14:00:09] [PASSED] NV12 Normal sizes
[14:00:09] [PASSED] NV12 Max sizes
[14:00:09] [PASSED] NV12 Invalid pitch
[14:00:09] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[14:00:09] [PASSED] NV12 different modifier per-plane
[14:00:09] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[14:00:09] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[14:00:09] [PASSED] NV12 Modifier for inexistent plane
[14:00:09] [PASSED] NV12 Handle for inexistent plane
[14:00:09] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[14:00:09] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[14:00:09] [PASSED] YVU420 Normal sizes
[14:00:09] [PASSED] YVU420 Max sizes
[14:00:09] [PASSED] YVU420 Invalid pitch
[14:00:09] [PASSED] YVU420 Different pitches
[14:00:09] [PASSED] YVU420 Different buffer offsets/pitches
[14:00:09] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[14:00:09] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[14:00:09] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[14:00:09] [PASSED] YVU420 Valid modifier
[14:00:09] [PASSED] YVU420 Different modifiers per plane
[14:00:09] [PASSED] YVU420 Modifier for inexistent plane
[14:00:09] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[14:00:09] [PASSED] X0L2 Normal sizes
[14:00:09] [PASSED] X0L2 Max sizes
[14:00:09] [PASSED] X0L2 Invalid pitch
[14:00:09] [PASSED] X0L2 Pitch greater than minimum required
[14:00:09] [PASSED] X0L2 Handle for inexistent plane
[14:00:09] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[14:00:09] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[14:00:09] [PASSED] X0L2 Valid modifier
[14:00:09] [PASSED] X0L2 Modifier for inexistent plane
[14:00:09] =========== [PASSED] drm_test_framebuffer_create ===========
[14:00:09] [PASSED] drm_test_framebuffer_free
[14:00:09] [PASSED] drm_test_framebuffer_init
[14:00:09] [PASSED] drm_test_framebuffer_init_bad_format
[14:00:09] [PASSED] drm_test_framebuffer_init_dev_mismatch
[14:00:09] [PASSED] drm_test_framebuffer_lookup
[14:00:09] [PASSED] drm_test_framebuffer_lookup_inexistent
[14:00:09] [PASSED] drm_test_framebuffer_modifiers_not_supported
[14:00:09] ================= [PASSED] drm_framebuffer =================
[14:00:09] ================ drm_gem_shmem (8 subtests) ================
[14:00:09] [PASSED] drm_gem_shmem_test_obj_create
[14:00:09] [PASSED] drm_gem_shmem_test_obj_create_private
[14:00:09] [PASSED] drm_gem_shmem_test_pin_pages
[14:00:09] [PASSED] drm_gem_shmem_test_vmap
[14:00:09] [PASSED] drm_gem_shmem_test_get_pages_sgt
[14:00:09] [PASSED] drm_gem_shmem_test_get_sg_table
[14:00:09] [PASSED] drm_gem_shmem_test_madvise
[14:00:09] [PASSED] drm_gem_shmem_test_purge
[14:00:09] ================== [PASSED] drm_gem_shmem ==================
[14:00:09] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[14:00:09] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[14:00:09] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[14:00:09] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[14:00:09] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[14:00:09] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[14:00:09] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[14:00:09] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[14:00:09] [PASSED] Automatic
[14:00:09] [PASSED] Full
[14:00:09] [PASSED] Limited 16:235
[14:00:09] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[14:00:09] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[14:00:09] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[14:00:09] [PASSED] drm_test_check_disable_connector
[14:00:09] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[14:00:09] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[14:00:09] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[14:00:09] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[14:00:09] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[14:00:09] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[14:00:09] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[14:00:09] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[14:00:09] [PASSED] drm_test_check_output_bpc_dvi
[14:00:09] [PASSED] drm_test_check_output_bpc_format_vic_1
[14:00:09] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[14:00:09] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[14:00:09] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[14:00:09] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[14:00:09] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[14:00:09] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[14:00:09] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[14:00:09] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[14:00:09] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[14:00:09] [PASSED] drm_test_check_broadcast_rgb_value
[14:00:09] [PASSED] drm_test_check_bpc_8_value
[14:00:09] [PASSED] drm_test_check_bpc_10_value
[14:00:09] [PASSED] drm_test_check_bpc_12_value
[14:00:09] [PASSED] drm_test_check_format_value
[14:00:09] [PASSED] drm_test_check_tmds_char_value
[14:00:09] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[14:00:09] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[14:00:09] [PASSED] drm_test_check_mode_valid
[14:00:09] [PASSED] drm_test_check_mode_valid_reject
[14:00:09] [PASSED] drm_test_check_mode_valid_reject_rate
[14:00:09] [PASSED] drm_test_check_mode_valid_reject_max_clock
[14:00:09] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[14:00:09] ================= drm_managed (2 subtests) =================
[14:00:09] [PASSED] drm_test_managed_release_action
[14:00:09] [PASSED] drm_test_managed_run_action
[14:00:09] =================== [PASSED] drm_managed ===================
[14:00:09] =================== drm_mm (6 subtests) ====================
[14:00:09] [PASSED] drm_test_mm_init
[14:00:09] [PASSED] drm_test_mm_debug
[14:00:09] [PASSED] drm_test_mm_align32
[14:00:09] [PASSED] drm_test_mm_align64
[14:00:09] [PASSED] drm_test_mm_lowest
[14:00:09] [PASSED] drm_test_mm_highest
[14:00:09] ===================== [PASSED] drm_mm ======================
[14:00:09] ============= drm_modes_analog_tv (5 subtests) =============
[14:00:09] [PASSED] drm_test_modes_analog_tv_mono_576i
[14:00:09] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[14:00:09] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[14:00:09] [PASSED] drm_test_modes_analog_tv_pal_576i
[14:00:09] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[14:00:09] =============== [PASSED] drm_modes_analog_tv ===============
[14:00:09] ============== drm_plane_helper (2 subtests) ===============
[14:00:09] =============== drm_test_check_plane_state ================
[14:00:09] [PASSED] clipping_simple
[14:00:09] [PASSED] clipping_rotate_reflect
[14:00:09] [PASSED] positioning_simple
[14:00:09] [PASSED] upscaling
[14:00:09] [PASSED] downscaling
[14:00:09] [PASSED] rounding1
[14:00:09] [PASSED] rounding2
[14:00:09] [PASSED] rounding3
[14:00:09] [PASSED] rounding4
[14:00:09] =========== [PASSED] drm_test_check_plane_state ============
[14:00:09] =========== drm_test_check_invalid_plane_state ============
[14:00:09] [PASSED] positioning_invalid
[14:00:09] [PASSED] upscaling_invalid
[14:00:09] [PASSED] downscaling_invalid
[14:00:09] ======= [PASSED] drm_test_check_invalid_plane_state ========
[14:00:09] ================ [PASSED] drm_plane_helper =================
[14:00:09] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[14:00:09] ====== drm_test_connector_helper_tv_get_modes_check =======
[14:00:09] [PASSED] None
[14:00:09] [PASSED] PAL
[14:00:09] [PASSED] NTSC
[14:00:09] [PASSED] Both, NTSC Default
[14:00:09] [PASSED] Both, PAL Default
[14:00:09] [PASSED] Both, NTSC Default, with PAL on command-line
[14:00:09] [PASSED] Both, PAL Default, with NTSC on command-line
[14:00:09] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[14:00:09] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[14:00:09] ================== drm_rect (9 subtests) ===================
[14:00:09] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[14:00:09] [PASSED] drm_test_rect_clip_scaled_not_clipped
[14:00:09] [PASSED] drm_test_rect_clip_scaled_clipped
[14:00:09] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[14:00:09] ================= drm_test_rect_intersect =================
[14:00:09] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[14:00:09] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[14:00:09] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[14:00:09] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[14:00:09] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[14:00:09] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[14:00:09] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[14:00:09] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[14:00:09] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[14:00:09] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[14:00:09] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[14:00:09] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[14:00:09] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[14:00:09] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[14:00:09] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[14:00:09] ============= [PASSED] drm_test_rect_intersect =============
[14:00:09] ================ drm_test_rect_calc_hscale ================
[14:00:09] [PASSED] normal use
[14:00:09] [PASSED] out of max range
[14:00:09] [PASSED] out of min range
[14:00:09] [PASSED] zero dst
[14:00:09] [PASSED] negative src
[14:00:09] [PASSED] negative dst
[14:00:09] ============ [PASSED] drm_test_rect_calc_hscale ============
[14:00:09] ================ drm_test_rect_calc_vscale ================
[14:00:09] [PASSED] normal use
[14:00:09] [PASSED] out of max range
[14:00:09] [PASSED] out of min range
[14:00:09] [PASSED] zero dst
[14:00:09] [PASSED] negative src
[14:00:09] [PASSED] negative dst
[14:00:09] ============ [PASSED] drm_test_rect_calc_vscale ============
[14:00:09] ================== drm_test_rect_rotate ===================
[14:00:09] [PASSED] reflect-x
[14:00:09] [PASSED] reflect-y
[14:00:09] [PASSED] rotate-0
[14:00:09] [PASSED] rotate-90
[14:00:09] [PASSED] rotate-180
[14:00:09] [PASSED] rotate-270
stty: 'standard input': Inappropriate ioctl for device
[14:00:09] ============== [PASSED] drm_test_rect_rotate ===============
[14:00:09] ================ drm_test_rect_rotate_inv =================
[14:00:09] [PASSED] reflect-x
[14:00:09] [PASSED] reflect-y
[14:00:09] [PASSED] rotate-0
[14:00:09] [PASSED] rotate-90
[14:00:09] [PASSED] rotate-180
[14:00:09] [PASSED] rotate-270
[14:00:09] ============ [PASSED] drm_test_rect_rotate_inv =============
[14:00:09] ==================== [PASSED] drm_rect =====================
[14:00:09] ============ drm_sysfb_modeset_test (1 subtest) ============
[14:00:09] ============ drm_test_sysfb_build_fourcc_list =============
[14:00:09] [PASSED] no native formats
[14:00:09] [PASSED] XRGB8888 as native format
[14:00:09] [PASSED] remove duplicates
[14:00:09] [PASSED] convert alpha formats
[14:00:09] [PASSED] random formats
[14:00:09] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[14:00:09] ============= [PASSED] drm_sysfb_modeset_test ==============
[14:00:09] ============================================================
[14:00:09] Testing complete. Ran 616 tests: passed: 616
[14:00:09] Elapsed time: 27.518s total, 1.605s configuring, 25.694s building, 0.185s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[14:00:09] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[14:00:11] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[14:00:18] Starting KUnit Kernel (1/1)...
[14:00:18] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[14:00:19] ================= ttm_device (5 subtests) ==================
[14:00:19] [PASSED] ttm_device_init_basic
[14:00:19] [PASSED] ttm_device_init_multiple
[14:00:19] [PASSED] ttm_device_fini_basic
[14:00:19] [PASSED] ttm_device_init_no_vma_man
[14:00:19] ================== ttm_device_init_pools ==================
[14:00:19] [PASSED] No DMA allocations, no DMA32 required
[14:00:19] [PASSED] DMA allocations, DMA32 required
[14:00:19] [PASSED] No DMA allocations, DMA32 required
[14:00:19] [PASSED] DMA allocations, no DMA32 required
[14:00:19] ============== [PASSED] ttm_device_init_pools ==============
[14:00:19] =================== [PASSED] ttm_device ====================
[14:00:19] ================== ttm_pool (8 subtests) ===================
[14:00:19] ================== ttm_pool_alloc_basic ===================
[14:00:19] [PASSED] One page
[14:00:19] [PASSED] More than one page
[14:00:19] [PASSED] Above the allocation limit
[14:00:19] [PASSED] One page, with coherent DMA mappings enabled
[14:00:19] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[14:00:19] ============== [PASSED] ttm_pool_alloc_basic ===============
[14:00:19] ============== ttm_pool_alloc_basic_dma_addr ==============
[14:00:19] [PASSED] One page
[14:00:19] [PASSED] More than one page
[14:00:19] [PASSED] Above the allocation limit
[14:00:19] [PASSED] One page, with coherent DMA mappings enabled
[14:00:19] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[14:00:19] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[14:00:19] [PASSED] ttm_pool_alloc_order_caching_match
[14:00:19] [PASSED] ttm_pool_alloc_caching_mismatch
[14:00:19] [PASSED] ttm_pool_alloc_order_mismatch
[14:00:19] [PASSED] ttm_pool_free_dma_alloc
[14:00:19] [PASSED] ttm_pool_free_no_dma_alloc
[14:00:19] [PASSED] ttm_pool_fini_basic
[14:00:19] ==================== [PASSED] ttm_pool =====================
[14:00:19] ================ ttm_resource (8 subtests) =================
[14:00:19] ================= ttm_resource_init_basic =================
[14:00:19] [PASSED] Init resource in TTM_PL_SYSTEM
[14:00:19] [PASSED] Init resource in TTM_PL_VRAM
[14:00:19] [PASSED] Init resource in a private placement
[14:00:19] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[14:00:19] ============= [PASSED] ttm_resource_init_basic =============
[14:00:19] [PASSED] ttm_resource_init_pinned
[14:00:19] [PASSED] ttm_resource_fini_basic
[14:00:19] [PASSED] ttm_resource_manager_init_basic
[14:00:19] [PASSED] ttm_resource_manager_usage_basic
[14:00:19] [PASSED] ttm_resource_manager_set_used_basic
[14:00:19] [PASSED] ttm_sys_man_alloc_basic
[14:00:19] [PASSED] ttm_sys_man_free_basic
[14:00:19] ================== [PASSED] ttm_resource ===================
[14:00:19] =================== ttm_tt (15 subtests) ===================
[14:00:19] ==================== ttm_tt_init_basic ====================
[14:00:19] [PASSED] Page-aligned size
[14:00:19] [PASSED] Extra pages requested
[14:00:19] ================ [PASSED] ttm_tt_init_basic ================
[14:00:19] [PASSED] ttm_tt_init_misaligned
[14:00:19] [PASSED] ttm_tt_fini_basic
[14:00:19] [PASSED] ttm_tt_fini_sg
[14:00:19] [PASSED] ttm_tt_fini_shmem
[14:00:19] [PASSED] ttm_tt_create_basic
[14:00:19] [PASSED] ttm_tt_create_invalid_bo_type
[14:00:19] [PASSED] ttm_tt_create_ttm_exists
[14:00:19] [PASSED] ttm_tt_create_failed
[14:00:19] [PASSED] ttm_tt_destroy_basic
[14:00:19] [PASSED] ttm_tt_populate_null_ttm
[14:00:19] [PASSED] ttm_tt_populate_populated_ttm
[14:00:19] [PASSED] ttm_tt_unpopulate_basic
[14:00:19] [PASSED] ttm_tt_unpopulate_empty_ttm
[14:00:19] [PASSED] ttm_tt_swapin_basic
[14:00:19] ===================== [PASSED] ttm_tt ======================
[14:00:19] =================== ttm_bo (14 subtests) ===================
[14:00:19] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[14:00:19] [PASSED] Cannot be interrupted and sleeps
[14:00:19] [PASSED] Cannot be interrupted, locks straight away
[14:00:19] [PASSED] Can be interrupted, sleeps
[14:00:19] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[14:00:19] [PASSED] ttm_bo_reserve_locked_no_sleep
[14:00:19] [PASSED] ttm_bo_reserve_no_wait_ticket
[14:00:19] [PASSED] ttm_bo_reserve_double_resv
[14:00:19] [PASSED] ttm_bo_reserve_interrupted
[14:00:19] [PASSED] ttm_bo_reserve_deadlock
[14:00:19] [PASSED] ttm_bo_unreserve_basic
[14:00:19] [PASSED] ttm_bo_unreserve_pinned
[14:00:19] [PASSED] ttm_bo_unreserve_bulk
[14:00:19] [PASSED] ttm_bo_put_basic
[14:00:19] [PASSED] ttm_bo_put_shared_resv
[14:00:19] [PASSED] ttm_bo_pin_basic
[14:00:19] [PASSED] ttm_bo_pin_unpin_resource
[14:00:19] [PASSED] ttm_bo_multiple_pin_one_unpin
[14:00:19] ===================== [PASSED] ttm_bo ======================
[14:00:19] ============== ttm_bo_validate (21 subtests) ===============
[14:00:19] ============== ttm_bo_init_reserved_sys_man ===============
[14:00:19] [PASSED] Buffer object for userspace
[14:00:19] [PASSED] Kernel buffer object
[14:00:19] [PASSED] Shared buffer object
[14:00:19] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[14:00:19] ============== ttm_bo_init_reserved_mock_man ==============
[14:00:19] [PASSED] Buffer object for userspace
[14:00:19] [PASSED] Kernel buffer object
[14:00:19] [PASSED] Shared buffer object
[14:00:19] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[14:00:19] [PASSED] ttm_bo_init_reserved_resv
[14:00:19] ================== ttm_bo_validate_basic ==================
[14:00:19] [PASSED] Buffer object for userspace
[14:00:19] [PASSED] Kernel buffer object
[14:00:19] [PASSED] Shared buffer object
[14:00:19] ============== [PASSED] ttm_bo_validate_basic ==============
[14:00:19] [PASSED] ttm_bo_validate_invalid_placement
[14:00:19] ============= ttm_bo_validate_same_placement ==============
[14:00:19] [PASSED] System manager
[14:00:19] [PASSED] VRAM manager
[14:00:19] ========= [PASSED] ttm_bo_validate_same_placement ==========
[14:00:19] [PASSED] ttm_bo_validate_failed_alloc
[14:00:19] [PASSED] ttm_bo_validate_pinned
[14:00:19] [PASSED] ttm_bo_validate_busy_placement
[14:00:19] ================ ttm_bo_validate_multihop =================
[14:00:19] [PASSED] Buffer object for userspace
[14:00:19] [PASSED] Kernel buffer object
[14:00:19] [PASSED] Shared buffer object
[14:00:19] ============ [PASSED] ttm_bo_validate_multihop =============
[14:00:19] ========== ttm_bo_validate_no_placement_signaled ==========
[14:00:19] [PASSED] Buffer object in system domain, no page vector
[14:00:19] [PASSED] Buffer object in system domain with an existing page vector
[14:00:19] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[14:00:19] ======== ttm_bo_validate_no_placement_not_signaled ========
[14:00:19] [PASSED] Buffer object for userspace
[14:00:19] [PASSED] Kernel buffer object
[14:00:19] [PASSED] Shared buffer object
[14:00:19] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[14:00:19] [PASSED] ttm_bo_validate_move_fence_signaled
[14:00:19] ========= ttm_bo_validate_move_fence_not_signaled =========
[14:00:19] [PASSED] Waits for GPU
[14:00:19] [PASSED] Tries to lock straight away
[14:00:19] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[14:00:19] [PASSED] ttm_bo_validate_happy_evict
[14:00:19] [PASSED] ttm_bo_validate_all_pinned_evict
[14:00:19] [PASSED] ttm_bo_validate_allowed_only_evict
[14:00:19] [PASSED] ttm_bo_validate_deleted_evict
[14:00:19] [PASSED] ttm_bo_validate_busy_domain_evict
[14:00:19] [PASSED] ttm_bo_validate_evict_gutting
[14:00:19] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[14:00:19] ================= [PASSED] ttm_bo_validate =================
[14:00:19] ============================================================
[14:00:19] Testing complete. Ran 101 tests: passed: 101
[14:00:19] Elapsed time: 9.523s total, 1.573s configuring, 7.683s building, 0.228s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 14+ messages in thread
* ✗ Xe.CI.BAT: failure for drm/ttm: WIP limit the TTM pool to 32bit CPUs
2025-08-06 13:28 [PATCH] drm/ttm: WIP limit the TTM pool to 32bit CPUs Christian König
2025-08-06 13:58 ` ✗ CI.checkpatch: warning for " Patchwork
2025-08-06 14:00 ` ✓ CI.KUnit: success " Patchwork
@ 2025-08-06 15:07 ` Patchwork
2025-08-06 17:03 ` ✗ Xe.CI.Full: " Patchwork
` (3 subsequent siblings)
6 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2025-08-06 15:07 UTC (permalink / raw)
To: Christian König; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 4182 bytes --]
== Series Details ==
Series: drm/ttm: WIP limit the TTM pool to 32bit CPUs
URL : https://patchwork.freedesktop.org/series/152588/
State : failure
== Summary ==
CI Bug Log - changes from xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802_BAT -> xe-pw-152588v1_BAT
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-152588v1_BAT absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-152588v1_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (10 -> 9)
------------------------------
Missing (1): bat-adlp-vm
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-152588v1_BAT:
### IGT changes ###
#### Possible regressions ####
* igt@kms_pipe_crc_basic@hang-read-crc@pipe-a-edp-1:
- bat-adlp-7: [PASS][1] -> [FAIL][2] +26 other tests fail
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/bat-adlp-7/igt@kms_pipe_crc_basic@hang-read-crc@pipe-a-edp-1.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/bat-adlp-7/igt@kms_pipe_crc_basic@hang-read-crc@pipe-a-edp-1.html
* igt@kms_pipe_crc_basic@read-crc-frame-sequence:
- bat-lnl-1: [PASS][3] -> [FAIL][4] +26 other tests fail
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/bat-lnl-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/bat-lnl-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence.html
* igt@xe_pat@pat-index-xe2@dw:
- bat-lnl-2: [PASS][5] -> [FAIL][6] +3 other tests fail
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/bat-lnl-2/igt@xe_pat@pat-index-xe2@dw.html
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/bat-lnl-2/igt@xe_pat@pat-index-xe2@dw.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_pipe_crc_basic@nonblocking-crc:
- {bat-ptl-2}: [PASS][7] -> [FAIL][8] +15 other tests fail
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/bat-ptl-2/igt@kms_pipe_crc_basic@nonblocking-crc.html
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/bat-ptl-2/igt@kms_pipe_crc_basic@nonblocking-crc.html
* igt@xe_pat@pat-index-xe2@blt:
- {bat-ptl-1}: [PASS][9] -> [FAIL][10] +5 other tests fail
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/bat-ptl-1/igt@xe_pat@pat-index-xe2@blt.html
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/bat-ptl-1/igt@xe_pat@pat-index-xe2@blt.html
Known issues
------------
Here are the changes found in xe-pw-152588v1_BAT that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_frontbuffer_tracking@basic:
- bat-adlp-7: [PASS][11] -> [FAIL][12] ([Intel XE#5671])
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/bat-adlp-7/igt@kms_frontbuffer_tracking@basic.html
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/bat-adlp-7/igt@kms_frontbuffer_tracking@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel XE#5671]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5671
Build changes
-------------
* Linux: xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802 -> xe-pw-152588v1
IGT_8487: 8487
xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802: 886b8d8ef3839f604e3e7f6187ac6c46eb21b802
xe-pw-152588v1: 152588v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/index.html
[-- Attachment #2: Type: text/html, Size: 4945 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* ✗ Xe.CI.Full: failure for drm/ttm: WIP limit the TTM pool to 32bit CPUs
2025-08-06 13:28 [PATCH] drm/ttm: WIP limit the TTM pool to 32bit CPUs Christian König
` (2 preceding siblings ...)
2025-08-06 15:07 ` ✗ Xe.CI.BAT: failure " Patchwork
@ 2025-08-06 17:03 ` Patchwork
2025-08-06 17:43 ` [PATCH] " Thomas Hellström
` (2 subsequent siblings)
6 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2025-08-06 17:03 UTC (permalink / raw)
To: Christian König; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 44547 bytes --]
== Series Details ==
Series: drm/ttm: WIP limit the TTM pool to 32bit CPUs
URL : https://patchwork.freedesktop.org/series/152588/
State : failure
== Summary ==
CI Bug Log - changes from xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802_FULL -> xe-pw-152588v1_FULL
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-152588v1_FULL absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-152588v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (4 -> 4)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-152588v1_FULL:
### IGT changes ###
#### Possible regressions ####
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt:
- shard-lnl: [PASS][1] -> [FAIL][2] +349 other tests fail
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-lnl-5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-lnl-8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-hdmi-a-1:
- shard-adlp: [PASS][3] -> [FAIL][4] +346 other tests fail
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-adlp-3/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-hdmi-a-1.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-adlp-1/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-hdmi-a-1.html
Known issues
------------
Here are the changes found in xe-pw-152588v1_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_async_flips@crc:
- shard-adlp: [PASS][5] -> [FAIL][6] ([Intel XE#1874] / [Intel XE#3884]) +1 other test fail
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-adlp-3/igt@kms_async_flips@crc.html
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-adlp-1/igt@kms_async_flips@crc.html
* igt@kms_async_flips@crc@pipe-c-hdmi-a-1:
- shard-adlp: [PASS][7] -> [FAIL][8] ([Intel XE#3884]) +7 other tests fail
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-adlp-3/igt@kms_async_flips@crc@pipe-c-hdmi-a-1.html
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-adlp-1/igt@kms_async_flips@crc@pipe-c-hdmi-a-1.html
* igt@kms_big_fb@4-tiled-32bpp-rotate-270:
- shard-dg2-set2: NOTRUN -> [SKIP][9] ([Intel XE#316]) +1 other test skip
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-dg2-464/igt@kms_big_fb@4-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-lnl: [PASS][10] -> [FAIL][11] ([Intel XE#1231]) +6 other tests fail
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-lnl-5/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-lnl-8/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
- shard-adlp: [PASS][12] -> [DMESG-FAIL][13] ([Intel XE#4543]) +1 other test dmesg-fail
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-adlp-4/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-adlp-6/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-270:
- shard-dg2-set2: NOTRUN -> [SKIP][14] ([Intel XE#1124]) +2 other tests skip
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-dg2-463/igt@kms_big_fb@yf-tiled-16bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-0:
- shard-bmg: NOTRUN -> [SKIP][15] ([Intel XE#1124]) +4 other tests skip
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-bmg-7/igt@kms_big_fb@yf-tiled-32bpp-rotate-0.html
* igt@kms_bw@connected-linear-tiling-3-displays-3840x2160p:
- shard-dg2-set2: NOTRUN -> [SKIP][16] ([Intel XE#2191])
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-dg2-464/igt@kms_bw@connected-linear-tiling-3-displays-3840x2160p.html
* igt@kms_bw@connected-linear-tiling-4-displays-3840x2160p:
- shard-bmg: NOTRUN -> [SKIP][17] ([Intel XE#2314] / [Intel XE#2894])
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-bmg-7/igt@kms_bw@connected-linear-tiling-4-displays-3840x2160p.html
* igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs:
- shard-bmg: NOTRUN -> [SKIP][18] ([Intel XE#2887])
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-bmg-7/igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs.html
* igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-6:
- shard-dg2-set2: NOTRUN -> [SKIP][19] ([Intel XE#787]) +160 other tests skip
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-dg2-466/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-6.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
- shard-dg2-set2: NOTRUN -> [INCOMPLETE][20] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4522]) +1 other test incomplete
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-dp-2:
- shard-dg2-set2: NOTRUN -> [INCOMPLETE][21] ([Intel XE#3113])
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-dp-2.html
* igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-c-dp-2:
- shard-bmg: NOTRUN -> [SKIP][22] ([Intel XE#2652] / [Intel XE#787]) +3 other tests skip
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-bmg-7/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-c-dp-2.html
* igt@kms_ccs@random-ccs-data-y-tiled-ccs@pipe-d-dp-2:
- shard-dg2-set2: NOTRUN -> [SKIP][23] ([Intel XE#455] / [Intel XE#787]) +24 other tests skip
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-dg2-432/igt@kms_ccs@random-ccs-data-y-tiled-ccs@pipe-d-dp-2.html
* igt@kms_cdclk@mode-transition@pipe-d-dp-4:
- shard-dg2-set2: NOTRUN -> [SKIP][24] ([Intel XE#4417]) +3 other tests skip
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-dg2-466/igt@kms_cdclk@mode-transition@pipe-d-dp-4.html
* igt@kms_chamelium_color@ctm-0-25:
- shard-dg2-set2: NOTRUN -> [SKIP][25] ([Intel XE#306])
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-dg2-464/igt@kms_chamelium_color@ctm-0-25.html
* igt@kms_chamelium_frames@hdmi-aspect-ratio:
- shard-dg2-set2: NOTRUN -> [SKIP][26] ([Intel XE#373]) +2 other tests skip
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-dg2-464/igt@kms_chamelium_frames@hdmi-aspect-ratio.html
* igt@kms_color@deep-color:
- shard-lnl: [PASS][27] -> [FAIL][28] ([Intel XE#2881])
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-lnl-1/igt@kms_color@deep-color.html
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-lnl-7/igt@kms_color@deep-color.html
* igt@kms_content_protection@lic-type-0@pipe-a-dp-2:
- shard-bmg: NOTRUN -> [FAIL][29] ([Intel XE#1178])
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-bmg-8/igt@kms_content_protection@lic-type-0@pipe-a-dp-2.html
* igt@kms_content_protection@srm@pipe-a-dp-4:
- shard-dg2-set2: NOTRUN -> [FAIL][30] ([Intel XE#1178]) +1 other test fail
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-dg2-466/igt@kms_content_protection@srm@pipe-a-dp-4.html
* igt@kms_content_protection@uevent@pipe-a-dp-2:
- shard-dg2-set2: NOTRUN -> [FAIL][31] ([Intel XE#1188])
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-dg2-432/igt@kms_content_protection@uevent@pipe-a-dp-2.html
* igt@kms_cursor_crc@cursor-random-512x170:
- shard-bmg: NOTRUN -> [SKIP][32] ([Intel XE#2321])
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-bmg-6/igt@kms_cursor_crc@cursor-random-512x170.html
* igt@kms_cursor_crc@cursor-sliding-max-size:
- shard-dg2-set2: NOTRUN -> [SKIP][33] ([Intel XE#455]) +3 other tests skip
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-dg2-463/igt@kms_cursor_crc@cursor-sliding-max-size.html
* igt@kms_cursor_legacy@cursora-vs-flipb-atomic:
- shard-bmg: [PASS][34] -> [SKIP][35] ([Intel XE#2291])
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-2/igt@kms_cursor_legacy@cursora-vs-flipb-atomic.html
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-bmg-6/igt@kms_cursor_legacy@cursora-vs-flipb-atomic.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2:
- shard-dg2-set2: NOTRUN -> [SKIP][36] ([Intel XE#4494])
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-dg2-432/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2.html
* igt@kms_dp_link_training@non-uhbr-mst:
- shard-bmg: NOTRUN -> [SKIP][37] ([Intel XE#4354])
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-bmg-7/igt@kms_dp_link_training@non-uhbr-mst.html
* igt@kms_draw_crc@draw-method-render@rgb565-ytiled:
- shard-adlp: [PASS][38] -> [FAIL][39] ([Intel XE#1874]) +18 other tests fail
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-adlp-1/igt@kms_draw_crc@draw-method-render@rgb565-ytiled.html
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-adlp-6/igt@kms_draw_crc@draw-method-render@rgb565-ytiled.html
* igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests:
- shard-dg2-set2: NOTRUN -> [SKIP][40] ([Intel XE#4422])
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-dg2-464/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests.html
* igt@kms_flip@2x-flip-vs-expired-vblank:
- shard-dg2-set2: [PASS][41] -> [FAIL][42] ([Intel XE#301])
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-dg2-436/igt@kms_flip@2x-flip-vs-expired-vblank.html
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-dg2-432/igt@kms_flip@2x-flip-vs-expired-vblank.html
* igt@kms_flip@2x-flip-vs-expired-vblank@ad-hdmi-a2-dp2:
- shard-dg2-set2: NOTRUN -> [FAIL][43] ([Intel XE#301])
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-dg2-432/igt@kms_flip@2x-flip-vs-expired-vblank@ad-hdmi-a2-dp2.html
* igt@kms_flip@2x-modeset-vs-vblank-race:
- shard-bmg: [PASS][44] -> [SKIP][45] ([Intel XE#2316]) +5 other tests skip
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-4/igt@kms_flip@2x-modeset-vs-vblank-race.html
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-bmg-6/igt@kms_flip@2x-modeset-vs-vblank-race.html
* igt@kms_flip@flip-vs-dpms-on-nop-interruptible:
- shard-adlp: [PASS][46] -> [DMESG-WARN][47] ([Intel XE#4543]) +5 other tests dmesg-warn
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-adlp-8/igt@kms_flip@flip-vs-dpms-on-nop-interruptible.html
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-adlp-2/igt@kms_flip@flip-vs-dpms-on-nop-interruptible.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-bmg: [PASS][48] -> [INCOMPLETE][49] ([Intel XE#2049] / [Intel XE#2597]) +1 other test incomplete
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-4/igt@kms_flip@flip-vs-suspend-interruptible.html
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-bmg-1/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling:
- shard-bmg: NOTRUN -> [SKIP][50] ([Intel XE#2293] / [Intel XE#2380])
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-bmg-7/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
- shard-bmg: NOTRUN -> [SKIP][51] ([Intel XE#2293])
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-bmg-7/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-default-mode:
- shard-lnl: [PASS][52] -> [FAIL][53] ([Intel XE#4683]) +5 other tests fail
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-lnl-5/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-default-mode.html
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-lnl-5/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-msflip-blt:
- shard-dg2-set2: NOTRUN -> [SKIP][54] ([Intel XE#651]) +6 other tests skip
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-dg2-463/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@drrs-rgb565-draw-render:
- shard-bmg: NOTRUN -> [SKIP][55] ([Intel XE#2311]) +3 other tests skip
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-bmg-7/igt@kms_frontbuffer_tracking@drrs-rgb565-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt:
- shard-adlp: [PASS][56] -> [FAIL][57] ([Intel XE#5671]) +39 other tests fail
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-adlp-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-adlp-4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-blt:
- shard-bmg: NOTRUN -> [SKIP][58] ([Intel XE#2312]) +1 other test skip
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt:
- shard-bmg: NOTRUN -> [SKIP][59] ([Intel XE#2313])
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-bmg-7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-blt:
- shard-dg2-set2: NOTRUN -> [SKIP][60] ([Intel XE#653]) +4 other tests skip
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-dg2-464/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-blt.html
* igt@kms_hdr@invalid-metadata-sizes:
- shard-bmg: [PASS][61] -> [SKIP][62] ([Intel XE#1503])
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-1/igt@kms_hdr@invalid-metadata-sizes.html
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-bmg-6/igt@kms_hdr@invalid-metadata-sizes.html
* igt@kms_mmap_write_crc@main:
- shard-lnl: [PASS][63] -> [FAIL][64] ([Intel XE#3106]) +1 other test fail
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-lnl-5/igt@kms_mmap_write_crc@main.html
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-lnl-5/igt@kms_mmap_write_crc@main.html
* igt@kms_plane@pixel-format@pipe-a-plane-3:
- shard-lnl: [PASS][65] -> [FAIL][66] ([Intel XE#5195]) +6 other tests fail
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-lnl-1/igt@kms_plane@pixel-format@pipe-a-plane-3.html
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-lnl-5/igt@kms_plane@pixel-format@pipe-a-plane-3.html
* igt@kms_plane@planar-pixel-format-settings:
- shard-adlp: [PASS][67] -> [DMESG-WARN][68] ([Intel XE#2953] / [Intel XE#4173]) +3 other tests dmesg-warn
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-adlp-8/igt@kms_plane@planar-pixel-format-settings.html
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-adlp-9/igt@kms_plane@planar-pixel-format-settings.html
* igt@kms_plane_cursor@overlay@pipe-a-edp-1-size-128:
- shard-lnl: [PASS][69] -> [FAIL][70] ([Intel XE#1874]) +17 other tests fail
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-lnl-4/igt@kms_plane_cursor@overlay@pipe-a-edp-1-size-128.html
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-lnl-8/igt@kms_plane_cursor@overlay@pipe-a-edp-1-size-128.html
* igt@kms_plane_lowres@tiling-none@pipe-c-hdmi-a-1:
- shard-adlp: [PASS][71] -> [FAIL][72] ([Intel XE#4685]) +4 other tests fail
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-adlp-2/igt@kms_plane_lowres@tiling-none@pipe-c-hdmi-a-1.html
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-adlp-3/igt@kms_plane_lowres@tiling-none@pipe-c-hdmi-a-1.html
* igt@kms_plane_multiple@tiling-4@pipe-b-edp-1:
- shard-lnl: [PASS][73] -> [FAIL][74] ([Intel XE#4658]) +6 other tests fail
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-lnl-3/igt@kms_plane_multiple@tiling-4@pipe-b-edp-1.html
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-lnl-2/igt@kms_plane_multiple@tiling-4@pipe-b-edp-1.html
* igt@kms_psr2_sf@pr-overlay-plane-update-sf-dmg-area:
- shard-bmg: NOTRUN -> [SKIP][75] ([Intel XE#1489])
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-bmg-7/igt@kms_psr2_sf@pr-overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf:
- shard-dg2-set2: NOTRUN -> [SKIP][76] ([Intel XE#1489]) +1 other test skip
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-dg2-464/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf.html
* igt@kms_psr@psr-suspend:
- shard-bmg: NOTRUN -> [SKIP][77] ([Intel XE#2234] / [Intel XE#2850])
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-bmg-6/igt@kms_psr@psr-suspend.html
* igt@kms_psr@psr2-basic:
- shard-dg2-set2: NOTRUN -> [SKIP][78] ([Intel XE#2850] / [Intel XE#929])
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-dg2-464/igt@kms_psr@psr2-basic.html
* igt@kms_setmode@basic:
- shard-bmg: [PASS][79] -> [FAIL][80] ([Intel XE#2883]) +1 other test fail
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-4/igt@kms_setmode@basic.html
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-bmg-6/igt@kms_setmode@basic.html
* igt@kms_setmode@basic@pipe-b-edp-1:
- shard-lnl: [PASS][81] -> [FAIL][82] ([Intel XE#2883]) +2 other tests fail
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-lnl-3/igt@kms_setmode@basic@pipe-b-edp-1.html
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-lnl-3/igt@kms_setmode@basic@pipe-b-edp-1.html
* igt@xe_compute_preempt@compute-preempt-many:
- shard-dg2-set2: NOTRUN -> [SKIP][83] ([Intel XE#1280] / [Intel XE#455]) +1 other test skip
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-dg2-463/igt@xe_compute_preempt@compute-preempt-many.html
* igt@xe_eu_stall@blocking-read:
- shard-bmg: [PASS][84] -> [FAIL][85] ([Intel XE#5420])
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-3/igt@xe_eu_stall@blocking-read.html
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-bmg-3/igt@xe_eu_stall@blocking-read.html
* igt@xe_eudebug@basic-connect:
- shard-bmg: NOTRUN -> [SKIP][86] ([Intel XE#4837]) +1 other test skip
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-bmg-6/igt@xe_eudebug@basic-connect.html
* igt@xe_exec_basic@multigpu-no-exec-userptr-invalidate-race:
- shard-dg2-set2: [PASS][87] -> [SKIP][88] ([Intel XE#1392]) +4 other tests skip
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-dg2-433/igt@xe_exec_basic@multigpu-no-exec-userptr-invalidate-race.html
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-dg2-432/igt@xe_exec_basic@multigpu-no-exec-userptr-invalidate-race.html
* igt@xe_exec_basic@multigpu-once-null-rebind:
- shard-bmg: NOTRUN -> [SKIP][89] ([Intel XE#2322]) +1 other test skip
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-bmg-7/igt@xe_exec_basic@multigpu-once-null-rebind.html
* igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-rebind-prefetch:
- shard-dg2-set2: NOTRUN -> [SKIP][90] ([Intel XE#288]) +1 other test skip
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-dg2-463/igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-rebind-prefetch.html
* igt@xe_exec_sip_eudebug@breakpoint-writesip-twice:
- shard-dg2-set2: NOTRUN -> [SKIP][91] ([Intel XE#4837])
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-dg2-463/igt@xe_exec_sip_eudebug@breakpoint-writesip-twice.html
* igt@xe_exec_system_allocator@evict-malloc:
- shard-bmg: [PASS][92] -> [ABORT][93] ([Intel XE#3970])
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-6/igt@xe_exec_system_allocator@evict-malloc.html
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-bmg-2/igt@xe_exec_system_allocator@evict-malloc.html
* igt@xe_exec_system_allocator@threads-many-execqueues-mmap-free-huge-nomemset:
- shard-bmg: NOTRUN -> [SKIP][94] ([Intel XE#4943]) +2 other tests skip
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-bmg-7/igt@xe_exec_system_allocator@threads-many-execqueues-mmap-free-huge-nomemset.html
* igt@xe_exec_system_allocator@threads-shared-vm-many-execqueues-malloc-busy-nomemset:
- shard-dg2-set2: NOTRUN -> [SKIP][95] ([Intel XE#4915]) +44 other tests skip
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-dg2-464/igt@xe_exec_system_allocator@threads-shared-vm-many-execqueues-malloc-busy-nomemset.html
* igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-new-bo-map-nomemset:
- shard-lnl: [PASS][96] -> [FAIL][97] ([Intel XE#5018])
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-lnl-7/igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-new-bo-map-nomemset.html
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-lnl-3/igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-new-bo-map-nomemset.html
* igt@xe_media_fill@media-fill:
- shard-bmg: NOTRUN -> [SKIP][98] ([Intel XE#2459] / [Intel XE#2596])
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-bmg-6/igt@xe_media_fill@media-fill.html
* igt@xe_oa@mmio-triggered-reports:
- shard-dg2-set2: NOTRUN -> [SKIP][99] ([Intel XE#3573]) +1 other test skip
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-dg2-464/igt@xe_oa@mmio-triggered-reports.html
* igt@xe_pm@d3cold-i2c:
- shard-dg2-set2: NOTRUN -> [SKIP][100] ([Intel XE#5694])
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-dg2-464/igt@xe_pm@d3cold-i2c.html
* igt@xe_query@multigpu-query-uc-fw-version-huc:
- shard-bmg: NOTRUN -> [SKIP][101] ([Intel XE#944]) +1 other test skip
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-bmg-6/igt@xe_query@multigpu-query-uc-fw-version-huc.html
#### Possible fixes ####
* igt@kms_async_flips@async-flip-suspend-resume:
- shard-adlp: [DMESG-WARN][102] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][103] +3 other tests pass
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-adlp-9/igt@kms_async_flips@async-flip-suspend-resume.html
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-adlp-8/igt@kms_async_flips@async-flip-suspend-resume.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
- shard-bmg: [INCOMPLETE][104] ([Intel XE#3862]) -> [PASS][105] +1 other test pass
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-2/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-bmg-7/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
- shard-bmg: [SKIP][106] ([Intel XE#2291]) -> [PASS][107] +1 other test pass
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-bmg-7/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
* igt@kms_flip@2x-flip-vs-dpms-on-nop:
- shard-bmg: [SKIP][108] ([Intel XE#2316]) -> [PASS][109] +3 other tests pass
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-6/igt@kms_flip@2x-flip-vs-dpms-on-nop.html
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-bmg-7/igt@kms_flip@2x-flip-vs-dpms-on-nop.html
* igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-hdmi-a1:
- shard-adlp: [DMESG-WARN][110] ([Intel XE#4543]) -> [PASS][111] +5 other tests pass
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-adlp-1/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-hdmi-a1.html
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-adlp-2/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-hdmi-a1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-lnl: [FAIL][112] ([Intel XE#301]) -> [PASS][113] +1 other test pass
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-adlp: [DMESG-WARN][114] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#4543]) -> [PASS][115] +1 other test pass
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-adlp-1/igt@kms_flip@flip-vs-suspend-interruptible.html
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-adlp-6/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-y-to-y:
- shard-adlp: [DMESG-FAIL][116] ([Intel XE#4543]) -> [PASS][117]
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-adlp-1/igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-y-to-y.html
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-adlp-2/igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-y-to-y.html
* igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-to-x:
- shard-adlp: [FAIL][118] ([Intel XE#1874]) -> [PASS][119]
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-adlp-1/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-to-x.html
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-adlp-2/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-to-x.html
* igt@kms_hdr@static-toggle:
- shard-bmg: [SKIP][120] ([Intel XE#1503]) -> [PASS][121] +2 other tests pass
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-6/igt@kms_hdr@static-toggle.html
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-bmg-8/igt@kms_hdr@static-toggle.html
* igt@kms_plane_multiple@2x-tiling-none:
- shard-bmg: [SKIP][122] ([Intel XE#4596]) -> [PASS][123]
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-6/igt@kms_plane_multiple@2x-tiling-none.html
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-bmg-7/igt@kms_plane_multiple@2x-tiling-none.html
* igt@kms_plane_scaling@2x-scaler-multi-pipe:
- shard-bmg: [SKIP][124] ([Intel XE#2571]) -> [PASS][125]
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-6/igt@kms_plane_scaling@2x-scaler-multi-pipe.html
[125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-bmg-2/igt@kms_plane_scaling@2x-scaler-multi-pipe.html
* igt@kms_psr@psr2-suspend@edp-1:
- shard-lnl: [FAIL][126] ([Intel XE#5298]) -> [PASS][127] +1 other test pass
[126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-lnl-3/igt@kms_psr@psr2-suspend@edp-1.html
[127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-lnl-2/igt@kms_psr@psr2-suspend@edp-1.html
* igt@xe_exec_basic@multigpu-no-exec-basic-defer-mmap:
- shard-dg2-set2: [SKIP][128] ([Intel XE#1392]) -> [PASS][129] +9 other tests pass
[128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-dg2-432/igt@xe_exec_basic@multigpu-no-exec-basic-defer-mmap.html
[129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-dg2-466/igt@xe_exec_basic@multigpu-no-exec-basic-defer-mmap.html
* igt@xe_exec_system_allocator@threads-shared-vm-many-large-new-bo-map-nomemset:
- shard-lnl: [FAIL][130] ([Intel XE#5018]) -> [PASS][131]
[130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-lnl-2/igt@xe_exec_system_allocator@threads-shared-vm-many-large-new-bo-map-nomemset.html
[131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-lnl-7/igt@xe_exec_system_allocator@threads-shared-vm-many-large-new-bo-map-nomemset.html
* igt@xe_pmu@gt-frequency:
- shard-dg2-set2: [FAIL][132] ([Intel XE#4819]) -> [PASS][133] +1 other test pass
[132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-dg2-432/igt@xe_pmu@gt-frequency.html
[133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-dg2-466/igt@xe_pmu@gt-frequency.html
#### Warnings ####
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
- shard-dg2-set2: [INCOMPLETE][134] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345] / [Intel XE#4522]) -> [INCOMPLETE][135] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345])
[134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
[135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
* igt@kms_content_protection@atomic-dpms:
- shard-bmg: [FAIL][136] ([Intel XE#1178]) -> [SKIP][137] ([Intel XE#2341])
[136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-1/igt@kms_content_protection@atomic-dpms.html
[137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-bmg-6/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@lic-type-0:
- shard-bmg: [SKIP][138] ([Intel XE#2341]) -> [FAIL][139] ([Intel XE#1178])
[138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-6/igt@kms_content_protection@lic-type-0.html
[139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-bmg-8/igt@kms_content_protection@lic-type-0.html
* igt@kms_content_protection@uevent:
- shard-bmg: [FAIL][140] ([Intel XE#1188]) -> [SKIP][141] ([Intel XE#2341])
[140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-4/igt@kms_content_protection@uevent.html
[141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-bmg-6/igt@kms_content_protection@uevent.html
* igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt:
- shard-bmg: [SKIP][142] ([Intel XE#2312]) -> [SKIP][143] ([Intel XE#2311]) +12 other tests skip
[142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt.html
[143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-bmg-8/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt:
- shard-bmg: [SKIP][144] ([Intel XE#2312]) -> [SKIP][145] ([Intel XE#5390]) +6 other tests skip
[144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt.html
[145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][146] ([Intel XE#5390]) -> [SKIP][147] ([Intel XE#2312]) +3 other tests skip
[146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc.html
[147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][148] ([Intel XE#2311]) -> [SKIP][149] ([Intel XE#2312]) +13 other tests skip
[148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html
[149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-plflip-blt:
- shard-bmg: [SKIP][150] ([Intel XE#2313]) -> [SKIP][151] ([Intel XE#2312]) +9 other tests skip
[150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-plflip-blt.html
[151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt:
- shard-bmg: [SKIP][152] ([Intel XE#2312]) -> [SKIP][153] ([Intel XE#2313]) +12 other tests skip
[152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
[153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-bmg-8/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
* igt@kms_hdr@brightness-with-hdr:
- shard-bmg: [SKIP][154] ([Intel XE#3544]) -> [SKIP][155] ([Intel XE#3374] / [Intel XE#3544])
[154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-5/igt@kms_hdr@brightness-with-hdr.html
[155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/shard-bmg-8/igt@kms_hdr@brightness-with-hdr.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
[Intel XE#1188]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1188
[Intel XE#1231]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1231
[Intel XE#1280]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1280
[Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
[Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
[Intel XE#1874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1874
[Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
[Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
[Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
[Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
[Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
[Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
[Intel XE#2459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2459
[Intel XE#2571]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2571
[Intel XE#2596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2596
[Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
[Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
[Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
[Intel XE#2881]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2881
[Intel XE#2883]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2883
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
[Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
[Intel XE#3106]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3106
[Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
[Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
[Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
[Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
[Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
[Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
[Intel XE#3862]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3862
[Intel XE#3884]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3884
[Intel XE#3970]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3970
[Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
[Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
[Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
[Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
[Intel XE#4417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4417
[Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
[Intel XE#4494]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4494
[Intel XE#4522]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4522
[Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
[Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
[Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
[Intel XE#4658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4658
[Intel XE#4683]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4683
[Intel XE#4685]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4685
[Intel XE#4819]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4819
[Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
[Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
[Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
[Intel XE#5018]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5018
[Intel XE#5195]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5195
[Intel XE#5298]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5298
[Intel XE#5390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5390
[Intel XE#5420]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5420
[Intel XE#5671]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5671
[Intel XE#5694]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5694
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
[Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
[Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
Build changes
-------------
* Linux: xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802 -> xe-pw-152588v1
IGT_8487: 8487
xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802: 886b8d8ef3839f604e3e7f6187ac6c46eb21b802
xe-pw-152588v1: 152588v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152588v1/index.html
[-- Attachment #2: Type: text/html, Size: 51798 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] drm/ttm: WIP limit the TTM pool to 32bit CPUs
2025-08-06 13:28 [PATCH] drm/ttm: WIP limit the TTM pool to 32bit CPUs Christian König
` (3 preceding siblings ...)
2025-08-06 17:03 ` ✗ Xe.CI.Full: " Patchwork
@ 2025-08-06 17:43 ` Thomas Hellström
2025-08-07 9:53 ` Christian König
2025-08-09 4:07 ` kernel test robot
2025-08-12 10:36 ` Matthew Auld
6 siblings, 1 reply; 14+ messages in thread
From: Thomas Hellström @ 2025-08-06 17:43 UTC (permalink / raw)
To: Christian König, dri-devel, intel-gfx, intel-xe
Cc: airlied, matthew.brost
Hi, Christian
On Wed, 2025-08-06 at 15:28 +0200, Christian König wrote:
> On some old x86 systems we had the problem that changing the caching
> flags
> of system memory requires changing the global MTRR/PAT tables.
>
> But on any modern x86 system (CPUs introduced rughly after 2004) we
> actually don't need that any more and can update the caching flags
> directly in the PTEs of the CPU mapping. It was just never disabled
> because of the fear of regressions.
>
> We already use the PTE flags for encryption on x86 64bit for quite a
> while
> and all other supported platforms (Sparc, PowerPC, ARM, MIPS,
> LONGARCH)
> have never done anything different either.
IIRC from my VMWARE days, changing SEV encryption mode of a page still
requires changing all mappings including kernel maps?
__set_memory_enc_pgtable()
>
> So disable the page pool completely for 64bit systems and just insert
> a
> clflush to be on the safe side so that we never return memory with
> dirty
> cache lines.
>
> Testing on a Ryzen 5 and 7 shows that this has absolutely no
> performance
> impact and of hand the AMD CI can't find a problem either.
>
> Let's see what the i915 and XE CI systems say to that.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
I don't think we can do this. First Lunar Lake can in some situations,
just like the old Athlons, write-back clean cache lines which means
writebacks of speculative prefetches may overwrite GPU data. LNL makes
heavy use of non-coherent GPU mappings for performance.
Second, IIRC vm_insert_pfn_prot() on X86 will override the given
caching mode with the last caching mode set for the kernel linear map,
so if you try to set up a write-combined GPU mapping without a previous
call to set_pages_xxxxx it will actually end up cached. see
track_pfn_insert().
/Thomas
> ---
> drivers/gpu/drm/ttm/ttm_pool.c | 16 +++++++++++-----
> 1 file changed, 11 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/ttm/ttm_pool.c
> b/drivers/gpu/drm/ttm/ttm_pool.c
> index baf27c70a419..7487eac29398 100644
> --- a/drivers/gpu/drm/ttm/ttm_pool.c
> +++ b/drivers/gpu/drm/ttm/ttm_pool.c
> @@ -38,7 +38,7 @@
> #include <linux/highmem.h>
> #include <linux/sched/mm.h>
>
> -#ifdef CONFIG_X86
> +#ifdef CONFIG_X86_32
> #include <asm/set_memory.h>
> #endif
>
> @@ -46,6 +46,7 @@
> #include <drm/ttm/ttm_pool.h>
> #include <drm/ttm/ttm_tt.h>
> #include <drm/ttm/ttm_bo.h>
> +#include <drm/drm_cache.h>
>
> #include "ttm_module.h"
>
> @@ -192,7 +193,7 @@ static void ttm_pool_free_page(struct ttm_pool
> *pool, enum ttm_caching caching,
> struct ttm_pool_dma *dma;
> void *vaddr;
>
> -#ifdef CONFIG_X86
> +#ifdef CONFIG_X86_32
> /* We don't care that set_pages_wb is inefficient here. This
> is only
> * used when we have to shrink and CPU overhead is
> irrelevant then.
> */
> @@ -218,7 +219,7 @@ static void ttm_pool_free_page(struct ttm_pool
> *pool, enum ttm_caching caching,
> /* Apply any cpu-caching deferred during page allocation */
> static int ttm_pool_apply_caching(struct ttm_pool_alloc_state
> *alloc)
> {
> -#ifdef CONFIG_X86
> +#ifdef CONFIG_X86_32
> unsigned int num_pages = alloc->pages - alloc-
> >caching_divide;
>
> if (!num_pages)
> @@ -232,6 +233,11 @@ static int ttm_pool_apply_caching(struct
> ttm_pool_alloc_state *alloc)
> case ttm_uncached:
> return set_pages_array_uc(alloc->caching_divide,
> num_pages);
> }
> +
> +#elif defined(CONFIG_X86_64)
> + unsigned int num_pages = alloc->pages - alloc-
> >caching_divide;
> +
> + drm_clflush_pages(alloc->caching_divide, num_pages);
> #endif
> alloc->caching_divide = alloc->pages;
> return 0;
> @@ -342,7 +348,7 @@ static struct ttm_pool_type
> *ttm_pool_select_type(struct ttm_pool *pool,
> if (pool->use_dma_alloc)
> return &pool->caching[caching].orders[order];
>
> -#ifdef CONFIG_X86
> +#ifdef CONFIG_X86_32
> switch (caching) {
> case ttm_write_combined:
> if (pool->nid != NUMA_NO_NODE)
> @@ -980,7 +986,7 @@ long ttm_pool_backup(struct ttm_pool *pool,
> struct ttm_tt *tt,
> pool->use_dma_alloc || ttm_tt_is_backed_up(tt))
> return -EBUSY;
>
> -#ifdef CONFIG_X86
> +#ifdef CONFIG_X86_32
> /* Anything returned to the system needs to be cached. */
> if (tt->caching != ttm_cached)
> set_pages_array_wb(tt->pages, tt->num_pages);
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] drm/ttm: WIP limit the TTM pool to 32bit CPUs
2025-08-06 17:43 ` [PATCH] " Thomas Hellström
@ 2025-08-07 9:53 ` Christian König
2025-08-07 16:47 ` Thomas Hellström
0 siblings, 1 reply; 14+ messages in thread
From: Christian König @ 2025-08-07 9:53 UTC (permalink / raw)
To: Thomas Hellström, dri-devel, intel-gfx, intel-xe
Cc: airlied, matthew.brost
On 06.08.25 19:43, Thomas Hellström wrote:
> Hi, Christian
>
> On Wed, 2025-08-06 at 15:28 +0200, Christian König wrote:
>> On some old x86 systems we had the problem that changing the caching
>> flags
>> of system memory requires changing the global MTRR/PAT tables.
>>
>> But on any modern x86 system (CPUs introduced rughly after 2004) we
>> actually don't need that any more and can update the caching flags
>> directly in the PTEs of the CPU mapping. It was just never disabled
>> because of the fear of regressions.
>>
>> We already use the PTE flags for encryption on x86 64bit for quite a
>> while
>> and all other supported platforms (Sparc, PowerPC, ARM, MIPS,
>> LONGARCH)
>> have never done anything different either.
>
> IIRC from my VMWARE days, changing SEV encryption mode of a page still
> requires changing all mappings including kernel maps?
> __set_memory_enc_pgtable()
IIRC both Intel and AMD sacrifice a bit in the page address for that, e.g. for encryption the most significant bit is used to indicate if a page is encrypted or not.
I'm not aware that we need to change all kernel mappings for encryption, but could be that the hypervisor somehow depends on that.
>>
>> So disable the page pool completely for 64bit systems and just insert
>> a
>> clflush to be on the safe side so that we never return memory with
>> dirty
>> cache lines.
>>
>> Testing on a Ryzen 5 and 7 shows that this has absolutely no
>> performance
>> impact and of hand the AMD CI can't find a problem either.
>>
>> Let's see what the i915 and XE CI systems say to that.
>>
>> Signed-off-by: Christian König <christian.koenig@amd.com>
>
> I don't think we can do this. First Lunar Lake can in some situations,
> just like the old Athlons, write-back clean cache lines which means
> writebacks of speculative prefetches may overwrite GPU data.
So a speculative prefetch because of on an access to an adjacent page could causes the cache line to be fetched and then written back without any change to it?
Well it's surprising that even modern CPU do stuff like that. That could explain some of the problems we had with uncached mappings on ARM and RISC-V.
> LNL makes heavy use of non-coherent GPU mappings for performance.
That is even more surprising. At least on modern Ryzens that doesn't seem to have much performance impact any more at all.
I mean non-cached mappings where original introduced to avoid the extra overhead of going over the front side bus, but that design is long gone.
> Second, IIRC vm_insert_pfn_prot() on X86 will override the given
> caching mode with the last caching mode set for the kernel linear map,
> so if you try to set up a write-combined GPU mapping without a previous
> call to set_pages_xxxxx it will actually end up cached. see
> track_pfn_insert().
That is exactly the same incorrect assumption I made as well.
It's not the linear mapping where that comes from but a separate page attribute table, see /sys/kernel/debug/x86/pat_memtype_list.
Question is why the heck should we do this? I mean we keep an extra rb tree around to overwrite something the driver knows in the first place?
That is basically just tons of extra overhead for nothing as far as I can see.
Thanks for taking a look,
Christian.
>
> /Thomas
>
>
>> ---
>> drivers/gpu/drm/ttm/ttm_pool.c | 16 +++++++++++-----
>> 1 file changed, 11 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/ttm/ttm_pool.c
>> b/drivers/gpu/drm/ttm/ttm_pool.c
>> index baf27c70a419..7487eac29398 100644
>> --- a/drivers/gpu/drm/ttm/ttm_pool.c
>> +++ b/drivers/gpu/drm/ttm/ttm_pool.c
>> @@ -38,7 +38,7 @@
>> #include <linux/highmem.h>
>> #include <linux/sched/mm.h>
>>
>> -#ifdef CONFIG_X86
>> +#ifdef CONFIG_X86_32
>> #include <asm/set_memory.h>
>> #endif
>>
>> @@ -46,6 +46,7 @@
>> #include <drm/ttm/ttm_pool.h>
>> #include <drm/ttm/ttm_tt.h>
>> #include <drm/ttm/ttm_bo.h>
>> +#include <drm/drm_cache.h>
>>
>> #include "ttm_module.h"
>>
>> @@ -192,7 +193,7 @@ static void ttm_pool_free_page(struct ttm_pool
>> *pool, enum ttm_caching caching,
>> struct ttm_pool_dma *dma;
>> void *vaddr;
>>
>> -#ifdef CONFIG_X86
>> +#ifdef CONFIG_X86_32
>> /* We don't care that set_pages_wb is inefficient here. This
>> is only
>> * used when we have to shrink and CPU overhead is
>> irrelevant then.
>> */
>> @@ -218,7 +219,7 @@ static void ttm_pool_free_page(struct ttm_pool
>> *pool, enum ttm_caching caching,
>> /* Apply any cpu-caching deferred during page allocation */
>> static int ttm_pool_apply_caching(struct ttm_pool_alloc_state
>> *alloc)
>> {
>> -#ifdef CONFIG_X86
>> +#ifdef CONFIG_X86_32
>> unsigned int num_pages = alloc->pages - alloc-
>>> caching_divide;
>>
>> if (!num_pages)
>> @@ -232,6 +233,11 @@ static int ttm_pool_apply_caching(struct
>> ttm_pool_alloc_state *alloc)
>> case ttm_uncached:
>> return set_pages_array_uc(alloc->caching_divide,
>> num_pages);
>> }
>> +
>> +#elif defined(CONFIG_X86_64)
>> + unsigned int num_pages = alloc->pages - alloc-
>>> caching_divide;
>> +
>> + drm_clflush_pages(alloc->caching_divide, num_pages);
>> #endif
>> alloc->caching_divide = alloc->pages;
>> return 0;
>> @@ -342,7 +348,7 @@ static struct ttm_pool_type
>> *ttm_pool_select_type(struct ttm_pool *pool,
>> if (pool->use_dma_alloc)
>> return &pool->caching[caching].orders[order];
>>
>> -#ifdef CONFIG_X86
>> +#ifdef CONFIG_X86_32
>> switch (caching) {
>> case ttm_write_combined:
>> if (pool->nid != NUMA_NO_NODE)
>> @@ -980,7 +986,7 @@ long ttm_pool_backup(struct ttm_pool *pool,
>> struct ttm_tt *tt,
>> pool->use_dma_alloc || ttm_tt_is_backed_up(tt))
>> return -EBUSY;
>>
>> -#ifdef CONFIG_X86
>> +#ifdef CONFIG_X86_32
>> /* Anything returned to the system needs to be cached. */
>> if (tt->caching != ttm_cached)
>> set_pages_array_wb(tt->pages, tt->num_pages);
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] drm/ttm: WIP limit the TTM pool to 32bit CPUs
2025-08-07 9:53 ` Christian König
@ 2025-08-07 16:47 ` Thomas Hellström
2025-08-11 11:51 ` Christian König
0 siblings, 1 reply; 14+ messages in thread
From: Thomas Hellström @ 2025-08-07 16:47 UTC (permalink / raw)
To: Christian König, dri-devel, intel-gfx, intel-xe
Cc: airlied, matthew.brost
On Thu, 2025-08-07 at 11:53 +0200, Christian König wrote:
> On 06.08.25 19:43, Thomas Hellström wrote:
> > Hi, Christian
> >
> > On Wed, 2025-08-06 at 15:28 +0200, Christian König wrote:
> > > On some old x86 systems we had the problem that changing the
> > > caching
> > > flags
> > > of system memory requires changing the global MTRR/PAT tables.
> > >
> > > But on any modern x86 system (CPUs introduced rughly after 2004)
> > > we
> > > actually don't need that any more and can update the caching
> > > flags
> > > directly in the PTEs of the CPU mapping. It was just never
> > > disabled
> > > because of the fear of regressions.
> > >
> > > We already use the PTE flags for encryption on x86 64bit for
> > > quite a
> > > while
> > > and all other supported platforms (Sparc, PowerPC, ARM, MIPS,
> > > LONGARCH)
> > > have never done anything different either.
> >
> > IIRC from my VMWARE days, changing SEV encryption mode of a page
> > still
> > requires changing all mappings including kernel maps?
> > __set_memory_enc_pgtable()
>
> IIRC both Intel and AMD sacrifice a bit in the page address for that,
> e.g. for encryption the most significant bit is used to indicate if a
> page is encrypted or not.
>
> I'm not aware that we need to change all kernel mappings for
> encryption, but could be that the hypervisor somehow depends on that.
>
> > >
> > > So disable the page pool completely for 64bit systems and just
> > > insert
> > > a
> > > clflush to be on the safe side so that we never return memory
> > > with
> > > dirty
> > > cache lines.
> > >
> > > Testing on a Ryzen 5 and 7 shows that this has absolutely no
> > > performance
> > > impact and of hand the AMD CI can't find a problem either.
> > >
> > > Let's see what the i915 and XE CI systems say to that.
> > >
> > > Signed-off-by: Christian König <christian.koenig@amd.com>
> >
> > I don't think we can do this. First Lunar Lake can in some
> > situations,
> > just like the old Athlons, write-back clean cache lines which means
> > writebacks of speculative prefetches may overwrite GPU data.
>
> So a speculative prefetch because of on an access to an adjacent page
> could causes the cache line to be fetched and then written back
> without any change to it?
Exactly.
>
> Well it's surprising that even modern CPU do stuff like that. That
> could explain some of the problems we had with uncached mappings on
> ARM and RISC-V.
Yeah. I agree. Need to double-check with HW people whether that is gone
with Panther Lake. Don't have a confirmation yet on that.
>
> > LNL makes heavy use of non-coherent GPU mappings for performance.
>
> That is even more surprising. At least on modern Ryzens that doesn't
> seem to have much performance impact any more at all.
>
> I mean non-cached mappings where original introduced to avoid the
> extra overhead of going over the front side bus, but that design is
> long gone.
With LNL it's possible to set up GPU mapping to make the accesses
coherent with CPU but that's quite slow. A tradeoff in HW design.
If it wasn't for the writeback of speculative prefetches we could've
settled for only have TTM map the user-space mappings without changing
the kernel map, just like the i915 driver does for older GPUS.
>
> > Second, IIRC vm_insert_pfn_prot() on X86 will override the given
> > caching mode with the last caching mode set for the kernel linear
> > map,
> > so if you try to set up a write-combined GPU mapping without a
> > previous
> > call to set_pages_xxxxx it will actually end up cached. see
> > track_pfn_insert().
>
> That is exactly the same incorrect assumption I made as well.
>
> It's not the linear mapping where that comes from but a separate page
> attribute table, see /sys/kernel/debug/x86/pat_memtype_list.
>
> Question is why the heck should we do this? I mean we keep an extra
> rb tree around to overwrite something the driver knows in the first
> place?
>
> That is basically just tons of extra overhead for nothing as far as I
> can see.
IIRC it was PAT people enforcing the x86 documentation that aliased
mappings with conflicting caching attributes were not allowed. But it
has proven to work at least on those CPUs not suffering from the clean
cache-line writeback mentioned above.
FWIW If I understand the code correctly, i915 bypasses this by setting
up user-space mappings not by vm_insert_pfn_prot() but using
apply_to_page_range(), mapping the whole bo.
/Thomas
>
> Thanks for taking a look,
> Christian.
>
> >
> > /Thomas
> >
> >
> > > ---
> > > drivers/gpu/drm/ttm/ttm_pool.c | 16 +++++++++++-----
> > > 1 file changed, 11 insertions(+), 5 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/ttm/ttm_pool.c
> > > b/drivers/gpu/drm/ttm/ttm_pool.c
> > > index baf27c70a419..7487eac29398 100644
> > > --- a/drivers/gpu/drm/ttm/ttm_pool.c
> > > +++ b/drivers/gpu/drm/ttm/ttm_pool.c
> > > @@ -38,7 +38,7 @@
> > > #include <linux/highmem.h>
> > > #include <linux/sched/mm.h>
> > >
> > > -#ifdef CONFIG_X86
> > > +#ifdef CONFIG_X86_32
> > > #include <asm/set_memory.h>
> > > #endif
> > >
> > > @@ -46,6 +46,7 @@
> > > #include <drm/ttm/ttm_pool.h>
> > > #include <drm/ttm/ttm_tt.h>
> > > #include <drm/ttm/ttm_bo.h>
> > > +#include <drm/drm_cache.h>
> > >
> > > #include "ttm_module.h"
> > >
> > > @@ -192,7 +193,7 @@ static void ttm_pool_free_page(struct
> > > ttm_pool
> > > *pool, enum ttm_caching caching,
> > > struct ttm_pool_dma *dma;
> > > void *vaddr;
> > >
> > > -#ifdef CONFIG_X86
> > > +#ifdef CONFIG_X86_32
> > > /* We don't care that set_pages_wb is inefficient here.
> > > This
> > > is only
> > > * used when we have to shrink and CPU overhead is
> > > irrelevant then.
> > > */
> > > @@ -218,7 +219,7 @@ static void ttm_pool_free_page(struct
> > > ttm_pool
> > > *pool, enum ttm_caching caching,
> > > /* Apply any cpu-caching deferred during page allocation */
> > > static int ttm_pool_apply_caching(struct ttm_pool_alloc_state
> > > *alloc)
> > > {
> > > -#ifdef CONFIG_X86
> > > +#ifdef CONFIG_X86_32
> > > unsigned int num_pages = alloc->pages - alloc-
> > > > caching_divide;
> > >
> > > if (!num_pages)
> > > @@ -232,6 +233,11 @@ static int ttm_pool_apply_caching(struct
> > > ttm_pool_alloc_state *alloc)
> > > case ttm_uncached:
> > > return set_pages_array_uc(alloc->caching_divide,
> > > num_pages);
> > > }
> > > +
> > > +#elif defined(CONFIG_X86_64)
> > > + unsigned int num_pages = alloc->pages - alloc-
> > > > caching_divide;
> > > +
> > > + drm_clflush_pages(alloc->caching_divide, num_pages);
> > > #endif
> > > alloc->caching_divide = alloc->pages;
> > > return 0;
> > > @@ -342,7 +348,7 @@ static struct ttm_pool_type
> > > *ttm_pool_select_type(struct ttm_pool *pool,
> > > if (pool->use_dma_alloc)
> > > return &pool->caching[caching].orders[order];
> > >
> > > -#ifdef CONFIG_X86
> > > +#ifdef CONFIG_X86_32
> > > switch (caching) {
> > > case ttm_write_combined:
> > > if (pool->nid != NUMA_NO_NODE)
> > > @@ -980,7 +986,7 @@ long ttm_pool_backup(struct ttm_pool *pool,
> > > struct ttm_tt *tt,
> > > pool->use_dma_alloc || ttm_tt_is_backed_up(tt))
> > > return -EBUSY;
> > >
> > > -#ifdef CONFIG_X86
> > > +#ifdef CONFIG_X86_32
> > > /* Anything returned to the system needs to be cached.
> > > */
> > > if (tt->caching != ttm_cached)
> > > set_pages_array_wb(tt->pages, tt->num_pages);
> >
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] drm/ttm: WIP limit the TTM pool to 32bit CPUs
2025-08-06 13:28 [PATCH] drm/ttm: WIP limit the TTM pool to 32bit CPUs Christian König
` (4 preceding siblings ...)
2025-08-06 17:43 ` [PATCH] " Thomas Hellström
@ 2025-08-09 4:07 ` kernel test robot
2025-08-12 10:36 ` Matthew Auld
6 siblings, 0 replies; 14+ messages in thread
From: kernel test robot @ 2025-08-09 4:07 UTC (permalink / raw)
To: Christian König, dri-devel, intel-gfx, intel-xe
Cc: llvm, oe-kbuild-all, airlied, thomas.hellstrom, matthew.brost
Hi Christian,
kernel test robot noticed the following build errors:
[auto build test ERROR on drm-exynos/exynos-drm-next]
[also build test ERROR on linus/master v6.16 next-20250808]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Christian-K-nig/drm-ttm-WIP-limit-the-TTM-pool-to-32bit-CPUs/20250806-212941
base: https://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos.git exynos-drm-next
patch link: https://lore.kernel.org/r/20250806132838.1831-1-christian.koenig%40amd.com
patch subject: [PATCH] drm/ttm: WIP limit the TTM pool to 32bit CPUs
config: um-randconfig-001-20250809 (https://download.01.org/0day-ci/archive/20250809/202508091134.xJZroqY6-lkp@intel.com/config)
compiler: clang version 22.0.0git (https://github.com/llvm/llvm-project 3769ce013be2879bf0b329c14a16f5cb766f26ce)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250809/202508091134.xJZroqY6-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202508091134.xJZroqY6-lkp@intel.com/
All errors (new ones prefixed by >>, old ones prefixed by <<):
>> ERROR: modpost: "set_pages_array_wc" [drivers/gpu/drm/ttm/ttm.ko] undefined!
>> ERROR: modpost: "set_pages_array_uc" [drivers/gpu/drm/ttm/ttm.ko] undefined!
>> ERROR: modpost: "set_pages_wb" [drivers/gpu/drm/ttm/ttm.ko] undefined!
>> ERROR: modpost: "set_pages_array_wb" [drivers/gpu/drm/ttm/ttm.ko] undefined!
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] drm/ttm: WIP limit the TTM pool to 32bit CPUs
2025-08-07 16:47 ` Thomas Hellström
@ 2025-08-11 11:51 ` Christian König
2025-08-11 15:16 ` Thomas Hellström
0 siblings, 1 reply; 14+ messages in thread
From: Christian König @ 2025-08-11 11:51 UTC (permalink / raw)
To: Thomas Hellström, dri-devel, intel-gfx, intel-xe
Cc: airlied, matthew.brost
On 07.08.25 18:47, Thomas Hellström wrote:
>> Well it's surprising that even modern CPU do stuff like that. That
>> could explain some of the problems we had with uncached mappings on
>> ARM and RISC-V.
>
> Yeah. I agree. Need to double-check with HW people whether that is gone
> with Panther Lake. Don't have a confirmation yet on that.
Going to ask around AMD internally as well.
> If it wasn't for the writeback of speculative prefetches we could've
> settled for only have TTM map the user-space mappings without changing
> the kernel map, just like the i915 driver does for older GPUS.
We should probably come up with a CPU whitelist or blacklist where that is actually needed.
>>> Second, IIRC vm_insert_pfn_prot() on X86 will override the given
>>> caching mode with the last caching mode set for the kernel linear
>>> map,
>>> so if you try to set up a write-combined GPU mapping without a
>>> previous
>>> call to set_pages_xxxxx it will actually end up cached. see
>>> track_pfn_insert().
>>
>> That is exactly the same incorrect assumption I made as well.
>>
>> It's not the linear mapping where that comes from but a separate page
>> attribute table, see /sys/kernel/debug/x86/pat_memtype_list.
>>
>> Question is why the heck should we do this? I mean we keep an extra
>> rb tree around to overwrite something the driver knows in the first
>> place?
>>
>> That is basically just tons of extra overhead for nothing as far as I
>> can see.
>
> IIRC it was PAT people enforcing the x86 documentation that aliased
> mappings with conflicting caching attributes were not allowed. But it
> has proven to work at least on those CPUs not suffering from the clean
> cache-line writeback mentioned above.
Makes sense. With the PAT handling even accessing things through /dev/mem gives you the right caching.
Do you have a list of Intel CPUs where it works?
> FWIW If I understand the code correctly, i915 bypasses this by setting
> up user-space mappings not by vm_insert_pfn_prot() but using
> apply_to_page_range(), mapping the whole bo.
Yeah, that's probably not something we can do. Even filling in 2MiB of address space at a time caused performance problems for TTM.
We should probably just drop overriding the attributes in vmf_insert_pfn_prot().
Regards,
Christian.
>
> /Thomas
>
>
>>
>> Thanks for taking a look,
>> Christian.
>>
>>>
>>> /Thomas
>>>
>>>
>>>> ---
>>>> drivers/gpu/drm/ttm/ttm_pool.c | 16 +++++++++++-----
>>>> 1 file changed, 11 insertions(+), 5 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/ttm/ttm_pool.c
>>>> b/drivers/gpu/drm/ttm/ttm_pool.c
>>>> index baf27c70a419..7487eac29398 100644
>>>> --- a/drivers/gpu/drm/ttm/ttm_pool.c
>>>> +++ b/drivers/gpu/drm/ttm/ttm_pool.c
>>>> @@ -38,7 +38,7 @@
>>>> #include <linux/highmem.h>
>>>> #include <linux/sched/mm.h>
>>>>
>>>> -#ifdef CONFIG_X86
>>>> +#ifdef CONFIG_X86_32
>>>> #include <asm/set_memory.h>
>>>> #endif
>>>>
>>>> @@ -46,6 +46,7 @@
>>>> #include <drm/ttm/ttm_pool.h>
>>>> #include <drm/ttm/ttm_tt.h>
>>>> #include <drm/ttm/ttm_bo.h>
>>>> +#include <drm/drm_cache.h>
>>>>
>>>> #include "ttm_module.h"
>>>>
>>>> @@ -192,7 +193,7 @@ static void ttm_pool_free_page(struct
>>>> ttm_pool
>>>> *pool, enum ttm_caching caching,
>>>> struct ttm_pool_dma *dma;
>>>> void *vaddr;
>>>>
>>>> -#ifdef CONFIG_X86
>>>> +#ifdef CONFIG_X86_32
>>>> /* We don't care that set_pages_wb is inefficient here.
>>>> This
>>>> is only
>>>> * used when we have to shrink and CPU overhead is
>>>> irrelevant then.
>>>> */
>>>> @@ -218,7 +219,7 @@ static void ttm_pool_free_page(struct
>>>> ttm_pool
>>>> *pool, enum ttm_caching caching,
>>>> /* Apply any cpu-caching deferred during page allocation */
>>>> static int ttm_pool_apply_caching(struct ttm_pool_alloc_state
>>>> *alloc)
>>>> {
>>>> -#ifdef CONFIG_X86
>>>> +#ifdef CONFIG_X86_32
>>>> unsigned int num_pages = alloc->pages - alloc-
>>>>> caching_divide;
>>>>
>>>> if (!num_pages)
>>>> @@ -232,6 +233,11 @@ static int ttm_pool_apply_caching(struct
>>>> ttm_pool_alloc_state *alloc)
>>>> case ttm_uncached:
>>>> return set_pages_array_uc(alloc->caching_divide,
>>>> num_pages);
>>>> }
>>>> +
>>>> +#elif defined(CONFIG_X86_64)
>>>> + unsigned int num_pages = alloc->pages - alloc-
>>>>> caching_divide;
>>>> +
>>>> + drm_clflush_pages(alloc->caching_divide, num_pages);
>>>> #endif
>>>> alloc->caching_divide = alloc->pages;
>>>> return 0;
>>>> @@ -342,7 +348,7 @@ static struct ttm_pool_type
>>>> *ttm_pool_select_type(struct ttm_pool *pool,
>>>> if (pool->use_dma_alloc)
>>>> return &pool->caching[caching].orders[order];
>>>>
>>>> -#ifdef CONFIG_X86
>>>> +#ifdef CONFIG_X86_32
>>>> switch (caching) {
>>>> case ttm_write_combined:
>>>> if (pool->nid != NUMA_NO_NODE)
>>>> @@ -980,7 +986,7 @@ long ttm_pool_backup(struct ttm_pool *pool,
>>>> struct ttm_tt *tt,
>>>> pool->use_dma_alloc || ttm_tt_is_backed_up(tt))
>>>> return -EBUSY;
>>>>
>>>> -#ifdef CONFIG_X86
>>>> +#ifdef CONFIG_X86_32
>>>> /* Anything returned to the system needs to be cached.
>>>> */
>>>> if (tt->caching != ttm_cached)
>>>> set_pages_array_wb(tt->pages, tt->num_pages);
>>>
>>
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] drm/ttm: WIP limit the TTM pool to 32bit CPUs
2025-08-11 11:51 ` Christian König
@ 2025-08-11 15:16 ` Thomas Hellström
2025-08-12 9:17 ` Christian König
0 siblings, 1 reply; 14+ messages in thread
From: Thomas Hellström @ 2025-08-11 15:16 UTC (permalink / raw)
To: Christian König, dri-devel, intel-gfx, intel-xe
Cc: airlied, matthew.brost
On Mon, 2025-08-11 at 13:51 +0200, Christian König wrote:
> On 07.08.25 18:47, Thomas Hellström wrote:
> > > Well it's surprising that even modern CPU do stuff like that.
> > > That
> > > could explain some of the problems we had with uncached mappings
> > > on
> > > ARM and RISC-V.
> >
> > Yeah. I agree. Need to double-check with HW people whether that is
> > gone
> > with Panther Lake. Don't have a confirmation yet on that.
>
> Going to ask around AMD internally as well.
>
> > If it wasn't for the writeback of speculative prefetches we
> > could've
> > settled for only have TTM map the user-space mappings without
> > changing
> > the kernel map, just like the i915 driver does for older GPUS.
>
> We should probably come up with a CPU whitelist or blacklist where
> that is actually needed.
>
> > > > Second, IIRC vm_insert_pfn_prot() on X86 will override the
> > > > given
> > > > caching mode with the last caching mode set for the kernel
> > > > linear
> > > > map,
> > > > so if you try to set up a write-combined GPU mapping without a
> > > > previous
> > > > call to set_pages_xxxxx it will actually end up cached. see
> > > > track_pfn_insert().
> > >
> > > That is exactly the same incorrect assumption I made as well.
> > >
> > > It's not the linear mapping where that comes from but a separate
> > > page
> > > attribute table, see /sys/kernel/debug/x86/pat_memtype_list.
> > >
> > > Question is why the heck should we do this? I mean we keep an
> > > extra
> > > rb tree around to overwrite something the driver knows in the
> > > first
> > > place?
> > >
> > > That is basically just tons of extra overhead for nothing as far
> > > as I
> > > can see.
> >
> > IIRC it was PAT people enforcing the x86 documentation that aliased
> > mappings with conflicting caching attributes were not allowed. But
> > it
> > has proven to work at least on those CPUs not suffering from the
> > clean
> > cache-line writeback mentioned above.
>
> Makes sense. With the PAT handling even accessing things through
> /dev/mem gives you the right caching.
>
> Do you have a list of Intel CPUs where it works?
AFAIK LNL is the only one so far where it doesn't work. I need to get
more information internally.
>
> > FWIW If I understand the code correctly, i915 bypasses this by
> > setting
> > up user-space mappings not by vm_insert_pfn_prot() but using
> > apply_to_page_range(), mapping the whole bo.
>
> Yeah, that's probably not something we can do. Even filling in 2MiB
> of address space at a time caused performance problems for TTM.
Wasn't that because of repeated calls to vmf_insert_pfn_prot(),
repeating the caching checks and page-table walk all the time?
I think apply_to_page_range() should be pretty fast. Also, to avoid
regressions due to changing the number of prefaulted pages, we could
perhaps honor the MADV_RANDOM and MADV_SEQUENTIAL advises for UMD to
use; one faulting a single page only, one faulting the whole bo, but
also see below:
>
> We should probably just drop overriding the attributes in
> vmf_insert_pfn_prot().
I think either solution will see resistance with arch people. We should
probably involve them in the discussion.
Thanks,
/Thomas
>
> Regards,
> Christian.
>
> >
> > /Thomas
> >
> >
> > >
> > > Thanks for taking a look,
> > > Christian.
> > >
> > > >
> > > > /Thomas
> > > >
> > > >
> > > > > ---
> > > > > drivers/gpu/drm/ttm/ttm_pool.c | 16 +++++++++++-----
> > > > > 1 file changed, 11 insertions(+), 5 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/ttm/ttm_pool.c
> > > > > b/drivers/gpu/drm/ttm/ttm_pool.c
> > > > > index baf27c70a419..7487eac29398 100644
> > > > > --- a/drivers/gpu/drm/ttm/ttm_pool.c
> > > > > +++ b/drivers/gpu/drm/ttm/ttm_pool.c
> > > > > @@ -38,7 +38,7 @@
> > > > > #include <linux/highmem.h>
> > > > > #include <linux/sched/mm.h>
> > > > >
> > > > > -#ifdef CONFIG_X86
> > > > > +#ifdef CONFIG_X86_32
> > > > > #include <asm/set_memory.h>
> > > > > #endif
> > > > >
> > > > > @@ -46,6 +46,7 @@
> > > > > #include <drm/ttm/ttm_pool.h>
> > > > > #include <drm/ttm/ttm_tt.h>
> > > > > #include <drm/ttm/ttm_bo.h>
> > > > > +#include <drm/drm_cache.h>
> > > > >
> > > > > #include "ttm_module.h"
> > > > >
> > > > > @@ -192,7 +193,7 @@ static void ttm_pool_free_page(struct
> > > > > ttm_pool
> > > > > *pool, enum ttm_caching caching,
> > > > > struct ttm_pool_dma *dma;
> > > > > void *vaddr;
> > > > >
> > > > > -#ifdef CONFIG_X86
> > > > > +#ifdef CONFIG_X86_32
> > > > > /* We don't care that set_pages_wb is inefficient
> > > > > here.
> > > > > This
> > > > > is only
> > > > > * used when we have to shrink and CPU overhead is
> > > > > irrelevant then.
> > > > > */
> > > > > @@ -218,7 +219,7 @@ static void ttm_pool_free_page(struct
> > > > > ttm_pool
> > > > > *pool, enum ttm_caching caching,
> > > > > /* Apply any cpu-caching deferred during page allocation */
> > > > > static int ttm_pool_apply_caching(struct
> > > > > ttm_pool_alloc_state
> > > > > *alloc)
> > > > > {
> > > > > -#ifdef CONFIG_X86
> > > > > +#ifdef CONFIG_X86_32
> > > > > unsigned int num_pages = alloc->pages - alloc-
> > > > > > caching_divide;
> > > > >
> > > > > if (!num_pages)
> > > > > @@ -232,6 +233,11 @@ static int ttm_pool_apply_caching(struct
> > > > > ttm_pool_alloc_state *alloc)
> > > > > case ttm_uncached:
> > > > > return set_pages_array_uc(alloc-
> > > > > >caching_divide,
> > > > > num_pages);
> > > > > }
> > > > > +
> > > > > +#elif defined(CONFIG_X86_64)
> > > > > + unsigned int num_pages = alloc->pages - alloc-
> > > > > > caching_divide;
> > > > > +
> > > > > + drm_clflush_pages(alloc->caching_divide, num_pages);
> > > > > #endif
> > > > > alloc->caching_divide = alloc->pages;
> > > > > return 0;
> > > > > @@ -342,7 +348,7 @@ static struct ttm_pool_type
> > > > > *ttm_pool_select_type(struct ttm_pool *pool,
> > > > > if (pool->use_dma_alloc)
> > > > > return &pool-
> > > > > >caching[caching].orders[order];
> > > > >
> > > > > -#ifdef CONFIG_X86
> > > > > +#ifdef CONFIG_X86_32
> > > > > switch (caching) {
> > > > > case ttm_write_combined:
> > > > > if (pool->nid != NUMA_NO_NODE)
> > > > > @@ -980,7 +986,7 @@ long ttm_pool_backup(struct ttm_pool
> > > > > *pool,
> > > > > struct ttm_tt *tt,
> > > > > pool->use_dma_alloc || ttm_tt_is_backed_up(tt))
> > > > > return -EBUSY;
> > > > >
> > > > > -#ifdef CONFIG_X86
> > > > > +#ifdef CONFIG_X86_32
> > > > > /* Anything returned to the system needs to be
> > > > > cached.
> > > > > */
> > > > > if (tt->caching != ttm_cached)
> > > > > set_pages_array_wb(tt->pages, tt-
> > > > > >num_pages);
> > > >
> > >
> >
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] drm/ttm: WIP limit the TTM pool to 32bit CPUs
2025-08-11 15:16 ` Thomas Hellström
@ 2025-08-12 9:17 ` Christian König
2025-08-12 10:19 ` Thomas Hellström
0 siblings, 1 reply; 14+ messages in thread
From: Christian König @ 2025-08-12 9:17 UTC (permalink / raw)
To: Thomas Hellström, dri-devel, intel-gfx, intel-xe
Cc: airlied, matthew.brost
On 11.08.25 17:16, Thomas Hellström wrote:
>>
>>> FWIW If I understand the code correctly, i915 bypasses this by
>>> setting
>>> up user-space mappings not by vm_insert_pfn_prot() but using
>>> apply_to_page_range(), mapping the whole bo.
>>
>> Yeah, that's probably not something we can do. Even filling in 2MiB
>> of address space at a time caused performance problems for TTM.
>
> Wasn't that because of repeated calls to vmf_insert_pfn_prot(),
> repeating the caching checks and page-table walk all the time?
Only partially, the main problem was that only a fraction of the BO was actually CPU accessed. So filling in more than faulted was just overhead.
> I think apply_to_page_range() should be pretty fast. Also, to avoid
> regressions due to changing the number of prefaulted pages, we could
> perhaps honor the MADV_RANDOM and MADV_SEQUENTIAL advises for UMD to
> use; one faulting a single page only, one faulting the whole bo
Ah! In my thinking apply_to_page_range() would always fault in the whole BO, if that still works for only a partial range than that should be ok.
> , but
> also see below:
>
>>
>> We should probably just drop overriding the attributes in
>> vmf_insert_pfn_prot().
>
> I think either solution will see resistance with arch people. We should
> probably involve them in the discussion.
Any specific person I should CC or just x86@kernel.org?
Thanks,
Christian
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] drm/ttm: WIP limit the TTM pool to 32bit CPUs
2025-08-12 9:17 ` Christian König
@ 2025-08-12 10:19 ` Thomas Hellström
0 siblings, 0 replies; 14+ messages in thread
From: Thomas Hellström @ 2025-08-12 10:19 UTC (permalink / raw)
To: Christian König, dri-devel, intel-gfx, intel-xe
Cc: airlied, matthew.brost
On Tue, 2025-08-12 at 11:17 +0200, Christian König wrote:
> On 11.08.25 17:16, Thomas Hellström wrote:
> > >
> > > > FWIW If I understand the code correctly, i915 bypasses this by
> > > > setting
> > > > up user-space mappings not by vm_insert_pfn_prot() but using
> > > > apply_to_page_range(), mapping the whole bo.
> > >
> > > Yeah, that's probably not something we can do. Even filling in
> > > 2MiB
> > > of address space at a time caused performance problems for TTM.
> >
> > Wasn't that because of repeated calls to vmf_insert_pfn_prot(),
> > repeating the caching checks and page-table walk all the time?
>
> Only partially, the main problem was that only a fraction of the BO
> was actually CPU accessed. So filling in more than faulted was just
> overhead.
>
> > I think apply_to_page_range() should be pretty fast. Also, to avoid
> > regressions due to changing the number of prefaulted pages, we
> > could
> > perhaps honor the MADV_RANDOM and MADV_SEQUENTIAL advises for UMD
> > to
> > use; one faulting a single page only, one faulting the whole bo
>
> Ah! In my thinking apply_to_page_range() would always fault in the
> whole BO, if that still works for only a partial range than that
> should be ok.
Yes, it looks like it works with partial ranges.
>
> > , but
> > also see below:
> >
> > >
> > > We should probably just drop overriding the attributes in
> > > vmf_insert_pfn_prot().
> >
> > I think either solution will see resistance with arch people. We
> > should
> > probably involve them in the discussion.
>
> Any specific person I should CC or just x86@kernel.org?
scripts/get_maintainer.pl of a tiny change into the PAT code gives me
the following: Hopefully some of these should trigger some replies and
insights:
./scripts/get_maintainer.pl 0001-arch-mm-dummy-commit.patch
Dave Hansen <dave.hansen@linux.intel.com> (maintainer:X86 MM)
Andy Lutomirski <luto@kernel.org> (maintainer:X86 MM)
Peter Zijlstra <peterz@infradead.org> (maintainer:X86 MM)
Thomas Gleixner <tglx@linutronix.de> (maintainer:X86 ARCHITECTURE (32-
BIT AND 64-BIT))
Ingo Molnar <mingo@redhat.com> (maintainer:X86 ARCHITECTURE (32-BIT AND
64-BIT),commit_signer:10/16=62%,authored:2/16=12%)
Borislav Petkov <bp@alien8.de> (maintainer:X86 ARCHITECTURE (32-BIT AND
64-BIT))
x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT))
"H. Peter Anvin" <hpa@zytor.com> (reviewer:X86 ARCHITECTURE (32-BIT AND
64-BIT))
Andrew Morton <akpm@linux-foundation.org> (commit_signer:7/16=44%)
David Hildenbrand <david@redhat.com>
(commit_signer:6/16=38%,authored:6/16=38%,added_lines:68/105=65%,remove
d_lines:214/292=73%)
"Liam R. Howlett" <Liam.Howlett@oracle.com> (commit_signer:5/16=31%)
Lorenzo Stoakes <lorenzo.stoakes@oracle.com> (commit_signer:5/16=31%)
Sean Christopherson <seanjc@google.com>
(authored:2/16=12%,added_lines:15/105=14%,removed_lines:31/292=11%)
"Thomas Hellström" <thomas.hellstrom@linux.intel.com>
(authored:1/16=6%)
Shivank Garg <shivankg@amd.com> (authored:1/16=6%)
Peter Xu <peterx@redhat.com> (added_lines:7/105=7%)
Dan Williams <dan.j.williams@intel.com> (removed_lines:27/292=9%)
>
> Thanks,
> Christian
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] drm/ttm: WIP limit the TTM pool to 32bit CPUs
2025-08-06 13:28 [PATCH] drm/ttm: WIP limit the TTM pool to 32bit CPUs Christian König
` (5 preceding siblings ...)
2025-08-09 4:07 ` kernel test robot
@ 2025-08-12 10:36 ` Matthew Auld
6 siblings, 0 replies; 14+ messages in thread
From: Matthew Auld @ 2025-08-12 10:36 UTC (permalink / raw)
To: Christian König, dri-devel, intel-gfx, intel-xe
Cc: airlied, thomas.hellstrom, matthew.brost
On 06/08/2025 14:28, Christian König wrote:
> On some old x86 systems we had the problem that changing the caching flags
> of system memory requires changing the global MTRR/PAT tables.
>
> But on any modern x86 system (CPUs introduced rughly after 2004) we
> actually don't need that any more and can update the caching flags
> directly in the PTEs of the CPU mapping. It was just never disabled
> because of the fear of regressions.
>
> We already use the PTE flags for encryption on x86 64bit for quite a while
> and all other supported platforms (Sparc, PowerPC, ARM, MIPS, LONGARCH)
> have never done anything different either.
>
> So disable the page pool completely for 64bit systems and just insert a
> clflush to be on the safe side so that we never return memory with dirty
> cache lines.
>
> Testing on a Ryzen 5 and 7 shows that this has absolutely no performance
> impact and of hand the AMD CI can't find a problem either.
>
> Let's see what the i915 and XE CI systems say to that.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
> ---
> drivers/gpu/drm/ttm/ttm_pool.c | 16 +++++++++++-----
> 1 file changed, 11 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/ttm/ttm_pool.c b/drivers/gpu/drm/ttm/ttm_pool.c
> index baf27c70a419..7487eac29398 100644
> --- a/drivers/gpu/drm/ttm/ttm_pool.c
> +++ b/drivers/gpu/drm/ttm/ttm_pool.c
> @@ -38,7 +38,7 @@
> #include <linux/highmem.h>
> #include <linux/sched/mm.h>
>
> -#ifdef CONFIG_X86
> +#ifdef CONFIG_X86_32
> #include <asm/set_memory.h>
> #endif
>
> @@ -46,6 +46,7 @@
> #include <drm/ttm/ttm_pool.h>
> #include <drm/ttm/ttm_tt.h>
> #include <drm/ttm/ttm_bo.h>
> +#include <drm/drm_cache.h>
>
> #include "ttm_module.h"
>
> @@ -192,7 +193,7 @@ static void ttm_pool_free_page(struct ttm_pool *pool, enum ttm_caching caching,
> struct ttm_pool_dma *dma;
> void *vaddr;
>
> -#ifdef CONFIG_X86
> +#ifdef CONFIG_X86_32
> /* We don't care that set_pages_wb is inefficient here. This is only
> * used when we have to shrink and CPU overhead is irrelevant then.
> */
> @@ -218,7 +219,7 @@ static void ttm_pool_free_page(struct ttm_pool *pool, enum ttm_caching caching,
> /* Apply any cpu-caching deferred during page allocation */
> static int ttm_pool_apply_caching(struct ttm_pool_alloc_state *alloc)
> {
> -#ifdef CONFIG_X86
> +#ifdef CONFIG_X86_32
> unsigned int num_pages = alloc->pages - alloc->caching_divide;
>
> if (!num_pages)
> @@ -232,6 +233,11 @@ static int ttm_pool_apply_caching(struct ttm_pool_alloc_state *alloc)
> case ttm_uncached:
> return set_pages_array_uc(alloc->caching_divide, num_pages);
> }
> +
> +#elif defined(CONFIG_X86_64)
> + unsigned int num_pages = alloc->pages - alloc->caching_divide;
> +
> + drm_clflush_pages(alloc->caching_divide, num_pages);
Do we now also need manual clflushing for things like swap-in? Or what
caching type does copy_highpage() in ttm_tt_swapin() use now? Is it not
wb? If so, is that not one of the nice advantages of using set_pages_*
where raw kmap will respect the PAT setting?
> #endif
> alloc->caching_divide = alloc->pages;
> return 0;
> @@ -342,7 +348,7 @@ static struct ttm_pool_type *ttm_pool_select_type(struct ttm_pool *pool,
> if (pool->use_dma_alloc)
> return &pool->caching[caching].orders[order];
>
> -#ifdef CONFIG_X86
> +#ifdef CONFIG_X86_32
> switch (caching) {
> case ttm_write_combined:
> if (pool->nid != NUMA_NO_NODE)
> @@ -980,7 +986,7 @@ long ttm_pool_backup(struct ttm_pool *pool, struct ttm_tt *tt,
> pool->use_dma_alloc || ttm_tt_is_backed_up(tt))
> return -EBUSY;
>
> -#ifdef CONFIG_X86
> +#ifdef CONFIG_X86_32
> /* Anything returned to the system needs to be cached. */
> if (tt->caching != ttm_cached)
> set_pages_array_wb(tt->pages, tt->num_pages);
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2025-08-12 10:36 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
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2025-08-06 13:28 [PATCH] drm/ttm: WIP limit the TTM pool to 32bit CPUs Christian König
2025-08-06 13:58 ` ✗ CI.checkpatch: warning for " Patchwork
2025-08-06 14:00 ` ✓ CI.KUnit: success " Patchwork
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2025-08-06 17:43 ` [PATCH] " Thomas Hellström
2025-08-07 9:53 ` Christian König
2025-08-07 16:47 ` Thomas Hellström
2025-08-11 11:51 ` Christian König
2025-08-11 15:16 ` Thomas Hellström
2025-08-12 9:17 ` Christian König
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