From: "Borah, Chaitanya Kumar" <chaitanya.kumar.borah@intel.com>
To: "Kandpal, Suraj" <suraj.kandpal@intel.com>,
"Shankar, Uma" <uma.shankar@intel.com>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>,
"intel-xe@lists.freedesktop.org" <intel-xe@lists.freedesktop.org>,
"dri-devel@lists.freedesktop.org"
<dri-devel@lists.freedesktop.org>
Cc: "ville.syrjala@linux.intel.com" <ville.syrjala@linux.intel.com>,
"pekka.paalanen@collabora.com" <pekka.paalanen@collabora.com>,
"contact@emersion.fr" <contact@emersion.fr>,
"harry.wentland@amd.com" <harry.wentland@amd.com>,
"mwen@igalia.com" <mwen@igalia.com>,
"jadahl@redhat.com" <jadahl@redhat.com>,
"sebastian.wick@redhat.com" <sebastian.wick@redhat.com>,
"shashank.sharma@amd.com" <shashank.sharma@amd.com>,
"Sharma, Swati2" <swati2.sharma@intel.com>,
"alex.hung@amd.com" <alex.hung@amd.com>,
"Nikula, Jani" <jani.nikula@intel.com>
Subject: Re: [v6 12/16] drm/i915/color: Program Pre-CSC registers
Date: Wed, 19 Nov 2025 13:44:24 +0530 [thread overview]
Message-ID: <c32ad774-fcf8-4ec1-b95e-381acb034f03@intel.com> (raw)
In-Reply-To: <DM3PPF208195D8D2C6942F90EA6AEDEF719E3D6A@DM3PPF208195D8D.namprd11.prod.outlook.com>
On 11/18/2025 2:33 PM, Kandpal, Suraj wrote:
> Bspec link here,
> also if you can provide it as a reply so that I can verify the sequence for these writes
>
> Regards,
> Suraj Kandpal
I am not aware of any special sequence that is followed for programming
these registers other than the normal behavior of double buffer registers.
As to what to write into them, you can check the spec entries already
mentioned in the patch that adds them.
BSpec: 50411, 50412, 50413, 50414
==
Chaitanya
next prev parent reply other threads:[~2025-11-19 8:14 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-05 12:33 [v6 00/16] Plane Color Pipeline support for Intel platforms Uma Shankar
2025-11-05 12:33 ` [v6 01/16] [NOT FOR REVIEW] drm: AMD series squashed Uma Shankar
2025-11-05 12:33 ` [v6 02/16] drm/i915: Add identifiers for driver specific blocks Uma Shankar
2025-11-11 9:20 ` Kandpal, Suraj
2025-11-05 12:33 ` [v6 03/16] drm/i915: Add intel_color_op Uma Shankar
2025-11-18 6:06 ` Kandpal, Suraj
2025-11-05 12:34 ` [v6 04/16] drm/i915/color: Add helper to create intel colorop Uma Shankar
2025-11-18 6:09 ` Kandpal, Suraj
2025-11-05 12:34 ` [v6 05/16] drm/i915/color: Create a transfer function color pipeline Uma Shankar
2025-11-18 6:23 ` Kandpal, Suraj
2025-11-05 12:34 ` [v6 06/16] drm/i915/color: Add framework to program CSC Uma Shankar
2025-11-18 8:24 ` Kandpal, Suraj
2025-11-18 8:52 ` Borah, Chaitanya Kumar
2025-11-18 8:55 ` Kandpal, Suraj
2025-11-05 12:34 ` [v6 07/16] drm/i915/color: Preserve sign bit when int_bits is Zero Uma Shankar
2025-11-18 6:29 ` Kandpal, Suraj
2025-11-05 12:34 ` [v6 08/16] drm/i915/color: Add plane CTM callback for D12 and beyond Uma Shankar
2025-11-05 12:34 ` [v6 09/16] drm/i915: Add register definitions for Plane Degamma Uma Shankar
2025-11-18 8:56 ` Kandpal, Suraj
2025-11-05 12:34 ` [v6 10/16] drm/i915/color: Add framework to program PRE/POST CSC LUT Uma Shankar
2025-11-18 8:30 ` Kandpal, Suraj
2025-11-05 12:34 ` [v6 11/16] drm/i915: Add register definitions for Plane Post CSC Uma Shankar
2025-11-05 12:34 ` [v6 12/16] drm/i915/color: Program Pre-CSC registers Uma Shankar
2025-11-18 9:03 ` Kandpal, Suraj
2025-11-19 8:14 ` Borah, Chaitanya Kumar [this message]
2025-11-05 12:34 ` [v6 13/16] drm/i915/xelpd: Program Plane Post CSC Registers Uma Shankar
2025-11-06 13:16 ` kernel test robot
2025-11-05 12:34 ` [v6 14/16] drm/i915/display: Add registers for 3D LUT Uma Shankar
2025-11-10 12:08 ` Jani Nikula
2025-11-11 8:39 ` Borah, Chaitanya Kumar
2025-11-18 8:36 ` Kandpal, Suraj
2025-11-05 12:34 ` [v6 15/16] drm/i915/color: Add 3D LUT to color pipeline Uma Shankar
2025-11-10 12:09 ` Jani Nikula
2025-11-11 8:39 ` Borah, Chaitanya Kumar
2025-11-11 9:02 ` Jani Nikula
2025-11-18 8:50 ` Kandpal, Suraj
2025-11-18 8:56 ` Borah, Chaitanya Kumar
2025-11-05 12:34 ` [v6 16/16] drm/i915/color: Enable Plane Color Pipelines Uma Shankar
2025-11-18 8:52 ` Kandpal, Suraj
2025-11-05 12:36 ` ✗ CI.checkpatch: warning for Plane Color Pipeline support for Intel platforms (rev5) Patchwork
2025-11-05 12:37 ` ✓ CI.KUnit: success " Patchwork
2025-11-05 12:53 ` ✗ CI.checksparse: warning " Patchwork
2025-11-05 13:38 ` ✗ Xe.CI.BAT: failure " Patchwork
2025-11-05 18:36 ` ✗ Xe.CI.Full: " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=c32ad774-fcf8-4ec1-b95e-381acb034f03@intel.com \
--to=chaitanya.kumar.borah@intel.com \
--cc=alex.hung@amd.com \
--cc=contact@emersion.fr \
--cc=dri-devel@lists.freedesktop.org \
--cc=harry.wentland@amd.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=intel-xe@lists.freedesktop.org \
--cc=jadahl@redhat.com \
--cc=jani.nikula@intel.com \
--cc=mwen@igalia.com \
--cc=pekka.paalanen@collabora.com \
--cc=sebastian.wick@redhat.com \
--cc=shashank.sharma@amd.com \
--cc=suraj.kandpal@intel.com \
--cc=swati2.sharma@intel.com \
--cc=uma.shankar@intel.com \
--cc=ville.syrjala@linux.intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox