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From: Jani Nikula <jani.nikula@linux.intel.com>
To: Suraj Kandpal <suraj.kandpal@intel.com>,
	intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Cc: ankit.k.nautiyal@intel.com, swati2.sharma@intel.com,
	Suraj Kandpal <suraj.kandpal@intel.com>
Subject: Re: [PATCH] drm/i915/dp: Ignore HPD when in DPLL enable/disable cycle
Date: Fri, 17 Apr 2026 15:00:40 +0300	[thread overview]
Message-ID: <c3b5e61c68aae8242da2bd170736485ced2f9db2@intel.com> (raw)
In-Reply-To: <a99f71916d52b29e300ecac2207e0fb501d6a4a5@intel.com>

On Fri, 17 Apr 2026, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Fri, 17 Apr 2026, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
>> When we are enable/disable DPLL cycle there are chances the connected
>> monitors is still sending us HPD signals. This causes us to handle them
>> which require DPCD read. These sometimes race with the DPLL getting
>> disabled in between causing AUX failures via Timeout.
>> Introduce atomic variable link_teardown which is used to track if
>> we are in DPLL enable/disable cycle. We ignore HPDs during this time.
>> Re-enable after DPLL is up so that we can avoid populating logs
>> with expected logs AUX timeout failures.
>
> How is this not racy?

Oh, please don't cross-post trybot list with other lists.

>
>>
>> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_ddi.c           | 5 +++++
>>  drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
>>  drivers/gpu/drm/i915/display/intel_dp.c            | 5 +++++
>>  3 files changed, 11 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>> index 178074316a2c..4a523eb56bc4 100644
>> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>> @@ -2086,8 +2086,12 @@ static struct intel_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder)
>>  void intel_ddi_enable_clock(struct intel_encoder *encoder,
>>  			    const struct intel_crtc_state *crtc_state)
>>  {
>> +	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>> +
>>  	if (encoder->enable_clock)
>>  		encoder->enable_clock(encoder, crtc_state);
>> +
>> +	atomic_set(&dig_port->link_teardown, 0);
>>  }
>>  
>>  void intel_ddi_disable_clock(struct intel_encoder *encoder)
>> @@ -3181,6 +3185,7 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
>>  					dig_port->ddi_io_power_domain,
>>  					wakeref);
>>  
>> +	atomic_set(&dig_port->link_teardown, 1);
>>  	intel_ddi_disable_clock(encoder);
>>  
>>  	/* De-select Thunderbolt */
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index c81916761850..f59bbb2fb260 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -1985,6 +1985,7 @@ struct intel_digital_port {
>>  	enum intel_display_power_domain ddi_io_power_domain;
>>  	struct ref_tracker *ddi_io_wakeref;
>>  	struct ref_tracker *aux_wakeref;
>> +	atomic_t link_teardown;
>>  
>>  	struct intel_tc_port *tc;
>>  
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 35b8fb5740aa..9177fe9b3e84 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -6889,6 +6889,11 @@ intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
>>  	struct intel_dp *intel_dp = &dig_port->dp;
>>  	u8 dpcd[DP_RECEIVER_CAP_SIZE];
>>  
>> +	if (atomic_read(&dig_port->link_teardown)) {
>> +		drm_dbg_kms("Ignoring HPD since DPLL is getting disabled\n");
>> +		return IRQ_NONE;
>> +	}
>> +
>>  	if (dig_port->base.type == INTEL_OUTPUT_EDP &&
>>  	    (long_hpd ||
>>  	     intel_display_rpm_suspended(display) ||

-- 
Jani Nikula, Intel

  reply	other threads:[~2026-04-17 12:00 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-04-17  8:01 [PATCH] drm/i915/dp: Ignore HPD when in DPLL enable/disable cycle Suraj Kandpal
2026-04-17  8:27 ` Jani Nikula
2026-04-17 12:00   ` Jani Nikula [this message]
2026-04-17 14:42     ` Kandpal, Suraj
2026-04-17 15:35 ` Ville Syrjälä
2026-04-20 13:21 ` ✓ CI.KUnit: success for " Patchwork
2026-04-22  2:03 ` [PATCH] " kernel test robot
2026-04-22  2:46 ` kernel test robot

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