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From: "Hogander, Jouni" <jouni.hogander@intel.com>
To: "ville.syrjala@linux.intel.com" <ville.syrjala@linux.intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>
Cc: "intel-xe@lists.freedesktop.org" <intel-xe@lists.freedesktop.org>,
	"stable@vger.kernel.org" <stable@vger.kernel.org>
Subject: Re: [PATCH] drm/i915/psr: Reject async flips when selective fetch is enabled
Date: Thu, 6 Nov 2025 07:13:28 +0000	[thread overview]
Message-ID: <c4a4be9261eec75201ff5a8dcb8f5da2373a4884.camel@intel.com> (raw)
In-Reply-To: <20251105171015.22234-1-ville.syrjala@linux.intel.com>

On Wed, 2025-11-05 at 19:10 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The selective fetch code doesn't handle asycn flips correctly.
> There is a nonsense check for async flips in
> intel_psr2_sel_fetch_config_valid() but that only gets called
> for modesets/fastsets and thus does nothing for async flips.
> 
> Currently intel_async_flip_check_hw() is very unhappy as the
> selective fetch code pulls in planes that are not even async
> flips capable.
> 
> Reject async flips when selective fetch is enabled, until
> someone fixes this properly (ie. disable selective fetch while
> async flips are being issued).

Is it ok to allow psr2 hw tracking? Not directly related to this patch
so:

Reviewed-by: Jouni Högander <jouni.hogander@intel.com>

> 
> Cc: stable@vger.kernel.org
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 8 ++++++++
>  drivers/gpu/drm/i915/display/intel_psr.c     | 6 ------
>  2 files changed, 8 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 42ec78798666..10583592fefe 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6020,6 +6020,14 @@ static int intel_async_flip_check_uapi(struct
> intel_atomic_state *state,
>  		return -EINVAL;
>  	}
>  
> +	/* FIXME: selective fetch should be disabled for async flips
> */
> +	if (new_crtc_state->enable_psr2_sel_fetch) {
> +		drm_dbg_kms(display->drm,
> +			    "[CRTC:%d:%s] async flip disallowed with
> PSR2 selective fetch\n",
> +			    crtc->base.base.id, crtc->base.name);
> +		return -EINVAL;
> +	}
> +
>  	for_each_oldnew_intel_plane_in_state(state, plane,
> old_plane_state,
>  					     new_plane_state, i) {
>  		if (plane->pipe != crtc->pipe)
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 05014ffe3ce1..65d77aea9536 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1296,12 +1296,6 @@ static bool
> intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
>  		return false;
>  	}
>  
> -	if (crtc_state->uapi.async_flip) {
> -		drm_dbg_kms(display->drm,
> -			    "PSR2 sel fetch not enabled, async flip
> enabled\n");
> -		return false;
> -	}
> -
>  	return crtc_state->enable_psr2_sel_fetch = true;
>  }
>  


  parent reply	other threads:[~2025-11-06  7:13 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-05 17:10 [PATCH] drm/i915/psr: Reject async flips when selective fetch is enabled Ville Syrjala
2025-11-05 20:48 ` ✗ CI.checkpatch: warning for " Patchwork
2025-11-05 20:49 ` ✓ CI.KUnit: success " Patchwork
2025-11-06  7:13 ` Hogander, Jouni [this message]
2025-11-07 13:32   ` [PATCH] " Ville Syrjälä
2025-11-06  7:25 ` ✗ Xe.CI.Full: failure for " Patchwork

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