Re: [PATCH v6] drm/i915/display: change pipe allocation order for discrete platforms

[Jani Nikula <jani.nikula@intel.com>]

On Wed, 15 Apr 2026, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Mon, Apr 13, 2026 at 11:16:09AM +0300, Jani Nikula wrote:
>> When big joiner is enabled, it reserves the adjacent pipe as the
>> secondary pipe. This happens without the user space knowing, and
>> subsequent attempts at using the CRTC with that pipe will fail. If the
>> user space does not have a coping mechanism, i.e. trying another CRTC,
>> this leads to a black screen.
>> 
>> Try to reduce the impact of the problem on discrete platforms by mapping
>> the CRTCs to pipes in order A, C, B, and D. If the user space reserves
>> CRTCs in order, this should trick it to using pipes that are more likely
>> to be available for and after joining.
>> 
>> Limit this to discrete platforms, which have four pipes, and no eDP, a
>> combination that should benefit the most with least drawbacks.
>> 
>> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> Should be fine with the other stuff I posted earlier:
> https://lore.kernel.org/intel-gfx/20260408155744.13326-1-ville.syrjala@linux.intel.com/
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Thanks, pushed top topic/pipe-reorder, which already has the commits you
refer to.

BR,
Jani.

>
>> 
>> ---
>> 
>> v2: Also remove WARN_ON()
>> 
>> v3: Limit to discrete
>> 
>> v4: Revamp
>> 
>> v5: Don't screw up the loop variable, dummy
>> 
>> v6: Rebase, drop FIXME comment
>> ---
>>  drivers/gpu/drm/i915/display/intel_crtc.c | 29 ++++++++++++++++++++---
>>  1 file changed, 26 insertions(+), 3 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
>> index c88a6810c49f..03de219f7a64 100644
>> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
>> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
>> @@ -411,8 +411,6 @@ static int __intel_crtc_init(struct intel_display *display, enum pipe pipe)
>>  
>>  	cpu_latency_qos_add_request(&crtc->vblank_pm_qos, PM_QOS_DEFAULT_VALUE);
>>  
>> -	drm_WARN_ON(display->drm, drm_crtc_index(&crtc->base) != crtc->pipe);
>> -
>>  	if (HAS_CASF(display) && crtc->num_scalers >= 2)
>>  		drm_crtc_create_sharpness_strength_property(&crtc->base);
>>  
>> @@ -426,6 +424,31 @@ static int __intel_crtc_init(struct intel_display *display, enum pipe pipe)
>>  	return ret;
>>  }
>>  
>> +#define HAS_PIPE(display, pipe) (DISPLAY_RUNTIME_INFO(display)->pipe_mask & BIT(pipe))
>> +
>> +/*
>> + * Expose the pipes in order A, C, B, D on discrete platforms to trick user
>> + * space into using pipes that are more likely to be available for both a) user
>> + * space if pipe B has been reserved for the joiner, and b) the joiner if pipe A
>> + * doesn't need the joiner.
>> + *
>> + * Swap pipes B and C only if both are available i.e. not fused off.
>> + */
>> +static enum pipe reorder_pipe(struct intel_display *display, enum pipe pipe)
>> +{
>> +	if (!display->platform.dgfx || !HAS_PIPE(display, PIPE_B) || !HAS_PIPE(display, PIPE_C))
>> +		return pipe;
>> +
>> +	switch (pipe) {
>> +	case PIPE_B:
>> +		return PIPE_C;
>> +	case PIPE_C:
>> +		return PIPE_B;
>> +	default:
>> +		return pipe;
>> +	}
>> +}
>> +
>>  int intel_crtc_init(struct intel_display *display)
>>  {
>>  	enum pipe pipe;
>> @@ -435,7 +458,7 @@ int intel_crtc_init(struct intel_display *display)
>>  		    INTEL_NUM_PIPES(display), str_plural(INTEL_NUM_PIPES(display)));
>>  
>>  	for_each_pipe(display, pipe) {
>> -		ret = __intel_crtc_init(display, pipe);
>> +		ret = __intel_crtc_init(display, reorder_pipe(display, pipe));
>>  		if (ret)
>>  			return ret;
>>  	}
>> -- 
>> 2.47.3

-- 
Jani Nikula, Intel