Re: [PATCH 21/35] drm/i915/display: Enable MSA Ignore Timing PAR only when in not fixed_rr mode

["Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com>]

On 1/25/2025 2:45 AM, Ville Syrjälä wrote:
> On Fri, Jan 24, 2025 at 08:30:06PM +0530, Ankit Nautiyal wrote:
>> MSA Ignore Timing PAR enable is set in the DP sink when we enable variable
>> refresh rate. When using VRR timing generator for fixed refresh rate
>> we do not want to ignore the mode timings, as the refresh rate is still
>> fixed. Modify the checks to enable MSA Ignore Timing PAR only when not
>> in fixed_rr mode.
>>
>> v2: Initialize enable_msa_timing_par_ignore to false.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_ddi.c              | 2 +-
>>   drivers/gpu/drm/i915/display/intel_dp_link_training.c | 8 +++++++-
>>   2 files changed, 8 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>> index d48a3108f363..dac953b2af31 100644
>> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>> @@ -2281,7 +2281,7 @@ static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel
>>   {
>>   	struct intel_display *display = to_intel_display(intel_dp);
>>   
>> -	if (!intel_vrrtg_is_enabled(crtc_state))
>> +	if (!intel_vrrtg_is_enabled(crtc_state) || crtc_state->vrr.flipline == crtc_state->vrr.vmax)
>>   		return;
>>   
>>   	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL,
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> index 9cb22baafeeb..b8063807fd34 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> @@ -724,8 +724,14 @@ void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate, b
>>   static void intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp,
>>   					    const struct intel_crtc_state *crtc_state)
>>   {
>> +	bool enable_msa_timing_par_ignore = false;
>> +
>> +	/* Enable MSA TIMING PAR IGNORE only in non fixed_rr mode */
>> +	if (crtc_state->vrr.flipline && crtc_state->vrr.flipline != crtc_state->vrr.vmax)
>> +		enable_msa_timing_par_ignore = true;
>> +
>>   	intel_dp_link_training_set_mode(intel_dp,
>> -					crtc_state->port_clock, crtc_state->vrr.flipline);
>> +					crtc_state->port_clock, enable_msa_timing_par_ignore);
> We only set this during link training, so this won't work for fastsets.
> I think what we want is to just always set this when the timings are in
> the VRR range.

Got it, will check the vrr range here.

Regards,

Ankit

>>   }
>>   
>>   void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
>> -- 
>> 2.45.2