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d="scan'208";a="242714767" Received: from vpanait-mobl.ger.corp.intel.com (HELO localhost) ([10.245.245.203]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 May 2026 04:49:13 -0700 From: Jani Nikula To: Vinod Govindapillai , intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: vinod.govindapillai@intel.com, ville.syrjala@linux.intel.com Subject: Re: [PATCH v2 09/11] drm/i915/bw: consolidate the debug info of bw/dgv/psf data In-Reply-To: <20260511122816.1235478-10-vinod.govindapillai@intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs Bertel Jungin Aukio 5, 02600 Espoo, Finland References: <20260511122816.1235478-1-vinod.govindapillai@intel.com> <20260511122816.1235478-10-vinod.govindapillai@intel.com> Date: Tue, 12 May 2026 14:49:08 +0300 Message-ID: MIME-Version: 1.0 Content-Type: text/plain X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Mon, 11 May 2026, Vinod Govindapillai wrote: > Consolidate all the detaills about the bw, gqv and psf gv into > a common function and present it in an organised format > > Signed-off-by: Vinod Govindapillai > --- > drivers/gpu/drm/i915/display/intel_bw.c | 40 +++++++++++++++++-------- > 1 file changed, 27 insertions(+), 13 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c > index 858da1710a61..0bda13a3e31b 100644 > --- a/drivers/gpu/drm/i915/display/intel_bw.c > +++ b/drivers/gpu/drm/i915/display/intel_bw.c > @@ -483,6 +483,28 @@ static const struct intel_sa_info xe3lpd_3002_sa_info = { > .derating = 10, > }; > > +static void debug_print_bw_info(struct intel_display *display) > +{ > + int num_groups = ARRAY_SIZE(display->bw.max); > + int i; > + > + for (i = 0; i < num_groups; i++) { > + struct intel_bw_info *bi = &display->bw.max[i]; > + int j; > + > + drm_dbg_kms(display->drm, "BW%d: num_planes=%d num_qgv_points:%d\n", > + i, bi->num_planes, bi->num_qgv_points); > + > + for (j = 0; j < bi->num_qgv_points; j++) > + drm_dbg_kms(display->drm, "\tQGV %d: deratedbw=%u peakbw=%u\n", Please use a drm_printer, and drm_printf_indent(). > + j, bi->deratedbw[j], bi->peakbw[j]); > + > + for (j = 0; j < bi->num_psf_gv_points; j++) > + drm_dbg_kms(display->drm, "\tPSF GV %d bw=%u\n", > + j, bi->psf_bw[j]); > + } > +} > + > static bool is_tile_y_factored(struct intel_display *display) > { > /* TGL supports Y-tile for LPDDR4/5, but not for DDR4 */ > @@ -544,12 +566,11 @@ static int icl_get_bw_info(struct intel_display *display, > > bi->deratedbw[j] = min(maxdebw, > bw * (100 - sa->derating) / 100); > - > - drm_dbg_kms(display->drm, > - "BW%d / QGV %d: num_planes=%d deratedbw=%u\n", > - i, j, bi->num_planes, bi->deratedbw[j]); > } > } > + > + debug_print_bw_info(display); > + > /* > * In case if SAGV is disabled in BIOS, we always get 1 > * SAGV point, but we can't send PCode commands to restrict it > @@ -650,24 +671,17 @@ static int tgl_get_bw_info(struct intel_display *display, > bi->peakbw[j] = DIV_ROUND_CLOSEST(sp->dclk * > num_channels * > qi.channel_width, 8); > - > - drm_dbg_kms(display->drm, > - "BW%d / QGV %d: num_planes=%d deratedbw=%u peakbw: %u\n", > - i, j, bi->num_planes, bi->deratedbw[j], > - bi->peakbw[j]); > } > > for (j = 0; j < qi.num_psf_points; j++) { > const struct intel_psf_gv_point *sp = &qi.psf_points[j]; > > bi->psf_bw[j] = adl_calc_psf_bw(sp->clk); > - > - drm_dbg_kms(display->drm, > - "BW%d / PSF GV %d: num_planes=%d bw=%u\n", > - i, j, bi->num_planes, bi->psf_bw[j]); > } > } > > + debug_print_bw_info(display); > + > /* > * In case if SAGV is disabled in BIOS, we always get 1 > * SAGV point, but we can't send PCode commands to restrict it -- Jani Nikula, Intel