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Downgrade all the errors to non-fatal to prevent PCIe > bus driver from triggering a Secondary Bus Reset (SBR). This allows error > detection, containment and recovery in the driver. > > The Uncorrectable Error Severity Register has the 'Uncorrectable > Internal Error Severity' set to fatal by default. Set this to > non-fatal and unmask the error. > > Signed-off-by: Riana Tauro LGTM, Reviewed-by: Mallesh Koujalagi > --- > v2: clear stale uncorrectable internal status in status register > (Aravind) > > v3: abbrevate TLA's (Raag) > add a info message if USP does not support AER > > v4: add a success log (Raag) > --- > drivers/gpu/drm/xe/xe_device.c | 3 ++ > drivers/gpu/drm/xe/xe_ras.c | 78 ++++++++++++++++++++++++++++++++++ > drivers/gpu/drm/xe/xe_ras.h | 2 +- > 3 files changed, 82 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c > index 4b45b617a039..200d6bbb1b70 100644 > --- a/drivers/gpu/drm/xe/xe_device.c > +++ b/drivers/gpu/drm/xe/xe_device.c > @@ -62,6 +62,7 @@ > #include "xe_psmi.h" > #include "xe_pxp.h" > #include "xe_query.h" > +#include "xe_ras.h" > #include "xe_shrinker.h" > #include "xe_soc_remapper.h" > #include "xe_survivability_mode.h" > @@ -1048,6 +1049,8 @@ int xe_device_probe(struct xe_device *xe) > if (err) > goto err_unregister_display; > > + xe_ras_init(xe); > + > err = xe_device_sysfs_init(xe); > if (err) > goto err_unregister_display; > diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c > index 4cb16b419b0c..24642c309967 100644 > --- a/drivers/gpu/drm/xe/xe_ras.c > +++ b/drivers/gpu/drm/xe/xe_ras.c > @@ -91,3 +91,81 @@ void xe_ras_counter_threshold_crossed(struct xe_device *xe, > comp_to_str(component), sev_to_str(severity)); > } > } > + > +#ifdef CONFIG_PCIEAER > +static void aer_unmask_and_downgrade_internal_error(struct xe_device *xe) > +{ > + struct pci_dev *pdev = to_pci_dev(xe->drm.dev); > + struct pci_dev *vsp, *usp; > + u32 aer_uncorr_mask, aer_uncorr_sev, aer_uncorr_status; > + u16 aer_cap; > + > + /* > + * Device Hierarchy: > + * > + * Upstream Switch Port (USP)--> Virtual Switch Port (VSP)--> SGunit (GPU endpoint) > + */ > + vsp = pci_upstream_bridge(pdev); > + if (!vsp) > + return; > + > + usp = pci_upstream_bridge(vsp); > + if (!usp) > + return; > + > + aer_cap = usp->aer_cap; > + > + if (!aer_cap) { > + dev_info(&usp->dev, "USP doesn't support AER capability\n"); > + return; > + } > + > + /* > + * Clear any stale Uncorrectable Internal Error Status event in Uncorrectable Error > + * Status Register. > + */ > + pci_read_config_dword(usp, aer_cap + PCI_ERR_UNCOR_STATUS, &aer_uncorr_status); > + if (aer_uncorr_status & PCI_ERR_UNC_INTN) > + pci_write_config_dword(usp, aer_cap + PCI_ERR_UNCOR_STATUS, PCI_ERR_UNC_INTN); > + > + /* > + * All errors are steered to USP which is a PCIe AER Compliant device. > + * Downgrade all the errors to non-fatal to prevent PCIe bus driver > + * from triggering a Secondary Bus Reset (SBR). This allows error > + * detection, containment and recovery in the driver. > + * > + * The Uncorrectable Error Severity Register has the 'Uncorrectable > + * Internal Error Severity' set to fatal by default. Set this to > + * non-fatal and unmask the error. > + */ > + > + /* Initialize Uncorrectable Error Severity Register */ > + pci_read_config_dword(usp, aer_cap + PCI_ERR_UNCOR_SEVER, &aer_uncorr_sev); > + aer_uncorr_sev &= ~PCI_ERR_UNC_INTN; > + pci_write_config_dword(usp, aer_cap + PCI_ERR_UNCOR_SEVER, aer_uncorr_sev); > + > + /* Initialize Uncorrectable Error Mask Register */ > + pci_read_config_dword(usp, aer_cap + PCI_ERR_UNCOR_MASK, &aer_uncorr_mask); > + aer_uncorr_mask &= ~PCI_ERR_UNC_INTN; > + pci_write_config_dword(usp, aer_cap + PCI_ERR_UNCOR_MASK, aer_uncorr_mask); > + > + pci_save_state(usp); > + dev_dbg(&usp->dev, "Uncorrectable Internal Errors downgraded and unmasked\n"); > +} > +#endif > + > +/** > + * xe_ras_init - Initialize Xe RAS > + * @xe: xe device instance > + * > + * Initialize Xe RAS > + */ > +void xe_ras_init(struct xe_device *xe) > +{ > + if (!xe->info.has_sysctrl || IS_SRIOV_VF(xe)) > + return; > + > +#ifdef CONFIG_PCIEAER > + aer_unmask_and_downgrade_internal_error(xe); > +#endif > +} > diff --git a/drivers/gpu/drm/xe/xe_ras.h b/drivers/gpu/drm/xe/xe_ras.h > index ea90593b62dc..a88ea0a46766 100644 > --- a/drivers/gpu/drm/xe/xe_ras.h > +++ b/drivers/gpu/drm/xe/xe_ras.h > @@ -11,5 +11,5 @@ struct xe_sysctrl_event_response; > > void xe_ras_counter_threshold_crossed(struct xe_device *xe, > struct xe_sysctrl_event_response *response); > - > +void xe_ras_init(struct xe_device *xe); > #endif