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From: Riana Tauro <riana.tauro@intel.com>
To: Raag Jadav <raag.jadav@intel.com>
Cc: <intel-xe@lists.freedesktop.org>,
	<dri-devel@lists.freedesktop.org>,
	<aravind.iddamsetty@linux.intel.com>, <anshuman.gupta@intel.com>,
	<rodrigo.vivi@intel.com>, <joonas.lahtinen@linux.intel.com>,
	<simona.vetter@ffwll.ch>, <airlied@gmail.com>,
	<pratik.bari@intel.com>, <joshua.santosh.ranjan@intel.com>,
	<ashwin.kumar.kulkarni@intel.com>, <shubham.kumar@intel.com>,
	<ravi.kishore.koppuravuri@intel.com>
Subject: Re: [PATCH v5 3/5] drm/xe/xe_hw_error: Integrate DRM RAS with hardware error handling
Date: Tue, 10 Feb 2026 10:28:22 +0530	[thread overview]
Message-ID: <ce578a81-920d-4f5f-92aa-6f251aa3625f@intel.com> (raw)
In-Reply-To: <aYRVLYCqT9_SKX8k@black.igk.intel.com>



On 2/5/2026 2:00 PM, Raag Jadav wrote:
> On Mon, Feb 02, 2026 at 12:13:59PM +0530, Riana Tauro wrote:
>> Initialize DRM RAS in hw error init. Map the UAPI error severities
>> with the hardware error severities and refactor file.
>>
>> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
>> ---
>>   drivers/gpu/drm/xe/xe_drm_ras_types.h |  8 ++++
>>   drivers/gpu/drm/xe/xe_hw_error.c      | 68 ++++++++++++++++-----------
>>   2 files changed, 48 insertions(+), 28 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_drm_ras_types.h b/drivers/gpu/drm/xe/xe_drm_ras_types.h
>> index 0ac4ae324f37..beed48811d6a 100644
>> --- a/drivers/gpu/drm/xe/xe_drm_ras_types.h
>> +++ b/drivers/gpu/drm/xe/xe_drm_ras_types.h
>> @@ -11,6 +11,14 @@
>>   
>>   struct drm_ras_node;
>>   
>> +/* Error categories reported by hardware */
>> +enum hardware_error {
>> +	HARDWARE_ERROR_CORRECTABLE = 0,
>> +	HARDWARE_ERROR_NONFATAL = 1,
>> +	HARDWARE_ERROR_FATAL = 2,
> 
> I'd align "= x" using tabs for readability.

Will remove the values except the start

> 
>> +	HARDWARE_ERROR_MAX,
> 
> Guaranteed last member, so redundant comma.

Will fix it

> 
>> +};
> 
> Also, just curious. Are these expected to be reused anywhere?
> If not, they're probably better off in the .c file.
> 
> ...
> 
>> @@ -86,8 +78,8 @@ static void csc_hw_error_handler(struct xe_tile *tile, const enum hardware_error
>>   		fw_err = xe_mmio_read32(mmio, HEC_UNCORR_FW_ERR_DW0(base));
>>   		for_each_set_bit(err_bit, &fw_err, HEC_UNCORR_FW_ERR_BITS) {
>>   			drm_err_ratelimited(&xe->drm, HW_ERR
>> -					    "%s: HEC Uncorrected FW %s error reported, bit[%d] is set\n",
>> -					     hw_err_str, hec_uncorrected_fw_errors[err_bit],
>> +					    "HEC FW %s error reported, bit[%d] is set\n",
>> +					     hec_uncorrected_fw_errors[err_bit],
> 
> So we're dropping severity_str here? Did I miss something?

I removed it because uncorrected was mentioned in log. But removed that 
also by mistake

Will fix this. Thanks for catching this

> 
>>   					     err_bit);
> 
> ...
> 
>> +static int hw_error_info_init(struct xe_device *xe)
>> +{
>> +	int ret;
>> +
>> +	if (xe->info.platform != XE_PVC)
>> +		return 0;
>> +
>> +	ret = xe_drm_ras_allocate_nodes(xe);
> 
> Why not just
> 
> 	return xe_drm_ras_allocate_nodes();
> 
> Tidy? ;)

okay

> 
>> +	if (ret)
>> +		return ret;
>> +
>> +	return 0;
>> +}
>> +
>>   /*
>>    * Process hardware errors during boot
>>    */
>> @@ -172,11 +179,16 @@ static void process_hw_errors(struct xe_device *xe)
>>   void xe_hw_error_init(struct xe_device *xe)
>>   {
>>   	struct xe_tile *tile = xe_device_get_root_tile(xe);
>> +	int ret;
>>   
>>   	if (!IS_DGFX(xe) || IS_SRIOV_VF(xe))
>>   		return;
>>   
>>   	INIT_WORK(&tile->csc_hw_error_work, csc_hw_error_work);
>>   
>> +	ret = hw_error_info_init(xe);
>> +	if (ret)
>> +		drm_warn(&xe->drm, "Failed to allocate DRM RAS nodes\n");
> 
> This is less likely due to any hardware limitation, so I think
> drm_err() would be more appropriate here.

okay will fix it

Thanks
Riana

> 
> Raag
> 
>> +
>>   	process_hw_errors(xe);
>>   }
>> -- 
>> 2.47.1
>>


  reply	other threads:[~2026-02-10  4:58 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-02-02  6:43 [PATCH v5 0/5] Introduce DRM_RAS using generic netlink for RAS Riana Tauro
2026-02-02  6:43 ` [PATCH v5 1/5] drm/ras: Introduce the DRM RAS infrastructure over generic netlink Riana Tauro
2026-02-02 10:08   ` kernel test robot
2026-02-02 22:52   ` kernel test robot
2026-02-02  6:43 ` [PATCH v5 2/5] drm/xe/xe_drm_ras: Add support for XE DRM RAS Riana Tauro
2026-02-03 17:58   ` Raag Jadav
2026-02-10  4:20     ` Riana Tauro
2026-02-02  6:43 ` [PATCH v5 3/5] drm/xe/xe_hw_error: Integrate DRM RAS with hardware error handling Riana Tauro
2026-02-05  8:30   ` Raag Jadav
2026-02-10  4:58     ` Riana Tauro [this message]
2026-02-10  4:59       ` Riana Tauro
2026-02-02  6:44 ` [PATCH v5 4/5] drm/xe/xe_hw_error: Add support for Core-Compute errors Riana Tauro
2026-02-05 15:30   ` Raag Jadav
2026-02-10  5:58     ` Riana Tauro
2026-02-10 11:45       ` Raag Jadav
2026-02-12  3:25         ` Riana Tauro
2026-02-02  6:44 ` [PATCH v5 5/5] drm/xe/xe_hw_error: Add support for PVC SoC errors Riana Tauro
2026-02-05 18:10   ` Raag Jadav
2026-02-10  6:32     ` Riana Tauro
2026-02-10 11:52       ` Raag Jadav
2026-02-02 16:15 ` ✗ CI.checkpatch: warning for Introduce DRM_RAS using generic netlink for RAS (rev5) Patchwork
2026-02-02 16:16 ` ✓ CI.KUnit: success " Patchwork
2026-02-02 16:31 ` ✗ CI.checksparse: warning " Patchwork
2026-02-02 16:51 ` ✓ Xe.CI.BAT: success " Patchwork

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