[PATCH 00/12] drm/i915: mem/fsb/rawclk freq cleanups

[PATCH 00/12] drm/i915: mem/fsb/rawclk freq cleanups

[Jani Nikula]

This is a rewitten version of [1]. I think it's good progress overall
though there are still minor issues here and there.

BR,
Jani.


[1] https://lore.kernel.org/all/20240408172315.3418692-1-jani.nikula@intel.com/

Jani Nikula (12):
  drm/i915/wm: rename intel_get_cxsr_latency -> pnv_get_cxsr_latency
  drm/i915/wm: clarify logging on not finding CxSR latency config
  drm/i915/dram: separate fsb freq detection from mem freq
  drm/i915/dram: split out pnv DDR3 detection
  drm/i915/dram: rearrange mem freq init
  drm/i915: convert fsb_freq and mem_freq to kHz
  drm/i915: extend the fsb_freq initialization to more platforms
  drm/i915: use i9xx_fsb_freq() for GT clock frequency
  drm/i915/cdclk: use i9xx_fsb_freq() for rawclk_freq initialization
  drm/i915: move rawclk init to intel_cdclk_init()
  drm/i915: move rawclk from runtime to display runtime info
  drm/xe/display: drop unused rawclk_freq and RUNTIME_INFO()

 drivers/gpu/drm/i915/display/i9xx_wm.c        |  27 ++-
 .../gpu/drm/i915/display/intel_backlight.c    |  10 +-
 drivers/gpu/drm/i915/display/intel_cdclk.c    |  69 ++----
 drivers/gpu/drm/i915/display/intel_cdclk.h    |   1 -
 .../drm/i915/display/intel_display_device.c   |   2 +
 .../drm/i915/display/intel_display_device.h   |   2 +
 .../i915/display/intel_display_power_well.c   |   4 +-
 drivers/gpu/drm/i915/display/intel_dp_aux.c   |   4 +-
 drivers/gpu/drm/i915/display/intel_pps.c      |   2 +-
 .../gpu/drm/i915/gt/intel_gt_clock_utils.c    |   3 +-
 drivers/gpu/drm/i915/gt/intel_rps.c           |   4 +-
 drivers/gpu/drm/i915/intel_device_info.c      |   5 -
 drivers/gpu/drm/i915/intel_device_info.h      |   2 -
 drivers/gpu/drm/i915/soc/intel_dram.c         | 203 ++++++++++--------
 drivers/gpu/drm/i915/soc/intel_dram.h         |   1 +
 .../gpu/drm/xe/compat-i915-headers/i915_drv.h |   1 -
 drivers/gpu/drm/xe/xe_device_types.h          |   6 -
 17 files changed, 164 insertions(+), 182 deletions(-)

-- 
2.39.2

[PATCH 01/12] drm/i915/wm: rename intel_get_cxsr_latency -> pnv_get_cxsr_latency

[Jani Nikula]

Clarify that the function is specific to PNV, making subsequent changes
slightly easier to grasp.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/i9xx_wm.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
index 628e7192ebc9..8657ec0abd2d 100644
--- a/drivers/gpu/drm/i915/display/i9xx_wm.c
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
@@ -70,7 +70,7 @@ static const struct cxsr_latency cxsr_latency_table[] = {
 	{0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 };
 
-static const struct cxsr_latency *intel_get_cxsr_latency(struct drm_i915_private *i915)
+static const struct cxsr_latency *pnv_get_cxsr_latency(struct drm_i915_private *i915)
 {
 	int i;
 
@@ -635,7 +635,7 @@ static void pnv_update_wm(struct drm_i915_private *dev_priv)
 	u32 reg;
 	unsigned int wm;
 
-	latency = intel_get_cxsr_latency(dev_priv);
+	latency = pnv_get_cxsr_latency(dev_priv);
 	if (!latency) {
 		drm_dbg_kms(&dev_priv->drm,
 			    "Unknown FSB/MEM found, disable CxSR\n");
@@ -4022,7 +4022,7 @@ void i9xx_wm_init(struct drm_i915_private *dev_priv)
 		g4x_setup_wm_latency(dev_priv);
 		dev_priv->display.funcs.wm = &g4x_wm_funcs;
 	} else if (IS_PINEVIEW(dev_priv)) {
-		if (!intel_get_cxsr_latency(dev_priv)) {
+		if (!pnv_get_cxsr_latency(dev_priv)) {
 			drm_info(&dev_priv->drm,
 				 "failed to find known CxSR latency "
 				 "(found ddr%s fsb freq %d, mem freq %d), "
-- 
2.39.2

[PATCH 02/12] drm/i915/wm: clarify logging on not finding CxSR latency config

[Jani Nikula]

Clarify and unify the logging on not finding PNV CxSR latency config.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/i9xx_wm.c | 17 +++++++----------
 1 file changed, 7 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
index 8657ec0abd2d..8b8a0f305c3a 100644
--- a/drivers/gpu/drm/i915/display/i9xx_wm.c
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
@@ -75,7 +75,7 @@ static const struct cxsr_latency *pnv_get_cxsr_latency(struct drm_i915_private *
 	int i;
 
 	if (i915->fsb_freq == 0 || i915->mem_freq == 0)
-		return NULL;
+		goto err;
 
 	for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 		const struct cxsr_latency *latency = &cxsr_latency_table[i];
@@ -88,7 +88,10 @@ static const struct cxsr_latency *pnv_get_cxsr_latency(struct drm_i915_private *
 			return latency;
 	}
 
-	drm_dbg_kms(&i915->drm, "Unknown FSB/MEM found, disable CxSR\n");
+err:
+	drm_dbg_kms(&i915->drm,
+		    "Could not find CxSR latency for DDR%s, FSB %u MHz, MEM %u MHz\n",
+		    i915->is_ddr3 ? "3" : "2", i915->fsb_freq, i915->mem_freq);
 
 	return NULL;
 }
@@ -637,8 +640,7 @@ static void pnv_update_wm(struct drm_i915_private *dev_priv)
 
 	latency = pnv_get_cxsr_latency(dev_priv);
 	if (!latency) {
-		drm_dbg_kms(&dev_priv->drm,
-			    "Unknown FSB/MEM found, disable CxSR\n");
+		drm_dbg_kms(&dev_priv->drm, "Unknown FSB/MEM, disabling CxSR\n");
 		intel_set_memory_cxsr(dev_priv, false);
 		return;
 	}
@@ -4023,12 +4025,7 @@ void i9xx_wm_init(struct drm_i915_private *dev_priv)
 		dev_priv->display.funcs.wm = &g4x_wm_funcs;
 	} else if (IS_PINEVIEW(dev_priv)) {
 		if (!pnv_get_cxsr_latency(dev_priv)) {
-			drm_info(&dev_priv->drm,
-				 "failed to find known CxSR latency "
-				 "(found ddr%s fsb freq %d, mem freq %d), "
-				 "disabling CxSR\n",
-				 (dev_priv->is_ddr3 == 1) ? "3" : "2",
-				 dev_priv->fsb_freq, dev_priv->mem_freq);
+			drm_info(&dev_priv->drm,  "Unknown FSB/MEM, disabling CxSR\n");
 			/* Disable CxSR and never update its watermark again */
 			intel_set_memory_cxsr(dev_priv, false);
 			dev_priv->display.funcs.wm = &nop_funcs;
-- 
2.39.2

[PATCH 03/12] drm/i915/dram: separate fsb freq detection from mem freq

[Jani Nikula]

To simplify further changes, add separate functions for reading the fsb
frequency.

This ends up reading CLKCFG register twice, but it's not a big deal.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/soc/intel_dram.c | 106 +++++++++++++++-----------
 1 file changed, 60 insertions(+), 46 deletions(-)

diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c
index 18a879e98f03..3dce9b9a2c5e 100644
--- a/drivers/gpu/drm/i915/soc/intel_dram.c
+++ b/drivers/gpu/drm/i915/soc/intel_dram.c
@@ -49,21 +49,6 @@ static void pnv_detect_mem_freq(struct drm_i915_private *dev_priv)
 
 	tmp = intel_uncore_read(&dev_priv->uncore, CLKCFG);
 
-	switch (tmp & CLKCFG_FSB_MASK) {
-	case CLKCFG_FSB_533:
-		dev_priv->fsb_freq = 533; /* 133*4 */
-		break;
-	case CLKCFG_FSB_800:
-		dev_priv->fsb_freq = 800; /* 200*4 */
-		break;
-	case CLKCFG_FSB_667:
-		dev_priv->fsb_freq =  667; /* 167*4 */
-		break;
-	case CLKCFG_FSB_400:
-		dev_priv->fsb_freq = 400; /* 100*4 */
-		break;
-	}
-
 	switch (tmp & CLKCFG_MEM_MASK) {
 	case CLKCFG_MEM_533:
 		dev_priv->mem_freq = 533;
@@ -83,7 +68,7 @@ static void pnv_detect_mem_freq(struct drm_i915_private *dev_priv)
 
 static void ilk_detect_mem_freq(struct drm_i915_private *dev_priv)
 {
-	u16 ddrpll, csipll;
+	u16 ddrpll;
 
 	ddrpll = intel_uncore_read16(&dev_priv->uncore, DDRMPLL1);
 	switch (ddrpll & 0xff) {
@@ -105,36 +90,6 @@ static void ilk_detect_mem_freq(struct drm_i915_private *dev_priv)
 		dev_priv->mem_freq = 0;
 		break;
 	}
-
-	csipll = intel_uncore_read16(&dev_priv->uncore, CSIPLL0);
-	switch (csipll & 0x3ff) {
-	case 0x00c:
-		dev_priv->fsb_freq = 3200;
-		break;
-	case 0x00e:
-		dev_priv->fsb_freq = 3733;
-		break;
-	case 0x010:
-		dev_priv->fsb_freq = 4266;
-		break;
-	case 0x012:
-		dev_priv->fsb_freq = 4800;
-		break;
-	case 0x014:
-		dev_priv->fsb_freq = 5333;
-		break;
-	case 0x016:
-		dev_priv->fsb_freq = 5866;
-		break;
-	case 0x018:
-		dev_priv->fsb_freq = 6400;
-		break;
-	default:
-		drm_dbg(&dev_priv->drm, "unknown fsb frequency 0x%04x\n",
-			csipll & 0x3ff);
-		dev_priv->fsb_freq = 0;
-		break;
-	}
 }
 
 static void chv_detect_mem_freq(struct drm_i915_private *i915)
@@ -192,6 +147,64 @@ static void detect_mem_freq(struct drm_i915_private *i915)
 		drm_dbg(&i915->drm, "DDR speed: %d MHz\n", i915->mem_freq);
 }
 
+static unsigned int pnv_fsb_freq(struct drm_i915_private *i915)
+{
+	u32 fsb;
+
+	fsb = intel_uncore_read(&i915->uncore, CLKCFG) & CLKCFG_FSB_MASK;
+
+	switch (fsb) {
+	case CLKCFG_FSB_400:
+		return 400;
+	case CLKCFG_FSB_533:
+		return 533;
+	case CLKCFG_FSB_667:
+		return 667;
+	case CLKCFG_FSB_800:
+		return 800;
+	}
+
+	return 0;
+}
+
+static unsigned int ilk_fsb_freq(struct drm_i915_private *dev_priv)
+{
+	u16 fsb;
+
+	fsb = intel_uncore_read16(&dev_priv->uncore, CSIPLL0) & 0x3ff;
+
+	switch (fsb) {
+	case 0x00c:
+		return 3200;
+	case 0x00e:
+		return 3733;
+	case 0x010:
+		return 4266;
+	case 0x012:
+		return 4800;
+	case 0x014:
+		return 5333;
+	case 0x016:
+		return 5866;
+	case 0x018:
+		return 6400;
+	default:
+		drm_dbg(&dev_priv->drm, "unknown fsb frequency 0x%04x\n", fsb);
+		return 0;
+	}
+}
+
+static void detect_fsb_freq(struct drm_i915_private *i915)
+{
+	if (GRAPHICS_VER(i915) == 5)
+		i915->fsb_freq = ilk_fsb_freq(i915);
+	else if (IS_PINEVIEW(i915))
+		i915->fsb_freq = pnv_fsb_freq(i915);
+
+	if (i915->fsb_freq)
+		drm_dbg(&i915->drm, "FSB frequency: %d MHz\n", i915->fsb_freq);
+}
+
 static int intel_dimm_num_devices(const struct dram_dimm_info *dimm)
 {
 	return dimm->ranks * 64 / (dimm->width ?: 1);
@@ -661,6 +674,7 @@ void intel_dram_detect(struct drm_i915_private *i915)
 	struct dram_info *dram_info = &i915->dram_info;
 	int ret;
 
+	detect_fsb_freq(i915);
 	detect_mem_freq(i915);
 
 	if (GRAPHICS_VER(i915) < 9 || IS_DG2(i915) || !HAS_DISPLAY(i915))
-- 
2.39.2

[PATCH 04/12] drm/i915/dram: split out pnv DDR3 detection

[Jani Nikula]

Split out the PNV DDR3 detection to a distinct step instead of
conflating it with mem freq detection.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/soc/intel_dram.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c
index 3dce9b9a2c5e..1a4db52ac258 100644
--- a/drivers/gpu/drm/i915/soc/intel_dram.c
+++ b/drivers/gpu/drm/i915/soc/intel_dram.c
@@ -43,6 +43,11 @@ static const char *intel_dram_type_str(enum intel_dram_type type)
 
 #undef DRAM_TYPE_STR
 
+static bool pnv_is_ddr3(struct drm_i915_private *i915)
+{
+	return intel_uncore_read(&i915->uncore, CSHRDDR3CTL) & CSHRDDR3CTL_DDR3;
+}
+
 static void pnv_detect_mem_freq(struct drm_i915_private *dev_priv)
 {
 	u32 tmp;
@@ -60,10 +65,6 @@ static void pnv_detect_mem_freq(struct drm_i915_private *dev_priv)
 		dev_priv->mem_freq = 800;
 		break;
 	}
-
-	/* detect pineview DDR3 setting */
-	tmp = intel_uncore_read(&dev_priv->uncore, CSHRDDR3CTL);
-	dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 }
 
 static void ilk_detect_mem_freq(struct drm_i915_private *dev_priv)
@@ -143,6 +144,9 @@ static void detect_mem_freq(struct drm_i915_private *i915)
 	else if (IS_VALLEYVIEW(i915))
 		vlv_detect_mem_freq(i915);
 
+	if (IS_PINEVIEW(i915))
+		i915->is_ddr3 = pnv_is_ddr3(i915);
+
 	if (i915->mem_freq)
 		drm_dbg(&i915->drm, "DDR speed: %d MHz\n", i915->mem_freq);
 }
-- 
2.39.2

[PATCH 05/12] drm/i915/dram: rearrange mem freq init

[Jani Nikula]

Follow the same style in mem freq init as in fsb freq init, returning
the value instead of assigning in multiple places.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/soc/intel_dram.c | 59 ++++++++++++---------------
 1 file changed, 25 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c
index 1a4db52ac258..266ed6cfa485 100644
--- a/drivers/gpu/drm/i915/soc/intel_dram.c
+++ b/drivers/gpu/drm/i915/soc/intel_dram.c
@@ -48,7 +48,7 @@ static bool pnv_is_ddr3(struct drm_i915_private *i915)
 	return intel_uncore_read(&i915->uncore, CSHRDDR3CTL) & CSHRDDR3CTL_DDR3;
 }
 
-static void pnv_detect_mem_freq(struct drm_i915_private *dev_priv)
+static unsigned int pnv_mem_freq(struct drm_i915_private *dev_priv)
 {
 	u32 tmp;
 
@@ -56,44 +56,38 @@ static void pnv_detect_mem_freq(struct drm_i915_private *dev_priv)
 
 	switch (tmp & CLKCFG_MEM_MASK) {
 	case CLKCFG_MEM_533:
-		dev_priv->mem_freq = 533;
-		break;
+		return 533;
 	case CLKCFG_MEM_667:
-		dev_priv->mem_freq = 667;
-		break;
+		return 667;
 	case CLKCFG_MEM_800:
-		dev_priv->mem_freq = 800;
-		break;
+		return 800;
 	}
+
+	return 0;
 }
 
-static void ilk_detect_mem_freq(struct drm_i915_private *dev_priv)
+static unsigned int ilk_mem_freq(struct drm_i915_private *dev_priv)
 {
 	u16 ddrpll;
 
 	ddrpll = intel_uncore_read16(&dev_priv->uncore, DDRMPLL1);
 	switch (ddrpll & 0xff) {
 	case 0xc:
-		dev_priv->mem_freq = 800;
-		break;
+		return 800;
 	case 0x10:
-		dev_priv->mem_freq = 1066;
-		break;
+		return 1066;
 	case 0x14:
-		dev_priv->mem_freq = 1333;
-		break;
+		return 1333;
 	case 0x18:
-		dev_priv->mem_freq = 1600;
-		break;
+		return 1600;
 	default:
 		drm_dbg(&dev_priv->drm, "unknown memory frequency 0x%02x\n",
 			ddrpll & 0xff);
-		dev_priv->mem_freq = 0;
-		break;
+		return 0;
 	}
 }
 
-static void chv_detect_mem_freq(struct drm_i915_private *i915)
+static unsigned int chv_mem_freq(struct drm_i915_private *i915)
 {
 	u32 val;
 
@@ -103,15 +97,13 @@ static void chv_detect_mem_freq(struct drm_i915_private *i915)
 
 	switch ((val >> 2) & 0x7) {
 	case 3:
-		i915->mem_freq = 2000;
-		break;
+		return 2000;
 	default:
-		i915->mem_freq = 1600;
-		break;
+		return 1600;
 	}
 }
 
-static void vlv_detect_mem_freq(struct drm_i915_private *i915)
+static unsigned int vlv_mem_freq(struct drm_i915_private *i915)
 {
 	u32 val;
 
@@ -122,27 +114,26 @@ static void vlv_detect_mem_freq(struct drm_i915_private *i915)
 	switch ((val >> 6) & 3) {
 	case 0:
 	case 1:
-		i915->mem_freq = 800;
-		break;
+		return 800;
 	case 2:
-		i915->mem_freq = 1066;
-		break;
+		return 1066;
 	case 3:
-		i915->mem_freq = 1333;
-		break;
+		return 1333;
 	}
+
+	return 0;
 }
 
 static void detect_mem_freq(struct drm_i915_private *i915)
 {
 	if (IS_PINEVIEW(i915))
-		pnv_detect_mem_freq(i915);
+		i915->mem_freq = pnv_mem_freq(i915);
 	else if (GRAPHICS_VER(i915) == 5)
-		ilk_detect_mem_freq(i915);
+		i915->mem_freq = ilk_mem_freq(i915);
 	else if (IS_CHERRYVIEW(i915))
-		chv_detect_mem_freq(i915);
+		i915->mem_freq = chv_mem_freq(i915);
 	else if (IS_VALLEYVIEW(i915))
-		vlv_detect_mem_freq(i915);
+		i915->mem_freq = vlv_mem_freq(i915);
 
 	if (IS_PINEVIEW(i915))
 		i915->is_ddr3 = pnv_is_ddr3(i915);
-- 
2.39.2

[PATCH 06/12] drm/i915: convert fsb_freq and mem_freq to kHz

[Jani Nikula]

We'll want to use fsb frequency for deriving GT clock and rawclk
frequencies in the future. Increase the accuracy by converting to
kHz. Do the same for mem freq to be aligned.

Round the frequencies ending in 666 to 667.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/i9xx_wm.c |  6 ++--
 drivers/gpu/drm/i915/gt/intel_rps.c    |  4 +--
 drivers/gpu/drm/i915/soc/intel_dram.c  | 50 +++++++++++++-------------
 3 files changed, 30 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
index 8b8a0f305c3a..08c5d122af8f 100644
--- a/drivers/gpu/drm/i915/display/i9xx_wm.c
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
@@ -83,14 +83,14 @@ static const struct cxsr_latency *pnv_get_cxsr_latency(struct drm_i915_private *
 
 		if (is_desktop == latency->is_desktop &&
 		    i915->is_ddr3 == latency->is_ddr3 &&
-		    i915->fsb_freq == latency->fsb_freq &&
-		    i915->mem_freq == latency->mem_freq)
+		    DIV_ROUND_CLOSEST(i915->fsb_freq, 1000) == latency->fsb_freq &&
+		    DIV_ROUND_CLOSEST(i915->mem_freq, 1000) == latency->mem_freq)
 			return latency;
 	}
 
 err:
 	drm_dbg_kms(&i915->drm,
-		    "Could not find CxSR latency for DDR%s, FSB %u MHz, MEM %u MHz\n",
+		    "Could not find CxSR latency for DDR%s, FSB %u kHz, MEM %u kHz\n",
 		    i915->is_ddr3 ? "3" : "2", i915->fsb_freq, i915->mem_freq);
 
 	return NULL;
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index c9cb2a391942..5d3de1cddcf6 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -280,9 +280,9 @@ static void gen5_rps_init(struct intel_rps *rps)
 	u32 rgvmodectl;
 	int c_m, i;
 
-	if (i915->fsb_freq <= 3200)
+	if (i915->fsb_freq <= 3200000)
 		c_m = 0;
-	else if (i915->fsb_freq <= 4800)
+	else if (i915->fsb_freq <= 4800000)
 		c_m = 1;
 	else
 		c_m = 2;
diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c
index 266ed6cfa485..ace9372244a4 100644
--- a/drivers/gpu/drm/i915/soc/intel_dram.c
+++ b/drivers/gpu/drm/i915/soc/intel_dram.c
@@ -56,11 +56,11 @@ static unsigned int pnv_mem_freq(struct drm_i915_private *dev_priv)
 
 	switch (tmp & CLKCFG_MEM_MASK) {
 	case CLKCFG_MEM_533:
-		return 533;
+		return 533333;
 	case CLKCFG_MEM_667:
-		return 667;
+		return 666667;
 	case CLKCFG_MEM_800:
-		return 800;
+		return 800000;
 	}
 
 	return 0;
@@ -73,13 +73,13 @@ static unsigned int ilk_mem_freq(struct drm_i915_private *dev_priv)
 	ddrpll = intel_uncore_read16(&dev_priv->uncore, DDRMPLL1);
 	switch (ddrpll & 0xff) {
 	case 0xc:
-		return 800;
+		return 800000;
 	case 0x10:
-		return 1066;
+		return 1066667;
 	case 0x14:
-		return 1333;
+		return 1333333;
 	case 0x18:
-		return 1600;
+		return 1600000;
 	default:
 		drm_dbg(&dev_priv->drm, "unknown memory frequency 0x%02x\n",
 			ddrpll & 0xff);
@@ -97,9 +97,9 @@ static unsigned int chv_mem_freq(struct drm_i915_private *i915)
 
 	switch ((val >> 2) & 0x7) {
 	case 3:
-		return 2000;
+		return 2000000;
 	default:
-		return 1600;
+		return 1600000;
 	}
 }
 
@@ -114,11 +114,11 @@ static unsigned int vlv_mem_freq(struct drm_i915_private *i915)
 	switch ((val >> 6) & 3) {
 	case 0:
 	case 1:
-		return 800;
+		return 800000;
 	case 2:
-		return 1066;
+		return 1066667;
 	case 3:
-		return 1333;
+		return 1333333;
 	}
 
 	return 0;
@@ -139,7 +139,7 @@ static void detect_mem_freq(struct drm_i915_private *i915)
 		i915->is_ddr3 = pnv_is_ddr3(i915);
 
 	if (i915->mem_freq)
-		drm_dbg(&i915->drm, "DDR speed: %d MHz\n", i915->mem_freq);
+		drm_dbg(&i915->drm, "DDR speed: %d kHz\n", i915->mem_freq);
 }
 
 static unsigned int pnv_fsb_freq(struct drm_i915_private *i915)
@@ -150,13 +150,13 @@ static unsigned int pnv_fsb_freq(struct drm_i915_private *i915)
 
 	switch (fsb) {
 	case CLKCFG_FSB_400:
-		return 400;
+		return 400000;
 	case CLKCFG_FSB_533:
-		return 533;
+		return 533333;
 	case CLKCFG_FSB_667:
-		return 667;
+		return 666667;
 	case CLKCFG_FSB_800:
-		return 800;
+		return 800000;
 	}
 
 	return 0;
@@ -170,19 +170,19 @@ static unsigned int ilk_fsb_freq(struct drm_i915_private *dev_priv)
 
 	switch (fsb) {
 	case 0x00c:
-		return 3200;
+		return 3200000;
 	case 0x00e:
-		return 3733;
+		return 3733333;
 	case 0x010:
-		return 4266;
+		return 4266667;
 	case 0x012:
-		return 4800;
+		return 4800000;
 	case 0x014:
-		return 5333;
+		return 5333333;
 	case 0x016:
-		return 5866;
+		return 5866667;
 	case 0x018:
-		return 6400;
+		return 6400000;
 	default:
 		drm_dbg(&dev_priv->drm, "unknown fsb frequency 0x%04x\n", fsb);
 		return 0;
@@ -197,7 +197,7 @@ static void detect_fsb_freq(struct drm_i915_private *i915)
 		i915->fsb_freq = pnv_fsb_freq(i915);
 
 	if (i915->fsb_freq)
-		drm_dbg(&i915->drm, "FSB frequency: %d MHz\n", i915->fsb_freq);
+		drm_dbg(&i915->drm, "FSB frequency: %d kHz\n", i915->fsb_freq);
 }
 
 static int intel_dimm_num_devices(const struct dram_dimm_info *dimm)
-- 
2.39.2

[PATCH 07/12] drm/i915: extend the fsb_freq initialization to more platforms

[Jani Nikula]

Initialize fsb frequency for more platforms to be able to use it for GT
clock and rawclk frequency initialization.

Note: There's a discrepancy between existing pnv_fsb_freq() and
i9xx_hrawclk() regarding CLKCFG interpretation. Presume all PNV is
mobile.

FIXME: What should the default or failure mode be when the value is
unknown?

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/soc/intel_dram.c | 54 ++++++++++++++++++++-------
 1 file changed, 40 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c
index ace9372244a4..74b5b70e91f9 100644
--- a/drivers/gpu/drm/i915/soc/intel_dram.c
+++ b/drivers/gpu/drm/i915/soc/intel_dram.c
@@ -142,24 +142,50 @@ static void detect_mem_freq(struct drm_i915_private *i915)
 		drm_dbg(&i915->drm, "DDR speed: %d kHz\n", i915->mem_freq);
 }
 
-static unsigned int pnv_fsb_freq(struct drm_i915_private *i915)
+static unsigned int i9xx_fsb_freq(struct drm_i915_private *i915)
 {
 	u32 fsb;
 
 	fsb = intel_uncore_read(&i915->uncore, CLKCFG) & CLKCFG_FSB_MASK;
 
-	switch (fsb) {
-	case CLKCFG_FSB_400:
-		return 400000;
-	case CLKCFG_FSB_533:
-		return 533333;
-	case CLKCFG_FSB_667:
-		return 666667;
-	case CLKCFG_FSB_800:
-		return 800000;
+	if (IS_PINEVIEW(i915) || IS_MOBILE(i915)) {
+		switch (fsb) {
+		case CLKCFG_FSB_400:
+			return 400000;
+		case CLKCFG_FSB_533:
+			return 533333;
+		case CLKCFG_FSB_667:
+			return 666667;
+		case CLKCFG_FSB_800:
+			return 800000;
+		case CLKCFG_FSB_1067:
+			return 1066667;
+		case CLKCFG_FSB_1333:
+			return 1333333;
+		default:
+			MISSING_CASE(fsb);
+			return 1333333;
+		}
+	} else {
+		switch (fsb) {
+		case CLKCFG_FSB_400_ALT:
+			return 400000;
+		case CLKCFG_FSB_533:
+			return 533333;
+		case CLKCFG_FSB_667:
+			return 666667;
+		case CLKCFG_FSB_800:
+			return 800000;
+		case CLKCFG_FSB_1067_ALT:
+			return 1066667;
+		case CLKCFG_FSB_1333_ALT:
+			return 1333333;
+		case CLKCFG_FSB_1600_ALT:
+			return 1600000;
+		default:
+			return 533333;
+		}
 	}
-
-	return 0;
 }
 
 static unsigned int ilk_fsb_freq(struct drm_i915_private *dev_priv)
@@ -193,8 +219,8 @@ static void detect_fsb_freq(struct drm_i915_private *i915)
 {
 	if (GRAPHICS_VER(i915) == 5)
 		i915->fsb_freq = ilk_fsb_freq(i915);
-	else if (IS_PINEVIEW(i915))
-		i915->fsb_freq = pnv_fsb_freq(i915);
+	else if (GRAPHICS_VER(i915) == 3 || GRAPHICS_VER(i915) == 4)
+		i915->fsb_freq = i9xx_fsb_freq(i915);
 
 	if (i915->fsb_freq)
 		drm_dbg(&i915->drm, "FSB frequency: %d kHz\n", i915->fsb_freq);
-- 
2.39.2

[PATCH 08/12] drm/i915: use i9xx_fsb_freq() for GT clock frequency

[Jani Nikula]

Reuse i9xx_fsb_freq() for GT clock frequency initialization instead of
depending on rawclk_freq.

Note: If the init order was changed, we could use i915->fsb_freq
directly. However, GT clock initialization is done in
i915_driver_mmio_probe(), but intel_dram_detect() later in
i915_driver_hw_probe(), with a dependency on intel_pcode_init().

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c | 3 ++-
 drivers/gpu/drm/i915/soc/intel_dram.c          | 2 +-
 drivers/gpu/drm/i915/soc/intel_dram.h          | 1 +
 3 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
index 7c9be4fd1c8c..6e63505fe478 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
@@ -9,6 +9,7 @@
 #include "intel_gt_clock_utils.h"
 #include "intel_gt_print.h"
 #include "intel_gt_regs.h"
+#include "soc/intel_dram.h"
 
 static u32 read_reference_ts_freq(struct intel_uncore *uncore)
 {
@@ -151,7 +152,7 @@ static u32 gen4_read_clock_frequency(struct intel_uncore *uncore)
 	 *
 	 * Testing on actual hardware has shown there is no /16.
 	 */
-	return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000;
+	return DIV_ROUND_CLOSEST(i9xx_fsb_freq(uncore->i915), 4) * 1000;
 }
 
 static u32 read_clock_frequency(struct intel_uncore *uncore)
diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c
index 74b5b70e91f9..389bcf4b1abd 100644
--- a/drivers/gpu/drm/i915/soc/intel_dram.c
+++ b/drivers/gpu/drm/i915/soc/intel_dram.c
@@ -142,7 +142,7 @@ static void detect_mem_freq(struct drm_i915_private *i915)
 		drm_dbg(&i915->drm, "DDR speed: %d kHz\n", i915->mem_freq);
 }
 
-static unsigned int i9xx_fsb_freq(struct drm_i915_private *i915)
+unsigned int i9xx_fsb_freq(struct drm_i915_private *i915)
 {
 	u32 fsb;
 
diff --git a/drivers/gpu/drm/i915/soc/intel_dram.h b/drivers/gpu/drm/i915/soc/intel_dram.h
index 4ba13c13162c..a10136eda674 100644
--- a/drivers/gpu/drm/i915/soc/intel_dram.h
+++ b/drivers/gpu/drm/i915/soc/intel_dram.h
@@ -10,5 +10,6 @@ struct drm_i915_private;
 
 void intel_dram_edram_detect(struct drm_i915_private *i915);
 void intel_dram_detect(struct drm_i915_private *i915);
+unsigned int i9xx_fsb_freq(struct drm_i915_private *i915);
 
 #endif /* __INTEL_DRAM_H__ */
-- 
2.39.2

[PATCH 09/12] drm/i915/cdclk: use i9xx_fsb_freq() for rawclk_freq initialization

[Jani Nikula]

Instead of duplicating the CLKCFG parsing, reuse i9xx_fsb_freq() to
figure out rawclk_freq where applicable.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 46 ++--------------------
 1 file changed, 3 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index b78154c82a71..c731c489c925 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -23,6 +23,7 @@
 
 #include <linux/time.h>
 
+#include "soc/intel_dram.h"
 #include "hsw_ips.h"
 #include "i915_reg.h"
 #include "intel_atomic.h"
@@ -3529,10 +3530,8 @@ static int vlv_hrawclk(struct drm_i915_private *dev_priv)
 				      CCK_DISPLAY_REF_CLOCK_CONTROL);
 }
 
-static int i9xx_hrawclk(struct drm_i915_private *dev_priv)
+static int i9xx_hrawclk(struct drm_i915_private *i915)
 {
-	u32 clkcfg;
-
 	/*
 	 * hrawclock is 1/4 the FSB frequency
 	 *
@@ -3543,46 +3542,7 @@ static int i9xx_hrawclk(struct drm_i915_private *dev_priv)
 	 * don't know which registers have that information,
 	 * and all the relevant docs have gone to bit heaven :(
 	 */
-	clkcfg = intel_de_read(dev_priv, CLKCFG) & CLKCFG_FSB_MASK;
-
-	if (IS_MOBILE(dev_priv)) {
-		switch (clkcfg) {
-		case CLKCFG_FSB_400:
-			return 100000;
-		case CLKCFG_FSB_533:
-			return 133333;
-		case CLKCFG_FSB_667:
-			return 166667;
-		case CLKCFG_FSB_800:
-			return 200000;
-		case CLKCFG_FSB_1067:
-			return 266667;
-		case CLKCFG_FSB_1333:
-			return 333333;
-		default:
-			MISSING_CASE(clkcfg);
-			return 133333;
-		}
-	} else {
-		switch (clkcfg) {
-		case CLKCFG_FSB_400_ALT:
-			return 100000;
-		case CLKCFG_FSB_533:
-			return 133333;
-		case CLKCFG_FSB_667:
-			return 166667;
-		case CLKCFG_FSB_800:
-			return 200000;
-		case CLKCFG_FSB_1067_ALT:
-			return 266667;
-		case CLKCFG_FSB_1333_ALT:
-			return 333333;
-		case CLKCFG_FSB_1600_ALT:
-			return 400000;
-		default:
-			return 133333;
-		}
-	}
+	return DIV_ROUND_CLOSEST(i9xx_fsb_freq(i915), 4);
 }
 
 /**
-- 
2.39.2

[PATCH 10/12] drm/i915: move rawclk init to intel_cdclk_init()

[Jani Nikula]

The rawclk initialization is a bit out of place in
intel_device_info_runtime_init(). Move it to intel_cdclk_init(), with a
bit of refactoring on intel_read_rawclk().

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 23 +++++++++++-----------
 drivers/gpu/drm/i915/display/intel_cdclk.h |  1 -
 drivers/gpu/drm/i915/intel_device_info.c   |  4 ----
 3 files changed, 11 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index c731c489c925..55c2dfe5422f 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3218,6 +3218,8 @@ int intel_cdclk_state_set_joined_mbus(struct intel_atomic_state *state, bool joi
 	return intel_atomic_lock_global_state(&cdclk_state->base);
 }
 
+static void intel_rawclk_init(struct drm_i915_private *dev_priv);
+
 int intel_cdclk_init(struct drm_i915_private *dev_priv)
 {
 	struct intel_cdclk_state *cdclk_state;
@@ -3229,6 +3231,8 @@ int intel_cdclk_init(struct drm_i915_private *dev_priv)
 	intel_atomic_global_obj_init(dev_priv, &dev_priv->display.cdclk.obj,
 				     &cdclk_state->base, &intel_cdclk_funcs);
 
+	intel_rawclk_init(dev_priv);
+
 	return 0;
 }
 
@@ -3545,16 +3549,13 @@ static int i9xx_hrawclk(struct drm_i915_private *i915)
 	return DIV_ROUND_CLOSEST(i9xx_fsb_freq(i915), 4);
 }
 
-/**
- * intel_read_rawclk - Determine the current RAWCLK frequency
- * @dev_priv: i915 device
- *
- * Determine the current RAWCLK frequency. RAWCLK is a fixed
- * frequency clock so this needs to done only once.
+/*
+ * Initialize the current RAWCLK frequency. RAWCLK is a fixed frequency clock so
+ * this needs to done only once.
  */
-u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
+static void intel_rawclk_init(struct drm_i915_private *dev_priv)
 {
-	u32 freq;
+	u32 freq = 0;
 
 	if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTL)
 		/*
@@ -3573,11 +3574,9 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
 		freq = vlv_hrawclk(dev_priv);
 	else if (DISPLAY_VER(dev_priv) >= 3)
 		freq = i9xx_hrawclk(dev_priv);
-	else
-		/* no rawclk on other platforms, or no need to know it */
-		return 0;
 
-	return freq;
+	RUNTIME_INFO(dev_priv)->rawclk_freq = freq;
+	drm_dbg_kms(&dev_priv->drm, "rawclk rate: %d kHz\n", freq);
 }
 
 static int i915_cdclk_info_show(struct seq_file *m, void *unused)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index cfdcdec07a4d..a3f950d5a366 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -64,7 +64,6 @@ void intel_cdclk_uninit_hw(struct drm_i915_private *i915);
 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
 void intel_update_cdclk(struct drm_i915_private *dev_priv);
-u32 intel_read_rawclk(struct drm_i915_private *dev_priv);
 bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a,
 			       const struct intel_cdclk_config *b);
 int intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 862f4b705227..cc7a8fb0a87d 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -370,10 +370,6 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 			 "Disabling ppGTT for VT-d support\n");
 		runtime->ppgtt_type = INTEL_PPGTT_NONE;
 	}
-
-	runtime->rawclk_freq = intel_read_rawclk(dev_priv);
-	drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq);
-
 }
 
 /*
-- 
2.39.2

[PATCH 11/12] drm/i915: move rawclk from runtime to display runtime info

[Jani Nikula]

It's mostly about display, so move it under display.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_backlight.c         | 10 +++++-----
 drivers/gpu/drm/i915/display/intel_cdclk.c             |  2 +-
 drivers/gpu/drm/i915/display/intel_display_device.c    |  2 ++
 drivers/gpu/drm/i915/display/intel_display_device.h    |  2 ++
 .../gpu/drm/i915/display/intel_display_power_well.c    |  4 ++--
 drivers/gpu/drm/i915/display/intel_dp_aux.c            |  4 ++--
 drivers/gpu/drm/i915/display/intel_pps.c               |  2 +-
 drivers/gpu/drm/i915/intel_device_info.c               |  1 -
 drivers/gpu/drm/i915/intel_device_info.h               |  2 --
 9 files changed, 15 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c b/drivers/gpu/drm/i915/display/intel_backlight.c
index 071668bfe5d1..66ee925287c2 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -1011,7 +1011,7 @@ static u32 cnp_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
 {
 	struct drm_i915_private *i915 = to_i915(connector->base.dev);
 
-	return DIV_ROUND_CLOSEST(KHz(RUNTIME_INFO(i915)->rawclk_freq),
+	return DIV_ROUND_CLOSEST(KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq),
 				 pwm_freq_hz);
 }
 
@@ -1073,7 +1073,7 @@ static u32 pch_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
 {
 	struct drm_i915_private *i915 = to_i915(connector->base.dev);
 
-	return DIV_ROUND_CLOSEST(KHz(RUNTIME_INFO(i915)->rawclk_freq),
+	return DIV_ROUND_CLOSEST(KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq),
 				 pwm_freq_hz * 128);
 }
 
@@ -1091,7 +1091,7 @@ static u32 i9xx_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
 	int clock;
 
 	if (IS_PINEVIEW(i915))
-		clock = KHz(RUNTIME_INFO(i915)->rawclk_freq);
+		clock = KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq);
 	else
 		clock = KHz(i915->display.cdclk.hw.cdclk);
 
@@ -1109,7 +1109,7 @@ static u32 i965_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
 	int clock;
 
 	if (IS_G4X(i915))
-		clock = KHz(RUNTIME_INFO(i915)->rawclk_freq);
+		clock = KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq);
 	else
 		clock = KHz(i915->display.cdclk.hw.cdclk);
 
@@ -1133,7 +1133,7 @@ static u32 vlv_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
 			clock = MHz(25);
 		mul = 16;
 	} else {
-		clock = KHz(RUNTIME_INFO(i915)->rawclk_freq);
+		clock = KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq);
 		mul = 128;
 	}
 
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 55c2dfe5422f..ced320fbad46 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3575,7 +3575,7 @@ static void intel_rawclk_init(struct drm_i915_private *dev_priv)
 	else if (DISPLAY_VER(dev_priv) >= 3)
 		freq = i9xx_hrawclk(dev_priv);
 
-	RUNTIME_INFO(dev_priv)->rawclk_freq = freq;
+	DISPLAY_RUNTIME_INFO(dev_priv)->rawclk_freq = freq;
 	drm_dbg_kms(&dev_priv->drm, "rawclk rate: %d kHz\n", freq);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index cf093bc0cb28..a3d4d9ef6e33 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -1151,6 +1151,8 @@ void intel_display_device_info_print(const struct intel_display_device_info *inf
 	drm_printf(p, "has_hdcp: %s\n", str_yes_no(runtime->has_hdcp));
 	drm_printf(p, "has_dmc: %s\n", str_yes_no(runtime->has_dmc));
 	drm_printf(p, "has_dsc: %s\n", str_yes_no(runtime->has_dsc));
+
+	drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq);
 }
 
 /*
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 17ddf82f0b6e..aa627885758b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -111,6 +111,8 @@ struct drm_printer;
 	(DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
 
 struct intel_display_runtime_info {
+	u32 rawclk_freq;
+
 	struct {
 		u16 ver;
 		u16 rel;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 83f616097a29..a6b156c4388e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -1176,9 +1176,9 @@ static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
 		       MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
 	intel_de_write(dev_priv, CBR1_VLV, 0);
 
-	drm_WARN_ON(&dev_priv->drm, RUNTIME_INFO(dev_priv)->rawclk_freq == 0);
+	drm_WARN_ON(&dev_priv->drm, DISPLAY_RUNTIME_INFO(dev_priv)->rawclk_freq == 0);
 	intel_de_write(dev_priv, RAWCLK_FREQ_VLV,
-		       DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq,
+		       DIV_ROUND_CLOSEST(DISPLAY_RUNTIME_INFO(dev_priv)->rawclk_freq,
 					 1000));
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index b8a53bb174da..cbc817bb0cc3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -83,7 +83,7 @@ static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 	 * The clock divider is based off the hrawclk, and would like to run at
 	 * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
 	 */
-	return DIV_ROUND_CLOSEST(RUNTIME_INFO(i915)->rawclk_freq, 2000);
+	return DIV_ROUND_CLOSEST(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq, 2000);
 }
 
 static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
@@ -103,7 +103,7 @@ static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 	if (dig_port->aux_ch == AUX_CH_A)
 		freq = i915->display.cdclk.hw.cdclk;
 	else
-		freq = RUNTIME_INFO(i915)->rawclk_freq;
+		freq = DISPLAY_RUNTIME_INFO(i915)->rawclk_freq;
 	return DIV_ROUND_CLOSEST(freq, 2000);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 73046ef58d8e..8ca2800f614c 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -1468,7 +1468,7 @@ static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	u32 pp_on, pp_off, port_sel = 0;
-	int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000;
+	int div = DISPLAY_RUNTIME_INFO(dev_priv)->rawclk_freq / 1000;
 	struct pps_registers regs;
 	enum port port = dp_to_dig_port(intel_dp)->base.port;
 	const struct edp_power_seq *seq = &intel_dp->pps.pps_delays;
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index cc7a8fb0a87d..042e01124128 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -124,7 +124,6 @@ void intel_device_info_print(const struct intel_device_info *info,
 #undef PRINT_FLAG
 
 	drm_printf(p, "has_pooled_eu: %s\n", str_yes_no(runtime->has_pooled_eu));
-	drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq);
 }
 
 #define ID(id) (id)
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index d1a2abc7e513..fb8a08623eb0 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -204,8 +204,6 @@ struct intel_runtime_info {
 
 	u16 device_id;
 
-	u32 rawclk_freq;
-
 	struct intel_step_info step;
 
 	unsigned int page_sizes; /* page sizes supported by the HW */
-- 
2.39.2

[PATCH 12/12] drm/xe/display: drop unused rawclk_freq and RUNTIME_INFO()

[Jani Nikula]

With rawclk_freq moved to display runtime info, xe has no users left for
them.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 1 -
 drivers/gpu/drm/xe/xe_device_types.h              | 6 ------
 2 files changed, 7 deletions(-)

diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
index cd4632276141..6c5830875091 100644
--- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
+++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
@@ -181,7 +181,6 @@ struct i915_sched_attr {
 	     intel_runtime_pm_put((rpm), (wf)), (wf) = 0)
 
 #define pdev_to_i915 pdev_to_xe_device
-#define RUNTIME_INFO(xe)		(&(xe)->info.i915_runtime)
 
 #define FORCEWAKE_ALL XE_FORCEWAKE_ALL
 
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index d834905a3786..0211e4d8a0f2 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -288,12 +288,6 @@ struct xe_device {
 		u8 has_atomic_enable_pte_bit:1;
 		/** @info.has_device_atomics_on_smem: Supports device atomics on SMEM */
 		u8 has_device_atomics_on_smem:1;
-
-#if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
-		struct {
-			u32 rawclk_freq;
-		} i915_runtime;
-#endif
 	} info;
 
 	/** @irq: device interrupt state */
-- 
2.39.2

✓ CI.Patch_applied: success for drm/i915: mem/fsb/rawclk freq cleanups

[Patchwork]

== Series Details ==

Series: drm/i915: mem/fsb/rawclk freq cleanups
URL   : https://patchwork.freedesktop.org/series/134144/
State : success

== Summary ==

=== Applying kernel patches on branch 'drm-tip' with base: ===
Base commit: 19284ac03993 drm-tip: 2024y-05m-28d-14h-14m-11s UTC integration manifest
=== git am output follows ===
Applying: drm/i915/wm: rename intel_get_cxsr_latency -> pnv_get_cxsr_latency
Applying: drm/i915/wm: clarify logging on not finding CxSR latency config
Applying: drm/i915/dram: separate fsb freq detection from mem freq
Applying: drm/i915/dram: split out pnv DDR3 detection
Applying: drm/i915/dram: rearrange mem freq init
Applying: drm/i915: convert fsb_freq and mem_freq to kHz
Applying: drm/i915: extend the fsb_freq initialization to more platforms
Applying: drm/i915: use i9xx_fsb_freq() for GT clock frequency
Applying: drm/i915/cdclk: use i9xx_fsb_freq() for rawclk_freq initialization
Applying: drm/i915: move rawclk init to intel_cdclk_init()
Applying: drm/i915: move rawclk from runtime to display runtime info
Applying: drm/xe/display: drop unused rawclk_freq and RUNTIME_INFO()

✓ CI.checkpatch: success for drm/i915: mem/fsb/rawclk freq cleanups

[Patchwork]

== Series Details ==

Series: drm/i915: mem/fsb/rawclk freq cleanups
URL   : https://patchwork.freedesktop.org/series/134144/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
51ce9f6cd981d42d7467409d7dbc559a450abc1e
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit a749f3fffe7e7e6bc0e79d0159ea304340905bf7
Author: Jani Nikula <jani.nikula@intel.com>
Date:   Tue May 28 17:25:01 2024 +0300

    drm/xe/display: drop unused rawclk_freq and RUNTIME_INFO()
    
    With rawclk_freq moved to display runtime info, xe has no users left for
    them.
    
    Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+ /mt/dim checkpatch 19284ac0399309b4e564175aef99ca2dcbc34825 drm-intel
ff542f7154ee drm/i915/wm: rename intel_get_cxsr_latency -> pnv_get_cxsr_latency
1d704fd2a634 drm/i915/wm: clarify logging on not finding CxSR latency config
85df19516943 drm/i915/dram: separate fsb freq detection from mem freq
968f4f6dc887 drm/i915/dram: split out pnv DDR3 detection
20874fa61638 drm/i915/dram: rearrange mem freq init
8bb036e0941b drm/i915: convert fsb_freq and mem_freq to kHz
d7c6fe9df1a3 drm/i915: extend the fsb_freq initialization to more platforms
0b7cb056a8a7 drm/i915: use i9xx_fsb_freq() for GT clock frequency
a7f1309a1bf9 drm/i915/cdclk: use i9xx_fsb_freq() for rawclk_freq initialization
9a1316f49525 drm/i915: move rawclk init to intel_cdclk_init()
a9dcb1e79d2f drm/i915: move rawclk from runtime to display runtime info
a749f3fffe7e drm/xe/display: drop unused rawclk_freq and RUNTIME_INFO()

✗ CI.KUnit: failure for drm/i915: mem/fsb/rawclk freq cleanups

[Patchwork]

== Series Details ==

Series: drm/i915: mem/fsb/rawclk freq cleanups
URL   : https://patchwork.freedesktop.org/series/134144/
State : failure

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[14:32:32] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[14:32:37] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make ARCH=um O=.kunit --jobs=48
../lib/iomap.c:156:5: warning: no previous prototype for ‘ioread64_lo_hi’ [-Wmissing-prototypes]
  156 | u64 ioread64_lo_hi(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~
../lib/iomap.c:163:5: warning: no previous prototype for ‘ioread64_hi_lo’ [-Wmissing-prototypes]
  163 | u64 ioread64_hi_lo(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~
../lib/iomap.c:170:5: warning: no previous prototype for ‘ioread64be_lo_hi’ [-Wmissing-prototypes]
  170 | u64 ioread64be_lo_hi(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~~~
../lib/iomap.c:178:5: warning: no previous prototype for ‘ioread64be_hi_lo’ [-Wmissing-prototypes]
  178 | u64 ioread64be_hi_lo(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~~~
../lib/iomap.c:264:6: warning: no previous prototype for ‘iowrite64_lo_hi’ [-Wmissing-prototypes]
  264 | void iowrite64_lo_hi(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~
../lib/iomap.c:272:6: warning: no previous prototype for ‘iowrite64_hi_lo’ [-Wmissing-prototypes]
  272 | void iowrite64_hi_lo(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~
../lib/iomap.c:280:6: warning: no previous prototype for ‘iowrite64be_lo_hi’ [-Wmissing-prototypes]
  280 | void iowrite64be_lo_hi(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~~~
../lib/iomap.c:288:6: warning: no previous prototype for ‘iowrite64be_hi_lo’ [-Wmissing-prototypes]
  288 | void iowrite64be_hi_lo(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~~~

[14:33:11] Starting KUnit Kernel (1/1)...
[14:33:11] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[14:33:11] =================== guc_dbm (7 subtests) ===================
[14:33:11] [PASSED] test_empty
[14:33:11] [PASSED] test_default
[14:33:11] ======================== test_size  ========================
[14:33:11] [PASSED] 4
[14:33:11] [PASSED] 8
[14:33:11] [PASSED] 32
[14:33:11] [PASSED] 256
[14:33:11] ==================== [PASSED] test_size ====================
[14:33:11] ======================= test_reuse  ========================
[14:33:11] [PASSED] 4
[14:33:11] [PASSED] 8
[14:33:11] [PASSED] 32
[14:33:11] [PASSED] 256
[14:33:11] =================== [PASSED] test_reuse ====================
[14:33:11] =================== test_range_overlap  ====================
[14:33:11] [PASSED] 4
[14:33:11] [PASSED] 8
[14:33:11] [PASSED] 32
[14:33:11] [PASSED] 256
[14:33:11] =============== [PASSED] test_range_overlap ================
[14:33:11] =================== test_range_compact  ====================
[14:33:11] [PASSED] 4
[14:33:11] [PASSED] 8
[14:33:11] [PASSED] 32
[14:33:11] [PASSED] 256
[14:33:11] =============== [PASSED] test_range_compact ================
[14:33:11] ==================== test_range_spare  =====================
[14:33:11] [PASSED] 4
[14:33:11] [PASSED] 8
[14:33:11] [PASSED] 32
[14:33:11] [PASSED] 256
[14:33:11] ================ [PASSED] test_range_spare =================
[14:33:11] ===================== [PASSED] guc_dbm =====================
[14:33:11] =================== guc_idm (6 subtests) ===================
[14:33:11] [PASSED] bad_init
[14:33:11] [PASSED] no_init
[14:33:11] [PASSED] init_fini
[14:33:11] [PASSED] check_used
[14:33:11] [PASSED] check_quota
[14:33:11] [PASSED] check_all
[14:33:11] ===================== [PASSED] guc_idm =====================
[14:33:11] ================== no_relay (3 subtests) ===================
[14:33:11] [PASSED] xe_drops_guc2pf_if_not_ready
[14:33:11] [PASSED] xe_drops_guc2vf_if_not_ready
[14:33:11] [PASSED] xe_rejects_send_if_not_ready
[14:33:11] ==================== [PASSED] no_relay =====================
[14:33:11] ================== pf_relay (14 subtests) ==================
[14:33:11] [PASSED] pf_rejects_guc2pf_too_short
[14:33:11] [PASSED] pf_rejects_guc2pf_too_long
[14:33:11] [PASSED] pf_rejects_guc2pf_no_payload
[14:33:11] [PASSED] pf_fails_no_payload
[14:33:11] [PASSED] pf_fails_bad_origin
[14:33:11] [PASSED] pf_fails_bad_type
[14:33:11] [PASSED] pf_txn_reports_error
[14:33:11] [PASSED] pf_txn_sends_pf2guc
[14:33:11] [PASSED] pf_sends_pf2guc
[14:33:11] [SKIPPED] pf_loopback_nop
[14:33:11] [SKIPPED] pf_loopback_echo
[14:33:11] [SKIPPED] pf_loopback_fail
[14:33:11] [SKIPPED] pf_loopback_busy
[14:33:11] [SKIPPED] pf_loopback_retry
[14:33:11] ==================== [PASSED] pf_relay =====================
[14:33:11] ================== vf_relay (3 subtests) ===================
[14:33:11] [PASSED] vf_rejects_guc2vf_too_short
[14:33:11] [PASSED] vf_rejects_guc2vf_too_long
[14:33:11] [PASSED] vf_rejects_guc2vf_no_payload
[14:33:11] ==================== [PASSED] vf_relay =====================
[14:33:11] ================= pf_service (11 subtests) =================
[14:33:11] [PASSED] pf_negotiate_any
[14:33:11] [PASSED] pf_negotiate_base_match
[14:33:11] [PASSED] pf_negotiate_base_newer
[14:33:11] [PASSED] pf_negotiate_base_next
[14:33:11] [SKIPPED] pf_negotiate_base_older
[14:33:11] [PASSED] pf_negotiate_base_prev
[14:33:11] [PASSED] pf_negotiate_latest_match
[14:33:11] [PASSED] pf_negotiate_latest_newer
[14:33:11] [PASSED] pf_negotiate_latest_next
[14:33:11] [SKIPPED] pf_negotiate_latest_older
[14:33:11] [SKIPPED] pf_negotiate_latest_prev
[14:33:11] =================== [PASSED] pf_service ====================
[14:33:11] ===================== lmtt (1 subtest) =====================
[14:33:11] ======================== test_ops  =========================
[14:33:11] [PASSED] 2-level
[14:33:11] [PASSED] multi-level
[14:33:11] ==================== [PASSED] test_ops =====================
[14:33:11] ====================== [PASSED] lmtt =======================
[14:33:11] ==================== xe_bo (2 subtests) ====================
[14:33:11] [SKIPPED] xe_ccs_migrate_kunit
[14:33:11] [SKIPPED] xe_bo_evict_kunit
[14:33:11] ===================== [SKIPPED] xe_bo ======================
[14:33:11] ================== xe_dma_buf (1 subtest) ==================
[14:33:11] [SKIPPED] xe_dma_buf_kunit
[14:33:11] =================== [SKIPPED] xe_dma_buf ===================
[14:33:11] ================== xe_migrate (1 subtest) ==================
[14:33:11] [SKIPPED] xe_migrate_sanity_kunit
[14:33:11] =================== [SKIPPED] xe_migrate ===================
[14:33:11] =================== xe_mocs (2 subtests) ===================
[14:33:11] [SKIPPED] xe_live_mocs_kernel_kunit
[14:33:11] [SKIPPED] xe_live_mocs_reset_kunit
[14:33:11] ==================== [SKIPPED] xe_mocs =====================
[14:33:11] ==================== args (11 subtests) ====================
[14:33:11] [PASSED] count_args_test
[14:33:11] [PASSED] call_args_example
[14:33:11] [PASSED] call_args_test
[14:33:11] [PASSED] drop_first_arg_example
[14:33:11] [PASSED] drop_first_arg_test
[14:33:11] [PASSED] first_arg_example
[14:33:11] [PASSED] first_arg_test
[14:33:11] [PASSED] last_arg_example
[14:33:11] [PASSED] last_arg_test
[14:33:11] [PASSED] pick_arg_example
[14:33:11] [PASSED] sep_comma_example
[14:33:11] ====================== [PASSED] args =======================
[14:33:11] =================== xe_pci (2 subtests) ====================
[14:33:11] [PASSED] xe_gmdid_graphics_ip
[14:33:11] [PASSED] xe_gmdid_media_ip
[14:33:11] ===================== [PASSED] xe_pci ======================
[14:33:11] ==================== xe_rtp (1 subtest) ====================
[14:33:11] ================== xe_rtp_process_tests  ===================
[14:33:11] [PASSED] coalesce-same-reg
[14:33:11] [PASSED] no-match-no-add
[14:33:11] [PASSED] no-match-no-add-multiple-rules
[14:33:11] [PASSED] two-regs-two-entries
[14:33:11] [PASSED] clr-one-set-other
[14:33:11] [PASSED] set-field
[14:33:11] [PASSED] conflict-duplicate
[14:33:11] [PASSED] conflict-not-disjoint
[14:33:11] [PASSED] conflict-reg-type
[14:33:11] ============== [PASSED] xe_rtp_process_tests ===============
stty: 'standard input': Inappropriate ioctl for device
[14:33:11] ===================== [PASSED] xe_rtp ======================
[14:33:11] ==================== xe_wa (1 subtest) =====================
[14:33:11] ======================== xe_wa_gt  =========================
[14:33:11] [PASSED] TIGERLAKE (B0)
[14:33:11] [PASSED] DG1 (A0)
[14:33:11] [PASSED] DG1 (B0)
[14:33:11] [PASSED] ALDERLAKE_S (A0)
[14:33:11] [PASSED] ALDERLAKE_S (B0)
[14:33:11] [PASSED] ALDERLAKE_S (C0)
[14:33:11] [PASSED] ALDERLAKE_S (D0)
[14:33:11] [PASSED] ALDERLAKE_P (A0)
[14:33:11] [PASSED] ALDERLAKE_P (B0)
[14:33:11] [PASSED] ALDERLAKE_P (C0)
[14:33:11] [PASSED] ALDERLAKE_S_RPLS (D0)
[14:33:11] [PASSED] ALDERLAKE_P_RPLU (E0)
[14:33:11] [PASSED] DG2_G10 (C0)
[14:33:11] [PASSED] DG2_G11 (B1)
[14:33:11] [PASSED] DG2_G12 (A1)
[14:33:11] [PASSED] METEORLAKE (g:A0, m:A0)
[14:33:11] [PASSED] METEORLAKE (g:A0, m:A0)
[14:33:11] [PASSED] METEORLAKE (g:A0, m:A0)
[14:33:11] [PASSED] LUNARLAKE (g:A0, m:A0)
[14:33:11] [PASSED] LUNARLAKE (g:B0, m:A0)
[14:33:11] ==================== [PASSED] xe_wa_gt =====================
[14:33:11] ====================== [PASSED] xe_wa ======================
[14:33:11] ============================================================
[14:33:11] Testing complete. Ran 109 tests: passed: 95, skipped: 14
[14:33:11] Elapsed time: 39.033s total, 4.914s configuring, 33.849s building, 0.217s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
ERROR:root:
WARNING: unmet direct dependencies detected for DRM_DISPLAY_HDMI_STATE_HELPER
  Depends on [n]: HAS_IOMEM [=y] && DRM [=y] && DRM_DISPLAY_HELPER [=y] && DRM_DISPLAY_HDMI_HELPER [=n]
  Selected by [y]:
  - DRM_KUNIT_TEST [=y] && HAS_IOMEM [=y] && DRM [=y] && KUNIT [=y] && MMU [=y]

WARNING: unmet direct dependencies detected for DRM_DISPLAY_HDMI_STATE_HELPER
  Depends on [n]: HAS_IOMEM [=y] && DRM [=y] && DRM_DISPLAY_HELPER [=y] && DRM_DISPLAY_HDMI_HELPER [=n]
  Selected by [y]:
  - DRM_KUNIT_TEST [=y] && HAS_IOMEM [=y] && DRM [=y] && KUNIT [=y] && MMU [=y]

WARNING: unmet direct dependencies detected for DRM_DISPLAY_HDMI_STATE_HELPER
  Depends on [n]: HAS_IOMEM [=y] && DRM [=y] && DRM_DISPLAY_HELPER [=y] && DRM_DISPLAY_HDMI_HELPER [=n]
  Selected by [y]:
  - DRM_KUNIT_TEST [=y] && HAS_IOMEM [=y] && DRM [=y] && KUNIT [=y] && MMU [=y]
../lib/iomap.c:156:5: warning: no previous prototype for ‘ioread64_lo_hi’ [-Wmissing-prototypes]
  156 | u64 ioread64_lo_hi(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~
../lib/iomap.c:163:5: warning: no previous prototype for ‘ioread64_hi_lo’ [-Wmissing-prototypes]
  163 | u64 ioread64_hi_lo(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~
../lib/iomap.c:170:5: warning: no previous prototype for ‘ioread64be_lo_hi’ [-Wmissing-prototypes]
  170 | u64 ioread64be_lo_hi(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~~~
../lib/iomap.c:178:5: warning: no previous prototype for ‘ioread64be_hi_lo’ [-Wmissing-prototypes]
  178 | u64 ioread64be_hi_lo(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~~~
../lib/iomap.c:264:6: warning: no previous prototype for ‘iowrite64_lo_hi’ [-Wmissing-prototypes]
  264 | void iowrite64_lo_hi(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~
../lib/iomap.c:272:6: warning: no previous prototype for ‘iowrite64_hi_lo’ [-Wmissing-prototypes]
  272 | void iowrite64_hi_lo(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~
../lib/iomap.c:280:6: warning: no previous prototype for ‘iowrite64be_lo_hi’ [-Wmissing-prototypes]
  280 | void iowrite64be_lo_hi(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~~~
../lib/iomap.c:288:6: warning: no previous prototype for ‘iowrite64be_hi_lo’ [-Wmissing-prototypes]
  288 | void iowrite64be_hi_lo(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~~~
/usr/bin/ld: drivers/gpu/drm/tests/drm_connector_test.o: in function `drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc':
drm_connector_test.c:(.text+0x570): undefined reference to `drm_hdmi_compute_mode_clock'
/usr/bin/ld: drivers/gpu/drm/tests/drm_connector_test.o: in function `drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc':
drm_connector_test.c:(.text+0x760): undefined reference to `drm_hdmi_compute_mode_clock'
/usr/bin/ld: drivers/gpu/drm/tests/drm_connector_test.o: in function `drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc':
drm_connector_test.c:(.text+0x950): undefined reference to `drm_hdmi_compute_mode_clock'
/usr/bin/ld: drivers/gpu/drm/tests/drm_connector_test.o: in function `drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc':
drm_connector_test.c:(.text+0xb40): undefined reference to `drm_hdmi_compute_mode_clock'
/usr/bin/ld: drivers/gpu/drm/tests/drm_connector_test.o: in function `drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc':
drm_connector_test.c:(.text+0xd30): undefined reference to `drm_hdmi_compute_mode_clock'
/usr/bin/ld: drivers/gpu/drm/tests/drm_connector_test.o:drm_connector_test.c:(.text+0xf26): more undefined references to `drm_hdmi_compute_mode_clock' follow
/usr/bin/ld: drivers/gpu/drm/display/drm_hdmi_state_helper.o: in function `drm_atomic_helper_connector_hdmi_check':
drm_hdmi_state_helper.c:(.text+0x9d8): undefined reference to `drm_hdmi_avi_infoframe_colorimetry'
/usr/bin/ld: drm_hdmi_state_helper.c:(.text+0x9ea): undefined reference to `drm_hdmi_avi_infoframe_bars'
/usr/bin/ld: drm_hdmi_state_helper.c:(.text+0xa54): undefined reference to `drm_hdmi_infoframe_set_hdr_metadata'
collect2: error: ld returned 1 exit status
make[3]: *** [../scripts/Makefile.vmlinux:34: vmlinux] Error 1
make[2]: *** [/kernel/Makefile:1171: vmlinux] Error 2
make[1]: *** [/kernel/Makefile:240: __sub-make] Error 2
make: *** [Makefile:240: __sub-make] Error 2

[14:33:11] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[14:33:13] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make ARCH=um O=.kunit --jobs=48
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

Re: [PATCH 10/12] drm/i915: move rawclk init to intel_cdclk_init()

[Jani Nikula]

On Tue, 28 May 2024, Jani Nikula <jani.nikula@intel.com> wrote:
> The rawclk initialization is a bit out of place in
> intel_device_info_runtime_init(). Move it to intel_cdclk_init(), with a
> bit of refactoring on intel_read_rawclk().

Note: This also starts to initialize rawclk_frew for xe, which didn't
happen before. Apparently we didn't need it yet? Or the only user was
backlight max deduction?

BR,
Jani.

>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 23 +++++++++++-----------
>  drivers/gpu/drm/i915/display/intel_cdclk.h |  1 -
>  drivers/gpu/drm/i915/intel_device_info.c   |  4 ----
>  3 files changed, 11 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index c731c489c925..55c2dfe5422f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -3218,6 +3218,8 @@ int intel_cdclk_state_set_joined_mbus(struct intel_atomic_state *state, bool joi
>  	return intel_atomic_lock_global_state(&cdclk_state->base);
>  }
>  
> +static void intel_rawclk_init(struct drm_i915_private *dev_priv);
> +
>  int intel_cdclk_init(struct drm_i915_private *dev_priv)
>  {
>  	struct intel_cdclk_state *cdclk_state;
> @@ -3229,6 +3231,8 @@ int intel_cdclk_init(struct drm_i915_private *dev_priv)
>  	intel_atomic_global_obj_init(dev_priv, &dev_priv->display.cdclk.obj,
>  				     &cdclk_state->base, &intel_cdclk_funcs);
>  
> +	intel_rawclk_init(dev_priv);
> +
>  	return 0;
>  }
>  
> @@ -3545,16 +3549,13 @@ static int i9xx_hrawclk(struct drm_i915_private *i915)
>  	return DIV_ROUND_CLOSEST(i9xx_fsb_freq(i915), 4);
>  }
>  
> -/**
> - * intel_read_rawclk - Determine the current RAWCLK frequency
> - * @dev_priv: i915 device
> - *
> - * Determine the current RAWCLK frequency. RAWCLK is a fixed
> - * frequency clock so this needs to done only once.
> +/*
> + * Initialize the current RAWCLK frequency. RAWCLK is a fixed frequency clock so
> + * this needs to done only once.
>   */
> -u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
> +static void intel_rawclk_init(struct drm_i915_private *dev_priv)
>  {
> -	u32 freq;
> +	u32 freq = 0;
>  
>  	if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTL)
>  		/*
> @@ -3573,11 +3574,9 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
>  		freq = vlv_hrawclk(dev_priv);
>  	else if (DISPLAY_VER(dev_priv) >= 3)
>  		freq = i9xx_hrawclk(dev_priv);
> -	else
> -		/* no rawclk on other platforms, or no need to know it */
> -		return 0;
>  
> -	return freq;
> +	RUNTIME_INFO(dev_priv)->rawclk_freq = freq;
> +	drm_dbg_kms(&dev_priv->drm, "rawclk rate: %d kHz\n", freq);
>  }
>  
>  static int i915_cdclk_info_show(struct seq_file *m, void *unused)
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
> index cfdcdec07a4d..a3f950d5a366 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
> @@ -64,7 +64,6 @@ void intel_cdclk_uninit_hw(struct drm_i915_private *i915);
>  void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
>  void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
>  void intel_update_cdclk(struct drm_i915_private *dev_priv);
> -u32 intel_read_rawclk(struct drm_i915_private *dev_priv);
>  bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a,
>  			       const struct intel_cdclk_config *b);
>  int intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 862f4b705227..cc7a8fb0a87d 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -370,10 +370,6 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>  			 "Disabling ppGTT for VT-d support\n");
>  		runtime->ppgtt_type = INTEL_PPGTT_NONE;
>  	}
> -
> -	runtime->rawclk_freq = intel_read_rawclk(dev_priv);
> -	drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq);
> -
>  }
>  
>  /*

-- 
Jani Nikula, Intel

Re: [PATCH 01/12] drm/i915/wm: rename intel_get_cxsr_latency -> pnv_get_cxsr_latency

[Matt Roper]

On Tue, May 28, 2024 at 05:24:50PM +0300, Jani Nikula wrote:
> Clarify that the function is specific to PNV, making subsequent changes
> slightly easier to grasp.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/display/i9xx_wm.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
> index 628e7192ebc9..8657ec0abd2d 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_wm.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
> @@ -70,7 +70,7 @@ static const struct cxsr_latency cxsr_latency_table[] = {
>  	{0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
>  };
>  
> -static const struct cxsr_latency *intel_get_cxsr_latency(struct drm_i915_private *i915)
> +static const struct cxsr_latency *pnv_get_cxsr_latency(struct drm_i915_private *i915)
>  {
>  	int i;
>  
> @@ -635,7 +635,7 @@ static void pnv_update_wm(struct drm_i915_private *dev_priv)
>  	u32 reg;
>  	unsigned int wm;
>  
> -	latency = intel_get_cxsr_latency(dev_priv);
> +	latency = pnv_get_cxsr_latency(dev_priv);
>  	if (!latency) {
>  		drm_dbg_kms(&dev_priv->drm,
>  			    "Unknown FSB/MEM found, disable CxSR\n");
> @@ -4022,7 +4022,7 @@ void i9xx_wm_init(struct drm_i915_private *dev_priv)
>  		g4x_setup_wm_latency(dev_priv);
>  		dev_priv->display.funcs.wm = &g4x_wm_funcs;
>  	} else if (IS_PINEVIEW(dev_priv)) {
> -		if (!intel_get_cxsr_latency(dev_priv)) {
> +		if (!pnv_get_cxsr_latency(dev_priv)) {
>  			drm_info(&dev_priv->drm,
>  				 "failed to find known CxSR latency "
>  				 "(found ddr%s fsb freq %d, mem freq %d), "
> -- 
> 2.39.2
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 02/12] drm/i915/wm: clarify logging on not finding CxSR latency config

[Matt Roper]

On Tue, May 28, 2024 at 05:24:51PM +0300, Jani Nikula wrote:
> Clarify and unify the logging on not finding PNV CxSR latency config.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/i9xx_wm.c | 17 +++++++----------
>  1 file changed, 7 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
> index 8657ec0abd2d..8b8a0f305c3a 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_wm.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
> @@ -75,7 +75,7 @@ static const struct cxsr_latency *pnv_get_cxsr_latency(struct drm_i915_private *
>  	int i;
>  
>  	if (i915->fsb_freq == 0 || i915->mem_freq == 0)
> -		return NULL;
> +		goto err;

Is there even a need for this check?  0/0 will fail to match anything in
the table and will just drop through to the debug message anyway, right?


Matt

>  
>  	for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
>  		const struct cxsr_latency *latency = &cxsr_latency_table[i];
> @@ -88,7 +88,10 @@ static const struct cxsr_latency *pnv_get_cxsr_latency(struct drm_i915_private *
>  			return latency;
>  	}
>  
> -	drm_dbg_kms(&i915->drm, "Unknown FSB/MEM found, disable CxSR\n");
> +err:
> +	drm_dbg_kms(&i915->drm,
> +		    "Could not find CxSR latency for DDR%s, FSB %u MHz, MEM %u MHz\n",
> +		    i915->is_ddr3 ? "3" : "2", i915->fsb_freq, i915->mem_freq);
>  
>  	return NULL;
>  }
> @@ -637,8 +640,7 @@ static void pnv_update_wm(struct drm_i915_private *dev_priv)
>  
>  	latency = pnv_get_cxsr_latency(dev_priv);
>  	if (!latency) {
> -		drm_dbg_kms(&dev_priv->drm,
> -			    "Unknown FSB/MEM found, disable CxSR\n");
> +		drm_dbg_kms(&dev_priv->drm, "Unknown FSB/MEM, disabling CxSR\n");
>  		intel_set_memory_cxsr(dev_priv, false);
>  		return;
>  	}
> @@ -4023,12 +4025,7 @@ void i9xx_wm_init(struct drm_i915_private *dev_priv)
>  		dev_priv->display.funcs.wm = &g4x_wm_funcs;
>  	} else if (IS_PINEVIEW(dev_priv)) {
>  		if (!pnv_get_cxsr_latency(dev_priv)) {
> -			drm_info(&dev_priv->drm,
> -				 "failed to find known CxSR latency "
> -				 "(found ddr%s fsb freq %d, mem freq %d), "
> -				 "disabling CxSR\n",
> -				 (dev_priv->is_ddr3 == 1) ? "3" : "2",
> -				 dev_priv->fsb_freq, dev_priv->mem_freq);
> +			drm_info(&dev_priv->drm,  "Unknown FSB/MEM, disabling CxSR\n");
>  			/* Disable CxSR and never update its watermark again */
>  			intel_set_memory_cxsr(dev_priv, false);
>  			dev_priv->display.funcs.wm = &nop_funcs;
> -- 
> 2.39.2
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 03/12] drm/i915/dram: separate fsb freq detection from mem freq

[Matt Roper]

On Tue, May 28, 2024 at 05:24:52PM +0300, Jani Nikula wrote:
> To simplify further changes, add separate functions for reading the fsb
> frequency.
> 
> This ends up reading CLKCFG register twice, but it's not a big deal.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/soc/intel_dram.c | 106 +++++++++++++++-----------
>  1 file changed, 60 insertions(+), 46 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c
> index 18a879e98f03..3dce9b9a2c5e 100644
> --- a/drivers/gpu/drm/i915/soc/intel_dram.c
> +++ b/drivers/gpu/drm/i915/soc/intel_dram.c
> @@ -49,21 +49,6 @@ static void pnv_detect_mem_freq(struct drm_i915_private *dev_priv)
>  
>  	tmp = intel_uncore_read(&dev_priv->uncore, CLKCFG);
>  
> -	switch (tmp & CLKCFG_FSB_MASK) {
> -	case CLKCFG_FSB_533:
> -		dev_priv->fsb_freq = 533; /* 133*4 */
> -		break;
> -	case CLKCFG_FSB_800:
> -		dev_priv->fsb_freq = 800; /* 200*4 */
> -		break;
> -	case CLKCFG_FSB_667:
> -		dev_priv->fsb_freq =  667; /* 167*4 */
> -		break;
> -	case CLKCFG_FSB_400:
> -		dev_priv->fsb_freq = 400; /* 100*4 */
> -		break;
> -	}
> -
>  	switch (tmp & CLKCFG_MEM_MASK) {
>  	case CLKCFG_MEM_533:
>  		dev_priv->mem_freq = 533;
> @@ -83,7 +68,7 @@ static void pnv_detect_mem_freq(struct drm_i915_private *dev_priv)
>  
>  static void ilk_detect_mem_freq(struct drm_i915_private *dev_priv)
>  {
> -	u16 ddrpll, csipll;
> +	u16 ddrpll;
>  
>  	ddrpll = intel_uncore_read16(&dev_priv->uncore, DDRMPLL1);
>  	switch (ddrpll & 0xff) {
> @@ -105,36 +90,6 @@ static void ilk_detect_mem_freq(struct drm_i915_private *dev_priv)
>  		dev_priv->mem_freq = 0;
>  		break;
>  	}
> -
> -	csipll = intel_uncore_read16(&dev_priv->uncore, CSIPLL0);
> -	switch (csipll & 0x3ff) {
> -	case 0x00c:
> -		dev_priv->fsb_freq = 3200;
> -		break;
> -	case 0x00e:
> -		dev_priv->fsb_freq = 3733;
> -		break;
> -	case 0x010:
> -		dev_priv->fsb_freq = 4266;
> -		break;
> -	case 0x012:
> -		dev_priv->fsb_freq = 4800;
> -		break;
> -	case 0x014:
> -		dev_priv->fsb_freq = 5333;
> -		break;
> -	case 0x016:
> -		dev_priv->fsb_freq = 5866;
> -		break;
> -	case 0x018:
> -		dev_priv->fsb_freq = 6400;
> -		break;
> -	default:
> -		drm_dbg(&dev_priv->drm, "unknown fsb frequency 0x%04x\n",
> -			csipll & 0x3ff);
> -		dev_priv->fsb_freq = 0;
> -		break;
> -	}
>  }
>  
>  static void chv_detect_mem_freq(struct drm_i915_private *i915)
> @@ -192,6 +147,64 @@ static void detect_mem_freq(struct drm_i915_private *i915)
>  		drm_dbg(&i915->drm, "DDR speed: %d MHz\n", i915->mem_freq);
>  }
>  
> +static unsigned int pnv_fsb_freq(struct drm_i915_private *i915)
> +{
> +	u32 fsb;
> +
> +	fsb = intel_uncore_read(&i915->uncore, CLKCFG) & CLKCFG_FSB_MASK;
> +
> +	switch (fsb) {
> +	case CLKCFG_FSB_400:
> +		return 400;
> +	case CLKCFG_FSB_533:
> +		return 533;
> +	case CLKCFG_FSB_667:
> +		return 667;
> +	case CLKCFG_FSB_800:
> +		return 800;
> +	}
> +
> +	return 0;
> +}
> +
> +static unsigned int ilk_fsb_freq(struct drm_i915_private *dev_priv)
> +{
> +	u16 fsb;
> +
> +	fsb = intel_uncore_read16(&dev_priv->uncore, CSIPLL0) & 0x3ff;
> +
> +	switch (fsb) {
> +	case 0x00c:
> +		return 3200;
> +	case 0x00e:
> +		return 3733;
> +	case 0x010:
> +		return 4266;
> +	case 0x012:
> +		return 4800;
> +	case 0x014:
> +		return 5333;
> +	case 0x016:
> +		return 5866;
> +	case 0x018:
> +		return 6400;
> +	default:
> +		drm_dbg(&dev_priv->drm, "unknown fsb frequency 0x%04x\n", fsb);
> +		return 0;
> +	}
> +}
> +
> +static void detect_fsb_freq(struct drm_i915_private *i915)
> +{
> +	if (GRAPHICS_VER(i915) == 5)
> +		i915->fsb_freq = ilk_fsb_freq(i915);
> +	else if (IS_PINEVIEW(i915))
> +		i915->fsb_freq = pnv_fsb_freq(i915);
> +
> +	if (i915->fsb_freq)
> +		drm_dbg(&i915->drm, "FSB frequency: %d MHz\n", i915->fsb_freq);
> +}
> +
>  static int intel_dimm_num_devices(const struct dram_dimm_info *dimm)
>  {
>  	return dimm->ranks * 64 / (dimm->width ?: 1);
> @@ -661,6 +674,7 @@ void intel_dram_detect(struct drm_i915_private *i915)
>  	struct dram_info *dram_info = &i915->dram_info;
>  	int ret;
>  
> +	detect_fsb_freq(i915);
>  	detect_mem_freq(i915);
>  
>  	if (GRAPHICS_VER(i915) < 9 || IS_DG2(i915) || !HAS_DISPLAY(i915))
> -- 
> 2.39.2
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 04/12] drm/i915/dram: split out pnv DDR3 detection

[Matt Roper]

On Tue, May 28, 2024 at 05:24:53PM +0300, Jani Nikula wrote:
> Split out the PNV DDR3 detection to a distinct step instead of
> conflating it with mem freq detection.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/soc/intel_dram.c | 12 ++++++++----
>  1 file changed, 8 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c
> index 3dce9b9a2c5e..1a4db52ac258 100644
> --- a/drivers/gpu/drm/i915/soc/intel_dram.c
> +++ b/drivers/gpu/drm/i915/soc/intel_dram.c
> @@ -43,6 +43,11 @@ static const char *intel_dram_type_str(enum intel_dram_type type)
>  
>  #undef DRAM_TYPE_STR
>  
> +static bool pnv_is_ddr3(struct drm_i915_private *i915)
> +{
> +	return intel_uncore_read(&i915->uncore, CSHRDDR3CTL) & CSHRDDR3CTL_DDR3;
> +}
> +
>  static void pnv_detect_mem_freq(struct drm_i915_private *dev_priv)
>  {
>  	u32 tmp;
> @@ -60,10 +65,6 @@ static void pnv_detect_mem_freq(struct drm_i915_private *dev_priv)
>  		dev_priv->mem_freq = 800;
>  		break;
>  	}
> -
> -	/* detect pineview DDR3 setting */
> -	tmp = intel_uncore_read(&dev_priv->uncore, CSHRDDR3CTL);
> -	dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
>  }
>  
>  static void ilk_detect_mem_freq(struct drm_i915_private *dev_priv)
> @@ -143,6 +144,9 @@ static void detect_mem_freq(struct drm_i915_private *i915)
>  	else if (IS_VALLEYVIEW(i915))
>  		vlv_detect_mem_freq(i915);
>  
> +	if (IS_PINEVIEW(i915))
> +		i915->is_ddr3 = pnv_is_ddr3(i915);
> +
>  	if (i915->mem_freq)
>  		drm_dbg(&i915->drm, "DDR speed: %d MHz\n", i915->mem_freq);
>  }
> -- 
> 2.39.2
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 05/12] drm/i915/dram: rearrange mem freq init

[Matt Roper]

On Tue, May 28, 2024 at 05:24:54PM +0300, Jani Nikula wrote:
> Follow the same style in mem freq init as in fsb freq init, returning
> the value instead of assigning in multiple places.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/soc/intel_dram.c | 59 ++++++++++++---------------
>  1 file changed, 25 insertions(+), 34 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c
> index 1a4db52ac258..266ed6cfa485 100644
> --- a/drivers/gpu/drm/i915/soc/intel_dram.c
> +++ b/drivers/gpu/drm/i915/soc/intel_dram.c
> @@ -48,7 +48,7 @@ static bool pnv_is_ddr3(struct drm_i915_private *i915)
>  	return intel_uncore_read(&i915->uncore, CSHRDDR3CTL) & CSHRDDR3CTL_DDR3;
>  }
>  
> -static void pnv_detect_mem_freq(struct drm_i915_private *dev_priv)
> +static unsigned int pnv_mem_freq(struct drm_i915_private *dev_priv)
>  {
>  	u32 tmp;
>  
> @@ -56,44 +56,38 @@ static void pnv_detect_mem_freq(struct drm_i915_private *dev_priv)
>  
>  	switch (tmp & CLKCFG_MEM_MASK) {
>  	case CLKCFG_MEM_533:
> -		dev_priv->mem_freq = 533;
> -		break;
> +		return 533;
>  	case CLKCFG_MEM_667:
> -		dev_priv->mem_freq = 667;
> -		break;
> +		return 667;
>  	case CLKCFG_MEM_800:
> -		dev_priv->mem_freq = 800;
> -		break;
> +		return 800;
>  	}
> +
> +	return 0;
>  }
>  
> -static void ilk_detect_mem_freq(struct drm_i915_private *dev_priv)
> +static unsigned int ilk_mem_freq(struct drm_i915_private *dev_priv)
>  {
>  	u16 ddrpll;
>  
>  	ddrpll = intel_uncore_read16(&dev_priv->uncore, DDRMPLL1);
>  	switch (ddrpll & 0xff) {
>  	case 0xc:
> -		dev_priv->mem_freq = 800;
> -		break;
> +		return 800;
>  	case 0x10:
> -		dev_priv->mem_freq = 1066;
> -		break;
> +		return 1066;
>  	case 0x14:
> -		dev_priv->mem_freq = 1333;
> -		break;
> +		return 1333;
>  	case 0x18:
> -		dev_priv->mem_freq = 1600;
> -		break;
> +		return 1600;
>  	default:
>  		drm_dbg(&dev_priv->drm, "unknown memory frequency 0x%02x\n",
>  			ddrpll & 0xff);
> -		dev_priv->mem_freq = 0;
> -		break;
> +		return 0;
>  	}
>  }
>  
> -static void chv_detect_mem_freq(struct drm_i915_private *i915)
> +static unsigned int chv_mem_freq(struct drm_i915_private *i915)
>  {
>  	u32 val;
>  
> @@ -103,15 +97,13 @@ static void chv_detect_mem_freq(struct drm_i915_private *i915)
>  
>  	switch ((val >> 2) & 0x7) {
>  	case 3:
> -		i915->mem_freq = 2000;
> -		break;
> +		return 2000;
>  	default:
> -		i915->mem_freq = 1600;
> -		break;
> +		return 1600;
>  	}
>  }
>  
> -static void vlv_detect_mem_freq(struct drm_i915_private *i915)
> +static unsigned int vlv_mem_freq(struct drm_i915_private *i915)
>  {
>  	u32 val;
>  
> @@ -122,27 +114,26 @@ static void vlv_detect_mem_freq(struct drm_i915_private *i915)
>  	switch ((val >> 6) & 3) {
>  	case 0:
>  	case 1:
> -		i915->mem_freq = 800;
> -		break;
> +		return 800;
>  	case 2:
> -		i915->mem_freq = 1066;
> -		break;
> +		return 1066;
>  	case 3:
> -		i915->mem_freq = 1333;
> -		break;
> +		return 1333;
>  	}
> +
> +	return 0;
>  }
>  
>  static void detect_mem_freq(struct drm_i915_private *i915)
>  {
>  	if (IS_PINEVIEW(i915))
> -		pnv_detect_mem_freq(i915);
> +		i915->mem_freq = pnv_mem_freq(i915);
>  	else if (GRAPHICS_VER(i915) == 5)
> -		ilk_detect_mem_freq(i915);
> +		i915->mem_freq = ilk_mem_freq(i915);
>  	else if (IS_CHERRYVIEW(i915))
> -		chv_detect_mem_freq(i915);
> +		i915->mem_freq = chv_mem_freq(i915);
>  	else if (IS_VALLEYVIEW(i915))
> -		vlv_detect_mem_freq(i915);
> +		i915->mem_freq = vlv_mem_freq(i915);
>  
>  	if (IS_PINEVIEW(i915))
>  		i915->is_ddr3 = pnv_is_ddr3(i915);
> -- 
> 2.39.2
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 06/12] drm/i915: convert fsb_freq and mem_freq to kHz

[Matt Roper]

On Tue, May 28, 2024 at 05:24:55PM +0300, Jani Nikula wrote:
> We'll want to use fsb frequency for deriving GT clock and rawclk
> frequencies in the future. Increase the accuracy by converting to
> kHz. Do the same for mem freq to be aligned.
> 
> Round the frequencies ending in 666 to 667.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Would it be worth adding a "_khz" suffix to the structure fields to help
clarify the units?

Either way,

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/display/i9xx_wm.c |  6 ++--
>  drivers/gpu/drm/i915/gt/intel_rps.c    |  4 +--
>  drivers/gpu/drm/i915/soc/intel_dram.c  | 50 +++++++++++++-------------
>  3 files changed, 30 insertions(+), 30 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
> index 8b8a0f305c3a..08c5d122af8f 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_wm.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
> @@ -83,14 +83,14 @@ static const struct cxsr_latency *pnv_get_cxsr_latency(struct drm_i915_private *
>  
>  		if (is_desktop == latency->is_desktop &&
>  		    i915->is_ddr3 == latency->is_ddr3 &&
> -		    i915->fsb_freq == latency->fsb_freq &&
> -		    i915->mem_freq == latency->mem_freq)
> +		    DIV_ROUND_CLOSEST(i915->fsb_freq, 1000) == latency->fsb_freq &&
> +		    DIV_ROUND_CLOSEST(i915->mem_freq, 1000) == latency->mem_freq)
>  			return latency;
>  	}
>  
>  err:
>  	drm_dbg_kms(&i915->drm,
> -		    "Could not find CxSR latency for DDR%s, FSB %u MHz, MEM %u MHz\n",
> +		    "Could not find CxSR latency for DDR%s, FSB %u kHz, MEM %u kHz\n",
>  		    i915->is_ddr3 ? "3" : "2", i915->fsb_freq, i915->mem_freq);
>  
>  	return NULL;
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
> index c9cb2a391942..5d3de1cddcf6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -280,9 +280,9 @@ static void gen5_rps_init(struct intel_rps *rps)
>  	u32 rgvmodectl;
>  	int c_m, i;
>  
> -	if (i915->fsb_freq <= 3200)
> +	if (i915->fsb_freq <= 3200000)
>  		c_m = 0;
> -	else if (i915->fsb_freq <= 4800)
> +	else if (i915->fsb_freq <= 4800000)
>  		c_m = 1;
>  	else
>  		c_m = 2;
> diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c
> index 266ed6cfa485..ace9372244a4 100644
> --- a/drivers/gpu/drm/i915/soc/intel_dram.c
> +++ b/drivers/gpu/drm/i915/soc/intel_dram.c
> @@ -56,11 +56,11 @@ static unsigned int pnv_mem_freq(struct drm_i915_private *dev_priv)
>  
>  	switch (tmp & CLKCFG_MEM_MASK) {
>  	case CLKCFG_MEM_533:
> -		return 533;
> +		return 533333;
>  	case CLKCFG_MEM_667:
> -		return 667;
> +		return 666667;
>  	case CLKCFG_MEM_800:
> -		return 800;
> +		return 800000;
>  	}
>  
>  	return 0;
> @@ -73,13 +73,13 @@ static unsigned int ilk_mem_freq(struct drm_i915_private *dev_priv)
>  	ddrpll = intel_uncore_read16(&dev_priv->uncore, DDRMPLL1);
>  	switch (ddrpll & 0xff) {
>  	case 0xc:
> -		return 800;
> +		return 800000;
>  	case 0x10:
> -		return 1066;
> +		return 1066667;
>  	case 0x14:
> -		return 1333;
> +		return 1333333;
>  	case 0x18:
> -		return 1600;
> +		return 1600000;
>  	default:
>  		drm_dbg(&dev_priv->drm, "unknown memory frequency 0x%02x\n",
>  			ddrpll & 0xff);
> @@ -97,9 +97,9 @@ static unsigned int chv_mem_freq(struct drm_i915_private *i915)
>  
>  	switch ((val >> 2) & 0x7) {
>  	case 3:
> -		return 2000;
> +		return 2000000;
>  	default:
> -		return 1600;
> +		return 1600000;
>  	}
>  }
>  
> @@ -114,11 +114,11 @@ static unsigned int vlv_mem_freq(struct drm_i915_private *i915)
>  	switch ((val >> 6) & 3) {
>  	case 0:
>  	case 1:
> -		return 800;
> +		return 800000;
>  	case 2:
> -		return 1066;
> +		return 1066667;
>  	case 3:
> -		return 1333;
> +		return 1333333;
>  	}
>  
>  	return 0;
> @@ -139,7 +139,7 @@ static void detect_mem_freq(struct drm_i915_private *i915)
>  		i915->is_ddr3 = pnv_is_ddr3(i915);
>  
>  	if (i915->mem_freq)
> -		drm_dbg(&i915->drm, "DDR speed: %d MHz\n", i915->mem_freq);
> +		drm_dbg(&i915->drm, "DDR speed: %d kHz\n", i915->mem_freq);
>  }
>  
>  static unsigned int pnv_fsb_freq(struct drm_i915_private *i915)
> @@ -150,13 +150,13 @@ static unsigned int pnv_fsb_freq(struct drm_i915_private *i915)
>  
>  	switch (fsb) {
>  	case CLKCFG_FSB_400:
> -		return 400;
> +		return 400000;
>  	case CLKCFG_FSB_533:
> -		return 533;
> +		return 533333;
>  	case CLKCFG_FSB_667:
> -		return 667;
> +		return 666667;
>  	case CLKCFG_FSB_800:
> -		return 800;
> +		return 800000;
>  	}
>  
>  	return 0;
> @@ -170,19 +170,19 @@ static unsigned int ilk_fsb_freq(struct drm_i915_private *dev_priv)
>  
>  	switch (fsb) {
>  	case 0x00c:
> -		return 3200;
> +		return 3200000;
>  	case 0x00e:
> -		return 3733;
> +		return 3733333;
>  	case 0x010:
> -		return 4266;
> +		return 4266667;
>  	case 0x012:
> -		return 4800;
> +		return 4800000;
>  	case 0x014:
> -		return 5333;
> +		return 5333333;
>  	case 0x016:
> -		return 5866;
> +		return 5866667;
>  	case 0x018:
> -		return 6400;
> +		return 6400000;
>  	default:
>  		drm_dbg(&dev_priv->drm, "unknown fsb frequency 0x%04x\n", fsb);
>  		return 0;
> @@ -197,7 +197,7 @@ static void detect_fsb_freq(struct drm_i915_private *i915)
>  		i915->fsb_freq = pnv_fsb_freq(i915);
>  
>  	if (i915->fsb_freq)
> -		drm_dbg(&i915->drm, "FSB frequency: %d MHz\n", i915->fsb_freq);
> +		drm_dbg(&i915->drm, "FSB frequency: %d kHz\n", i915->fsb_freq);
>  }
>  
>  static int intel_dimm_num_devices(const struct dram_dimm_info *dimm)
> -- 
> 2.39.2
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 07/12] drm/i915: extend the fsb_freq initialization to more platforms

[Matt Roper]

On Tue, May 28, 2024 at 05:24:56PM +0300, Jani Nikula wrote:
> Initialize fsb frequency for more platforms to be able to use it for GT
> clock and rawclk frequency initialization.
> 
> Note: There's a discrepancy between existing pnv_fsb_freq() and
> i9xx_hrawclk() regarding CLKCFG interpretation. Presume all PNV is
> mobile.

Do you just mean we assume PNV always treats CLKCFG the same way mobile
platforms do?  Because we have both mobile and non-mobile platforms
defined in the driver (pnv_m_info vs pnv_g_info) and that matches
https://ark.intel.com/content/www/us/en/ark/products/codename/32201/products-formerly-pineview.html
that lists both desktop and mobile.


Matt

> 
> FIXME: What should the default or failure mode be when the value is
> unknown?
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/soc/intel_dram.c | 54 ++++++++++++++++++++-------
>  1 file changed, 40 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c
> index ace9372244a4..74b5b70e91f9 100644
> --- a/drivers/gpu/drm/i915/soc/intel_dram.c
> +++ b/drivers/gpu/drm/i915/soc/intel_dram.c
> @@ -142,24 +142,50 @@ static void detect_mem_freq(struct drm_i915_private *i915)
>  		drm_dbg(&i915->drm, "DDR speed: %d kHz\n", i915->mem_freq);
>  }
>  
> -static unsigned int pnv_fsb_freq(struct drm_i915_private *i915)
> +static unsigned int i9xx_fsb_freq(struct drm_i915_private *i915)
>  {
>  	u32 fsb;
>  
>  	fsb = intel_uncore_read(&i915->uncore, CLKCFG) & CLKCFG_FSB_MASK;
>  
> -	switch (fsb) {
> -	case CLKCFG_FSB_400:
> -		return 400000;
> -	case CLKCFG_FSB_533:
> -		return 533333;
> -	case CLKCFG_FSB_667:
> -		return 666667;
> -	case CLKCFG_FSB_800:
> -		return 800000;
> +	if (IS_PINEVIEW(i915) || IS_MOBILE(i915)) {
> +		switch (fsb) {
> +		case CLKCFG_FSB_400:
> +			return 400000;
> +		case CLKCFG_FSB_533:
> +			return 533333;
> +		case CLKCFG_FSB_667:
> +			return 666667;
> +		case CLKCFG_FSB_800:
> +			return 800000;
> +		case CLKCFG_FSB_1067:
> +			return 1066667;
> +		case CLKCFG_FSB_1333:
> +			return 1333333;
> +		default:
> +			MISSING_CASE(fsb);
> +			return 1333333;
> +		}
> +	} else {
> +		switch (fsb) {
> +		case CLKCFG_FSB_400_ALT:
> +			return 400000;
> +		case CLKCFG_FSB_533:
> +			return 533333;
> +		case CLKCFG_FSB_667:
> +			return 666667;
> +		case CLKCFG_FSB_800:
> +			return 800000;
> +		case CLKCFG_FSB_1067_ALT:
> +			return 1066667;
> +		case CLKCFG_FSB_1333_ALT:
> +			return 1333333;
> +		case CLKCFG_FSB_1600_ALT:
> +			return 1600000;
> +		default:
> +			return 533333;
> +		}
>  	}
> -
> -	return 0;
>  }
>  
>  static unsigned int ilk_fsb_freq(struct drm_i915_private *dev_priv)
> @@ -193,8 +219,8 @@ static void detect_fsb_freq(struct drm_i915_private *i915)
>  {
>  	if (GRAPHICS_VER(i915) == 5)
>  		i915->fsb_freq = ilk_fsb_freq(i915);
> -	else if (IS_PINEVIEW(i915))
> -		i915->fsb_freq = pnv_fsb_freq(i915);
> +	else if (GRAPHICS_VER(i915) == 3 || GRAPHICS_VER(i915) == 4)
> +		i915->fsb_freq = i9xx_fsb_freq(i915);
>  
>  	if (i915->fsb_freq)
>  		drm_dbg(&i915->drm, "FSB frequency: %d kHz\n", i915->fsb_freq);
> -- 
> 2.39.2
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 02/12] drm/i915/wm: clarify logging on not finding CxSR latency config

[Jani Nikula]

On Wed, 29 May 2024, Matt Roper <matthew.d.roper@intel.com> wrote:
> On Tue, May 28, 2024 at 05:24:51PM +0300, Jani Nikula wrote:
>> Clarify and unify the logging on not finding PNV CxSR latency config.
>> 
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/i9xx_wm.c | 17 +++++++----------
>>  1 file changed, 7 insertions(+), 10 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
>> index 8657ec0abd2d..8b8a0f305c3a 100644
>> --- a/drivers/gpu/drm/i915/display/i9xx_wm.c
>> +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
>> @@ -75,7 +75,7 @@ static const struct cxsr_latency *pnv_get_cxsr_latency(struct drm_i915_private *
>>  	int i;
>>  
>>  	if (i915->fsb_freq == 0 || i915->mem_freq == 0)
>> -		return NULL;
>> +		goto err;
>
> Is there even a need for this check?  0/0 will fail to match anything in
> the table and will just drop through to the debug message anyway, right?

True, could be dropped. I just thought it was more explicit this way,
but maybe fewer lines is better.

BR,
Jani.

>
>
> Matt
>
>>  
>>  	for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
>>  		const struct cxsr_latency *latency = &cxsr_latency_table[i];
>> @@ -88,7 +88,10 @@ static const struct cxsr_latency *pnv_get_cxsr_latency(struct drm_i915_private *
>>  			return latency;
>>  	}
>>  
>> -	drm_dbg_kms(&i915->drm, "Unknown FSB/MEM found, disable CxSR\n");
>> +err:
>> +	drm_dbg_kms(&i915->drm,
>> +		    "Could not find CxSR latency for DDR%s, FSB %u MHz, MEM %u MHz\n",
>> +		    i915->is_ddr3 ? "3" : "2", i915->fsb_freq, i915->mem_freq);
>>  
>>  	return NULL;
>>  }
>> @@ -637,8 +640,7 @@ static void pnv_update_wm(struct drm_i915_private *dev_priv)
>>  
>>  	latency = pnv_get_cxsr_latency(dev_priv);
>>  	if (!latency) {
>> -		drm_dbg_kms(&dev_priv->drm,
>> -			    "Unknown FSB/MEM found, disable CxSR\n");
>> +		drm_dbg_kms(&dev_priv->drm, "Unknown FSB/MEM, disabling CxSR\n");
>>  		intel_set_memory_cxsr(dev_priv, false);
>>  		return;
>>  	}
>> @@ -4023,12 +4025,7 @@ void i9xx_wm_init(struct drm_i915_private *dev_priv)
>>  		dev_priv->display.funcs.wm = &g4x_wm_funcs;
>>  	} else if (IS_PINEVIEW(dev_priv)) {
>>  		if (!pnv_get_cxsr_latency(dev_priv)) {
>> -			drm_info(&dev_priv->drm,
>> -				 "failed to find known CxSR latency "
>> -				 "(found ddr%s fsb freq %d, mem freq %d), "
>> -				 "disabling CxSR\n",
>> -				 (dev_priv->is_ddr3 == 1) ? "3" : "2",
>> -				 dev_priv->fsb_freq, dev_priv->mem_freq);
>> +			drm_info(&dev_priv->drm,  "Unknown FSB/MEM, disabling CxSR\n");
>>  			/* Disable CxSR and never update its watermark again */
>>  			intel_set_memory_cxsr(dev_priv, false);
>>  			dev_priv->display.funcs.wm = &nop_funcs;
>> -- 
>> 2.39.2
>> 

-- 
Jani Nikula, Intel

Re: [PATCH 06/12] drm/i915: convert fsb_freq and mem_freq to kHz

[Jani Nikula]

On Wed, 29 May 2024, Matt Roper <matthew.d.roper@intel.com> wrote:
> On Tue, May 28, 2024 at 05:24:55PM +0300, Jani Nikula wrote:
>> We'll want to use fsb frequency for deriving GT clock and rawclk
>> frequencies in the future. Increase the accuracy by converting to
>> kHz. Do the same for mem freq to be aligned.
>> 
>> Round the frequencies ending in 666 to 667.
>> 
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> Would it be worth adding a "_khz" suffix to the structure fields to help
> clarify the units?

Thought about it, but decided kHz is pretty much the norm, and it's
everything else that should have a suffix to clarify the units!

> Either way,
>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

Thanks,
Jani.

>
>> ---
>>  drivers/gpu/drm/i915/display/i9xx_wm.c |  6 ++--
>>  drivers/gpu/drm/i915/gt/intel_rps.c    |  4 +--
>>  drivers/gpu/drm/i915/soc/intel_dram.c  | 50 +++++++++++++-------------
>>  3 files changed, 30 insertions(+), 30 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
>> index 8b8a0f305c3a..08c5d122af8f 100644
>> --- a/drivers/gpu/drm/i915/display/i9xx_wm.c
>> +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
>> @@ -83,14 +83,14 @@ static const struct cxsr_latency *pnv_get_cxsr_latency(struct drm_i915_private *
>>  
>>  		if (is_desktop == latency->is_desktop &&
>>  		    i915->is_ddr3 == latency->is_ddr3 &&
>> -		    i915->fsb_freq == latency->fsb_freq &&
>> -		    i915->mem_freq == latency->mem_freq)
>> +		    DIV_ROUND_CLOSEST(i915->fsb_freq, 1000) == latency->fsb_freq &&
>> +		    DIV_ROUND_CLOSEST(i915->mem_freq, 1000) == latency->mem_freq)
>>  			return latency;
>>  	}
>>  
>>  err:
>>  	drm_dbg_kms(&i915->drm,
>> -		    "Could not find CxSR latency for DDR%s, FSB %u MHz, MEM %u MHz\n",
>> +		    "Could not find CxSR latency for DDR%s, FSB %u kHz, MEM %u kHz\n",
>>  		    i915->is_ddr3 ? "3" : "2", i915->fsb_freq, i915->mem_freq);
>>  
>>  	return NULL;
>> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
>> index c9cb2a391942..5d3de1cddcf6 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
>> @@ -280,9 +280,9 @@ static void gen5_rps_init(struct intel_rps *rps)
>>  	u32 rgvmodectl;
>>  	int c_m, i;
>>  
>> -	if (i915->fsb_freq <= 3200)
>> +	if (i915->fsb_freq <= 3200000)
>>  		c_m = 0;
>> -	else if (i915->fsb_freq <= 4800)
>> +	else if (i915->fsb_freq <= 4800000)
>>  		c_m = 1;
>>  	else
>>  		c_m = 2;
>> diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c
>> index 266ed6cfa485..ace9372244a4 100644
>> --- a/drivers/gpu/drm/i915/soc/intel_dram.c
>> +++ b/drivers/gpu/drm/i915/soc/intel_dram.c
>> @@ -56,11 +56,11 @@ static unsigned int pnv_mem_freq(struct drm_i915_private *dev_priv)
>>  
>>  	switch (tmp & CLKCFG_MEM_MASK) {
>>  	case CLKCFG_MEM_533:
>> -		return 533;
>> +		return 533333;
>>  	case CLKCFG_MEM_667:
>> -		return 667;
>> +		return 666667;
>>  	case CLKCFG_MEM_800:
>> -		return 800;
>> +		return 800000;
>>  	}
>>  
>>  	return 0;
>> @@ -73,13 +73,13 @@ static unsigned int ilk_mem_freq(struct drm_i915_private *dev_priv)
>>  	ddrpll = intel_uncore_read16(&dev_priv->uncore, DDRMPLL1);
>>  	switch (ddrpll & 0xff) {
>>  	case 0xc:
>> -		return 800;
>> +		return 800000;
>>  	case 0x10:
>> -		return 1066;
>> +		return 1066667;
>>  	case 0x14:
>> -		return 1333;
>> +		return 1333333;
>>  	case 0x18:
>> -		return 1600;
>> +		return 1600000;
>>  	default:
>>  		drm_dbg(&dev_priv->drm, "unknown memory frequency 0x%02x\n",
>>  			ddrpll & 0xff);
>> @@ -97,9 +97,9 @@ static unsigned int chv_mem_freq(struct drm_i915_private *i915)
>>  
>>  	switch ((val >> 2) & 0x7) {
>>  	case 3:
>> -		return 2000;
>> +		return 2000000;
>>  	default:
>> -		return 1600;
>> +		return 1600000;
>>  	}
>>  }
>>  
>> @@ -114,11 +114,11 @@ static unsigned int vlv_mem_freq(struct drm_i915_private *i915)
>>  	switch ((val >> 6) & 3) {
>>  	case 0:
>>  	case 1:
>> -		return 800;
>> +		return 800000;
>>  	case 2:
>> -		return 1066;
>> +		return 1066667;
>>  	case 3:
>> -		return 1333;
>> +		return 1333333;
>>  	}
>>  
>>  	return 0;
>> @@ -139,7 +139,7 @@ static void detect_mem_freq(struct drm_i915_private *i915)
>>  		i915->is_ddr3 = pnv_is_ddr3(i915);
>>  
>>  	if (i915->mem_freq)
>> -		drm_dbg(&i915->drm, "DDR speed: %d MHz\n", i915->mem_freq);
>> +		drm_dbg(&i915->drm, "DDR speed: %d kHz\n", i915->mem_freq);
>>  }
>>  
>>  static unsigned int pnv_fsb_freq(struct drm_i915_private *i915)
>> @@ -150,13 +150,13 @@ static unsigned int pnv_fsb_freq(struct drm_i915_private *i915)
>>  
>>  	switch (fsb) {
>>  	case CLKCFG_FSB_400:
>> -		return 400;
>> +		return 400000;
>>  	case CLKCFG_FSB_533:
>> -		return 533;
>> +		return 533333;
>>  	case CLKCFG_FSB_667:
>> -		return 667;
>> +		return 666667;
>>  	case CLKCFG_FSB_800:
>> -		return 800;
>> +		return 800000;
>>  	}
>>  
>>  	return 0;
>> @@ -170,19 +170,19 @@ static unsigned int ilk_fsb_freq(struct drm_i915_private *dev_priv)
>>  
>>  	switch (fsb) {
>>  	case 0x00c:
>> -		return 3200;
>> +		return 3200000;
>>  	case 0x00e:
>> -		return 3733;
>> +		return 3733333;
>>  	case 0x010:
>> -		return 4266;
>> +		return 4266667;
>>  	case 0x012:
>> -		return 4800;
>> +		return 4800000;
>>  	case 0x014:
>> -		return 5333;
>> +		return 5333333;
>>  	case 0x016:
>> -		return 5866;
>> +		return 5866667;
>>  	case 0x018:
>> -		return 6400;
>> +		return 6400000;
>>  	default:
>>  		drm_dbg(&dev_priv->drm, "unknown fsb frequency 0x%04x\n", fsb);
>>  		return 0;
>> @@ -197,7 +197,7 @@ static void detect_fsb_freq(struct drm_i915_private *i915)
>>  		i915->fsb_freq = pnv_fsb_freq(i915);
>>  
>>  	if (i915->fsb_freq)
>> -		drm_dbg(&i915->drm, "FSB frequency: %d MHz\n", i915->fsb_freq);
>> +		drm_dbg(&i915->drm, "FSB frequency: %d kHz\n", i915->fsb_freq);
>>  }
>>  
>>  static int intel_dimm_num_devices(const struct dram_dimm_info *dimm)
>> -- 
>> 2.39.2
>> 

-- 
Jani Nikula, Intel

Re: [PATCH 07/12] drm/i915: extend the fsb_freq initialization to more platforms

[Jani Nikula]

On Wed, 29 May 2024, Matt Roper <matthew.d.roper@intel.com> wrote:
> On Tue, May 28, 2024 at 05:24:56PM +0300, Jani Nikula wrote:
>> Initialize fsb frequency for more platforms to be able to use it for GT
>> clock and rawclk frequency initialization.
>> 
>> Note: There's a discrepancy between existing pnv_fsb_freq() and
>> i9xx_hrawclk() regarding CLKCFG interpretation. Presume all PNV is
>> mobile.
>
> Do you just mean we assume PNV always treats CLKCFG the same way mobile
> platforms do?  Because we have both mobile and non-mobile platforms
> defined in the driver (pnv_m_info vs pnv_g_info) and that matches
> https://ark.intel.com/content/www/us/en/ark/products/codename/32201/products-formerly-pineview.html
> that lists both desktop and mobile.

Yeah. The problem is, current code in intel_dram.c and intel_cdclk.c
interpret the CLKCFG register differently for desktop PNV. At least one
of them is wrong. Basically I just picked one, and secretly hoped Ville
would tell me. ;)

BR,
Jani.


>
>
> Matt
>
>> 
>> FIXME: What should the default or failure mode be when the value is
>> unknown?
>> 
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>  drivers/gpu/drm/i915/soc/intel_dram.c | 54 ++++++++++++++++++++-------
>>  1 file changed, 40 insertions(+), 14 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c
>> index ace9372244a4..74b5b70e91f9 100644
>> --- a/drivers/gpu/drm/i915/soc/intel_dram.c
>> +++ b/drivers/gpu/drm/i915/soc/intel_dram.c
>> @@ -142,24 +142,50 @@ static void detect_mem_freq(struct drm_i915_private *i915)
>>  		drm_dbg(&i915->drm, "DDR speed: %d kHz\n", i915->mem_freq);
>>  }
>>  
>> -static unsigned int pnv_fsb_freq(struct drm_i915_private *i915)
>> +static unsigned int i9xx_fsb_freq(struct drm_i915_private *i915)
>>  {
>>  	u32 fsb;
>>  
>>  	fsb = intel_uncore_read(&i915->uncore, CLKCFG) & CLKCFG_FSB_MASK;
>>  
>> -	switch (fsb) {
>> -	case CLKCFG_FSB_400:
>> -		return 400000;
>> -	case CLKCFG_FSB_533:
>> -		return 533333;
>> -	case CLKCFG_FSB_667:
>> -		return 666667;
>> -	case CLKCFG_FSB_800:
>> -		return 800000;
>> +	if (IS_PINEVIEW(i915) || IS_MOBILE(i915)) {
>> +		switch (fsb) {
>> +		case CLKCFG_FSB_400:
>> +			return 400000;
>> +		case CLKCFG_FSB_533:
>> +			return 533333;
>> +		case CLKCFG_FSB_667:
>> +			return 666667;
>> +		case CLKCFG_FSB_800:
>> +			return 800000;
>> +		case CLKCFG_FSB_1067:
>> +			return 1066667;
>> +		case CLKCFG_FSB_1333:
>> +			return 1333333;
>> +		default:
>> +			MISSING_CASE(fsb);
>> +			return 1333333;
>> +		}
>> +	} else {
>> +		switch (fsb) {
>> +		case CLKCFG_FSB_400_ALT:
>> +			return 400000;
>> +		case CLKCFG_FSB_533:
>> +			return 533333;
>> +		case CLKCFG_FSB_667:
>> +			return 666667;
>> +		case CLKCFG_FSB_800:
>> +			return 800000;
>> +		case CLKCFG_FSB_1067_ALT:
>> +			return 1066667;
>> +		case CLKCFG_FSB_1333_ALT:
>> +			return 1333333;
>> +		case CLKCFG_FSB_1600_ALT:
>> +			return 1600000;
>> +		default:
>> +			return 533333;
>> +		}
>>  	}
>> -
>> -	return 0;
>>  }
>>  
>>  static unsigned int ilk_fsb_freq(struct drm_i915_private *dev_priv)
>> @@ -193,8 +219,8 @@ static void detect_fsb_freq(struct drm_i915_private *i915)
>>  {
>>  	if (GRAPHICS_VER(i915) == 5)
>>  		i915->fsb_freq = ilk_fsb_freq(i915);
>> -	else if (IS_PINEVIEW(i915))
>> -		i915->fsb_freq = pnv_fsb_freq(i915);
>> +	else if (GRAPHICS_VER(i915) == 3 || GRAPHICS_VER(i915) == 4)
>> +		i915->fsb_freq = i9xx_fsb_freq(i915);
>>  
>>  	if (i915->fsb_freq)
>>  		drm_dbg(&i915->drm, "FSB frequency: %d kHz\n", i915->fsb_freq);
>> -- 
>> 2.39.2
>> 

-- 
Jani Nikula, Intel

Re: [PATCH 07/12] drm/i915: extend the fsb_freq initialization to more platforms

[Jani Nikula]

On Thu, 30 May 2024, Jani Nikula <jani.nikula@intel.com> wrote:
> On Wed, 29 May 2024, Matt Roper <matthew.d.roper@intel.com> wrote:
>> On Tue, May 28, 2024 at 05:24:56PM +0300, Jani Nikula wrote:
>>> Initialize fsb frequency for more platforms to be able to use it for GT
>>> clock and rawclk frequency initialization.
>>> 
>>> Note: There's a discrepancy between existing pnv_fsb_freq() and
>>> i9xx_hrawclk() regarding CLKCFG interpretation. Presume all PNV is
>>> mobile.
>>
>> Do you just mean we assume PNV always treats CLKCFG the same way mobile
>> platforms do?  Because we have both mobile and non-mobile platforms
>> defined in the driver (pnv_m_info vs pnv_g_info) and that matches
>> https://ark.intel.com/content/www/us/en/ark/products/codename/32201/products-formerly-pineview.html
>> that lists both desktop and mobile.
>
> Yeah. The problem is, current code in intel_dram.c and intel_cdclk.c
> interpret the CLKCFG register differently for desktop PNV. At least one
> of them is wrong. Basically I just picked one, and secretly hoped Ville
> would tell me. ;)

Ville, do you have any idea about CLKCFG?

BR,
Jani.


>
> BR,
> Jani.
>
>
>>
>>
>> Matt
>>
>>> 
>>> FIXME: What should the default or failure mode be when the value is
>>> unknown?
>>> 
>>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>>> ---
>>>  drivers/gpu/drm/i915/soc/intel_dram.c | 54 ++++++++++++++++++++-------
>>>  1 file changed, 40 insertions(+), 14 deletions(-)
>>> 
>>> diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c
>>> index ace9372244a4..74b5b70e91f9 100644
>>> --- a/drivers/gpu/drm/i915/soc/intel_dram.c
>>> +++ b/drivers/gpu/drm/i915/soc/intel_dram.c
>>> @@ -142,24 +142,50 @@ static void detect_mem_freq(struct drm_i915_private *i915)
>>>  		drm_dbg(&i915->drm, "DDR speed: %d kHz\n", i915->mem_freq);
>>>  }
>>>  
>>> -static unsigned int pnv_fsb_freq(struct drm_i915_private *i915)
>>> +static unsigned int i9xx_fsb_freq(struct drm_i915_private *i915)
>>>  {
>>>  	u32 fsb;
>>>  
>>>  	fsb = intel_uncore_read(&i915->uncore, CLKCFG) & CLKCFG_FSB_MASK;
>>>  
>>> -	switch (fsb) {
>>> -	case CLKCFG_FSB_400:
>>> -		return 400000;
>>> -	case CLKCFG_FSB_533:
>>> -		return 533333;
>>> -	case CLKCFG_FSB_667:
>>> -		return 666667;
>>> -	case CLKCFG_FSB_800:
>>> -		return 800000;
>>> +	if (IS_PINEVIEW(i915) || IS_MOBILE(i915)) {
>>> +		switch (fsb) {
>>> +		case CLKCFG_FSB_400:
>>> +			return 400000;
>>> +		case CLKCFG_FSB_533:
>>> +			return 533333;
>>> +		case CLKCFG_FSB_667:
>>> +			return 666667;
>>> +		case CLKCFG_FSB_800:
>>> +			return 800000;
>>> +		case CLKCFG_FSB_1067:
>>> +			return 1066667;
>>> +		case CLKCFG_FSB_1333:
>>> +			return 1333333;
>>> +		default:
>>> +			MISSING_CASE(fsb);
>>> +			return 1333333;
>>> +		}
>>> +	} else {
>>> +		switch (fsb) {
>>> +		case CLKCFG_FSB_400_ALT:
>>> +			return 400000;
>>> +		case CLKCFG_FSB_533:
>>> +			return 533333;
>>> +		case CLKCFG_FSB_667:
>>> +			return 666667;
>>> +		case CLKCFG_FSB_800:
>>> +			return 800000;
>>> +		case CLKCFG_FSB_1067_ALT:
>>> +			return 1066667;
>>> +		case CLKCFG_FSB_1333_ALT:
>>> +			return 1333333;
>>> +		case CLKCFG_FSB_1600_ALT:
>>> +			return 1600000;
>>> +		default:
>>> +			return 533333;
>>> +		}
>>>  	}
>>> -
>>> -	return 0;
>>>  }
>>>  
>>>  static unsigned int ilk_fsb_freq(struct drm_i915_private *dev_priv)
>>> @@ -193,8 +219,8 @@ static void detect_fsb_freq(struct drm_i915_private *i915)
>>>  {
>>>  	if (GRAPHICS_VER(i915) == 5)
>>>  		i915->fsb_freq = ilk_fsb_freq(i915);
>>> -	else if (IS_PINEVIEW(i915))
>>> -		i915->fsb_freq = pnv_fsb_freq(i915);
>>> +	else if (GRAPHICS_VER(i915) == 3 || GRAPHICS_VER(i915) == 4)
>>> +		i915->fsb_freq = i9xx_fsb_freq(i915);
>>>  
>>>  	if (i915->fsb_freq)
>>>  		drm_dbg(&i915->drm, "FSB frequency: %d kHz\n", i915->fsb_freq);
>>> -- 
>>> 2.39.2
>>> 

-- 
Jani Nikula, Intel

Re: [PATCH 06/12] drm/i915: convert fsb_freq and mem_freq to kHz

[Ville Syrjälä]

On Tue, May 28, 2024 at 05:24:55PM +0300, Jani Nikula wrote:
> We'll want to use fsb frequency for deriving GT clock and rawclk
> frequencies in the future. Increase the accuracy by converting to
> kHz. Do the same for mem freq to be aligned.

mem_freq is used in:
- gen5_rps_init() -> needs to be adjusted, with care taken for rounding
- intel_gt_pm_frequency_dump() -> should probably be nuked from here

> 
> Round the frequencies ending in 666 to 667.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/i9xx_wm.c |  6 ++--
>  drivers/gpu/drm/i915/gt/intel_rps.c    |  4 +--
>  drivers/gpu/drm/i915/soc/intel_dram.c  | 50 +++++++++++++-------------
>  3 files changed, 30 insertions(+), 30 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
> index 8b8a0f305c3a..08c5d122af8f 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_wm.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
> @@ -83,14 +83,14 @@ static const struct cxsr_latency *pnv_get_cxsr_latency(struct drm_i915_private *
>  
>  		if (is_desktop == latency->is_desktop &&
>  		    i915->is_ddr3 == latency->is_ddr3 &&
> -		    i915->fsb_freq == latency->fsb_freq &&
> -		    i915->mem_freq == latency->mem_freq)
> +		    DIV_ROUND_CLOSEST(i915->fsb_freq, 1000) == latency->fsb_freq &&
> +		    DIV_ROUND_CLOSEST(i915->mem_freq, 1000) == latency->mem_freq)
>  			return latency;
>  	}
>  
>  err:
>  	drm_dbg_kms(&i915->drm,
> -		    "Could not find CxSR latency for DDR%s, FSB %u MHz, MEM %u MHz\n",
> +		    "Could not find CxSR latency for DDR%s, FSB %u kHz, MEM %u kHz\n",
>  		    i915->is_ddr3 ? "3" : "2", i915->fsb_freq, i915->mem_freq);
>  
>  	return NULL;
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
> index c9cb2a391942..5d3de1cddcf6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -280,9 +280,9 @@ static void gen5_rps_init(struct intel_rps *rps)
>  	u32 rgvmodectl;
>  	int c_m, i;
>  
> -	if (i915->fsb_freq <= 3200)
> +	if (i915->fsb_freq <= 3200000)
>  		c_m = 0;
> -	else if (i915->fsb_freq <= 4800)
> +	else if (i915->fsb_freq <= 4800000)
>  		c_m = 1;
>  	else
>  		c_m = 2;
> diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c
> index 266ed6cfa485..ace9372244a4 100644
> --- a/drivers/gpu/drm/i915/soc/intel_dram.c
> +++ b/drivers/gpu/drm/i915/soc/intel_dram.c
> @@ -56,11 +56,11 @@ static unsigned int pnv_mem_freq(struct drm_i915_private *dev_priv)
>  
>  	switch (tmp & CLKCFG_MEM_MASK) {
>  	case CLKCFG_MEM_533:
> -		return 533;
> +		return 533333;
>  	case CLKCFG_MEM_667:
> -		return 667;
> +		return 666667;
>  	case CLKCFG_MEM_800:
> -		return 800;
> +		return 800000;
>  	}
>  
>  	return 0;
> @@ -73,13 +73,13 @@ static unsigned int ilk_mem_freq(struct drm_i915_private *dev_priv)
>  	ddrpll = intel_uncore_read16(&dev_priv->uncore, DDRMPLL1);
>  	switch (ddrpll & 0xff) {
>  	case 0xc:
> -		return 800;
> +		return 800000;
>  	case 0x10:
> -		return 1066;
> +		return 1066667;
>  	case 0x14:
> -		return 1333;
> +		return 1333333;
>  	case 0x18:
> -		return 1600;
> +		return 1600000;
>  	default:
>  		drm_dbg(&dev_priv->drm, "unknown memory frequency 0x%02x\n",
>  			ddrpll & 0xff);
> @@ -97,9 +97,9 @@ static unsigned int chv_mem_freq(struct drm_i915_private *i915)
>  
>  	switch ((val >> 2) & 0x7) {
>  	case 3:
> -		return 2000;
> +		return 2000000;
>  	default:
> -		return 1600;
> +		return 1600000;
>  	}
>  }
>  
> @@ -114,11 +114,11 @@ static unsigned int vlv_mem_freq(struct drm_i915_private *i915)
>  	switch ((val >> 6) & 3) {
>  	case 0:
>  	case 1:
> -		return 800;
> +		return 800000;
>  	case 2:
> -		return 1066;
> +		return 1066667;
>  	case 3:
> -		return 1333;
> +		return 1333333;
>  	}
>  
>  	return 0;
> @@ -139,7 +139,7 @@ static void detect_mem_freq(struct drm_i915_private *i915)
>  		i915->is_ddr3 = pnv_is_ddr3(i915);
>  
>  	if (i915->mem_freq)
> -		drm_dbg(&i915->drm, "DDR speed: %d MHz\n", i915->mem_freq);
> +		drm_dbg(&i915->drm, "DDR speed: %d kHz\n", i915->mem_freq);
>  }
>  
>  static unsigned int pnv_fsb_freq(struct drm_i915_private *i915)
> @@ -150,13 +150,13 @@ static unsigned int pnv_fsb_freq(struct drm_i915_private *i915)
>  
>  	switch (fsb) {
>  	case CLKCFG_FSB_400:
> -		return 400;
> +		return 400000;
>  	case CLKCFG_FSB_533:
> -		return 533;
> +		return 533333;
>  	case CLKCFG_FSB_667:
> -		return 667;
> +		return 666667;
>  	case CLKCFG_FSB_800:
> -		return 800;
> +		return 800000;
>  	}
>  
>  	return 0;
> @@ -170,19 +170,19 @@ static unsigned int ilk_fsb_freq(struct drm_i915_private *dev_priv)
>  
>  	switch (fsb) {
>  	case 0x00c:
> -		return 3200;
> +		return 3200000;
>  	case 0x00e:
> -		return 3733;
> +		return 3733333;
>  	case 0x010:
> -		return 4266;
> +		return 4266667;
>  	case 0x012:
> -		return 4800;
> +		return 4800000;
>  	case 0x014:
> -		return 5333;
> +		return 5333333;
>  	case 0x016:
> -		return 5866;
> +		return 5866667;
>  	case 0x018:
> -		return 6400;
> +		return 6400000;
>  	default:
>  		drm_dbg(&dev_priv->drm, "unknown fsb frequency 0x%04x\n", fsb);
>  		return 0;
> @@ -197,7 +197,7 @@ static void detect_fsb_freq(struct drm_i915_private *i915)
>  		i915->fsb_freq = pnv_fsb_freq(i915);
>  
>  	if (i915->fsb_freq)
> -		drm_dbg(&i915->drm, "FSB frequency: %d MHz\n", i915->fsb_freq);
> +		drm_dbg(&i915->drm, "FSB frequency: %d kHz\n", i915->fsb_freq);
>  }
>  
>  static int intel_dimm_num_devices(const struct dram_dimm_info *dimm)
> -- 
> 2.39.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 07/12] drm/i915: extend the fsb_freq initialization to more platforms

[Ville Syrjälä]

On Tue, Jun 04, 2024 at 02:46:18PM +0300, Jani Nikula wrote:
> On Thu, 30 May 2024, Jani Nikula <jani.nikula@intel.com> wrote:
> > On Wed, 29 May 2024, Matt Roper <matthew.d.roper@intel.com> wrote:
> >> On Tue, May 28, 2024 at 05:24:56PM +0300, Jani Nikula wrote:
> >>> Initialize fsb frequency for more platforms to be able to use it for GT
> >>> clock and rawclk frequency initialization.
> >>> 
> >>> Note: There's a discrepancy between existing pnv_fsb_freq() and
> >>> i9xx_hrawclk() regarding CLKCFG interpretation. Presume all PNV is
> >>> mobile.
> >>
> >> Do you just mean we assume PNV always treats CLKCFG the same way mobile
> >> platforms do?  Because we have both mobile and non-mobile platforms
> >> defined in the driver (pnv_m_info vs pnv_g_info) and that matches
> >> https://ark.intel.com/content/www/us/en/ark/products/codename/32201/products-formerly-pineview.html
> >> that lists both desktop and mobile.
> >
> > Yeah. The problem is, current code in intel_dram.c and intel_cdclk.c
> > interpret the CLKCFG register differently for desktop PNV. At least one
> > of them is wrong. Basically I just picked one, and secretly hoped Ville
> > would tell me. ;)
> 
> Ville, do you have any idea about CLKCFG?

Acording to the datasheet PNV only really supports the 667MHz
option, so technically might not even matter. Maybe there's some
way to force it to use a different clock, but at least one "desktop"
PNV I looked at didn't have any knobs in the BIOS for this.

Anyways, based on past experience PNV always looks like a mobile
part, despite potentially being itself considered the "desktop"
variant. That interpretation also matches the existing
pnv_detect_mem_freq() implementation. So from that POV the
patch looks correct to me.

> 
> BR,
> Jani.
> 
> 
> >
> > BR,
> > Jani.
> >
> >
> >>
> >>
> >> Matt
> >>
> >>> 
> >>> FIXME: What should the default or failure mode be when the value is
> >>> unknown?
> >>> 
> >>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >>> ---
> >>>  drivers/gpu/drm/i915/soc/intel_dram.c | 54 ++++++++++++++++++++-------
> >>>  1 file changed, 40 insertions(+), 14 deletions(-)
> >>> 
> >>> diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c
> >>> index ace9372244a4..74b5b70e91f9 100644
> >>> --- a/drivers/gpu/drm/i915/soc/intel_dram.c
> >>> +++ b/drivers/gpu/drm/i915/soc/intel_dram.c
> >>> @@ -142,24 +142,50 @@ static void detect_mem_freq(struct drm_i915_private *i915)
> >>>  		drm_dbg(&i915->drm, "DDR speed: %d kHz\n", i915->mem_freq);
> >>>  }
> >>>  
> >>> -static unsigned int pnv_fsb_freq(struct drm_i915_private *i915)
> >>> +static unsigned int i9xx_fsb_freq(struct drm_i915_private *i915)
> >>>  {
> >>>  	u32 fsb;
> >>>  
> >>>  	fsb = intel_uncore_read(&i915->uncore, CLKCFG) & CLKCFG_FSB_MASK;
> >>>  
> >>> -	switch (fsb) {
> >>> -	case CLKCFG_FSB_400:
> >>> -		return 400000;
> >>> -	case CLKCFG_FSB_533:
> >>> -		return 533333;
> >>> -	case CLKCFG_FSB_667:
> >>> -		return 666667;
> >>> -	case CLKCFG_FSB_800:
> >>> -		return 800000;
> >>> +	if (IS_PINEVIEW(i915) || IS_MOBILE(i915)) {
> >>> +		switch (fsb) {
> >>> +		case CLKCFG_FSB_400:
> >>> +			return 400000;
> >>> +		case CLKCFG_FSB_533:
> >>> +			return 533333;
> >>> +		case CLKCFG_FSB_667:
> >>> +			return 666667;
> >>> +		case CLKCFG_FSB_800:
> >>> +			return 800000;
> >>> +		case CLKCFG_FSB_1067:
> >>> +			return 1066667;
> >>> +		case CLKCFG_FSB_1333:
> >>> +			return 1333333;
> >>> +		default:
> >>> +			MISSING_CASE(fsb);
> >>> +			return 1333333;
> >>> +		}
> >>> +	} else {
> >>> +		switch (fsb) {
> >>> +		case CLKCFG_FSB_400_ALT:
> >>> +			return 400000;
> >>> +		case CLKCFG_FSB_533:
> >>> +			return 533333;
> >>> +		case CLKCFG_FSB_667:
> >>> +			return 666667;
> >>> +		case CLKCFG_FSB_800:
> >>> +			return 800000;
> >>> +		case CLKCFG_FSB_1067_ALT:
> >>> +			return 1066667;
> >>> +		case CLKCFG_FSB_1333_ALT:
> >>> +			return 1333333;
> >>> +		case CLKCFG_FSB_1600_ALT:
> >>> +			return 1600000;
> >>> +		default:
> >>> +			return 533333;
> >>> +		}
> >>>  	}
> >>> -
> >>> -	return 0;
> >>>  }
> >>>  
> >>>  static unsigned int ilk_fsb_freq(struct drm_i915_private *dev_priv)
> >>> @@ -193,8 +219,8 @@ static void detect_fsb_freq(struct drm_i915_private *i915)
> >>>  {
> >>>  	if (GRAPHICS_VER(i915) == 5)
> >>>  		i915->fsb_freq = ilk_fsb_freq(i915);
> >>> -	else if (IS_PINEVIEW(i915))
> >>> -		i915->fsb_freq = pnv_fsb_freq(i915);
> >>> +	else if (GRAPHICS_VER(i915) == 3 || GRAPHICS_VER(i915) == 4)
> >>> +		i915->fsb_freq = i9xx_fsb_freq(i915);
> >>>  
> >>>  	if (i915->fsb_freq)
> >>>  		drm_dbg(&i915->drm, "FSB frequency: %d kHz\n", i915->fsb_freq);
> >>> -- 
> >>> 2.39.2
> >>> 
> 
> -- 
> Jani Nikula, Intel

-- 
Ville Syrjälä
Intel

Re: [PATCH 07/12] drm/i915: extend the fsb_freq initialization to more platforms

[Ville Syrjälä]

On Tue, May 28, 2024 at 05:24:56PM +0300, Jani Nikula wrote:
> Initialize fsb frequency for more platforms to be able to use it for GT
> clock and rawclk frequency initialization.
> 
> Note: There's a discrepancy between existing pnv_fsb_freq() and
> i9xx_hrawclk() regarding CLKCFG interpretation. Presume all PNV is
> mobile.
> 
> FIXME: What should the default or failure mode be when the value is
> unknown?
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/soc/intel_dram.c | 54 ++++++++++++++++++++-------
>  1 file changed, 40 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c
> index ace9372244a4..74b5b70e91f9 100644
> --- a/drivers/gpu/drm/i915/soc/intel_dram.c
> +++ b/drivers/gpu/drm/i915/soc/intel_dram.c
> @@ -142,24 +142,50 @@ static void detect_mem_freq(struct drm_i915_private *i915)
>  		drm_dbg(&i915->drm, "DDR speed: %d kHz\n", i915->mem_freq);
>  }
>  
> -static unsigned int pnv_fsb_freq(struct drm_i915_private *i915)
> +static unsigned int i9xx_fsb_freq(struct drm_i915_private *i915)
>  {
>  	u32 fsb;
>  
>  	fsb = intel_uncore_read(&i915->uncore, CLKCFG) & CLKCFG_FSB_MASK;
>  
> -	switch (fsb) {
> -	case CLKCFG_FSB_400:
> -		return 400000;
> -	case CLKCFG_FSB_533:
> -		return 533333;
> -	case CLKCFG_FSB_667:
> -		return 666667;
> -	case CLKCFG_FSB_800:
> -		return 800000;
> +	if (IS_PINEVIEW(i915) || IS_MOBILE(i915)) {
> +		switch (fsb) {
> +		case CLKCFG_FSB_400:
> +			return 400000;
> +		case CLKCFG_FSB_533:
> +			return 533333;
> +		case CLKCFG_FSB_667:
> +			return 666667;
> +		case CLKCFG_FSB_800:
> +			return 800000;
> +		case CLKCFG_FSB_1067:
> +			return 1066667;
> +		case CLKCFG_FSB_1333:
> +			return 1333333;
> +		default:
> +			MISSING_CASE(fsb);
> +			return 1333333;
> +		}
> +	} else {
> +		switch (fsb) {
> +		case CLKCFG_FSB_400_ALT:
> +			return 400000;
> +		case CLKCFG_FSB_533:
> +			return 533333;
> +		case CLKCFG_FSB_667:
> +			return 666667;
> +		case CLKCFG_FSB_800:
> +			return 800000;
> +		case CLKCFG_FSB_1067_ALT:
> +			return 1066667;
> +		case CLKCFG_FSB_1333_ALT:
> +			return 1333333;
> +		case CLKCFG_FSB_1600_ALT:
> +			return 1600000;
> +		default:

No MISSING_CASE() here?

> +			return 533333;

Why a different default value vs. the other branch?

> +		}
>  	}
> -
> -	return 0;
>  }
>  
>  static unsigned int ilk_fsb_freq(struct drm_i915_private *dev_priv)
> @@ -193,8 +219,8 @@ static void detect_fsb_freq(struct drm_i915_private *i915)
>  {
>  	if (GRAPHICS_VER(i915) == 5)
>  		i915->fsb_freq = ilk_fsb_freq(i915);
> -	else if (IS_PINEVIEW(i915))
> -		i915->fsb_freq = pnv_fsb_freq(i915);
> +	else if (GRAPHICS_VER(i915) == 3 || GRAPHICS_VER(i915) == 4)
> +		i915->fsb_freq = i9xx_fsb_freq(i915);
>  
>  	if (i915->fsb_freq)
>  		drm_dbg(&i915->drm, "FSB frequency: %d kHz\n", i915->fsb_freq);
> -- 
> 2.39.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 09/12] drm/i915/cdclk: use i9xx_fsb_freq() for rawclk_freq initialization

[Ville Syrjälä]

On Tue, May 28, 2024 at 05:24:58PM +0300, Jani Nikula wrote:
> Instead of duplicating the CLKCFG parsing, reuse i9xx_fsb_freq() to
> figure out rawclk_freq where applicable.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 46 ++--------------------
>  1 file changed, 3 insertions(+), 43 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index b78154c82a71..c731c489c925 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -23,6 +23,7 @@
>  
>  #include <linux/time.h>
>  
> +#include "soc/intel_dram.h"
>  #include "hsw_ips.h"
>  #include "i915_reg.h"
>  #include "intel_atomic.h"
> @@ -3529,10 +3530,8 @@ static int vlv_hrawclk(struct drm_i915_private *dev_priv)
>  				      CCK_DISPLAY_REF_CLOCK_CONTROL);
>  }
>  
> -static int i9xx_hrawclk(struct drm_i915_private *dev_priv)
> +static int i9xx_hrawclk(struct drm_i915_private *i915)
>  {
> -	u32 clkcfg;
> -
>  	/*
>  	 * hrawclock is 1/4 the FSB frequency
>  	 *
> @@ -3543,46 +3542,7 @@ static int i9xx_hrawclk(struct drm_i915_private *dev_priv)
>  	 * don't know which registers have that information,
>  	 * and all the relevant docs have gone to bit heaven :(
>  	 */

^ the note about the actual clock vs. straps should probably be moved
into i9xx_fsb_freq() as a followup.

> -	clkcfg = intel_de_read(dev_priv, CLKCFG) & CLKCFG_FSB_MASK;
> -
> -	if (IS_MOBILE(dev_priv)) {
> -		switch (clkcfg) {
> -		case CLKCFG_FSB_400:
> -			return 100000;
> -		case CLKCFG_FSB_533:
> -			return 133333;
> -		case CLKCFG_FSB_667:
> -			return 166667;
> -		case CLKCFG_FSB_800:
> -			return 200000;
> -		case CLKCFG_FSB_1067:
> -			return 266667;
> -		case CLKCFG_FSB_1333:
> -			return 333333;
> -		default:
> -			MISSING_CASE(clkcfg);
> -			return 133333;
> -		}
> -	} else {
> -		switch (clkcfg) {
> -		case CLKCFG_FSB_400_ALT:
> -			return 100000;
> -		case CLKCFG_FSB_533:
> -			return 133333;
> -		case CLKCFG_FSB_667:
> -			return 166667;
> -		case CLKCFG_FSB_800:
> -			return 200000;
> -		case CLKCFG_FSB_1067_ALT:
> -			return 266667;
> -		case CLKCFG_FSB_1333_ALT:
> -			return 333333;
> -		case CLKCFG_FSB_1600_ALT:
> -			return 400000;
> -		default:
> -			return 133333;
> -		}
> -	}
> +	return DIV_ROUND_CLOSEST(i9xx_fsb_freq(i915), 4);
>  }
>  
>  /**
> -- 
> 2.39.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 06/12] drm/i915: convert fsb_freq and mem_freq to kHz

[Jani Nikula]

On Wed, 05 Jun 2024, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Tue, May 28, 2024 at 05:24:55PM +0300, Jani Nikula wrote:
>> We'll want to use fsb frequency for deriving GT clock and rawclk
>> frequencies in the future. Increase the accuracy by converting to
>> kHz. Do the same for mem freq to be aligned.
>
> mem_freq is used in:
> - gen5_rps_init() -> needs to be adjusted, with care taken for rounding
> - intel_gt_pm_frequency_dump() -> should probably be nuked from here

Good catches. Sloppy on my part.

Thanks,
Jani.

>
>> 
>> Round the frequencies ending in 666 to 667.
>> 
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/i9xx_wm.c |  6 ++--
>>  drivers/gpu/drm/i915/gt/intel_rps.c    |  4 +--
>>  drivers/gpu/drm/i915/soc/intel_dram.c  | 50 +++++++++++++-------------
>>  3 files changed, 30 insertions(+), 30 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
>> index 8b8a0f305c3a..08c5d122af8f 100644
>> --- a/drivers/gpu/drm/i915/display/i9xx_wm.c
>> +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
>> @@ -83,14 +83,14 @@ static const struct cxsr_latency *pnv_get_cxsr_latency(struct drm_i915_private *
>>  
>>  		if (is_desktop == latency->is_desktop &&
>>  		    i915->is_ddr3 == latency->is_ddr3 &&
>> -		    i915->fsb_freq == latency->fsb_freq &&
>> -		    i915->mem_freq == latency->mem_freq)
>> +		    DIV_ROUND_CLOSEST(i915->fsb_freq, 1000) == latency->fsb_freq &&
>> +		    DIV_ROUND_CLOSEST(i915->mem_freq, 1000) == latency->mem_freq)
>>  			return latency;
>>  	}
>>  
>>  err:
>>  	drm_dbg_kms(&i915->drm,
>> -		    "Could not find CxSR latency for DDR%s, FSB %u MHz, MEM %u MHz\n",
>> +		    "Could not find CxSR latency for DDR%s, FSB %u kHz, MEM %u kHz\n",
>>  		    i915->is_ddr3 ? "3" : "2", i915->fsb_freq, i915->mem_freq);
>>  
>>  	return NULL;
>> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
>> index c9cb2a391942..5d3de1cddcf6 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
>> @@ -280,9 +280,9 @@ static void gen5_rps_init(struct intel_rps *rps)
>>  	u32 rgvmodectl;
>>  	int c_m, i;
>>  
>> -	if (i915->fsb_freq <= 3200)
>> +	if (i915->fsb_freq <= 3200000)
>>  		c_m = 0;
>> -	else if (i915->fsb_freq <= 4800)
>> +	else if (i915->fsb_freq <= 4800000)
>>  		c_m = 1;
>>  	else
>>  		c_m = 2;
>> diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c
>> index 266ed6cfa485..ace9372244a4 100644
>> --- a/drivers/gpu/drm/i915/soc/intel_dram.c
>> +++ b/drivers/gpu/drm/i915/soc/intel_dram.c
>> @@ -56,11 +56,11 @@ static unsigned int pnv_mem_freq(struct drm_i915_private *dev_priv)
>>  
>>  	switch (tmp & CLKCFG_MEM_MASK) {
>>  	case CLKCFG_MEM_533:
>> -		return 533;
>> +		return 533333;
>>  	case CLKCFG_MEM_667:
>> -		return 667;
>> +		return 666667;
>>  	case CLKCFG_MEM_800:
>> -		return 800;
>> +		return 800000;
>>  	}
>>  
>>  	return 0;
>> @@ -73,13 +73,13 @@ static unsigned int ilk_mem_freq(struct drm_i915_private *dev_priv)
>>  	ddrpll = intel_uncore_read16(&dev_priv->uncore, DDRMPLL1);
>>  	switch (ddrpll & 0xff) {
>>  	case 0xc:
>> -		return 800;
>> +		return 800000;
>>  	case 0x10:
>> -		return 1066;
>> +		return 1066667;
>>  	case 0x14:
>> -		return 1333;
>> +		return 1333333;
>>  	case 0x18:
>> -		return 1600;
>> +		return 1600000;
>>  	default:
>>  		drm_dbg(&dev_priv->drm, "unknown memory frequency 0x%02x\n",
>>  			ddrpll & 0xff);
>> @@ -97,9 +97,9 @@ static unsigned int chv_mem_freq(struct drm_i915_private *i915)
>>  
>>  	switch ((val >> 2) & 0x7) {
>>  	case 3:
>> -		return 2000;
>> +		return 2000000;
>>  	default:
>> -		return 1600;
>> +		return 1600000;
>>  	}
>>  }
>>  
>> @@ -114,11 +114,11 @@ static unsigned int vlv_mem_freq(struct drm_i915_private *i915)
>>  	switch ((val >> 6) & 3) {
>>  	case 0:
>>  	case 1:
>> -		return 800;
>> +		return 800000;
>>  	case 2:
>> -		return 1066;
>> +		return 1066667;
>>  	case 3:
>> -		return 1333;
>> +		return 1333333;
>>  	}
>>  
>>  	return 0;
>> @@ -139,7 +139,7 @@ static void detect_mem_freq(struct drm_i915_private *i915)
>>  		i915->is_ddr3 = pnv_is_ddr3(i915);
>>  
>>  	if (i915->mem_freq)
>> -		drm_dbg(&i915->drm, "DDR speed: %d MHz\n", i915->mem_freq);
>> +		drm_dbg(&i915->drm, "DDR speed: %d kHz\n", i915->mem_freq);
>>  }
>>  
>>  static unsigned int pnv_fsb_freq(struct drm_i915_private *i915)
>> @@ -150,13 +150,13 @@ static unsigned int pnv_fsb_freq(struct drm_i915_private *i915)
>>  
>>  	switch (fsb) {
>>  	case CLKCFG_FSB_400:
>> -		return 400;
>> +		return 400000;
>>  	case CLKCFG_FSB_533:
>> -		return 533;
>> +		return 533333;
>>  	case CLKCFG_FSB_667:
>> -		return 667;
>> +		return 666667;
>>  	case CLKCFG_FSB_800:
>> -		return 800;
>> +		return 800000;
>>  	}
>>  
>>  	return 0;
>> @@ -170,19 +170,19 @@ static unsigned int ilk_fsb_freq(struct drm_i915_private *dev_priv)
>>  
>>  	switch (fsb) {
>>  	case 0x00c:
>> -		return 3200;
>> +		return 3200000;
>>  	case 0x00e:
>> -		return 3733;
>> +		return 3733333;
>>  	case 0x010:
>> -		return 4266;
>> +		return 4266667;
>>  	case 0x012:
>> -		return 4800;
>> +		return 4800000;
>>  	case 0x014:
>> -		return 5333;
>> +		return 5333333;
>>  	case 0x016:
>> -		return 5866;
>> +		return 5866667;
>>  	case 0x018:
>> -		return 6400;
>> +		return 6400000;
>>  	default:
>>  		drm_dbg(&dev_priv->drm, "unknown fsb frequency 0x%04x\n", fsb);
>>  		return 0;
>> @@ -197,7 +197,7 @@ static void detect_fsb_freq(struct drm_i915_private *i915)
>>  		i915->fsb_freq = pnv_fsb_freq(i915);
>>  
>>  	if (i915->fsb_freq)
>> -		drm_dbg(&i915->drm, "FSB frequency: %d MHz\n", i915->fsb_freq);
>> +		drm_dbg(&i915->drm, "FSB frequency: %d kHz\n", i915->fsb_freq);
>>  }
>>  
>>  static int intel_dimm_num_devices(const struct dram_dimm_info *dimm)
>> -- 
>> 2.39.2

-- 
Jani Nikula, Intel

Re: [PATCH 07/12] drm/i915: extend the fsb_freq initialization to more platforms

[Jani Nikula]

On Wed, 05 Jun 2024, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Tue, May 28, 2024 at 05:24:56PM +0300, Jani Nikula wrote:
>> Initialize fsb frequency for more platforms to be able to use it for GT
>> clock and rawclk frequency initialization.
>> 
>> Note: There's a discrepancy between existing pnv_fsb_freq() and
>> i9xx_hrawclk() regarding CLKCFG interpretation. Presume all PNV is
>> mobile.
>> 
>> FIXME: What should the default or failure mode be when the value is
>> unknown?
>> 
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>  drivers/gpu/drm/i915/soc/intel_dram.c | 54 ++++++++++++++++++++-------
>>  1 file changed, 40 insertions(+), 14 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c
>> index ace9372244a4..74b5b70e91f9 100644
>> --- a/drivers/gpu/drm/i915/soc/intel_dram.c
>> +++ b/drivers/gpu/drm/i915/soc/intel_dram.c
>> @@ -142,24 +142,50 @@ static void detect_mem_freq(struct drm_i915_private *i915)
>>  		drm_dbg(&i915->drm, "DDR speed: %d kHz\n", i915->mem_freq);
>>  }
>>  
>> -static unsigned int pnv_fsb_freq(struct drm_i915_private *i915)
>> +static unsigned int i9xx_fsb_freq(struct drm_i915_private *i915)
>>  {
>>  	u32 fsb;
>>  
>>  	fsb = intel_uncore_read(&i915->uncore, CLKCFG) & CLKCFG_FSB_MASK;
>>  
>> -	switch (fsb) {
>> -	case CLKCFG_FSB_400:
>> -		return 400000;
>> -	case CLKCFG_FSB_533:
>> -		return 533333;
>> -	case CLKCFG_FSB_667:
>> -		return 666667;
>> -	case CLKCFG_FSB_800:
>> -		return 800000;
>> +	if (IS_PINEVIEW(i915) || IS_MOBILE(i915)) {
>> +		switch (fsb) {
>> +		case CLKCFG_FSB_400:
>> +			return 400000;
>> +		case CLKCFG_FSB_533:
>> +			return 533333;
>> +		case CLKCFG_FSB_667:
>> +			return 666667;
>> +		case CLKCFG_FSB_800:
>> +			return 800000;
>> +		case CLKCFG_FSB_1067:
>> +			return 1066667;
>> +		case CLKCFG_FSB_1333:
>> +			return 1333333;
>> +		default:
>> +			MISSING_CASE(fsb);
>> +			return 1333333;
>> +		}
>> +	} else {
>> +		switch (fsb) {
>> +		case CLKCFG_FSB_400_ALT:
>> +			return 400000;
>> +		case CLKCFG_FSB_533:
>> +			return 533333;
>> +		case CLKCFG_FSB_667:
>> +			return 666667;
>> +		case CLKCFG_FSB_800:
>> +			return 800000;
>> +		case CLKCFG_FSB_1067_ALT:
>> +			return 1066667;
>> +		case CLKCFG_FSB_1333_ALT:
>> +			return 1333333;
>> +		case CLKCFG_FSB_1600_ALT:
>> +			return 1600000;
>> +		default:
>
> No MISSING_CASE() here?

Whoops.

>
>> +			return 533333;
>
> Why a different default value vs. the other branch?

No idea. :/

>
>> +		}
>>  	}
>> -
>> -	return 0;
>>  }
>>  
>>  static unsigned int ilk_fsb_freq(struct drm_i915_private *dev_priv)
>> @@ -193,8 +219,8 @@ static void detect_fsb_freq(struct drm_i915_private *i915)
>>  {
>>  	if (GRAPHICS_VER(i915) == 5)
>>  		i915->fsb_freq = ilk_fsb_freq(i915);
>> -	else if (IS_PINEVIEW(i915))
>> -		i915->fsb_freq = pnv_fsb_freq(i915);
>> +	else if (GRAPHICS_VER(i915) == 3 || GRAPHICS_VER(i915) == 4)
>> +		i915->fsb_freq = i9xx_fsb_freq(i915);
>>  
>>  	if (i915->fsb_freq)
>>  		drm_dbg(&i915->drm, "FSB frequency: %d kHz\n", i915->fsb_freq);
>> -- 
>> 2.39.2

-- 
Jani Nikula, Intel