[PATCH v5 0/7] Add support for EU stall sampling

[PATCH v5 0/7] Add support for EU stall sampling

[Harish Chegondi]

The following patch series add support for EU stall sampling,
a new hardware feature first added in PVC and is being supported
in XE2 and later architecture GPUs. This feature would enable
capturing of EU stall data which include the IP address of the
instruction stalled and various stall reason counts.

Support for this feature is being added into Mesa.
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30142

A new test in the IGT repo:
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
is also under development to test this feature in the driver. This
patch has undergone basic testing with the new IGT test that is under
development.

Thank You.

v5: Addressed review feedback from v4 including
    a. Removed DRM_XE_EU_STALL_PROP_POLL_PERIOD from the uAPI (Ashutosh)
    b. Separated the patches for Xe_HPC and Xe2 (Matt R)
    c. Moved read() returning -EIO into a separate patch
    d. Removed spinlocks around set_bit() and clear_bit() (Matt R)
    e. Renamed several variables, structures and enums (Ashutosh and
Matt R)
    f. Addressed other review feedback.
v4: Addressed review feedback from v3 including
    a. Split the patch into multiple patches (Matt R)
    b. Added a new device query to get EU stall info (Ashutosh)
    c. Renamed all Dss to xecore (Matt R)
    d. Removed buffer size and disable at open input properties. (Matt R)
    e. Removed the "_SHIFT" macros (Matt R)
    f. Allocate the EU stall buffer only on system memory.
    g. Changed the work arounds to OOB (Matt R)
    h. Other review feedback.
v3: a. Removed data header and changed read() to return -EIO when data is dropped by the HW.
    b. Added a new DRM_XE_OBSERVATION_IOCTL_INFO to query EU stall data record info
    c. Added struct drm_xe_eu_stall_data_pvc and struct drm_xe_eu_stall_data_xe2
       to xe_drm.h. These declarations would help user space to parse the
       EU stall data
    d. Addressed other review comments from v2
v2: Rename xe perf layer as xe observation layer (Ashutosh)

Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

Harish Chegondi (7):
  drm/xe/topology: Add a function to find the index of the last enabled
    DSS in a mask
  drm/xe/eustall: Introduce API for EU stall sampling
  drm/xe/eustall: Implement EU stall sampling APIs for Xe_HPC
  drm/xe/eustall: Return -EIO error from read() if HW drops data
  drm/xe/eustall: Add EU stall sampling support for Xe2
  drm/xe/query: Add a device query to get EU stall data information
  drm/xe/eustall: Add workaround 22016596838 which applies to PVC.

 drivers/gpu/drm/xe/Makefile                |    1 +
 drivers/gpu/drm/xe/regs/xe_eu_stall_regs.h |   29 +
 drivers/gpu/drm/xe/xe_eu_stall.c           | 1054 ++++++++++++++++++++
 drivers/gpu/drm/xe/xe_eu_stall.h           |   58 ++
 drivers/gpu/drm/xe/xe_gt.c                 |    6 +
 drivers/gpu/drm/xe/xe_gt_topology.h        |   13 +
 drivers/gpu/drm/xe/xe_gt_types.h           |    3 +
 drivers/gpu/drm/xe/xe_observation.c        |   14 +
 drivers/gpu/drm/xe/xe_query.c              |   30 +
 drivers/gpu/drm/xe/xe_trace.h              |   33 +
 drivers/gpu/drm/xe/xe_wa_oob.rules         |    1 +
 include/uapi/drm/xe_drm.h                  |   62 ++
 12 files changed, 1304 insertions(+)
 create mode 100644 drivers/gpu/drm/xe/regs/xe_eu_stall_regs.h
 create mode 100644 drivers/gpu/drm/xe/xe_eu_stall.c
 create mode 100644 drivers/gpu/drm/xe/xe_eu_stall.h

-- 
2.45.1

[PATCH v5 1/7] drm/xe/topology: Add a function to find the index of the last enabled DSS in a mask

[Harish Chegondi]

Last enabled DSS in a DSS mask can help estimate the maximum DSSes enabled
in the DSS mask, as the enabled DSSes can be discontiguous.

Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
---
 drivers/gpu/drm/xe/xe_gt_topology.h | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_gt_topology.h b/drivers/gpu/drm/xe/xe_gt_topology.h
index 746b325bbf6e..a72d26ba0653 100644
--- a/drivers/gpu/drm/xe/xe_gt_topology.h
+++ b/drivers/gpu/drm/xe/xe_gt_topology.h
@@ -25,6 +25,19 @@ void xe_gt_topology_init(struct xe_gt *gt);
 
 void xe_gt_topology_dump(struct xe_gt *gt, struct drm_printer *p);
 
+/**
+ * xe_gt_topology_mask_last_dss() - Returns the index of the last DSS in a mask.
+ * @mask: Input DSS mask
+ *
+ * Return: Index of the last DSS in the input DSS mask,
+ *	   XE_MAX_DSS_FUSE_BITS if DSS mask is empty.
+ */
+static inline unsigned int
+xe_gt_topology_mask_last_dss(const xe_dss_mask_t mask)
+{
+	return find_last_bit(mask, XE_MAX_DSS_FUSE_BITS);
+}
+
 unsigned int
 xe_dss_mask_group_ffs(const xe_dss_mask_t mask, int groupsize, int groupnum);
 
-- 
2.45.1

[PATCH v5 2/7] drm/xe/eustall: Introduce API for EU stall sampling

[Harish Chegondi]

A new hardware feature first introduced in PVC gives capability to
periodically sample EU stall state and record counts for different stall
reasons, on a per IP basis, aggregate across all EUs in a subslice and
record the samples in a buffer in each subslice. Eventually, the aggregated
data is written out to a buffer in the memory. This feature is also
supported in XE2 and later architecture GPUs.

Use an existing IOCTL DRM_IOCTL_XE_OBSERVATION as interface into the driver
from the user space to do initial setup and obtain a file descriptor for
the EU stall counter data stream.  Input parameter to the IOCTL is a struct
drm_xe_observation_param in which observation_type should be set to
DRM_XE_OBSERVATION_TYPE_EU_STALL, observation_op should be
DRM_XE_OBSERVATION_OP_STREAM_OPEN and param should point to a chain of
drm_xe_ext_set_property structures in which each structure has a pair of
property and value. The EU stall sampling input properties are defined in
drm_xe_eu_stall_property_id enum.

With the file descriptor obtained from DRM_IOCTL_XE_OBSERVATION, user space
can enable and disable EU stall sampling with the IOCTLs:
DRM_XE_OBSERVATION_IOCTL_ENABLE and DRM_XE_OBSERVATION_IOCTL_DISABLE.
User space can also call poll() to check for availability of data in the
buffer. The data can be read with read(). Finally, the file descriptor
can be closed with close().

A user space consumer for this feature is Mesa.

Mesa PR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30142

Cc: Felix Degrood <felix.j.degrood@intel.com>
Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
---
 drivers/gpu/drm/xe/Makefile         |   1 +
 drivers/gpu/drm/xe/xe_eu_stall.c    | 282 ++++++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_eu_stall.h    |  12 ++
 drivers/gpu/drm/xe/xe_observation.c |  14 ++
 include/uapi/drm/xe_drm.h           |  39 ++++
 5 files changed, 348 insertions(+)
 create mode 100644 drivers/gpu/drm/xe/xe_eu_stall.c
 create mode 100644 drivers/gpu/drm/xe/xe_eu_stall.h

diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 95aabbb74a28..cc56764bc561 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -33,6 +33,7 @@ xe-y += xe_bb.o \
 	xe_device_sysfs.o \
 	xe_dma_buf.o \
 	xe_drm_client.o \
+	xe_eu_stall.o \
 	xe_exec.o \
 	xe_execlist.o \
 	xe_exec_queue.o \
diff --git a/drivers/gpu/drm/xe/xe_eu_stall.c b/drivers/gpu/drm/xe/xe_eu_stall.c
new file mode 100644
index 000000000000..e9209fc0d917
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_eu_stall.c
@@ -0,0 +1,282 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+#include <linux/anon_inodes.h>
+#include <linux/types.h>
+#include <linux/poll.h>
+#include <linux/fs.h>
+
+#include <uapi/drm/xe_drm.h>
+
+#include "xe_macros.h"
+#include "xe_device.h"
+#include "xe_eu_stall.h"
+#include "xe_gt_printk.h"
+#include "xe_gt_topology.h"
+#include "xe_observation.h"
+
+/**
+ * struct eu_stall_open_properties - EU stall sampling properties received
+ *				     from user space at open.
+ * @eu_stall_sampling_rate: EU stall sampling rate multiplier.
+ *			    HW will sample every (eu_stall_sampling_rate x 251) cycles.
+ * @event_report_count: Minimum number of EU stall data rows for poll to set POLLIN.
+ * @gt: GT on which EU stall data will be captured.
+ */
+struct eu_stall_open_properties {
+	u8 eu_stall_sampling_rate;
+	u32 event_report_count;
+	struct xe_gt *gt;
+};
+
+/**
+ * num_data_rows - Return the number of EU stall data rows of 64B each
+ *		   for a given data size.
+ *
+ * @data_size: EU stall data size
+ */
+static inline u32
+num_data_rows(u32 data_size)
+{
+	return (data_size >> 6);
+}
+
+static int set_prop_eu_stall_sampling_rate(struct xe_device *xe, u64 value,
+					   struct eu_stall_open_properties *props)
+{
+	if (value == 0 || value > 7) {
+		drm_dbg(&xe->drm, "Invalid EU stall sampling rate %llu\n", value);
+		return -EINVAL;
+	}
+	props->eu_stall_sampling_rate = value;
+	return 0;
+}
+
+static int set_prop_eu_stall_event_report_count(struct xe_device *xe, u64 value,
+						struct eu_stall_open_properties *props)
+{
+	u32 max_event_report_count;
+
+	max_event_report_count = num_data_rows(SZ_512K * XE_MAX_DSS_FUSE_BITS);
+	if (value == 0 || value > max_event_report_count) {
+		drm_dbg(&xe->drm, "Invalid EU stall poll event report count %llu\n", value);
+		drm_dbg(&xe->drm, "Minimum event report count is 1, maximum is %u\n",
+			max_event_report_count);
+		return -EINVAL;
+	}
+	props->event_report_count = value;
+	return 0;
+}
+
+static int set_prop_eu_stall_gt_id(struct xe_device *xe, u64 value,
+				   struct eu_stall_open_properties *props)
+{
+	if (value >= xe->info.gt_count) {
+		drm_dbg(&xe->drm, "Invalid GT ID %llu for EU stall sampling\n", value);
+		return -EINVAL;
+	}
+	props->gt = xe_device_get_gt(xe, value);
+	return 0;
+}
+
+typedef int (*set_eu_stall_property_fn)(struct xe_device *xe, u64 value,
+					struct eu_stall_open_properties *props);
+
+static const set_eu_stall_property_fn xe_set_eu_stall_property_funcs[] = {
+	[DRM_XE_EU_STALL_PROP_SAMPLE_RATE] = set_prop_eu_stall_sampling_rate,
+	[DRM_XE_EU_STALL_PROP_EVENT_REPORT_COUNT] = set_prop_eu_stall_event_report_count,
+	[DRM_XE_EU_STALL_PROP_GT_ID] = set_prop_eu_stall_gt_id,
+};
+
+static int xe_eu_stall_user_ext_set_property(struct xe_device *xe, u64 extension,
+					     struct eu_stall_open_properties *props)
+{
+	u64 __user *address = u64_to_user_ptr(extension);
+	struct drm_xe_ext_set_property ext;
+	int err;
+	u32 idx;
+
+	err = __copy_from_user(&ext, address, sizeof(ext));
+	if (XE_IOCTL_DBG(xe, err))
+		return -EFAULT;
+
+	if (XE_IOCTL_DBG(xe, ext.property >= ARRAY_SIZE(xe_set_eu_stall_property_funcs)) ||
+	    XE_IOCTL_DBG(xe, ext.pad))
+		return -EINVAL;
+
+	idx = array_index_nospec(ext.property, ARRAY_SIZE(xe_set_eu_stall_property_funcs));
+	return xe_set_eu_stall_property_funcs[idx](xe, ext.value, props);
+}
+
+typedef int (*xe_eu_stall_user_extension_fn)(struct xe_device *xe, u64 extension,
+					     struct eu_stall_open_properties *props);
+static const xe_eu_stall_user_extension_fn xe_eu_stall_user_extension_funcs[] = {
+	[DRM_XE_EU_STALL_EXTENSION_SET_PROPERTY] = xe_eu_stall_user_ext_set_property,
+};
+
+static int xe_eu_stall_user_extensions(struct xe_device *xe, u64 extension,
+				       struct eu_stall_open_properties *props)
+{
+	u64 __user *address = u64_to_user_ptr(extension);
+	struct drm_xe_user_extension ext;
+	int err;
+	u32 idx;
+
+	err = __copy_from_user(&ext, address, sizeof(ext));
+	if (XE_IOCTL_DBG(xe, err))
+		return -EFAULT;
+
+	if (XE_IOCTL_DBG(xe, ext.pad) ||
+	    XE_IOCTL_DBG(xe, ext.name >= ARRAY_SIZE(xe_eu_stall_user_extension_funcs)))
+		return -EINVAL;
+
+	idx = array_index_nospec(ext.name, ARRAY_SIZE(xe_eu_stall_user_extension_funcs));
+	err = xe_eu_stall_user_extension_funcs[idx](xe, extension, props);
+	if (XE_IOCTL_DBG(xe, err))
+		return err;
+
+	if (ext.next_extension)
+		return xe_eu_stall_user_extensions(xe, ext.next_extension, props);
+
+	return 0;
+}
+
+/**
+ * xe_eu_stall_stream_read - handles userspace read() of a EU stall data stream fd.
+ *
+ * @file: An xe EU stall data stream file
+ * @buf: destination buffer given by userspace
+ * @count: the number of bytes userspace wants to read
+ * @ppos: (inout) file seek position (unused)
+ *
+ * Userspace must enable the EU stall stream with DRM_XE_OBSERVATION_IOCTL_ENABLE
+ * before calling read().
+ *
+ * Returns: The number of bytes copied or a negative error code on failure.
+ */
+static ssize_t xe_eu_stall_stream_read(struct file *file, char __user *buf,
+				       size_t count, loff_t *ppos)
+{
+	ssize_t ret = 0;
+
+	return ret;
+}
+
+/**
+ * xe_eu_stall_stream_poll - handles userspace poll() of a EU stall data stream fd.
+ *
+ * @file: An xe EU stall data stream file
+ * @wait: Poll table
+ *
+ * Returns: Bit mask of returned events.
+ */
+static __poll_t
+xe_eu_stall_stream_poll(struct file *file, poll_table *wait)
+{
+	__poll_t ret = 0;
+
+	return ret;
+}
+
+/**
+ * xe_eu_stall_stream_ioctl - support ioctl() of a xe EU stall data stream fd.
+ *
+ * @file: An xe EU stall data stream file
+ * @cmd: the ioctl request
+ * @arg: the ioctl data
+ *
+ * Returns: zero on success or a negative error code.
+ *	    -EINVAL for an unknown ioctl request.
+ */
+static long xe_eu_stall_stream_ioctl(struct file *file,
+				     unsigned int cmd,
+				     unsigned long arg)
+{
+	switch (cmd) {
+	case DRM_XE_OBSERVATION_IOCTL_ENABLE:
+		return 0;
+	case DRM_XE_OBSERVATION_IOCTL_DISABLE:
+		return 0;
+	}
+
+	return -EINVAL;
+}
+
+/**
+ * xe_eu_stall_stream_close - handles userspace close() of a EU stall data
+ *			      stream file.
+ * @inode: anonymous inode associated with file
+ * @file: An xe EU stall data stream file
+ *
+ * Cleans up any resources associated with an open EU stall data stream file.
+ */
+static int xe_eu_stall_stream_close(struct inode *inode, struct file *file)
+{
+	return 0;
+}
+
+static const struct file_operations fops_eu_stall = {
+	.owner		= THIS_MODULE,
+	.llseek		= noop_llseek,
+	.release	= xe_eu_stall_stream_close,
+	.poll		= xe_eu_stall_stream_poll,
+	.read		= xe_eu_stall_stream_read,
+	.unlocked_ioctl = xe_eu_stall_stream_ioctl,
+	.compat_ioctl   = xe_eu_stall_stream_ioctl,
+};
+
+static inline bool has_eu_stall_sampling_support(struct xe_device *xe)
+{
+	return false;
+}
+
+/**
+ * xe_eu_stall_stream_open - Open a xe EU stall data stream fd
+ *
+ * @dev: DRM device pointer
+ * @data: pointer to first struct @drm_xe_ext_set_property in
+ *	  the chain of input properties from the user space.
+ * @file: DRM file pointer
+ *
+ * This function opens a EU stall data stream with input properties from
+ * the user space.
+ *
+ * Returns: EU stall data stream fd on success or a negative error code.
+ */
+int xe_eu_stall_stream_open(struct drm_device *dev,
+			    u64 data,
+			    struct drm_file *file)
+{
+	struct xe_device *xe = to_xe_device(dev);
+	struct eu_stall_open_properties props;
+	int ret, stream_fd;
+
+	memset(&props, 0, sizeof(struct eu_stall_open_properties));
+
+	ret = xe_eu_stall_user_extensions(xe, data, &props);
+	if (ret)
+		return ret;
+
+	if (!props.gt) {
+		drm_dbg(&xe->drm, "GT ID not provided for EU stall sampling\n");
+		return -EINVAL;
+	}
+
+	if (xe_observation_paranoid && !perfmon_capable()) {
+		xe_gt_dbg(props.gt, "Insufficient privileges for EU stall monitoring\n");
+		return -EACCES;
+	}
+
+	if (!has_eu_stall_sampling_support(xe)) {
+		xe_gt_dbg(props.gt, "EU stall monitoring is not supported on this platform\n");
+		return -EPERM;
+	}
+	stream_fd = anon_inode_getfd("[xe_eu_stall]", &fops_eu_stall,
+				     NULL, 0);
+	if (stream_fd < 0)
+		xe_gt_dbg(props.gt, "EU stall inode get fd failed : %d\n", stream_fd);
+
+	return stream_fd;
+}
diff --git a/drivers/gpu/drm/xe/xe_eu_stall.h b/drivers/gpu/drm/xe/xe_eu_stall.h
new file mode 100644
index 000000000000..70fc89480df2
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_eu_stall.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+#ifndef __XE_EU_STALL_H__
+#define __XE_EU_STALL_H__
+
+int xe_eu_stall_stream_open(struct drm_device *dev,
+			    u64 data,
+			    struct drm_file *file);
+#endif
diff --git a/drivers/gpu/drm/xe/xe_observation.c b/drivers/gpu/drm/xe/xe_observation.c
index 8ec1b84cbb9e..cca661de60ac 100644
--- a/drivers/gpu/drm/xe/xe_observation.c
+++ b/drivers/gpu/drm/xe/xe_observation.c
@@ -9,6 +9,7 @@
 #include <uapi/drm/xe_drm.h>
 
 #include "xe_oa.h"
+#include "xe_eu_stall.h"
 #include "xe_observation.h"
 
 u32 xe_observation_paranoid = true;
@@ -29,6 +30,17 @@ static int xe_oa_ioctl(struct drm_device *dev, struct drm_xe_observation_param *
 	}
 }
 
+static int xe_eu_stall_ioctl(struct drm_device *dev, struct drm_xe_observation_param *arg,
+			     struct drm_file *file)
+{
+	switch (arg->observation_op) {
+	case DRM_XE_OBSERVATION_OP_STREAM_OPEN:
+		return xe_eu_stall_stream_open(dev, arg->param, file);
+	default:
+		return -EINVAL;
+	}
+}
+
 /**
  * xe_observation_ioctl - The top level observation layer ioctl
  * @dev: @drm_device
@@ -51,6 +63,8 @@ int xe_observation_ioctl(struct drm_device *dev, void *data, struct drm_file *fi
 	switch (arg->observation_type) {
 	case DRM_XE_OBSERVATION_TYPE_OA:
 		return xe_oa_ioctl(dev, arg, file);
+	case DRM_XE_OBSERVATION_TYPE_EU_STALL:
+		return xe_eu_stall_ioctl(dev, arg, file);
 	default:
 		return -EINVAL;
 	}
diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
index 4a8a4a63e99c..80aaa5b50c8a 100644
--- a/include/uapi/drm/xe_drm.h
+++ b/include/uapi/drm/xe_drm.h
@@ -1397,6 +1397,8 @@ struct drm_xe_wait_user_fence {
 enum drm_xe_observation_type {
 	/** @DRM_XE_OBSERVATION_TYPE_OA: OA observation stream type */
 	DRM_XE_OBSERVATION_TYPE_OA,
+	/** @DRM_XE_OBSERVATION_TYPE_EU_STALL: EU stall sampling observation stream type */
+	DRM_XE_OBSERVATION_TYPE_EU_STALL,
 };
 
 /**
@@ -1713,6 +1715,43 @@ struct drm_xe_oa_stream_info {
 	__u64 reserved[3];
 };
 
+/**
+ * enum drm_xe_eu_stall_property_id - EU stall sampling input property ids.
+ *
+ * These properties are passed to the driver at open as a chain of
+ * @drm_xe_ext_set_property structures with @property set to these
+ * properties' enums and @value set to the corresponding values of these
+ * properties. @drm_xe_user_extension base.name should be set to
+ * @DRM_XE_EU_STALL_EXTENSION_SET_PROPERTY.
+ *
+ * With the file descriptor obtained from open, user space must enable
+ * the EU stall stream fd with @DRM_XE_OBSERVATION_IOCTL_ENABLE before
+ * calling read.
+ */
+enum drm_xe_eu_stall_property_id {
+#define DRM_XE_EU_STALL_EXTENSION_SET_PROPERTY		0
+	/**
+	 * @DRM_XE_EU_STALL_PROP_SAMPLE_RATE: Sampling rate
+	 * in multiples of 251 cycles. Valid values are 1 to 7.
+	 * If the value is 1, sampling interval is 251 cycles.
+	 * If the value is 7, sampling interval is 7 x 251 cycles.
+	 */
+	DRM_XE_EU_STALL_PROP_SAMPLE_RATE = 1,
+
+	/**
+	 * @DRM_XE_EU_STALL_PROP_EVENT_REPORT_COUNT: Minimum number of
+	 * EU stall data rows to be present in the kernel buffer for
+	 * poll() to set POLLIN (data present).
+	 */
+	DRM_XE_EU_STALL_PROP_EVENT_REPORT_COUNT,
+
+	/**
+	 * @DRM_XE_EU_STALL_PROP_GT_ID: GT ID of the GT on which
+	 * EU stall data will be captured.
+	 */
+	DRM_XE_EU_STALL_PROP_GT_ID,
+};
+
 #if defined(__cplusplus)
 }
 #endif
-- 
2.45.1

[PATCH v5 3/7] drm/xe/eustall: Implement EU stall sampling APIs for Xe_HPC

[Harish Chegondi]

Implement EU stall sampling APIs introduced in the previous patch for
Xe_HPC (PVC). Add register definitions and the code that accesses these
registers to the APIs.

Add initialization and clean up functions and their implementations,
EU stall enable and disable functions, poll() and read() implementations.

A timer thread periodically polls the EU stall data buffer write pointer
registers to look for any new data and caches the write pointer. The read
function compares the cached read and write pointers and copies any new
data to the user space.

Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_eu_stall_regs.h |  29 +
 drivers/gpu/drm/xe/xe_eu_stall.c           | 748 ++++++++++++++++++++-
 drivers/gpu/drm/xe/xe_eu_stall.h           |  43 ++
 drivers/gpu/drm/xe/xe_gt.c                 |   6 +
 drivers/gpu/drm/xe/xe_gt_types.h           |   3 +
 drivers/gpu/drm/xe/xe_trace.h              |  33 +
 6 files changed, 837 insertions(+), 25 deletions(-)
 create mode 100644 drivers/gpu/drm/xe/regs/xe_eu_stall_regs.h

diff --git a/drivers/gpu/drm/xe/regs/xe_eu_stall_regs.h b/drivers/gpu/drm/xe/regs/xe_eu_stall_regs.h
new file mode 100644
index 000000000000..2b742890b283
--- /dev/null
+++ b/drivers/gpu/drm/xe/regs/xe_eu_stall_regs.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+#ifndef _XE_EU_STALL_REGS_H_
+#define _XE_EU_STALL_REGS_H_
+
+#include "regs/xe_reg_defs.h"
+
+#define XEHPC_EUSTALL_BASE			XE_REG_MCR(0xe520)
+#define   XEHPC_EUSTALL_BASE_BUF_ADDR		REG_GENMASK(31, 6)
+#define   XEHPC_EUSTALL_BASE_XECORE_BUF_SZ	REG_GENMASK(5, 3)
+#define   XEHPC_EUSTALL_BASE_ENABLE_SAMPLING	REG_BIT(1)
+
+#define XEHPC_EUSTALL_BASE_UPPER		XE_REG_MCR(0xe524)
+
+#define XEHPC_EUSTALL_REPORT			XE_REG_MCR(0xe528, XE_REG_OPTION_MASKED)
+#define   XEHPC_EUSTALL_REPORT_WRITE_PTR_MASK	REG_GENMASK(15, 2)
+#define   XEHPC_EUSTALL_REPORT_OVERFLOW_DROP	REG_BIT(1)
+
+#define XEHPC_EUSTALL_REPORT1			XE_REG_MCR(0xe52c, XE_REG_OPTION_MASKED)
+#define   XEHPC_EUSTALL_REPORT1_READ_PTR_MASK	REG_GENMASK(15, 2)
+
+#define XEHPC_EUSTALL_CTRL			XE_REG_MCR(0xe53c, XE_REG_OPTION_MASKED)
+#define   EUSTALL_MOCS				REG_GENMASK(9, 3)
+#define   EUSTALL_SAMPLE_RATE			REG_GENMASK(2, 0)
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_eu_stall.c b/drivers/gpu/drm/xe/xe_eu_stall.c
index e9209fc0d917..5c69f68acb98 100644
--- a/drivers/gpu/drm/xe/xe_eu_stall.c
+++ b/drivers/gpu/drm/xe/xe_eu_stall.c
@@ -8,15 +8,27 @@
 #include <linux/poll.h>
 #include <linux/fs.h>
 
+#include <drm/drm_drv.h>
 #include <uapi/drm/xe_drm.h>
 
+#include "xe_bo.h"
+#include "xe_pm.h"
+#include "xe_trace.h"
 #include "xe_macros.h"
 #include "xe_device.h"
+#include "xe_gt_mcr.h"
 #include "xe_eu_stall.h"
 #include "xe_gt_printk.h"
+#include "xe_force_wake.h"
 #include "xe_gt_topology.h"
 #include "xe_observation.h"
 
+#include "regs/xe_gt_regs.h"
+#include "regs/xe_eu_stall_regs.h"
+
+#define POLL_FREQUENCY_HZ 100
+#define POLL_PERIOD_NS (NSEC_PER_SEC / POLL_FREQUENCY_HZ)
+
 /**
  * struct eu_stall_open_properties - EU stall sampling properties received
  *				     from user space at open.
@@ -31,6 +43,48 @@ struct eu_stall_open_properties {
 	struct xe_gt *gt;
 };
 
+/**
+ * struct drm_xe_eu_stall_data_pvc - EU stall data format for PVC
+ *
+ * Bits		Field
+ * 0  to 28	IP (addr)
+ * 29 to 36	active count
+ * 37 to 44	other count
+ * 45 to 52	control count
+ * 53 to 60	pipestall count
+ * 61 to 68	send count
+ * 69 to 76	dist_acc count
+ * 77 to 84	sbid count
+ * 85 to 92	sync count
+ * 93 to 100	inst_fetch count
+ */
+struct drm_xe_eu_stall_data_pvc {
+	__u64 ip_addr:29;
+	__u64 active_count:8;
+	__u64 other_count:8;
+	__u64 control_count:8;
+	__u64 pipestall_count:8;
+	__u64 send_count:8;
+	__u64 dist_acc_count:8;
+	__u64 sbid_count:8;
+	__u64 sync_count:8;
+	__u64 inst_fetch_count:8;
+	__u64 unused_bits:27;
+	__u64 unused[6];
+} __packed;
+
+static unsigned long
+xe_eu_stall_data_record_size(struct xe_device *xe)
+{
+	enum xe_platform platform = xe->info.platform;
+	unsigned long record_size = 0;
+
+	if (platform == XE_PVC)
+		record_size = sizeof(struct drm_xe_eu_stall_data_pvc);
+
+	return record_size;
+}
+
 /**
  * num_data_rows - Return the number of EU stall data rows of 64B each
  *		   for a given data size.
@@ -43,6 +97,36 @@ num_data_rows(u32 data_size)
 	return (data_size >> 6);
 }
 
+/**
+ * xe_eu_stall_init() - Allocate and initialize GT level EU stall data
+ *			structure xe_eu_stall_gt within struct xe_gt.
+ *
+ * @gt: GT being initialized.
+ *
+ * Returns: zero on success or a negative error code.
+ */
+int xe_eu_stall_init(struct xe_gt *gt)
+{
+	gt->eu_stall = kzalloc(sizeof(*gt->eu_stall), GFP_KERNEL);
+	if (!gt->eu_stall)
+		return -ENOMEM;
+
+	mutex_init(&gt->eu_stall->lock);
+	return 0;
+}
+
+/**
+ * xe_eu_stall_fini() - Clean up the GT level EU stall data
+ *			structure xe_eu_stall_gt within struct xe_gt.
+ *
+ * @gt: GT being cleaned up.
+ */
+void xe_eu_stall_fini(struct xe_gt *gt)
+{
+	mutex_destroy(&gt->eu_stall->lock);
+	kfree(gt->eu_stall);
+}
+
 static int set_prop_eu_stall_sampling_rate(struct xe_device *xe, u64 value,
 					   struct eu_stall_open_properties *props)
 {
@@ -143,6 +227,235 @@ static int xe_eu_stall_user_extensions(struct xe_device *xe, u64 extension,
 	return 0;
 }
 
+/**
+ * buf_data_size - Calculate the number of bytes in a circular buffer
+ *		   given the read and write pointers and the size of
+ *		   the buffer.
+ *
+ * @buf_size: Size of the circular buffer
+ * @read_ptr: Read pointer with an additional overflow bit
+ * @write_ptr: Write pointer with an additional overflow bit
+ *
+ * Since the read and write pointers have an additional overflow bit,
+ * this function calculates the offsets from the pointers and use the
+ * offsets to calculate the data size in the buffer.
+ *
+ * Returns: number of bytes of data in the buffer
+ */
+static u32
+buf_data_size(size_t buf_size, u32 read_ptr, u32 write_ptr)
+{
+	u32 read_offset, write_offset, size = 0;
+
+	read_offset = read_ptr & (buf_size - 1);
+	write_offset = write_ptr & (buf_size - 1);
+
+	if (write_offset > read_offset)
+		size = write_offset - read_offset;
+	else
+		size = buf_size - read_offset + write_offset;
+
+	return size;
+}
+
+/**
+ * eu_stall_data_buf_check - check for EU stall data in the buffer
+ *
+ * @stream: xe EU stall data stream instance
+ *
+ * Returns: true if the EU stall buffer contains minimum stall data as
+ *	    specified by the event report count, else false.
+ */
+static bool
+eu_stall_data_buf_check(struct xe_eu_stall_data_stream *stream)
+{
+	u32 read_ptr, write_ptr_reg, write_ptr, total_data = 0;
+	u32 buf_size = stream->per_xecore_buf_size;
+	struct xe_gt *gt = stream->gt;
+	struct per_xecore_buf *xecore_buf;
+	bool min_data_present;
+	u16 group, instance;
+	unsigned int xecore;
+
+	min_data_present = false;
+	for_each_dss_steering(xecore, gt, group, instance) {
+		xecore_buf = &stream->xecore_buf[xecore];
+		mutex_lock(&xecore_buf->lock);
+		read_ptr = xecore_buf->read;
+		write_ptr_reg = xe_gt_mcr_unicast_read(gt, XEHPC_EUSTALL_REPORT,
+						       group, instance);
+		write_ptr = REG_FIELD_GET(XEHPC_EUSTALL_REPORT_WRITE_PTR_MASK, write_ptr_reg);
+		write_ptr <<= 6;
+		write_ptr &= ((buf_size << 1) - 1);
+		if (write_ptr != read_ptr && !min_data_present) {
+			total_data += buf_data_size(buf_size, read_ptr, write_ptr);
+			/*
+			 * Check if there are at least minimum number of stall data
+			 * rows for poll() to indicate that the data is present.
+			 * Each stall data row is 64B (cacheline size).
+			 */
+			if (num_data_rows(total_data) >= stream->event_report_count)
+				min_data_present = true;
+		}
+		if (write_ptr_reg & XEHPC_EUSTALL_REPORT_OVERFLOW_DROP)
+			set_bit(xecore, stream->data_drop.mask);
+		xecore_buf->write = write_ptr;
+		mutex_unlock(&xecore_buf->lock);
+	}
+	return min_data_present;
+}
+
+static void
+clear_dropped_eviction_line_bit(struct xe_gt *gt, u16 group, u16 instance)
+{
+	u32 write_ptr_reg;
+
+	/* On PVC, the overflow bit has to be cleared by writing 1 to it. */
+	write_ptr_reg = _MASKED_BIT_ENABLE(XEHPC_EUSTALL_REPORT_OVERFLOW_DROP);
+
+	xe_gt_mcr_unicast_write(gt, XEHPC_EUSTALL_REPORT, write_ptr_reg, group, instance);
+}
+
+static int
+xe_eu_stall_data_buf_read(struct xe_eu_stall_data_stream *stream,
+			  char __user *buf, size_t count,
+			  size_t *total_size, struct xe_gt *gt,
+			  u16 group, u16 instance, unsigned int xecore)
+{
+	u32 read_ptr_reg, read_ptr, write_ptr;
+	u8 *xecore_start_vaddr, *read_vaddr;
+	struct xe_device *xe = gt_to_xe(gt);
+	struct per_xecore_buf *xecore_buf;
+	size_t size, copy_size, buf_size;
+	u32 read_offset, write_offset;
+	unsigned long record_size;
+
+	/* Hardware increments the read and write pointers such that they can
+	 * overflow into one additional bit. For example, a 256KB size buffer
+	 * offset pointer needs 18 bits. But HW uses 19 bits for the read and
+	 * write pointers. This technique avoids wasting a slot in the buffer.
+	 * Read and write offsets are calculated from the pointers in order to
+	 * check if the write pointer has wrapped around the array.
+	 */
+	xecore_buf = &stream->xecore_buf[xecore];
+	mutex_lock(&xecore_buf->lock);
+	xecore_start_vaddr = xecore_buf->vaddr;
+	read_ptr = xecore_buf->read;
+	write_ptr = xecore_buf->write;
+	buf_size = stream->per_xecore_buf_size;
+	read_offset = read_ptr & (buf_size - 1);
+	write_offset = write_ptr & (buf_size - 1);
+
+	if (write_ptr == read_ptr) {
+		mutex_unlock(&xecore_buf->lock);
+		return 0;
+	}
+
+	trace_xe_eu_stall_data_read(group, instance, read_ptr, write_ptr,
+				    read_offset, write_offset, *total_size);
+	/* If write pointer offset is less than the read pointer offset,
+	 * it means, write pointer has wrapped around the array.
+	 */
+	if (write_offset > read_offset)
+		size = write_offset - read_offset;
+	else
+		size = buf_size - read_offset + write_offset;
+
+	/* Read only the data that the user space buffer can accommodate */
+	if ((*total_size + size) > count) {
+		record_size = xe_eu_stall_data_record_size(xe);
+		size = count - *total_size;
+		size = (size / record_size) * record_size;
+	}
+
+	if (size == 0) {
+		mutex_unlock(&xecore_buf->lock);
+		return 0;
+	}
+
+	read_vaddr = xecore_start_vaddr + read_offset;
+
+	if (write_offset > read_offset) {
+		if (copy_to_user((buf + *total_size), read_vaddr, size)) {
+			mutex_unlock(&xecore_buf->lock);
+			return -EFAULT;
+		}
+	} else {
+		if (size >= (buf_size - read_offset))
+			copy_size = buf_size - read_offset;
+		else
+			copy_size = size;
+		if (copy_to_user((buf + *total_size), read_vaddr, copy_size)) {
+			mutex_unlock(&xecore_buf->lock);
+			return -EFAULT;
+		}
+		if (copy_to_user((buf + *total_size), xecore_start_vaddr, size - copy_size)) {
+			mutex_unlock(&xecore_buf->lock);
+			return -EFAULT;
+		}
+	}
+
+	*total_size += size;
+	read_ptr += size;
+
+	/* Read pointer can overflow into one additional bit */
+	read_ptr &= ((buf_size << 1) - 1);
+	read_ptr_reg = REG_FIELD_PREP(XEHPC_EUSTALL_REPORT1_READ_PTR_MASK, (read_ptr >> 6));
+	read_ptr_reg &= XEHPC_EUSTALL_REPORT1_READ_PTR_MASK;
+	read_ptr_reg = _MASKED_FIELD(XEHPC_EUSTALL_REPORT1_READ_PTR_MASK, read_ptr_reg);
+	xe_gt_mcr_unicast_write(gt, XEHPC_EUSTALL_REPORT1, read_ptr_reg, group, instance);
+	if (test_bit(xecore, stream->data_drop.mask)) {
+		clear_dropped_eviction_line_bit(gt, group, instance);
+		clear_bit(xecore, stream->data_drop.mask);
+	}
+	xecore_buf->read = read_ptr;
+	mutex_unlock(&xecore_buf->lock);
+	trace_xe_eu_stall_data_read(group, instance, read_ptr, write_ptr,
+				    read_offset, write_offset, *total_size);
+	return 0;
+}
+
+/**
+ * xe_eu_stall_stream_read_locked - copy EU stall counters data from the
+ *				    per xecore buffers to the userspace buffer
+ * @stream: A stream opened for EU stall count metrics
+ * @buf: destination buffer given by userspace
+ * @count: the number of bytes userspace wants to read
+ * @ppos: (inout) file seek position (unused)
+ *
+ * Returns: Number of bytes copied or a negative error code
+ * If we've successfully copied any data then reporting that takes
+ * precedence over any internal error status, so the data isn't lost.
+ */
+static ssize_t
+xe_eu_stall_stream_read_locked(struct xe_eu_stall_data_stream *stream,
+			       struct file *file, char __user *buf,
+			       size_t count, loff_t *ppos)
+{
+	struct xe_gt *gt = stream->gt;
+	size_t total_size = 0;
+	u16 group, instance;
+	unsigned int xecore;
+	int ret = 0;
+
+	if (count == 0)
+		return -EINVAL;
+
+	for_each_dss_steering(xecore, gt, group, instance) {
+		ret = xe_eu_stall_data_buf_read(stream, buf, count, &total_size,
+						gt, group, instance, xecore);
+		if (ret || count == total_size)
+			goto exit;
+	}
+exit:
+	if (total_size)
+		return total_size;
+	else if (ret)
+		return ret;
+	else
+		return -EAGAIN;
+}
+
 /**
  * xe_eu_stall_stream_read - handles userspace read() of a EU stall data stream fd.
  *
@@ -159,11 +472,259 @@ static int xe_eu_stall_user_extensions(struct xe_device *xe, u64 extension,
 static ssize_t xe_eu_stall_stream_read(struct file *file, char __user *buf,
 				       size_t count, loff_t *ppos)
 {
-	ssize_t ret = 0;
+	struct xe_eu_stall_data_stream *stream = file->private_data;
+	struct xe_gt *gt = stream->gt;
+	ssize_t ret;
+
+	if (!stream->enabled) {
+		xe_gt_dbg(gt, "EU stall data stream not enabled to read\n");
+		return -EINVAL;
+	}
+
+	if (!(file->f_flags & O_NONBLOCK)) {
+		do {
+			if (!stream->pollin) {
+				ret = wait_event_interruptible(stream->poll_wq, stream->pollin);
+				if (ret)
+					return -EINTR;
+			}
+
+			mutex_lock(&gt->eu_stall->lock);
+			ret = xe_eu_stall_stream_read_locked(stream, file, buf, count, ppos);
+			mutex_unlock(&gt->eu_stall->lock);
+		} while (ret == -EAGAIN);
+	} else {
+		mutex_lock(&gt->eu_stall->lock);
+		ret = xe_eu_stall_stream_read_locked(stream, file, buf, count, ppos);
+		mutex_unlock(&gt->eu_stall->lock);
+	}
+
+	stream->pollin = false;
 
 	return ret;
 }
 
+static void
+free_eu_stall_data_buf(struct xe_eu_stall_data_stream *stream)
+{
+	if (stream->bo) {
+		xe_bo_unpin_map_no_vm(stream->bo);
+		stream->bo = NULL;
+	}
+	destroy_workqueue(stream->buf_check_wq);
+}
+
+static int alloc_eu_stall_data_buf(struct xe_eu_stall_data_stream *stream,
+				   u16 num_xecore)
+{
+	struct xe_tile *tile = stream->gt->tile;
+	struct xe_bo *bo;
+	u32 size;
+
+	size = stream->per_xecore_buf_size * num_xecore;
+
+	bo = xe_bo_create_pin_map(tile->xe, tile, NULL,
+				  size, ttm_bo_type_kernel,
+				  XE_BO_FLAG_SYSTEM |
+				  XE_BO_FLAG_GGTT);
+	if (IS_ERR(bo))
+		return PTR_ERR(bo);
+
+	stream->bo = bo;
+
+	return 0;
+}
+
+static u32
+gen_eustall_base(struct xe_eu_stall_data_stream *stream, bool enable)
+{
+	u32 val = xe_bo_ggtt_addr(stream->bo);
+	u32 sz;
+
+	XE_WARN_ON(!IS_ALIGNED(val, 64));
+
+	switch (stream->per_xecore_buf_size) {
+	case SZ_128K:
+		sz = 0;
+		break;
+	case SZ_256K:
+		sz = 1;
+		break;
+	case SZ_512K:
+		sz = 2;
+		break;
+	default:
+		xe_gt_warn(stream->gt, "Missing case per XeCore buffer size == %lu)\n",
+			   (long)(stream->per_xecore_buf_size));
+		sz = 2;
+	}
+
+	val |= REG_FIELD_PREP(XEHPC_EUSTALL_BASE_XECORE_BUF_SZ, sz);
+	if (enable)
+		val |= XEHPC_EUSTALL_BASE_ENABLE_SAMPLING;
+
+	return val;
+}
+
+static void
+xe_eu_stall_stream_enable(struct xe_eu_stall_data_stream *stream)
+{
+	struct xe_gt *gt = stream->gt;
+	u32 reg_value;
+
+	/* Take runtime pm ref and forcewake to disable RC6 */
+	xe_pm_runtime_get(gt_to_xe(gt));
+	XE_WARN_ON(xe_force_wake_get(gt_to_fw(gt), XE_FW_RENDER));
+
+	reg_value = gen_eustall_base(stream, true);
+	xe_gt_mcr_multicast_write(gt, XEHPC_EUSTALL_BASE, reg_value);
+}
+
+static void
+xe_eu_stall_stream_disable(struct xe_eu_stall_data_stream *stream)
+{
+	struct xe_gt *gt = stream->gt;
+	u16 group, instance;
+	unsigned int xecore;
+	u32 reg_value;
+
+	/*
+	 * Before disabling EU stall sampling, check if any of the
+	 * XEHPC_EUSTALL_REPORT registers have the drop bit set. If set,
+	 * clear the bit. If the user space application reads all the
+	 * stall data, the drop bit would be cleared during the read.
+	 * But if there is any unread data and the drop bit is set for
+	 * any subslice, the drop bit would continue to be set even
+	 * after disabling EU stall sampling and may cause erroneous
+	 * stall data in the subsequent stall data sampling run.
+	 */
+	for_each_dss_steering(xecore, gt, group, instance) {
+		reg_value = xe_gt_mcr_unicast_read(gt, XEHPC_EUSTALL_REPORT,
+						   group, instance);
+		if (reg_value & XEHPC_EUSTALL_REPORT_OVERFLOW_DROP)
+			clear_dropped_eviction_line_bit(gt, group, instance);
+	}
+	reg_value = gen_eustall_base(stream, false);
+	xe_gt_mcr_multicast_write(gt, XEHPC_EUSTALL_BASE, reg_value);
+
+	xe_force_wake_put(gt_to_fw(gt), XE_FW_RENDER);
+	xe_pm_runtime_put(gt_to_xe(gt));
+}
+
+static void eu_stall_buf_check_work_fn(struct work_struct *work)
+{
+	struct xe_eu_stall_data_stream *stream =
+		container_of(work, typeof(*stream), buf_check_work);
+
+	if (eu_stall_data_buf_check(stream)) {
+		stream->pollin = true;
+		wake_up(&stream->poll_wq);
+	}
+}
+
+static enum
+hrtimer_restart eu_stall_poll_check_timer_cb(struct hrtimer *hrtimer)
+{
+	struct xe_eu_stall_data_stream *stream =
+		container_of(hrtimer, typeof(*stream), poll_check_timer);
+
+	queue_work(stream->buf_check_wq, &stream->buf_check_work);
+	hrtimer_forward_now(hrtimer, ns_to_ktime(stream->poll_period));
+
+	return HRTIMER_RESTART;
+}
+
+static int xe_eu_stall_stream_init(struct xe_eu_stall_data_stream *stream,
+				   struct eu_stall_open_properties *props)
+{
+	u32 write_ptr_reg, write_ptr, read_ptr_reg;
+	u32 vaddr_offset, base_reg_value;
+	struct xe_gt *gt = stream->gt;
+	struct per_xecore_buf *xecore_buf;
+	u16 group, instance, num_xecore;
+	xe_dss_mask_t all_xecore;
+	int ret, xecore;
+
+	init_waitqueue_head(&stream->poll_wq);
+	INIT_WORK(&stream->buf_check_work, eu_stall_buf_check_work_fn);
+	stream->buf_check_wq = alloc_ordered_workqueue("xe_eustall", 0);
+	if (!stream->buf_check_wq)
+		return -ENOMEM;
+	hrtimer_init(&stream->poll_check_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+	stream->poll_check_timer.function = eu_stall_poll_check_timer_cb;
+	stream->event_report_count = props->event_report_count;
+	stream->per_xecore_buf_size = SZ_512K;
+	stream->poll_period = POLL_PERIOD_NS;
+
+	bitmap_or(all_xecore, gt->fuse_topo.g_dss_mask, gt->fuse_topo.c_dss_mask,
+		  XE_MAX_DSS_FUSE_BITS);
+	/*
+	 * Enabled subslices can be discontiguous. Find the maximum number of subslices
+	 * that are enabled.
+	 */
+	num_xecore = xe_gt_topology_mask_last_dss(all_xecore) + 1;
+
+	ret = alloc_eu_stall_data_buf(stream, num_xecore);
+	if (ret)
+		return ret;
+
+	stream->xecore_buf = kcalloc(num_xecore, sizeof(*stream->xecore_buf), GFP_KERNEL);
+	if (!stream->xecore_buf)
+		return -ENOMEM;
+
+	bitmap_zero(stream->data_drop.mask, XE_MAX_DSS_FUSE_BITS);
+
+	xe_pm_runtime_get(gt_to_xe(gt));
+	XE_WARN_ON(xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL));
+
+	base_reg_value = gen_eustall_base(stream, false);
+	xe_gt_mcr_multicast_write(gt, XEHPC_EUSTALL_BASE, base_reg_value);
+	/* GGTT addresses can never be > 32 bits */
+	xe_gt_mcr_multicast_write(gt, XEHPC_EUSTALL_BASE_UPPER, 0);
+	base_reg_value = _MASKED_FIELD(EUSTALL_MOCS | EUSTALL_SAMPLE_RATE,
+				       REG_FIELD_PREP(EUSTALL_MOCS, gt->mocs.uc_index << 1) |
+				       REG_FIELD_PREP(EUSTALL_SAMPLE_RATE,
+						      props->eu_stall_sampling_rate));
+	xe_gt_mcr_multicast_write(gt, XEHPC_EUSTALL_CTRL, base_reg_value);
+
+	for_each_dss_steering(xecore, gt, group, instance) {
+		write_ptr_reg = xe_gt_mcr_unicast_read(gt, XEHPC_EUSTALL_REPORT,
+						       group, instance);
+		write_ptr = REG_FIELD_GET(XEHPC_EUSTALL_REPORT_WRITE_PTR_MASK, write_ptr_reg);
+		write_ptr <<= 6;
+		write_ptr &= ((stream->per_xecore_buf_size << 1) - 1);
+		read_ptr_reg = write_ptr >> 6;
+		read_ptr_reg = REG_FIELD_PREP(XEHPC_EUSTALL_REPORT1_READ_PTR_MASK, write_ptr);
+		read_ptr_reg &= XEHPC_EUSTALL_REPORT1_READ_PTR_MASK;
+		read_ptr_reg = _MASKED_FIELD(XEHPC_EUSTALL_REPORT1_READ_PTR_MASK, read_ptr_reg);
+		xe_gt_mcr_unicast_write(gt, XEHPC_EUSTALL_REPORT1,
+					read_ptr_reg, group, instance);
+		xecore_buf = &stream->xecore_buf[xecore];
+		vaddr_offset = xecore * stream->per_xecore_buf_size;
+		xecore_buf->vaddr = stream->bo->vmap.vaddr + vaddr_offset;
+		xecore_buf->write = write_ptr;
+		xecore_buf->read = write_ptr;
+		mutex_init(&xecore_buf->lock);
+	}
+	xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL);
+	xe_pm_runtime_put(gt_to_xe(gt));
+	return 0;
+}
+
+static __poll_t
+xe_eu_stall_stream_poll_locked(struct xe_eu_stall_data_stream *stream,
+			       struct file *file, poll_table *wait)
+{
+	__poll_t events = 0;
+
+	poll_wait(file, &stream->poll_wq, wait);
+
+	if (stream->pollin)
+		events |= EPOLLIN;
+
+	return events;
+}
+
 /**
  * xe_eu_stall_stream_poll - handles userspace poll() of a EU stall data stream fd.
  *
@@ -175,11 +736,60 @@ static ssize_t xe_eu_stall_stream_read(struct file *file, char __user *buf,
 static __poll_t
 xe_eu_stall_stream_poll(struct file *file, poll_table *wait)
 {
-	__poll_t ret = 0;
+	struct xe_eu_stall_data_stream *stream = file->private_data;
+	struct xe_gt *gt = stream->gt;
+	__poll_t ret;
+
+	mutex_lock(&gt->eu_stall->lock);
+	ret = xe_eu_stall_stream_poll_locked(stream, file, wait);
+	mutex_unlock(&gt->eu_stall->lock);
 
 	return ret;
 }
 
+static void
+xe_eu_stall_enable_locked(struct xe_eu_stall_data_stream *stream)
+{
+	if (stream->enabled)
+		return;
+
+	stream->enabled = true;
+
+	xe_eu_stall_stream_enable(stream);
+	hrtimer_start(&stream->poll_check_timer,
+		      ns_to_ktime(stream->poll_period),
+		      HRTIMER_MODE_REL);
+}
+
+static void
+xe_eu_stall_disable_locked(struct xe_eu_stall_data_stream *stream)
+{
+	if (!stream->enabled)
+		return;
+
+	stream->enabled = false;
+
+	hrtimer_cancel(&stream->poll_check_timer);
+	flush_workqueue(stream->buf_check_wq);
+	xe_eu_stall_stream_disable(stream);
+}
+
+static long
+xe_eu_stall_stream_ioctl_locked(struct xe_eu_stall_data_stream *stream,
+				unsigned int cmd, unsigned long arg)
+{
+	switch (cmd) {
+	case DRM_XE_OBSERVATION_IOCTL_ENABLE:
+		xe_eu_stall_enable_locked(stream);
+		return 0;
+	case DRM_XE_OBSERVATION_IOCTL_DISABLE:
+		xe_eu_stall_disable_locked(stream);
+		return 0;
+	}
+
+	return -EINVAL;
+}
+
 /**
  * xe_eu_stall_stream_ioctl - support ioctl() of a xe EU stall data stream fd.
  *
@@ -194,14 +804,22 @@ static long xe_eu_stall_stream_ioctl(struct file *file,
 				     unsigned int cmd,
 				     unsigned long arg)
 {
-	switch (cmd) {
-	case DRM_XE_OBSERVATION_IOCTL_ENABLE:
-		return 0;
-	case DRM_XE_OBSERVATION_IOCTL_DISABLE:
-		return 0;
-	}
+	struct xe_eu_stall_data_stream *stream = file->private_data;
+	struct xe_gt *gt = stream->gt;
+	long ret;
 
-	return -EINVAL;
+	mutex_lock(&gt->eu_stall->lock);
+	ret = xe_eu_stall_stream_ioctl_locked(stream, cmd, arg);
+	mutex_unlock(&gt->eu_stall->lock);
+
+	return ret;
+}
+
+static void
+xe_eu_stall_stream_close_locked(struct xe_eu_stall_data_stream *stream)
+{
+	xe_eu_stall_disable_locked(stream);
+	free_eu_stall_data_buf(stream);
 }
 
 /**
@@ -214,6 +832,19 @@ static long xe_eu_stall_stream_ioctl(struct file *file,
  */
 static int xe_eu_stall_stream_close(struct inode *inode, struct file *file)
 {
+	struct xe_eu_stall_data_stream *stream = file->private_data;
+	struct xe_gt *gt = stream->gt;
+
+	mutex_lock(&gt->eu_stall->lock);
+	xe_eu_stall_stream_close_locked(stream);
+	kfree(stream->xecore_buf);
+	kfree(stream);
+	gt->eu_stall->stream = NULL;
+	mutex_unlock(&gt->eu_stall->lock);
+
+	/* Release the reference the EU stall stream kept on the driver */
+	drm_dev_put(&gt->tile->xe->drm);
+
 	return 0;
 }
 
@@ -229,7 +860,79 @@ static const struct file_operations fops_eu_stall = {
 
 static inline bool has_eu_stall_sampling_support(struct xe_device *xe)
 {
-	return false;
+	return ((xe->info.platform == XE_PVC) ? true : false);
+}
+
+/**
+ * xe_eu_stall_stream_open_locked - Open a EU stall data stream FD.
+ * @dev: drm device instance
+ * @props: individually validated u64 property value pairs
+ * @file: drm file
+ *
+ * Returns: zero on success or a negative error code.
+ */
+static int
+xe_eu_stall_stream_open_locked(struct drm_device *dev,
+			       struct eu_stall_open_properties *props,
+			       struct drm_file *file)
+{
+	struct xe_device *xe = to_xe_device(dev);
+	struct xe_eu_stall_data_stream *stream;
+	struct xe_gt *gt = props->gt;
+	unsigned long f_flags = 0;
+	int ret, stream_fd;
+
+	if (!has_eu_stall_sampling_support(xe)) {
+		xe_gt_dbg(gt, "EU stall monitoring is not supported on this platform\n");
+		return -EPERM;
+	}
+
+	if (xe_observation_paranoid && !perfmon_capable()) {
+		xe_gt_dbg(gt, "Insufficient privileges for EU stall monitoring\n");
+		return -EACCES;
+	}
+
+	/* Only one session can be active at any time */
+	if (gt->eu_stall->stream) {
+		xe_gt_dbg(gt, "EU stall sampling session already active\n");
+		return -EBUSY;
+	}
+
+	stream = kzalloc(sizeof(*stream), GFP_KERNEL);
+	if (!stream)
+		return -ENOMEM;
+
+	gt->eu_stall->stream = stream;
+	stream->gt = gt;
+
+	ret = xe_eu_stall_stream_init(stream, props);
+	if (ret) {
+		xe_gt_dbg(gt, "EU stall stream init failed : %d\n", ret);
+		goto err_alloc;
+	}
+
+	stream_fd = anon_inode_getfd("[xe_eu_stall]", &fops_eu_stall,
+				     stream, f_flags);
+	if (stream_fd < 0) {
+		ret = stream_fd;
+		xe_gt_dbg(gt, "EU stall inode get fd failed : %d\n", ret);
+		goto err_open;
+	}
+
+	/* Take a reference on the driver that will be kept with stream_fd
+	 * until its release.
+	 */
+	drm_dev_get(&gt->tile->xe->drm);
+
+	return stream_fd;
+
+err_open:
+	free_eu_stall_data_buf(stream);
+err_alloc:
+	gt->eu_stall->stream = NULL;
+	kfree(stream->xecore_buf);
+	kfree(stream);
+	return ret;
 }
 
 /**
@@ -251,10 +954,15 @@ int xe_eu_stall_stream_open(struct drm_device *dev,
 {
 	struct xe_device *xe = to_xe_device(dev);
 	struct eu_stall_open_properties props;
-	int ret, stream_fd;
+	int ret;
 
 	memset(&props, 0, sizeof(struct eu_stall_open_properties));
 
+	/* Set default values */
+	props.gt = NULL;
+	props.eu_stall_sampling_rate = 4;
+	props.event_report_count = 1;
+
 	ret = xe_eu_stall_user_extensions(xe, data, &props);
 	if (ret)
 		return ret;
@@ -264,19 +972,9 @@ int xe_eu_stall_stream_open(struct drm_device *dev,
 		return -EINVAL;
 	}
 
-	if (xe_observation_paranoid && !perfmon_capable()) {
-		xe_gt_dbg(props.gt, "Insufficient privileges for EU stall monitoring\n");
-		return -EACCES;
-	}
+	mutex_lock(&props.gt->eu_stall->lock);
+	ret = xe_eu_stall_stream_open_locked(dev, &props, file);
+	mutex_unlock(&props.gt->eu_stall->lock);
 
-	if (!has_eu_stall_sampling_support(xe)) {
-		xe_gt_dbg(props.gt, "EU stall monitoring is not supported on this platform\n");
-		return -EPERM;
-	}
-	stream_fd = anon_inode_getfd("[xe_eu_stall]", &fops_eu_stall,
-				     NULL, 0);
-	if (stream_fd < 0)
-		xe_gt_dbg(props.gt, "EU stall inode get fd failed : %d\n", stream_fd);
-
-	return stream_fd;
+	return ret;
 }
diff --git a/drivers/gpu/drm/xe/xe_eu_stall.h b/drivers/gpu/drm/xe/xe_eu_stall.h
index 70fc89480df2..00896812db41 100644
--- a/drivers/gpu/drm/xe/xe_eu_stall.h
+++ b/drivers/gpu/drm/xe/xe_eu_stall.h
@@ -6,6 +6,49 @@
 #ifndef __XE_EU_STALL_H__
 #define __XE_EU_STALL_H__
 
+#include "xe_gt_types.h"
+
+struct per_xecore_buf {
+	u8 *vaddr;
+	u32 write;
+	u32 read;
+	/* lock to protect read and write pointers */
+	struct mutex lock;
+};
+
+/**
+ * struct xe_eu_stall_data_stream - state of EU stall data stream FD
+ */
+struct xe_eu_stall_data_stream {
+	bool pollin;
+	bool enabled;
+	u64 poll_period;
+	u32 event_report_count;
+	size_t per_xecore_buf_size;
+	wait_queue_head_t poll_wq;
+
+	struct xe_gt *gt;
+	struct xe_bo *bo;
+	struct per_xecore_buf *xecore_buf;
+	struct {
+		xe_dss_mask_t mask;
+	} data_drop;
+	struct hrtimer poll_check_timer;
+	struct work_struct buf_check_work;
+	struct workqueue_struct *buf_check_wq;
+};
+
+struct xe_eu_stall_gt {
+	/* Lock to protect stream */
+	struct mutex lock;
+
+	/* Execution Unit (EU) stall data stream */
+	struct xe_eu_stall_data_stream *stream;
+};
+
+int xe_eu_stall_init(struct xe_gt *gt);
+void xe_eu_stall_fini(struct xe_gt *gt);
+
 int xe_eu_stall_stream_open(struct drm_device *dev,
 			    u64 data,
 			    struct drm_file *file);
diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
index d6744be01a68..6e9598ddabd7 100644
--- a/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@ -59,6 +59,7 @@
 #include "xe_vm.h"
 #include "xe_wa.h"
 #include "xe_wopcm.h"
+#include "xe_eu_stall.h"
 
 static void gt_fini(struct drm_device *drm, void *arg)
 {
@@ -158,6 +159,7 @@ void xe_gt_remove(struct xe_gt *gt)
 		xe_hw_fence_irq_finish(&gt->fence_irq[i]);
 
 	xe_gt_disable_host_l2_vram(gt);
+	xe_eu_stall_fini(gt);
 }
 
 static void gt_reset_worker(struct work_struct *w);
@@ -622,6 +624,10 @@ int xe_gt_init(struct xe_gt *gt)
 
 	xe_gt_record_user_engines(gt);
 
+	err = xe_eu_stall_init(gt);
+	if (err)
+		return err;
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
index 6e66bf0e8b3f..833a1a67e9ae 100644
--- a/drivers/gpu/drm/xe/xe_gt_types.h
+++ b/drivers/gpu/drm/xe/xe_gt_types.h
@@ -430,6 +430,9 @@ struct xe_gt {
 
 	/** @oa: oa observation subsystem per gt info */
 	struct xe_oa_gt oa;
+
+	/** @eu_stall: EU stall counters subsystem per gt info */
+	struct xe_eu_stall_gt *eu_stall;
 };
 
 #endif
diff --git a/drivers/gpu/drm/xe/xe_trace.h b/drivers/gpu/drm/xe/xe_trace.h
index de682978c4bf..bcc34e47808a 100644
--- a/drivers/gpu/drm/xe/xe_trace.h
+++ b/drivers/gpu/drm/xe/xe_trace.h
@@ -424,6 +424,39 @@ DEFINE_EVENT(xe_pm_runtime, xe_pm_runtime_get_ioctl,
 	     TP_ARGS(xe, caller)
 );
 
+TRACE_EVENT(xe_eu_stall_data_read,
+	    TP_PROTO(u8 slice, u8 subslice,
+		     u32 read_ptr, u32 write_ptr,
+		     u32 read_offset, u32 write_offset,
+		     size_t total_size),
+	    TP_ARGS(slice, subslice, read_ptr, write_ptr,
+		    read_offset, write_offset, total_size),
+
+	    TP_STRUCT__entry(__field(u8, slice)
+			     __field(u8, subslice)
+			     __field(u32, read_ptr)
+			     __field(u32, write_ptr)
+			     __field(u32, read_offset)
+			     __field(u32, write_offset)
+			     __field(size_t, total_size)
+			     ),
+
+	    TP_fast_assign(__entry->slice = slice;
+			   __entry->subslice = subslice;
+			   __entry->read_ptr = read_ptr;
+			   __entry->write_ptr = write_ptr;
+			   __entry->read_offset = read_offset;
+			   __entry->write_offset = write_offset;
+			   __entry->total_size = total_size;
+			   ),
+
+	    TP_printk("slice:%u subslice:%u readptr:0x%x writeptr:0x%x read off:%u write off:%u size:%zu ",
+		      __entry->slice, __entry->subslice,
+		      __entry->read_ptr, __entry->write_ptr,
+		      __entry->read_offset, __entry->write_offset,
+		      __entry->total_size)
+);
+
 #endif
 
 /* This part must be outside protection */
-- 
2.45.1

[PATCH v5 4/7] drm/xe/eustall: Return -EIO error from read() if HW drops data

[Harish Chegondi]

If the user space doesn't read the EU stall data fast enough,
it is possible that the EU stall data buffer can get filled,
and if the hardware wants to write more data, it simply drops
data due to unavailable buffer space. In that case, hardware
sets a bit in a register. If the driver detects data drop,
the driver read() returns -EIO error to let the user space
know that HW has dropped data. The -EIO error is returned
even if there is EU stall data in the buffer. A subsequent
read by the user space returns the remaining EU stall data.

Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
---
 drivers/gpu/drm/xe/xe_eu_stall.c | 12 ++++++++++++
 drivers/gpu/drm/xe/xe_eu_stall.h |  1 +
 2 files changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_eu_stall.c b/drivers/gpu/drm/xe/xe_eu_stall.c
index 5c69f68acb98..96ac08cc7bf2 100644
--- a/drivers/gpu/drm/xe/xe_eu_stall.c
+++ b/drivers/gpu/drm/xe/xe_eu_stall.c
@@ -468,6 +468,7 @@ xe_eu_stall_stream_read_locked(struct xe_eu_stall_data_stream *stream,
  * before calling read().
  *
  * Returns: The number of bytes copied or a negative error code on failure.
+ *	    -EIO if HW drops any EU stall data when the buffer is full.
  */
 static ssize_t xe_eu_stall_stream_read(struct file *file, char __user *buf,
 				       size_t count, loff_t *ppos)
@@ -481,6 +482,16 @@ static ssize_t xe_eu_stall_stream_read(struct file *file, char __user *buf,
 		return -EINVAL;
 	}
 
+	if (bitmap_weight(stream->data_drop.mask, XE_MAX_DSS_FUSE_BITS)) {
+		if (!stream->data_drop.reported_to_user) {
+			stream->data_drop.reported_to_user = true;
+			xe_gt_dbg(gt, "EU stall data dropped in XeCores: %*pb\n",
+				  XE_MAX_DSS_FUSE_BITS, stream->data_drop.mask);
+			return -EIO;
+		}
+		stream->data_drop.reported_to_user = false;
+	}
+
 	if (!(file->f_flags & O_NONBLOCK)) {
 		do {
 			if (!stream->pollin) {
@@ -672,6 +683,7 @@ static int xe_eu_stall_stream_init(struct xe_eu_stall_data_stream *stream,
 	if (!stream->xecore_buf)
 		return -ENOMEM;
 
+	stream->data_drop.reported_to_user = false;
 	bitmap_zero(stream->data_drop.mask, XE_MAX_DSS_FUSE_BITS);
 
 	xe_pm_runtime_get(gt_to_xe(gt));
diff --git a/drivers/gpu/drm/xe/xe_eu_stall.h b/drivers/gpu/drm/xe/xe_eu_stall.h
index 00896812db41..d9482e1b522b 100644
--- a/drivers/gpu/drm/xe/xe_eu_stall.h
+++ b/drivers/gpu/drm/xe/xe_eu_stall.h
@@ -31,6 +31,7 @@ struct xe_eu_stall_data_stream {
 	struct xe_bo *bo;
 	struct per_xecore_buf *xecore_buf;
 	struct {
+		bool reported_to_user;
 		xe_dss_mask_t mask;
 	} data_drop;
 	struct hrtimer poll_check_timer;
-- 
2.45.1

[PATCH v5 5/7] drm/xe/eustall: Add EU stall sampling support for Xe2

[Harish Chegondi]

Add EU stall sampling support for Xe2 architecture GPUs - LNL and BMG.
EU stall data format for LNL and BMG is different from that of PVC.

Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
---
 drivers/gpu/drm/xe/xe_eu_stall.c | 52 ++++++++++++++++++++++++++++++--
 1 file changed, 49 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_eu_stall.c b/drivers/gpu/drm/xe/xe_eu_stall.c
index 96ac08cc7bf2..9169a31f620c 100644
--- a/drivers/gpu/drm/xe/xe_eu_stall.c
+++ b/drivers/gpu/drm/xe/xe_eu_stall.c
@@ -73,6 +73,42 @@ struct drm_xe_eu_stall_data_pvc {
 	__u64 unused[6];
 } __packed;
 
+/**
+ * struct drm_xe_eu_stall_data_xe2 - EU stall data format for LNL, BMG
+ *
+ * Bits		Field
+ * 0  to 28	IP (addr)
+ * 29 to 36	Tdr count
+ * 37 to 44	other count
+ * 45 to 52	control count
+ * 53 to 60	pipestall count
+ * 61 to 68	send count
+ * 69 to 76	dist_acc count
+ * 77 to 84	sbid count
+ * 85 to 92	sync count
+ * 93 to 100	inst_fetch count
+ * 101 to 108	Active count
+ * 109 to 111	Exid
+ * 112		EndFlag (is always 1)
+ */
+struct drm_xe_eu_stall_data_xe2 {
+	__u64 ip_addr:29;
+	__u64 tdr_count:8;
+	__u64 other_count:8;
+	__u64 control_count:8;
+	__u64 pipestall_count:8;
+	__u64 send_count:8;
+	__u64 dist_acc_count:8;
+	__u64 sbid_count:8;
+	__u64 sync_count:8;
+	__u64 inst_fetch_count:8;
+	__u64 active_count:8;
+	__u64 ex_id:3;
+	__u64 end_flag:1;
+	__u64 unused_bits:15;
+	__u64 unused[6];
+} __packed;
+
 static unsigned long
 xe_eu_stall_data_record_size(struct xe_device *xe)
 {
@@ -81,6 +117,8 @@ xe_eu_stall_data_record_size(struct xe_device *xe)
 
 	if (platform == XE_PVC)
 		record_size = sizeof(struct drm_xe_eu_stall_data_pvc);
+	else if ((platform == XE_LUNARLAKE) || (platform == XE_BATTLEMAGE))
+		record_size = sizeof(struct drm_xe_eu_stall_data_xe2);
 
 	return record_size;
 }
@@ -308,10 +346,16 @@ eu_stall_data_buf_check(struct xe_eu_stall_data_stream *stream)
 static void
 clear_dropped_eviction_line_bit(struct xe_gt *gt, u16 group, u16 instance)
 {
+	struct xe_device *xe = gt_to_xe(gt);
 	u32 write_ptr_reg;
 
-	/* On PVC, the overflow bit has to be cleared by writing 1 to it. */
-	write_ptr_reg = _MASKED_BIT_ENABLE(XEHPC_EUSTALL_REPORT_OVERFLOW_DROP);
+	/* On PVC, the overflow bit has to be cleared by writing 1 to it.
+	 * On other GPUs, the bit has to be cleared by writing 0 to it.
+	 */
+	if (GRAPHICS_VER(xe) >= 20)
+		write_ptr_reg = _MASKED_BIT_DISABLE(XEHPC_EUSTALL_REPORT_OVERFLOW_DROP);
+	else
+		write_ptr_reg = _MASKED_BIT_ENABLE(XEHPC_EUSTALL_REPORT_OVERFLOW_DROP);
 
 	xe_gt_mcr_unicast_write(gt, XEHPC_EUSTALL_REPORT, write_ptr_reg, group, instance);
 }
@@ -872,7 +916,9 @@ static const struct file_operations fops_eu_stall = {
 
 static inline bool has_eu_stall_sampling_support(struct xe_device *xe)
 {
-	return ((xe->info.platform == XE_PVC) ? true : false);
+	return ((xe->info.platform == XE_PVC ||
+		 xe->info.platform == XE_LUNARLAKE ||
+		 xe->info.platform == XE_BATTLEMAGE) ? true : false);
 }
 
 /**
-- 
2.45.1

[PATCH v5 6/7] drm/xe/query: Add a device query to get EU stall data information

[Harish Chegondi]

User space can find the EU stall data record size and capabilities
with the DRM_IOCTL_XE_DEVICE_QUERY with .query set to
DRM_XE_DEVICE_QUERY_EU_STALL. query data is returned in
a struct drm_xe_query_eu_stall.

Any capabilities in EU stall sampling as of this patch are considered
as base capabilities. Any new capabilities added later will need
a new capabilities flag.

Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
---
 drivers/gpu/drm/xe/xe_eu_stall.c |  2 +-
 drivers/gpu/drm/xe/xe_eu_stall.h |  2 ++
 drivers/gpu/drm/xe/xe_query.c    | 30 ++++++++++++++++++++++++++++++
 include/uapi/drm/xe_drm.h        | 23 +++++++++++++++++++++++
 4 files changed, 56 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_eu_stall.c b/drivers/gpu/drm/xe/xe_eu_stall.c
index 9169a31f620c..297b36910296 100644
--- a/drivers/gpu/drm/xe/xe_eu_stall.c
+++ b/drivers/gpu/drm/xe/xe_eu_stall.c
@@ -109,7 +109,7 @@ struct drm_xe_eu_stall_data_xe2 {
 	__u64 unused[6];
 } __packed;
 
-static unsigned long
+unsigned long
 xe_eu_stall_data_record_size(struct xe_device *xe)
 {
 	enum xe_platform platform = xe->info.platform;
diff --git a/drivers/gpu/drm/xe/xe_eu_stall.h b/drivers/gpu/drm/xe/xe_eu_stall.h
index d9482e1b522b..48061778263b 100644
--- a/drivers/gpu/drm/xe/xe_eu_stall.h
+++ b/drivers/gpu/drm/xe/xe_eu_stall.h
@@ -53,4 +53,6 @@ void xe_eu_stall_fini(struct xe_gt *gt);
 int xe_eu_stall_stream_open(struct drm_device *dev,
 			    u64 data,
 			    struct drm_file *file);
+unsigned long
+xe_eu_stall_data_record_size(struct xe_device *xe);
 #endif
diff --git a/drivers/gpu/drm/xe/xe_query.c b/drivers/gpu/drm/xe/xe_query.c
index 3eda616f1502..8c4f7f961dbe 100644
--- a/drivers/gpu/drm/xe/xe_query.c
+++ b/drivers/gpu/drm/xe/xe_query.c
@@ -26,6 +26,7 @@
 #include "xe_oa.h"
 #include "xe_ttm_vram_mgr.h"
 #include "xe_wa.h"
+#include "xe_eu_stall.h"
 
 static const u16 xe_to_user_engine_class[] = {
 	[XE_ENGINE_CLASS_RENDER] = DRM_XE_ENGINE_CLASS_RENDER,
@@ -696,6 +697,34 @@ static int query_oa_units(struct xe_device *xe,
 	return ret ? -EFAULT : 0;
 }
 
+static int query_eu_stall_data(struct xe_device *xe,
+			       struct drm_xe_device_query *query)
+{
+	size_t size = sizeof(struct drm_xe_query_eu_stall);
+	void __user *query_ptr = u64_to_user_ptr(query->data);
+	struct drm_xe_query_eu_stall *info;
+	int ret;
+
+	if (query->size == 0) {
+		query->size = size;
+		return 0;
+	} else if (XE_IOCTL_DBG(xe, query->size != size)) {
+		return -EINVAL;
+	}
+
+	info = kzalloc(size, GFP_KERNEL);
+	if (!info)
+		return -ENOMEM;
+
+	info->capabilities = DRM_XE_EU_STALL_CAPS_BASE;
+	info->record_size = xe_eu_stall_data_record_size(xe);
+
+	ret = copy_to_user(query_ptr, info, size);
+	kfree(info);
+
+	return ret ? -EFAULT : 0;
+}
+
 static int (* const xe_query_funcs[])(struct xe_device *xe,
 				      struct drm_xe_device_query *query) = {
 	query_engines,
@@ -707,6 +736,7 @@ static int (* const xe_query_funcs[])(struct xe_device *xe,
 	query_engine_cycles,
 	query_uc_fw_version,
 	query_oa_units,
+	query_eu_stall_data,
 };
 
 int xe_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
index 80aaa5b50c8a..8fffd05d2c7e 100644
--- a/include/uapi/drm/xe_drm.h
+++ b/include/uapi/drm/xe_drm.h
@@ -700,6 +700,7 @@ struct drm_xe_device_query {
 #define DRM_XE_DEVICE_QUERY_ENGINE_CYCLES	6
 #define DRM_XE_DEVICE_QUERY_UC_FW_VERSION	7
 #define DRM_XE_DEVICE_QUERY_OA_UNITS		8
+#define DRM_XE_DEVICE_QUERY_EU_STALL		9
 	/** @query: The type of data to query */
 	__u32 query;
 
@@ -1752,6 +1753,28 @@ enum drm_xe_eu_stall_property_id {
 	DRM_XE_EU_STALL_PROP_GT_ID,
 };
 
+/**
+ * struct drm_xe_query_eu_stall - Information about EU stall data
+ *
+ * If a query is made with a struct @drm_xe_device_query where .query
+ * is equal to @DRM_XE_DEVICE_QUERY_EU_STALL, then the reply uses
+ * struct @drm_xe_query_eu_stall in .data.
+ */
+struct drm_xe_query_eu_stall {
+	/** @extensions: Pointer to the first extension struct, if any */
+	__u64 extensions;
+
+	/** @record_size: size of each EU stall data record */
+	__u64 record_size;
+
+	/** @capabilities: EU stall capabilities bit-mask */
+	__u64 capabilities;
+#define DRM_XE_EU_STALL_CAPS_BASE		(1 << 0)
+
+	/** @reserved: Reserved */
+	__u64 reserved[5];
+};
+
 #if defined(__cplusplus)
 }
 #endif
-- 
2.45.1

[PATCH v5 7/7] drm/xe/eustall: Add workaround 22016596838 which applies to PVC.

[Harish Chegondi]

Add PVC workaround 22016596838 that disables EU DOP gating
during EU stall sampling.

Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
---
 drivers/gpu/drm/xe/xe_eu_stall.c   | 16 ++++++++++++++++
 drivers/gpu/drm/xe/xe_wa_oob.rules |  1 +
 2 files changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_eu_stall.c b/drivers/gpu/drm/xe/xe_eu_stall.c
index 297b36910296..9050f687cace 100644
--- a/drivers/gpu/drm/xe/xe_eu_stall.c
+++ b/drivers/gpu/drm/xe/xe_eu_stall.c
@@ -13,6 +13,7 @@
 
 #include "xe_bo.h"
 #include "xe_pm.h"
+#include "xe_wa.h"
 #include "xe_trace.h"
 #include "xe_macros.h"
 #include "xe_device.h"
@@ -26,6 +27,8 @@
 #include "regs/xe_gt_regs.h"
 #include "regs/xe_eu_stall_regs.h"
 
+#include <generated/xe_wa_oob.h>
+
 #define POLL_FREQUENCY_HZ 100
 #define POLL_PERIOD_NS (NSEC_PER_SEC / POLL_FREQUENCY_HZ)
 
@@ -631,6 +634,14 @@ xe_eu_stall_stream_enable(struct xe_eu_stall_data_stream *stream)
 	xe_pm_runtime_get(gt_to_xe(gt));
 	XE_WARN_ON(xe_force_wake_get(gt_to_fw(gt), XE_FW_RENDER));
 
+	/*
+	 * Wa_22016596838:pvc
+	 * Disable EU DOP gating for PVC.
+	 */
+	if (XE_WA(gt, 22016596838))
+		xe_gt_mcr_multicast_write(gt, ROW_CHICKEN2,
+					  _MASKED_BIT_ENABLE(DISABLE_DOP_GATING));
+
 	reg_value = gen_eustall_base(stream, true);
 	xe_gt_mcr_multicast_write(gt, XEHPC_EUSTALL_BASE, reg_value);
 }
@@ -662,6 +673,11 @@ xe_eu_stall_stream_disable(struct xe_eu_stall_data_stream *stream)
 	reg_value = gen_eustall_base(stream, false);
 	xe_gt_mcr_multicast_write(gt, XEHPC_EUSTALL_BASE, reg_value);
 
+	/* Wa_22016596838:pvc */
+	if (XE_WA(gt, 22016596838))
+		xe_gt_mcr_multicast_write(gt, ROW_CHICKEN2,
+					  _MASKED_BIT_DISABLE(DISABLE_DOP_GATING));
+
 	xe_force_wake_put(gt_to_fw(gt), XE_FW_RENDER);
 	xe_pm_runtime_put(gt_to_xe(gt));
 }
diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
index 3ed12a85cc60..c10be71ac766 100644
--- a/drivers/gpu/drm/xe/xe_wa_oob.rules
+++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
@@ -5,6 +5,7 @@
 22011391025	PLATFORM(DG2)
 22012727170	SUBPLATFORM(DG2, G11)
 22012727685	SUBPLATFORM(DG2, G11)
+22016596838	PLATFORM(PVC)
 18020744125	PLATFORM(PVC)
 1509372804	PLATFORM(PVC), GRAPHICS_STEP(A0, C0)
 1409600907	GRAPHICS_VERSION_RANGE(1200, 1250)
-- 
2.45.1

✓ CI.Patch_applied: success for Add support for EU stall sampling

[Patchwork]

== Series Details ==

Series: Add support for EU stall sampling
URL   : https://patchwork.freedesktop.org/series/141483/
State : success

== Summary ==

=== Applying kernel patches on branch 'drm-tip' with base: ===
Base commit: 90014f8026e3 drm-tip: 2024y-11m-18d-09h-06m-48s UTC integration manifest
=== git am output follows ===
Applying: drm/xe/topology: Add a function to find the index of the last enabled DSS in a mask
Applying: drm/xe/eustall: Introduce API for EU stall sampling
Applying: drm/xe/eustall: Implement EU stall sampling APIs for Xe_HPC
Applying: drm/xe/eustall: Return -EIO error from read() if HW drops data
Applying: drm/xe/eustall: Add EU stall sampling support for Xe2
Applying: drm/xe/query: Add a device query to get EU stall data information
Applying: drm/xe/eustall: Add workaround 22016596838 which applies to PVC.

✗ CI.checkpatch: warning for Add support for EU stall sampling

[Patchwork]

== Series Details ==

Series: Add support for EU stall sampling
URL   : https://patchwork.freedesktop.org/series/141483/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
30ab6715fc09baee6cc14cb3c89ad8858688d474
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 9d37d60530b445de8e59d86de950e3cd90c95bc3
Author: Harish Chegondi <harish.chegondi@intel.com>
Date:   Mon Nov 18 01:07:19 2024 -0800

    drm/xe/eustall: Add workaround 22016596838 which applies to PVC.
    
    Add PVC workaround 22016596838 that disables EU DOP gating
    during EU stall sampling.
    
    Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
+ /mt/dim checkpatch 90014f8026e31874d368834834253debd131268b drm-intel
cce2b6a054a7 drm/xe/topology: Add a function to find the index of the last enabled DSS in a mask
47afe7bf6bc1 drm/xe/eustall: Introduce API for EU stall sampling
-:50: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#50: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 384 lines checked
510e2d03ea07 drm/xe/eustall: Implement EU stall sampling APIs for Xe_HPC
-:21: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#21: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 984 lines checked
e89cb924c290 drm/xe/eustall: Return -EIO error from read() if HW drops data
9d603dbee2ea drm/xe/eustall: Add EU stall sampling support for Xe2
0a2b514a2d5f drm/xe/query: Add a device query to get EU stall data information
9d37d60530b4 drm/xe/eustall: Add workaround 22016596838 which applies to PVC.

✓ CI.KUnit: success for Add support for EU stall sampling

[Patchwork]

== Series Details ==

Series: Add support for EU stall sampling
URL   : https://patchwork.freedesktop.org/series/141483/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[13:22:55] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[13:22:59] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json ARCH=um O=.kunit --jobs=48
../lib/iomap.c:156:5: warning: no previous prototype for ‘ioread64_lo_hi’ [-Wmissing-prototypes]
  156 | u64 ioread64_lo_hi(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~
../lib/iomap.c:163:5: warning: no previous prototype for ‘ioread64_hi_lo’ [-Wmissing-prototypes]
  163 | u64 ioread64_hi_lo(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~
../lib/iomap.c:170:5: warning: no previous prototype for ‘ioread64be_lo_hi’ [-Wmissing-prototypes]
  170 | u64 ioread64be_lo_hi(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~~~
../lib/iomap.c:178:5: warning: no previous prototype for ‘ioread64be_hi_lo’ [-Wmissing-prototypes]
  178 | u64 ioread64be_hi_lo(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~~~
../lib/iomap.c:264:6: warning: no previous prototype for ‘iowrite64_lo_hi’ [-Wmissing-prototypes]
  264 | void iowrite64_lo_hi(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~
../lib/iomap.c:272:6: warning: no previous prototype for ‘iowrite64_hi_lo’ [-Wmissing-prototypes]
  272 | void iowrite64_hi_lo(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~
../lib/iomap.c:280:6: warning: no previous prototype for ‘iowrite64be_lo_hi’ [-Wmissing-prototypes]
  280 | void iowrite64be_lo_hi(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~~~
../lib/iomap.c:288:6: warning: no previous prototype for ‘iowrite64be_hi_lo’ [-Wmissing-prototypes]
  288 | void iowrite64be_hi_lo(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~~~

[13:23:27] Starting KUnit Kernel (1/1)...
[13:23:27] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[13:23:27] =================== guc_dbm (7 subtests) ===================
[13:23:27] [PASSED] test_empty
[13:23:27] [PASSED] test_default
[13:23:27] ======================== test_size  ========================
[13:23:27] [PASSED] 4
[13:23:27] [PASSED] 8
[13:23:27] [PASSED] 32
[13:23:27] [PASSED] 256
[13:23:27] ==================== [PASSED] test_size ====================
[13:23:27] ======================= test_reuse  ========================
[13:23:27] [PASSED] 4
[13:23:27] [PASSED] 8
[13:23:27] [PASSED] 32
[13:23:27] [PASSED] 256
[13:23:27] =================== [PASSED] test_reuse ====================
[13:23:27] =================== test_range_overlap  ====================
[13:23:27] [PASSED] 4
[13:23:27] [PASSED] 8
[13:23:27] [PASSED] 32
[13:23:27] [PASSED] 256
[13:23:27] =============== [PASSED] test_range_overlap ================
[13:23:27] =================== test_range_compact  ====================
[13:23:27] [PASSED] 4
[13:23:27] [PASSED] 8
[13:23:27] [PASSED] 32
[13:23:27] [PASSED] 256
[13:23:27] =============== [PASSED] test_range_compact ================
[13:23:27] ==================== test_range_spare  =====================
[13:23:27] [PASSED] 4
[13:23:27] [PASSED] 8
[13:23:27] [PASSED] 32
[13:23:27] [PASSED] 256
[13:23:27] ================ [PASSED] test_range_spare =================
[13:23:27] ===================== [PASSED] guc_dbm =====================
[13:23:27] =================== guc_idm (6 subtests) ===================
[13:23:27] [PASSED] bad_init
[13:23:27] [PASSED] no_init
[13:23:27] [PASSED] init_fini
[13:23:27] [PASSED] check_used
[13:23:27] [PASSED] check_quota
[13:23:27] [PASSED] check_all
[13:23:27] ===================== [PASSED] guc_idm =====================
[13:23:27] ================== no_relay (3 subtests) ===================
[13:23:27] [PASSED] xe_drops_guc2pf_if_not_ready
[13:23:27] [PASSED] xe_drops_guc2vf_if_not_ready
[13:23:27] [PASSED] xe_rejects_send_if_not_ready
[13:23:27] ==================== [PASSED] no_relay =====================
[13:23:27] ================== pf_relay (14 subtests) ==================
[13:23:27] [PASSED] pf_rejects_guc2pf_too_short
[13:23:27] [PASSED] pf_rejects_guc2pf_too_long
[13:23:27] [PASSED] pf_rejects_guc2pf_no_payload
[13:23:27] [PASSED] pf_fails_no_payload
[13:23:27] [PASSED] pf_fails_bad_origin
[13:23:27] [PASSED] pf_fails_bad_type
[13:23:27] [PASSED] pf_txn_reports_error
[13:23:27] [PASSED] pf_txn_sends_pf2guc
[13:23:27] [PASSED] pf_sends_pf2guc
[13:23:27] [SKIPPED] pf_loopback_nop
[13:23:27] [SKIPPED] pf_loopback_echo
[13:23:27] [SKIPPED] pf_loopback_fail
[13:23:27] [SKIPPED] pf_loopback_busy
[13:23:27] [SKIPPED] pf_loopback_retry
[13:23:27] ==================== [PASSED] pf_relay =====================
[13:23:27] ================== vf_relay (3 subtests) ===================
[13:23:27] [PASSED] vf_rejects_guc2vf_too_short
[13:23:27] [PASSED] vf_rejects_guc2vf_too_long
[13:23:27] [PASSED] vf_rejects_guc2vf_no_payload
[13:23:27] ==================== [PASSED] vf_relay =====================
[13:23:27] ================= pf_service (11 subtests) =================
[13:23:27] [PASSED] pf_negotiate_any
[13:23:27] [PASSED] pf_negotiate_base_match
[13:23:27] [PASSED] pf_negotiate_base_newer
[13:23:27] [PASSED] pf_negotiate_base_next
[13:23:27] [SKIPPED] pf_negotiate_base_older
[13:23:27] [PASSED] pf_negotiate_base_prev
[13:23:27] [PASSED] pf_negotiate_latest_match
[13:23:27] [PASSED] pf_negotiate_latest_newer
[13:23:27] [PASSED] pf_negotiate_latest_next
[13:23:27] [SKIPPED] pf_negotiate_latest_older
[13:23:27] [SKIPPED] pf_negotiate_latest_prev
[13:23:27] =================== [PASSED] pf_service ====================
[13:23:27] ===================== lmtt (1 subtest) =====================
[13:23:27] ======================== test_ops  =========================
[13:23:27] [PASSED] 2-level
[13:23:27] [PASSED] multi-level
[13:23:27] ==================== [PASSED] test_ops =====================
[13:23:27] ====================== [PASSED] lmtt =======================
[13:23:27] =================== xe_mocs (2 subtests) ===================
[13:23:27] ================ xe_live_mocs_kernel_kunit  ================
[13:23:27] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[13:23:27] ================ xe_live_mocs_reset_kunit  =================
[13:23:27] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[13:23:27] ==================== [SKIPPED] xe_mocs =====================
[13:23:27] ================= xe_migrate (2 subtests) ==================
[13:23:27] ================= xe_migrate_sanity_kunit  =================
[13:23:27] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[13:23:27] ================== xe_validate_ccs_kunit  ==================
[13:23:27] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[13:23:27] =================== [SKIPPED] xe_migrate ===================
[13:23:27] ================== xe_dma_buf (1 subtest) ==================
[13:23:27] ==================== xe_dma_buf_kunit  =====================
[13:23:27] ================ [SKIPPED] xe_dma_buf_kunit ================
[13:23:27] =================== [SKIPPED] xe_dma_buf ===================
[13:23:27] ==================== xe_bo (3 subtests) ====================
[13:23:27] ================== xe_ccs_migrate_kunit  ===================
[13:23:27] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[13:23:27] ==================== xe_bo_evict_kunit  ====================
[13:23:27] =============== [SKIPPED] xe_bo_evict_kunit ================
[13:23:27] =================== xe_bo_shrink_kunit  ====================
[13:23:27] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[13:23:27] ===================== [SKIPPED] xe_bo ======================
[13:23:27] ==================== args (11 subtests) ====================
[13:23:27] [PASSED] count_args_test
[13:23:27] [PASSED] call_args_example
[13:23:27] [PASSED] call_args_test
[13:23:27] [PASSED] drop_first_arg_example
[13:23:27] [PASSED] drop_first_arg_test
[13:23:27] [PASSED] first_arg_example
[13:23:27] [PASSED] first_arg_test
[13:23:27] [PASSED] last_arg_example
[13:23:27] [PASSED] last_arg_test
[13:23:27] [PASSED] pick_arg_example
[13:23:27] [PASSED] sep_comma_examplestty: 'standard input': Inappropriate ioctl for device

[13:23:27] ====================== [PASSED] args =======================
[13:23:27] =================== xe_pci (2 subtests) ====================
[13:23:27] [PASSED] xe_gmdid_graphics_ip
[13:23:27] [PASSED] xe_gmdid_media_ip
[13:23:27] ===================== [PASSED] xe_pci ======================
[13:23:27] =================== xe_rtp (2 subtests) ====================
[13:23:27] =============== xe_rtp_process_to_sr_tests  ================
[13:23:27] [PASSED] coalesce-same-reg
[13:23:27] [PASSED] no-match-no-add
[13:23:27] [PASSED] match-or
[13:23:27] [PASSED] match-or-xfail
[13:23:27] [PASSED] no-match-no-add-multiple-rules
[13:23:27] [PASSED] two-regs-two-entries
[13:23:27] [PASSED] clr-one-set-other
[13:23:27] [PASSED] set-field
[13:23:27] [PASSED] conflict-duplicate
[13:23:27] [PASSED] conflict-not-disjoint
[13:23:27] [PASSED] conflict-reg-type
[13:23:27] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[13:23:27] ================== xe_rtp_process_tests  ===================
[13:23:27] [PASSED] active1
[13:23:27] [PASSED] active2
[13:23:27] [PASSED] active-inactive
[13:23:27] [PASSED] inactive-active
[13:23:27] [PASSED] inactive-1st_or_active-inactive
[13:23:27] [PASSED] inactive-2nd_or_active-inactive
[13:23:27] [PASSED] inactive-last_or_active-inactive
[13:23:27] [PASSED] inactive-no_or_active-inactive
[13:23:27] ============== [PASSED] xe_rtp_process_tests ===============
[13:23:27] ===================== [PASSED] xe_rtp ======================
[13:23:27] ==================== xe_wa (1 subtest) =====================
[13:23:27] ======================== xe_wa_gt  =========================
[13:23:27] [PASSED] TIGERLAKE (B0)
[13:23:27] [PASSED] DG1 (A0)
[13:23:27] [PASSED] DG1 (B0)
[13:23:27] [PASSED] ALDERLAKE_S (A0)
[13:23:27] [PASSED] ALDERLAKE_S (B0)
[13:23:27] [PASSED] ALDERLAKE_S (C0)
[13:23:27] [PASSED] ALDERLAKE_S (D0)
[13:23:27] [PASSED] ALDERLAKE_P (A0)
[13:23:27] [PASSED] ALDERLAKE_P (B0)
[13:23:27] [PASSED] ALDERLAKE_P (C0)
[13:23:27] [PASSED] ALDERLAKE_S_RPLS (D0)
[13:23:27] [PASSED] ALDERLAKE_P_RPLU (E0)
[13:23:27] [PASSED] DG2_G10 (C0)
[13:23:27] [PASSED] DG2_G11 (B1)
[13:23:27] [PASSED] DG2_G12 (A1)
[13:23:27] [PASSED] METEORLAKE (g:A0, m:A0)
[13:23:27] [PASSED] METEORLAKE (g:A0, m:A0)
[13:23:27] [PASSED] METEORLAKE (g:A0, m:A0)
[13:23:27] [PASSED] LUNARLAKE (g:A0, m:A0)
[13:23:27] [PASSED] LUNARLAKE (g:B0, m:A0)
[13:23:27] [PASSED] BATTLEMAGE (g:A0, m:A1)
[13:23:27] ==================== [PASSED] xe_wa_gt =====================
[13:23:27] ====================== [PASSED] xe_wa ======================
[13:23:27] ============================================================
[13:23:27] Testing complete. Ran 122 tests: passed: 106, skipped: 16
[13:23:28] Elapsed time: 32.981s total, 4.426s configuring, 28.288s building, 0.220s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[13:23:28] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[13:23:29] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json ARCH=um O=.kunit --jobs=48
../lib/iomap.c:156:5: warning: no previous prototype for ‘ioread64_lo_hi’ [-Wmissing-prototypes]
  156 | u64 ioread64_lo_hi(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~
../lib/iomap.c:163:5: warning: no previous prototype for ‘ioread64_hi_lo’ [-Wmissing-prototypes]
  163 | u64 ioread64_hi_lo(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~
../lib/iomap.c:170:5: warning: no previous prototype for ‘ioread64be_lo_hi’ [-Wmissing-prototypes]
  170 | u64 ioread64be_lo_hi(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~~~
../lib/iomap.c:178:5: warning: no previous prototype for ‘ioread64be_hi_lo’ [-Wmissing-prototypes]
  178 | u64 ioread64be_hi_lo(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~~~
../lib/iomap.c:264:6: warning: no previous prototype for ‘iowrite64_lo_hi’ [-Wmissing-prototypes]
  264 | void iowrite64_lo_hi(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~
../lib/iomap.c:272:6: warning: no previous prototype for ‘iowrite64_hi_lo’ [-Wmissing-prototypes]
  272 | void iowrite64_hi_lo(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~
../lib/iomap.c:280:6: warning: no previous prototype for ‘iowrite64be_lo_hi’ [-Wmissing-prototypes]
  280 | void iowrite64be_lo_hi(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~~~
../lib/iomap.c:288:6: warning: no previous prototype for ‘iowrite64be_hi_lo’ [-Wmissing-prototypes]
  288 | void iowrite64be_hi_lo(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~~~

[13:23:52] Starting KUnit Kernel (1/1)...
[13:23:52] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[13:23:52] ================== drm_buddy (7 subtests) ==================
[13:23:52] [PASSED] drm_test_buddy_alloc_limit
[13:23:52] [PASSED] drm_test_buddy_alloc_optimistic
[13:23:52] [PASSED] drm_test_buddy_alloc_pessimistic
[13:23:52] [PASSED] drm_test_buddy_alloc_pathological
[13:23:52] [PASSED] drm_test_buddy_alloc_contiguous
[13:23:52] [PASSED] drm_test_buddy_alloc_clear
[13:23:52] [PASSED] drm_test_buddy_alloc_range_bias
[13:23:52] ==================== [PASSED] drm_buddy ====================
[13:23:52] ============= drm_cmdline_parser (40 subtests) =============
[13:23:52] [PASSED] drm_test_cmdline_force_d_only
[13:23:52] [PASSED] drm_test_cmdline_force_D_only_dvi
[13:23:52] [PASSED] drm_test_cmdline_force_D_only_hdmi
[13:23:52] [PASSED] drm_test_cmdline_force_D_only_not_digital
[13:23:52] [PASSED] drm_test_cmdline_force_e_only
[13:23:52] [PASSED] drm_test_cmdline_res
[13:23:52] [PASSED] drm_test_cmdline_res_vesa
[13:23:52] [PASSED] drm_test_cmdline_res_vesa_rblank
[13:23:52] [PASSED] drm_test_cmdline_res_rblank
[13:23:52] [PASSED] drm_test_cmdline_res_bpp
[13:23:52] [PASSED] drm_test_cmdline_res_refresh
[13:23:52] [PASSED] drm_test_cmdline_res_bpp_refresh
[13:23:52] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[13:23:52] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[13:23:52] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[13:23:52] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[13:23:52] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[13:23:52] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[13:23:52] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[13:23:52] [PASSED] drm_test_cmdline_res_margins_force_on
[13:23:52] [PASSED] drm_test_cmdline_res_vesa_margins
[13:23:52] [PASSED] drm_test_cmdline_name
[13:23:52] [PASSED] drm_test_cmdline_name_bpp
[13:23:52] [PASSED] drm_test_cmdline_name_option
[13:23:52] [PASSED] drm_test_cmdline_name_bpp_option
[13:23:52] [PASSED] drm_test_cmdline_rotate_0
[13:23:52] [PASSED] drm_test_cmdline_rotate_90
[13:23:52] [PASSED] drm_test_cmdline_rotate_180
[13:23:52] [PASSED] drm_test_cmdline_rotate_270
[13:23:52] [PASSED] drm_test_cmdline_hmirror
[13:23:52] [PASSED] drm_test_cmdline_vmirror
[13:23:52] [PASSED] drm_test_cmdline_margin_options
[13:23:52] [PASSED] drm_test_cmdline_multiple_options
[13:23:52] [PASSED] drm_test_cmdline_bpp_extra_and_option
[13:23:52] [PASSED] drm_test_cmdline_extra_and_option
[13:23:52] [PASSED] drm_test_cmdline_freestanding_options
[13:23:52] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[13:23:52] [PASSED] drm_test_cmdline_panel_orientation
[13:23:52] ================ drm_test_cmdline_invalid  =================
[13:23:52] [PASSED] margin_only
[13:23:52] [PASSED] interlace_only
[13:23:52] [PASSED] res_missing_x
[13:23:52] [PASSED] res_missing_y
[13:23:52] [PASSED] res_bad_y
[13:23:52] [PASSED] res_missing_y_bpp
[13:23:52] [PASSED] res_bad_bpp
[13:23:52] [PASSED] res_bad_refresh
[13:23:52] [PASSED] res_bpp_refresh_force_on_off
[13:23:52] [PASSED] res_invalid_mode
[13:23:52] [PASSED] res_bpp_wrong_place_mode
[13:23:52] [PASSED] name_bpp_refresh
[13:23:52] [PASSED] name_refresh
[13:23:52] [PASSED] name_refresh_wrong_mode
[13:23:52] [PASSED] name_refresh_invalid_mode
[13:23:52] [PASSED] rotate_multiple
[13:23:52] [PASSED] rotate_invalid_val
[13:23:52] [PASSED] rotate_truncated
[13:23:52] [PASSED] invalid_option
[13:23:52] [PASSED] invalid_tv_option
[13:23:52] [PASSED] truncated_tv_option
[13:23:52] ============ [PASSED] drm_test_cmdline_invalid =============
[13:23:52] =============== drm_test_cmdline_tv_options  ===============
[13:23:52] [PASSED] NTSC
[13:23:52] [PASSED] NTSC_443
[13:23:52] [PASSED] NTSC_J
[13:23:52] [PASSED] PAL
[13:23:52] [PASSED] PAL_M
[13:23:52] [PASSED] PAL_N
[13:23:52] [PASSED] SECAM
[13:23:52] [PASSED] MONO_525
[13:23:52] [PASSED] MONO_625
[13:23:52] =========== [PASSED] drm_test_cmdline_tv_options ===========
[13:23:52] =============== [PASSED] drm_cmdline_parser ================
[13:23:52] ========== drmm_connector_hdmi_init (19 subtests) ==========
[13:23:52] [PASSED] drm_test_connector_hdmi_init_valid
[13:23:52] [PASSED] drm_test_connector_hdmi_init_bpc_8
[13:23:52] [PASSED] drm_test_connector_hdmi_init_bpc_10
[13:23:52] [PASSED] drm_test_connector_hdmi_init_bpc_12
[13:23:52] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[13:23:52] [PASSED] drm_test_connector_hdmi_init_bpc_null
[13:23:52] [PASSED] drm_test_connector_hdmi_init_formats_empty
[13:23:52] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[13:23:52] [PASSED] drm_test_connector_hdmi_init_null_ddc
[13:23:52] [PASSED] drm_test_connector_hdmi_init_null_product
[13:23:52] [PASSED] drm_test_connector_hdmi_init_null_vendor
[13:23:52] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[13:23:52] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[13:23:52] [PASSED] drm_test_connector_hdmi_init_product_valid
[13:23:52] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[13:23:52] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[13:23:52] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[13:23:52] ========= drm_test_connector_hdmi_init_type_valid  =========
[13:23:52] [PASSED] HDMI-A
[13:23:52] [PASSED] HDMI-B
[13:23:52] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[13:23:52] ======== drm_test_connector_hdmi_init_type_invalid  ========
[13:23:52] [PASSED] Unknown
[13:23:52] [PASSED] VGA
[13:23:52] [PASSED] DVI-I
[13:23:52] [PASSED] DVI-D
[13:23:52] [PASSED] DVI-A
[13:23:52] [PASSED] Composite
[13:23:52] [PASSED] SVIDEO
[13:23:52] [PASSED] LVDS
[13:23:52] [PASSED] Component
[13:23:52] [PASSED] DIN
[13:23:52] [PASSED] DP
[13:23:52] [PASSED] TV
[13:23:52] [PASSED] eDP
[13:23:52] [PASSED] Virtual
[13:23:52] [PASSED] DSI
[13:23:52] [PASSED] DPI
[13:23:52] [PASSED] Writeback
[13:23:52] [PASSED] SPI
[13:23:52] [PASSED] USB
[13:23:52] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[13:23:52] ============ [PASSED] drmm_connector_hdmi_init =============
[13:23:52] ============= drmm_connector_init (3 subtests) =============
[13:23:52] [PASSED] drm_test_drmm_connector_init
[13:23:52] [PASSED] drm_test_drmm_connector_init_null_ddc
[13:23:52] ========= drm_test_drmm_connector_init_type_valid  =========
[13:23:52] [PASSED] Unknown
[13:23:52] [PASSED] VGA
[13:23:52] [PASSED] DVI-I
[13:23:52] [PASSED] DVI-D
[13:23:52] [PASSED] DVI-A
[13:23:52] [PASSED] Composite
[13:23:52] [PASSED] SVIDEO
[13:23:52] [PASSED] LVDS
[13:23:52] [PASSED] Component
[13:23:52] [PASSED] DIN
[13:23:52] [PASSED] DP
[13:23:52] [PASSED] HDMI-A
[13:23:52] [PASSED] HDMI-B
[13:23:52] [PASSED] TV
[13:23:52] [PASSED] eDP
[13:23:52] [PASSED] Virtual
[13:23:52] [PASSED] DSI
[13:23:52] [PASSED] DPI
[13:23:52] [PASSED] Writeback
[13:23:52] [PASSED] SPI
[13:23:52] [PASSED] USB
[13:23:52] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[13:23:52] =============== [PASSED] drmm_connector_init ===============
[13:23:52] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[13:23:52] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[13:23:52] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[13:23:52] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[13:23:52] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[13:23:52] ========== drm_test_get_tv_mode_from_name_valid  ===========
[13:23:52] [PASSED] NTSC
[13:23:52] [PASSED] NTSC-443
[13:23:52] [PASSED] NTSC-J
[13:23:52] [PASSED] PAL
[13:23:52] [PASSED] PAL-M
[13:23:52] [PASSED] PAL-N
[13:23:52] [PASSED] SECAM
[13:23:52] [PASSED] Mono
[13:23:52] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[13:23:52] [PASSED] drm_test_get_tv_mode_from_name_truncated
[13:23:52] ============ [PASSED] drm_get_tv_mode_from_name ============
[13:23:52] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[13:23:52] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[13:23:52] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[13:23:52] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[13:23:52] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[13:23:52] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[13:23:52] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[13:23:52] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[13:23:52] [PASSED] VIC 96
[13:23:52] [PASSED] VIC 97
[13:23:52] [PASSED] VIC 101
[13:23:52] [PASSED] VIC 102
[13:23:52] [PASSED] VIC 106
[13:23:52] [PASSED] VIC 107
[13:23:52] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[13:23:52] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[13:23:52] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[13:23:52] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[13:23:52] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[13:23:52] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[13:23:52] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[13:23:52] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[13:23:52] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[13:23:52] [PASSED] Automatic
[13:23:52] [PASSED] Full
[13:23:52] [PASSED] Limited 16:235
[13:23:52] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[13:23:52] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[13:23:52] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[13:23:52] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[13:23:52] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[13:23:52] [PASSED] RGB
[13:23:52] [PASSED] YUV 4:2:0
[13:23:52] [PASSED] YUV 4:2:2
[13:23:52] [PASSED] YUV 4:4:4
[13:23:52] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[13:23:52] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[13:23:52] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[13:23:52] ============= drm_damage_helper (21 subtests) ==============
[13:23:52] [PASSED] drm_test_damage_iter_no_damage
[13:23:52] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[13:23:52] [PASSED] drm_test_damage_iter_no_damage_src_moved
[13:23:52] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[13:23:52] [PASSED] drm_test_damage_iter_no_damage_not_visible
[13:23:52] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[13:23:52] [PASSED] drm_test_damage_iter_no_damage_no_fb
[13:23:52] [PASSED] drm_test_damage_iter_simple_damage
[13:23:52] [PASSED] drm_test_damage_iter_single_damage
[13:23:52] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[13:23:52] [PASSED] drm_test_damage_iter_single_damage_outside_src
[13:23:52] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[13:23:52] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[13:23:52] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[13:23:52] [PASSED] drm_test_damage_iter_single_damage_src_moved
[13:23:52] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[13:23:52] [PASSED] drm_test_damage_iter_damage
[13:23:52] [PASSED] drm_test_damage_iter_damage_one_intersect
[13:23:52] [PASSED] drm_test_damage_iter_damage_one_outside
[13:23:52] [PASSED] drm_test_damage_iter_damage_src_moved
[13:23:52] [PASSED] drm_test_damage_iter_damage_not_visible
[13:23:52] ================ [PASSED] drm_damage_helper ================
[13:23:52] ============== drm_dp_mst_helper (3 subtests) ==============
[13:23:52] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[13:23:52] [PASSED] Clock 154000 BPP 30 DSC disabled
[13:23:52] [PASSED] Clock 234000 BPP 30 DSC disabled
[13:23:52] [PASSED] Clock 297000 BPP 24 DSC disabled
[13:23:52] [PASSED] Clock 332880 BPP 24 DSC enabled
[13:23:52] [PASSED] Clock 324540 BPP 24 DSC enabled
[13:23:52] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[13:23:52] ============== drm_test_dp_mst_calc_pbn_div  ===============
[13:23:52] [PASSED] Link rate 2000000 lane count 4
[13:23:52] [PASSED] Link rate 2000000 lane count 2
[13:23:52] [PASSED] Link rate 2000000 lane count 1
[13:23:52] [PASSED] Link rate 1350000 lane count 4
[13:23:52] [PASSED] Link rate 1350000 lane count 2
[13:23:52] [PASSED] Link rate 1350000 lane count 1
[13:23:52] [PASSED] Link rate 1000000 lane count 4
[13:23:52] [PASSED] Link rate 1000000 lane count 2
[13:23:52] [PASSED] Link rate 1000000 lane count 1
[13:23:52] [PASSED] Link rate 810000 lane count 4
[13:23:52] [PASSED] Link rate 810000 lane count 2
[13:23:52] [PASSED] Link rate 810000 lane count 1
[13:23:52] [PASSED] Link rate 540000 lane count 4
[13:23:52] [PASSED] Link rate 540000 lane count 2
[13:23:52] [PASSED] Link rate 540000 lane count 1
[13:23:52] [PASSED] Link rate 270000 lane count 4
[13:23:52] [PASSED] Link rate 270000 lane count 2
[13:23:52] [PASSED] Link rate 270000 lane count 1
[13:23:52] [PASSED] Link rate 162000 lane count 4
[13:23:52] [PASSED] Link rate 162000 lane count 2
[13:23:52] [PASSED] Link rate 162000 lane count 1
[13:23:52] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[13:23:52] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[13:23:52] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[13:23:52] [PASSED] DP_POWER_UP_PHY with port number
[13:23:52] [PASSED] DP_POWER_DOWN_PHY with port number
[13:23:52] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[13:23:52] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[13:23:52] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[13:23:52] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[13:23:52] [PASSED] DP_QUERY_PAYLOAD with port number
[13:23:52] [PASSED] DP_QUERY_PAYLOAD with VCPI
[13:23:52] [PASSED] DP_REMOTE_DPCD_READ with port number
[13:23:52] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[13:23:52] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[13:23:52] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[13:23:52] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[13:23:52] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[13:23:52] [PASSED] DP_REMOTE_I2C_READ with port number
[13:23:52] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[13:23:52] [PASSED] DP_REMOTE_I2C_READ with transactions array
[13:23:52] [PASSED] DP_REMOTE_I2C_WRITE with port number
[13:23:52] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[13:23:52] [PASSED] DP_REMOTE_I2C_WRITE with data array
[13:23:52] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[13:23:52] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[13:23:52] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[13:23:52] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[13:23:52] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[13:23:52] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[13:23:52] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[13:23:52] ================ [PASSED] drm_dp_mst_helper ================
[13:23:52] ================== drm_exec (7 subtests) ===================
[13:23:52] [PASSED] sanitycheck
[13:23:52] [PASSED] test_lock
[13:23:52] [PASSED] test_lock_unlock
[13:23:52] [PASSED] test_duplicates
[13:23:52] [PASSED] test_prepare
[13:23:52] [PASSED] test_prepare_array
[13:23:52] [PASSED] test_multiple_loops
[13:23:52] ==================== [PASSED] drm_exec =====================
[13:23:52] =========== drm_format_helper_test (17 subtests) ===========
[13:23:52] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[13:23:52] [PASSED] single_pixel_source_buffer
[13:23:52] [PASSED] single_pixel_clip_rectangle
[13:23:52] [PASSED] well_known_colors
[13:23:52] [PASSED] destination_pitch
[13:23:52] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[13:23:52] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[13:23:52] [PASSED] single_pixel_source_buffer
[13:23:52] [PASSED] single_pixel_clip_rectangle
[13:23:52] [PASSED] well_known_colors
[13:23:52] [PASSED] destination_pitch
[13:23:52] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[13:23:52] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[13:23:52] [PASSED] single_pixel_source_buffer
[13:23:52] [PASSED] single_pixel_clip_rectangle
[13:23:52] [PASSED] well_known_colors
[13:23:52] [PASSED] destination_pitch
[13:23:52] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[13:23:52] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[13:23:52] [PASSED] single_pixel_source_buffer
[13:23:52] [PASSED] single_pixel_clip_rectangle
[13:23:52] [PASSED] well_known_colors
[13:23:52] [PASSED] destination_pitch
[13:23:52] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[13:23:52] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[13:23:52] [PASSED] single_pixel_source_buffer
[13:23:52] [PASSED] single_pixel_clip_rectangle
[13:23:52] [PASSED] well_known_colors
[13:23:52] [PASSED] destination_pitch
[13:23:52] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[13:23:52] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[13:23:52] [PASSED] single_pixel_source_buffer
[13:23:52] [PASSED] single_pixel_clip_rectangle
[13:23:52] [PASSED] well_known_colors
[13:23:52] [PASSED] destination_pitch
[13:23:52] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[13:23:52] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[13:23:52] [PASSED] single_pixel_source_buffer
[13:23:52] [PASSED] single_pixel_clip_rectangle
[13:23:52] [PASSED] well_known_colors
[13:23:52] [PASSED] destination_pitch
[13:23:52] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[13:23:52] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[13:23:52] [PASSED] single_pixel_source_buffer
[13:23:52] [PASSED] single_pixel_clip_rectangle
[13:23:52] [PASSED] well_known_colors
[13:23:52] [PASSED] destination_pitch
[13:23:52] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[13:23:52] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[13:23:52] [PASSED] single_pixel_source_buffer
[13:23:52] [PASSED] single_pixel_clip_rectangle
[13:23:52] [PASSED] well_known_colors
[13:23:52] [PASSED] destination_pitch
[13:23:52] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[13:23:52] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[13:23:52] [PASSED] single_pixel_source_buffer
[13:23:52] [PASSED] single_pixel_clip_rectangle
[13:23:52] [PASSED] well_known_colors
[13:23:52] [PASSED] destination_pitch
[13:23:52] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[13:23:52] ============== drm_test_fb_xrgb8888_to_mono  ===============
[13:23:52] [PASSED] single_pixel_source_buffer
[13:23:52] [PASSED] single_pixel_clip_rectangle
[13:23:52] [PASSED] well_known_colors
[13:23:52] [PASSED] destination_pitch
[13:23:52] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[13:23:52] ==================== drm_test_fb_swab  =====================
[13:23:52] [PASSED] single_pixel_source_buffer
[13:23:52] [PASSED] single_pixel_clip_rectangle
[13:23:52] [PASSED] well_known_colors
[13:23:52] [PASSED] destination_pitch
[13:23:52] ================ [PASSED] drm_test_fb_swab =================
[13:23:52] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[13:23:52] [PASSED] single_pixel_source_buffer
[13:23:52] [PASSED] single_pixel_clip_rectangle
[13:23:52] [PASSED] well_known_colors
[13:23:52] [PASSED] destination_pitch
[13:23:52] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[13:23:52] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[13:23:52] [PASSED] single_pixel_source_buffer
[13:23:52] [PASSED] single_pixel_clip_rectangle
[13:23:52] [PASSED] well_known_colors
[13:23:52] [PASSED] destination_pitch
[13:23:52] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[13:23:52] ================= drm_test_fb_clip_offset  =================
[13:23:52] [PASSED] pass through
[13:23:52] [PASSED] horizontal offset
[13:23:52] [PASSED] vertical offset
[13:23:52] [PASSED] horizontal and vertical offset
[13:23:52] [PASSED] horizontal offset (custom pitch)
[13:23:52] [PASSED] vertical offset (custom pitch)
[13:23:52] [PASSED] horizontal and vertical offset (custom pitch)
[13:23:52] ============= [PASSED] drm_test_fb_clip_offset =============
[13:23:52] ============== drm_test_fb_build_fourcc_list  ==============
[13:23:52] [PASSED] no native formats
[13:23:52] [PASSED] XRGB8888 as native format
[13:23:52] [PASSED] remove duplicates
[13:23:52] [PASSED] convert alpha formats
[13:23:52] [PASSED] random formats
[13:23:52] ========== [PASSED] drm_test_fb_build_fourcc_list ==========
[13:23:52] =================== drm_test_fb_memcpy  ====================
[13:23:52] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[13:23:52] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[13:23:52] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[13:23:52] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[13:23:52] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[13:23:52] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[13:23:52] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[13:23:52] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[13:23:52] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[13:23:52] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[13:23:52] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[13:23:52] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[13:23:52] =============== [PASSED] drm_test_fb_memcpy ================
[13:23:52] ============= [PASSED] drm_format_helper_test ==============
[13:23:52] ================= drm_format (18 subtests) =================
[13:23:52] [PASSED] drm_test_format_block_width_invalid
[13:23:52] [PASSED] drm_test_format_block_width_one_plane
[13:23:52] [PASSED] drm_test_format_block_width_two_plane
[13:23:52] [PASSED] drm_test_format_block_width_three_plane
[13:23:52] [PASSED] drm_test_format_block_width_tiled
[13:23:52] [PASSED] drm_test_format_block_height_invalid
[13:23:52] [PASSED] drm_test_format_block_height_one_plane
[13:23:52] [PASSED] drm_test_format_block_height_two_plane
[13:23:52] [PASSED] drm_test_format_block_height_three_plane
[13:23:52] [PASSED] drm_test_format_block_height_tiled
[13:23:52] [PASSED] drm_test_format_min_pitch_invalid
[13:23:52] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[13:23:52] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[13:23:52] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[13:23:52] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[13:23:52] [PASSED] drm_test_format_min_pitch_two_plane
[13:23:52] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[13:23:52] [PASSED] drm_test_format_min_pitch_tiled
[13:23:52] =================== [PASSED] drm_format ====================
[13:23:52] ============== drm_framebuffer (10 subtests) ===============
[13:23:52] ========== drm_test_framebuffer_check_src_coords  ==========
[13:23:52] [PASSED] Success: source fits into fb
[13:23:52] [PASSED] Fail: overflowing fb with x-axis coordinate
[13:23:52] [PASSED] Fail: overflowing fb with y-axis coordinate
[13:23:52] [PASSED] Fail: overflowing fb with source width
[13:23:52] [PASSED] Fail: overflowing fb with source height
[13:23:52] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[13:23:52] [PASSED] drm_test_framebuffer_cleanup
[13:23:52] =============== drm_test_framebuffer_create  ===============
[13:23:52] [PASSED] ABGR8888 normal sizes
[13:23:52] [PASSED] ABGR8888 max sizes
[13:23:52] [PASSED] ABGR8888 pitch greater than min required
[13:23:52] [PASSED] ABGR8888 pitch less than min required
[13:23:52] [PASSED] ABGR8888 Invalid width
[13:23:52] [PASSED] ABGR8888 Invalid buffer handle
[13:23:52] [PASSED] No pixel format
[13:23:52] [PASSED] ABGR8888 Width 0
[13:23:52] [PASSED] ABGR8888 Height 0
[13:23:52] [PASSED] ABGR8888 Out of bound height * pitch combination
[13:23:52] [PASSED] ABGR8888 Large buffer offset
[13:23:52] [PASSED] ABGR8888 Buffer offset for inexistent plane
[13:23:52] [PASSED] ABGR8888 Invalid flag
[13:23:52] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[13:23:52] [PASSED] ABGR8888 Valid buffer modifier
[13:23:52] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[13:23:52] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[13:23:52] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[13:23:52] [PASSED] NV12 Normal sizes
[13:23:52] [PASSED] NV12 Max sizes
[13:23:52] [PASSED] NV12 Invalid pitch
[13:23:52] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[13:23:52] [PASSED] NV12 different  modifier per-plane
[13:23:52] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[13:23:52] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[13:23:52] [PASSED] NV12 Modifier for inexistent plane
[13:23:52] [PASSED] NV12 Handle for inexistent plane
[13:23:52] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[13:23:52] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[13:23:52] [PASSED] YVU420 Normal sizes
[13:23:52] [PASSED] YVU420 Max sizes
[13:23:52] [PASSED] YVU420 Invalid pitch
[13:23:52] [PASSED] YVU420 Different pitches
[13:23:52] [PASSED] YVU420 Different buffer offsets/pitches
[13:23:52] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[13:23:52] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[13:23:52] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[13:23:52] [PASSED] YVU420 Valid modifier
[13:23:52] [PASSED] YVU420 Different modifiers per plane
[13:23:52] [PASSED] YVU420 Modifier for inexistent plane
[13:23:52] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[13:23:52] [PASSED] X0L2 Normal sizes
[13:23:52] [PASSED] X0L2 Max sizes
[13:23:52] [PASSED] X0L2 Invalid pitch
[13:23:52] [PASSED] X0L2 Pitch greater than minimum required
[13:23:52] [PASSED] X0L2 Handle for inexistent plane
[13:23:52] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[13:23:52] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[13:23:52] [PASSED] X0L2 Valid modifier
[13:23:52] [PASSED] X0L2 Modifier for inexistent plane
[13:23:52] =========== [PASSED] drm_test_framebuffer_create ===========
[13:23:52] [PASSED] drm_test_framebuffer_free
[13:23:52] [PASSED] drm_test_framebuffer_init
[13:23:52] [PASSED] drm_test_framebuffer_init_bad_format
[13:23:52] [PASSED] drm_test_framebuffer_init_dev_mismatch
[13:23:52] [PASSED] drm_test_framebuffer_lookup
[13:23:52] [PASSED] drm_test_framebuffer_lookup_inexistent
[13:23:52] [PASSED] drm_test_framebuffer_modifiers_not_supported
[13:23:52] ================= [PASSED] drm_framebuffer =================
[13:23:52] ================ drm_gem_shmem (8 subtests) ================
[13:23:52] [PASSED] drm_gem_shmem_test_obj_create
[13:23:52] [PASSED] drm_gem_shmem_test_obj_create_private
[13:23:52] [PASSED] drm_gem_shmem_test_pin_pages
[13:23:52] [PASSED] drm_gem_shmem_test_vmap
[13:23:52] [PASSED] drm_gem_shmem_test_get_pages_sgt
[13:23:52] [PASSED] drm_gem_shmem_test_get_sg_table
[13:23:52] [PASSED] drm_gem_shmem_test_madvise
[13:23:52] [PASSED] drm_gem_shmem_test_purge
[13:23:52] ================== [PASSED] drm_gem_shmem ==================
[13:23:52] === drm_atomic_helper_connector_hdmi_check (22 subtests) ===
[13:23:52] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[13:23:52] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[13:23:52] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[13:23:52] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[13:23:52] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[13:23:52] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[13:23:52] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[13:23:52] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[13:23:52] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[13:23:52] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback
[13:23:52] [PASSED] drm_test_check_max_tmds_rate_format_fallback
[13:23:52] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[13:23:52] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[13:23:52] [PASSED] drm_test_check_output_bpc_dvi
[13:23:52] [PASSED] drm_test_check_output_bpc_format_vic_1
[13:23:52] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[13:23:52] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[13:23:52] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[13:23:52] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[13:23:52] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[13:23:52] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[13:23:52] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[13:23:52] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[13:23:52] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[13:23:52] [PASSED] drm_test_check_broadcast_rgb_value
[13:23:52] [PASSED] drm_test_check_bpc_8_value
[13:23:52] [PASSED] drm_test_check_bpc_10_value
[13:23:52] [PASSED] drm_test_check_bpc_12_value
[13:23:52] [PASSED] drm_test_check_format_value
[13:23:52] [PASSED] drm_test_check_tmds_char_value
[13:23:52] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[13:23:52] ================= drm_managed (2 subtests) =================
[13:23:52] [PASSED] drm_test_managed_release_action
[13:23:52] [PASSED] drm_test_managed_run_action
[13:23:52] =================== [PASSED] drm_managed ===================
[13:23:52] =================== drm_mm (6 subtests) ====================
[13:23:52] [PASSED] drm_test_mm_init
[13:23:52] [PASSED] drm_test_mm_debug
[13:23:52] [PASSED] drm_test_mm_align32
[13:23:52] [PASSED] drm_test_mm_align64
[13:23:52] [PASSED] drm_test_mm_lowest
[13:23:52] [PASSED] drm_test_mm_highest
[13:23:52] ===================== [PASSED] drm_mm ======================
[13:23:52] ============= drm_modes_analog_tv (5 subtests) =============
[13:23:52] [PASSED] drm_test_modes_analog_tv_mono_576i
[13:23:52] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[13:23:52] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[13:23:52] [PASSED] drm_test_modes_analog_tv_pal_576i
[13:23:52] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[13:23:52] =============== [PASSED] drm_modes_analog_tv ===============
stty: 'standard input': Inappropriate ioctl for device
[13:23:52] ============== drm_plane_helper (2 subtests) ===============
[13:23:52] =============== drm_test_check_plane_state  ================
[13:23:52] [PASSED] clipping_simple
[13:23:52] [PASSED] clipping_rotate_reflect
[13:23:52] [PASSED] positioning_simple
[13:23:52] [PASSED] upscaling
[13:23:52] [PASSED] downscaling
[13:23:52] [PASSED] rounding1
[13:23:52] [PASSED] rounding2
[13:23:52] [PASSED] rounding3
[13:23:52] [PASSED] rounding4
[13:23:52] =========== [PASSED] drm_test_check_plane_state ============
[13:23:52] =========== drm_test_check_invalid_plane_state  ============
[13:23:52] [PASSED] positioning_invalid
[13:23:52] [PASSED] upscaling_invalid
[13:23:52] [PASSED] downscaling_invalid
[13:23:52] ======= [PASSED] drm_test_check_invalid_plane_state ========
[13:23:52] ================ [PASSED] drm_plane_helper =================
[13:23:52] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[13:23:52] ====== drm_test_connector_helper_tv_get_modes_check  =======
[13:23:52] [PASSED] None
[13:23:52] [PASSED] PAL
[13:23:52] [PASSED] NTSC
[13:23:52] [PASSED] Both, NTSC Default
[13:23:52] [PASSED] Both, PAL Default
[13:23:52] [PASSED] Both, NTSC Default, with PAL on command-line
[13:23:52] [PASSED] Both, PAL Default, with NTSC on command-line
[13:23:52] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[13:23:52] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[13:23:52] ================== drm_rect (9 subtests) ===================
[13:23:52] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[13:23:52] [PASSED] drm_test_rect_clip_scaled_not_clipped
[13:23:52] [PASSED] drm_test_rect_clip_scaled_clipped
[13:23:52] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[13:23:52] ================= drm_test_rect_intersect  =================
[13:23:52] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[13:23:52] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[13:23:52] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[13:23:52] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[13:23:52] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[13:23:52] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[13:23:52] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[13:23:52] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[13:23:52] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[13:23:52] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[13:23:52] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[13:23:52] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[13:23:52] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[13:23:52] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[13:23:52] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[13:23:52] ============= [PASSED] drm_test_rect_intersect =============
[13:23:52] ================ drm_test_rect_calc_hscale  ================
[13:23:52] [PASSED] normal use
[13:23:52] [PASSED] out of max range
[13:23:52] [PASSED] out of min range
[13:23:52] [PASSED] zero dst
[13:23:52] [PASSED] negative src
[13:23:52] [PASSED] negative dst
[13:23:52] ============ [PASSED] drm_test_rect_calc_hscale ============
[13:23:52] ================ drm_test_rect_calc_vscale  ================
[13:23:52] [PASSED] normal use
[13:23:52] [PASSED] out of max range
[13:23:52] [PASSED] out of min range
[13:23:52] [PASSED] zero dst
[13:23:52] [PASSED] negative src
[13:23:52] [PASSED] negative dst
[13:23:52] ============ [PASSED] drm_test_rect_calc_vscale ============
[13:23:52] ================== drm_test_rect_rotate  ===================
[13:23:52] [PASSED] reflect-x
[13:23:52] [PASSED] reflect-y
[13:23:52] [PASSED] rotate-0
[13:23:52] [PASSED] rotate-90
[13:23:52] [PASSED] rotate-180
[13:23:52] [PASSED] rotate-270
[13:23:52] ============== [PASSED] drm_test_rect_rotate ===============
[13:23:52] ================ drm_test_rect_rotate_inv  =================
[13:23:52] [PASSED] reflect-x
[13:23:52] [PASSED] reflect-y
[13:23:52] [PASSED] rotate-0
[13:23:52] [PASSED] rotate-90
[13:23:52] [PASSED] rotate-180
[13:23:52] [PASSED] rotate-270
[13:23:52] ============ [PASSED] drm_test_rect_rotate_inv =============
[13:23:52] ==================== [PASSED] drm_rect =====================
[13:23:52] ============================================================
[13:23:52] Testing complete. Ran 526 tests: passed: 526
[13:23:52] Elapsed time: 24.389s total, 1.669s configuring, 22.551s building, 0.167s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[13:23:52] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[13:23:54] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json ARCH=um O=.kunit --jobs=48
[13:24:01] Starting KUnit Kernel (1/1)...
[13:24:01] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[13:24:01] ================= ttm_device (5 subtests) ==================
[13:24:01] [PASSED] ttm_device_init_basic
[13:24:01] [PASSED] ttm_device_init_multiple
[13:24:01] [PASSED] ttm_device_fini_basic
[13:24:01] [PASSED] ttm_device_init_no_vma_man
[13:24:01] ================== ttm_device_init_pools  ==================
[13:24:01] [PASSED] No DMA allocations, no DMA32 required
[13:24:01] [PASSED] DMA allocations, DMA32 required
[13:24:01] [PASSED] No DMA allocations, DMA32 required
[13:24:01] [PASSED] DMA allocations, no DMA32 required
[13:24:01] ============== [PASSED] ttm_device_init_pools ==============
[13:24:01] =================== [PASSED] ttm_device ====================
[13:24:01] ================== ttm_pool (8 subtests) ===================
[13:24:01] ================== ttm_pool_alloc_basic  ===================
[13:24:01] [PASSED] One page
[13:24:01] [PASSED] More than one page
[13:24:01] [PASSED] Above the allocation limit
[13:24:01] [PASSED] One page, with coherent DMA mappings enabled
[13:24:01] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[13:24:01] ============== [PASSED] ttm_pool_alloc_basic ===============
[13:24:01] ============== ttm_pool_alloc_basic_dma_addr  ==============
[13:24:01] [PASSED] One page
[13:24:01] [PASSED] More than one page
[13:24:01] [PASSED] Above the allocation limit
[13:24:01] [PASSED] One page, with coherent DMA mappings enabled
[13:24:01] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[13:24:01] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[13:24:01] [PASSED] ttm_pool_alloc_order_caching_match
[13:24:01] [PASSED] ttm_pool_alloc_caching_mismatch
[13:24:01] [PASSED] ttm_pool_alloc_order_mismatch
[13:24:01] [PASSED] ttm_pool_free_dma_alloc
[13:24:01] [PASSED] ttm_pool_free_no_dma_alloc
[13:24:01] [PASSED] ttm_pool_fini_basic
[13:24:01] ==================== [PASSED] ttm_pool =====================
[13:24:01] ================ ttm_resource (8 subtests) =================
[13:24:01] ================= ttm_resource_init_basic  =================
[13:24:01] [PASSED] Init resource in TTM_PL_SYSTEM
[13:24:01] [PASSED] Init resource in TTM_PL_VRAM
[13:24:01] [PASSED] Init resource in a private placement
[13:24:01] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[13:24:01] ============= [PASSED] ttm_resource_init_basic =============
[13:24:01] [PASSED] ttm_resource_init_pinned
[13:24:01] [PASSED] ttm_resource_fini_basic
[13:24:01] [PASSED] ttm_resource_manager_init_basic
[13:24:01] [PASSED] ttm_resource_manager_usage_basic
[13:24:01] [PASSED] ttm_resource_manager_set_used_basic
[13:24:01] [PASSED] ttm_sys_man_alloc_basic
[13:24:01] [PASSED] ttm_sys_man_free_basic
[13:24:01] ================== [PASSED] ttm_resource ===================
[13:24:01] =================== ttm_tt (15 subtests) ===================
[13:24:01] ==================== ttm_tt_init_basic  ====================
[13:24:01] [PASSED] Page-aligned size
[13:24:01] [PASSED] Extra pages requested
[13:24:01] ================ [PASSED] ttm_tt_init_basic ================
[13:24:01] [PASSED] ttm_tt_init_misaligned
[13:24:01] [PASSED] ttm_tt_fini_basic
[13:24:01] [PASSED] ttm_tt_fini_sg
[13:24:01] [PASSED] ttm_tt_fini_shmem
[13:24:01] [PASSED] ttm_tt_create_basic
[13:24:01] [PASSED] ttm_tt_create_invalid_bo_type
[13:24:01] [PASSED] ttm_tt_create_ttm_exists
[13:24:01] [PASSED] ttm_tt_create_failed
[13:24:01] [PASSED] ttm_tt_destroy_basic
[13:24:01] [PASSED] ttm_tt_populate_null_ttm
[13:24:01] [PASSED] ttm_tt_populate_populated_ttm
[13:24:01] [PASSED] ttm_tt_unpopulate_basic
[13:24:01] [PASSED] ttm_tt_unpopulate_empty_ttm
[13:24:01] [PASSED] ttm_tt_swapin_basic
[13:24:01] ===================== [PASSED] ttm_tt ======================
[13:24:01] =================== ttm_bo (14 subtests) ===================
[13:24:01] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[13:24:01] [PASSED] Cannot be interrupted and sleeps
[13:24:01] [PASSED] Cannot be interrupted, locks straight away
[13:24:01] [PASSED] Can be interrupted, sleeps
[13:24:01] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[13:24:01] [PASSED] ttm_bo_reserve_locked_no_sleep
[13:24:01] [PASSED] ttm_bo_reserve_no_wait_ticket
[13:24:01] [PASSED] ttm_bo_reserve_double_resv
[13:24:01] [PASSED] ttm_bo_reserve_interrupted
[13:24:01] [PASSED] ttm_bo_reserve_deadlock
[13:24:01] [PASSED] ttm_bo_unreserve_basic
[13:24:01] [PASSED] ttm_bo_unreserve_pinned
[13:24:01] [PASSED] ttm_bo_unreserve_bulk
[13:24:01] [PASSED] ttm_bo_put_basic
[13:24:01] [PASSED] ttm_bo_put_shared_resv
[13:24:01] [PASSED] ttm_bo_pin_basic
[13:24:01] [PASSED] ttm_bo_pin_unpin_resource
[13:24:01] [PASSED] ttm_bo_multiple_pin_one_unpin
[13:24:01] ===================== [PASSED] ttm_bo ======================
[13:24:01] ============== ttm_bo_validate (22 subtests) ===============
[13:24:01] ============== ttm_bo_init_reserved_sys_man  ===============
[13:24:01] [PASSED] Buffer object for userspace
[13:24:01] [PASSED] Kernel buffer object
[13:24:01] [PASSED] Shared buffer object
[13:24:01] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[13:24:01] ============== ttm_bo_init_reserved_mock_man  ==============
[13:24:01] [PASSED] Buffer object for userspace
[13:24:01] [PASSED] Kernel buffer object
[13:24:01] [PASSED] Shared buffer object
[13:24:01] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[13:24:01] [PASSED] ttm_bo_init_reserved_resv
[13:24:01] ================== ttm_bo_validate_basic  ==================
[13:24:01] [PASSED] Buffer object for userspace
[13:24:01] [PASSED] Kernel buffer object
[13:24:01] [PASSED] Shared buffer object
[13:24:01] ============== [PASSED] ttm_bo_validate_basic ==============
[13:24:01] [PASSED] ttm_bo_validate_invalid_placement
[13:24:01] ============= ttm_bo_validate_same_placement  ==============
[13:24:01] [PASSED] System manager
[13:24:01] [PASSED] VRAM manager
[13:24:01] ========= [PASSED] ttm_bo_validate_same_placement ==========
[13:24:01] [PASSED] ttm_bo_validate_failed_alloc
[13:24:01] [PASSED] ttm_bo_validate_pinned
[13:24:01] [PASSED] ttm_bo_validate_busy_placement
[13:24:01] ================ ttm_bo_validate_multihop  =================
[13:24:01] [PASSED] Buffer object for userspace
[13:24:01] [PASSED] Kernel buffer object
[13:24:01] [PASSED] Shared buffer object
[13:24:01] ============ [PASSED] ttm_bo_validate_multihop =============
[13:24:01] ========== ttm_bo_validate_no_placement_signaled  ==========
[13:24:01] [PASSED] Buffer object in system domain, no page vector
[13:24:01] [PASSED] Buffer object in system domain with an existing page vector
[13:24:01] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[13:24:01] ======== ttm_bo_validate_no_placement_not_signaled  ========
[13:24:01] [PASSED] Buffer object for userspace
[13:24:01] [PASSED] Kernel buffer object
[13:24:01] [PASSED] Shared buffer object
[13:24:01] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[13:24:01] [PASSED] ttm_bo_validate_move_fence_signaled
[13:24:01] ========= ttm_bo_validate_move_fence_not_signaled  =========
[13:24:01] [PASSED] Waits for GPU
[13:24:01] [PASSED] Tries to lock straight away
[13:24:02] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[13:24:02] [PASSED] ttm_bo_validate_swapout
[13:24:02] [PASSED] ttm_bo_validate_happy_evict
[13:24:02] [PASSED] ttm_bo_validate_all_pinned_evict
[13:24:02] [PASSED] ttm_bo_validate_allowed_only_evict
[13:24:02] [PASSED] ttm_bo_validate_deleted_evict
[13:24:02] [PASSED] ttm_bo_validate_busy_domain_evict
[13:24:02] [PASSED] ttm_bo_validate_evict_gutting
[13:24:02] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[13:24:02] ================= [PASSED] ttm_bo_validate =================
[13:24:02] ============================================================
[13:24:02] Testing complete. Ran 102 tests: passed: 102
[13:24:02] Elapsed time: 9.792s total, 1.582s configuring, 7.541s building, 0.555s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ CI.Build: success for Add support for EU stall sampling

[Patchwork]

== Series Details ==

Series: Add support for EU stall sampling
URL   : https://patchwork.freedesktop.org/series/141483/
State : success

== Summary ==

lib/modules/6.12.0-xe/kernel/arch/x86/events/rapl.ko
lib/modules/6.12.0-xe/kernel/arch/x86/kvm/
lib/modules/6.12.0-xe/kernel/arch/x86/kvm/kvm.ko
lib/modules/6.12.0-xe/kernel/arch/x86/kvm/kvm-intel.ko
lib/modules/6.12.0-xe/kernel/arch/x86/kvm/kvm-amd.ko
lib/modules/6.12.0-xe/kernel/kernel/
lib/modules/6.12.0-xe/kernel/kernel/kheaders.ko
lib/modules/6.12.0-xe/kernel/crypto/
lib/modules/6.12.0-xe/kernel/crypto/ecrdsa_generic.ko
lib/modules/6.12.0-xe/kernel/crypto/xcbc.ko
lib/modules/6.12.0-xe/kernel/crypto/serpent_generic.ko
lib/modules/6.12.0-xe/kernel/crypto/aria_generic.ko
lib/modules/6.12.0-xe/kernel/crypto/crypto_simd.ko
lib/modules/6.12.0-xe/kernel/crypto/adiantum.ko
lib/modules/6.12.0-xe/kernel/crypto/tcrypt.ko
lib/modules/6.12.0-xe/kernel/crypto/crypto_engine.ko
lib/modules/6.12.0-xe/kernel/crypto/zstd.ko
lib/modules/6.12.0-xe/kernel/crypto/asymmetric_keys/
lib/modules/6.12.0-xe/kernel/crypto/asymmetric_keys/pkcs7_test_key.ko
lib/modules/6.12.0-xe/kernel/crypto/asymmetric_keys/pkcs8_key_parser.ko
lib/modules/6.12.0-xe/kernel/crypto/des_generic.ko
lib/modules/6.12.0-xe/kernel/crypto/xctr.ko
lib/modules/6.12.0-xe/kernel/crypto/authenc.ko
lib/modules/6.12.0-xe/kernel/crypto/sm4_generic.ko
lib/modules/6.12.0-xe/kernel/crypto/keywrap.ko
lib/modules/6.12.0-xe/kernel/crypto/camellia_generic.ko
lib/modules/6.12.0-xe/kernel/crypto/sm3.ko
lib/modules/6.12.0-xe/kernel/crypto/pcrypt.ko
lib/modules/6.12.0-xe/kernel/crypto/aegis128.ko
lib/modules/6.12.0-xe/kernel/crypto/af_alg.ko
lib/modules/6.12.0-xe/kernel/crypto/algif_aead.ko
lib/modules/6.12.0-xe/kernel/crypto/cmac.ko
lib/modules/6.12.0-xe/kernel/crypto/sm3_generic.ko
lib/modules/6.12.0-xe/kernel/crypto/aes_ti.ko
lib/modules/6.12.0-xe/kernel/crypto/chacha_generic.ko
lib/modules/6.12.0-xe/kernel/crypto/poly1305_generic.ko
lib/modules/6.12.0-xe/kernel/crypto/nhpoly1305.ko
lib/modules/6.12.0-xe/kernel/crypto/crc32_generic.ko
lib/modules/6.12.0-xe/kernel/crypto/essiv.ko
lib/modules/6.12.0-xe/kernel/crypto/ccm.ko
lib/modules/6.12.0-xe/kernel/crypto/wp512.ko
lib/modules/6.12.0-xe/kernel/crypto/streebog_generic.ko
lib/modules/6.12.0-xe/kernel/crypto/authencesn.ko
lib/modules/6.12.0-xe/kernel/crypto/echainiv.ko
lib/modules/6.12.0-xe/kernel/crypto/lrw.ko
lib/modules/6.12.0-xe/kernel/crypto/cryptd.ko
lib/modules/6.12.0-xe/kernel/crypto/crypto_user.ko
lib/modules/6.12.0-xe/kernel/crypto/algif_hash.ko
lib/modules/6.12.0-xe/kernel/crypto/vmac.ko
lib/modules/6.12.0-xe/kernel/crypto/polyval-generic.ko
lib/modules/6.12.0-xe/kernel/crypto/hctr2.ko
lib/modules/6.12.0-xe/kernel/crypto/842.ko
lib/modules/6.12.0-xe/kernel/crypto/pcbc.ko
lib/modules/6.12.0-xe/kernel/crypto/ansi_cprng.ko
lib/modules/6.12.0-xe/kernel/crypto/cast6_generic.ko
lib/modules/6.12.0-xe/kernel/crypto/twofish_common.ko
lib/modules/6.12.0-xe/kernel/crypto/twofish_generic.ko
lib/modules/6.12.0-xe/kernel/crypto/lz4hc.ko
lib/modules/6.12.0-xe/kernel/crypto/blowfish_generic.ko
lib/modules/6.12.0-xe/kernel/crypto/md4.ko
lib/modules/6.12.0-xe/kernel/crypto/chacha20poly1305.ko
lib/modules/6.12.0-xe/kernel/crypto/curve25519-generic.ko
lib/modules/6.12.0-xe/kernel/crypto/lz4.ko
lib/modules/6.12.0-xe/kernel/crypto/rmd160.ko
lib/modules/6.12.0-xe/kernel/crypto/algif_skcipher.ko
lib/modules/6.12.0-xe/kernel/crypto/cast5_generic.ko
lib/modules/6.12.0-xe/kernel/crypto/fcrypt.ko
lib/modules/6.12.0-xe/kernel/crypto/ecdsa_generic.ko
lib/modules/6.12.0-xe/kernel/crypto/sm4.ko
lib/modules/6.12.0-xe/kernel/crypto/cast_common.ko
lib/modules/6.12.0-xe/kernel/crypto/blowfish_common.ko
lib/modules/6.12.0-xe/kernel/crypto/michael_mic.ko
lib/modules/6.12.0-xe/kernel/crypto/async_tx/
lib/modules/6.12.0-xe/kernel/crypto/async_tx/async_xor.ko
lib/modules/6.12.0-xe/kernel/crypto/async_tx/async_tx.ko
lib/modules/6.12.0-xe/kernel/crypto/async_tx/async_memcpy.ko
lib/modules/6.12.0-xe/kernel/crypto/async_tx/async_pq.ko
lib/modules/6.12.0-xe/kernel/crypto/async_tx/async_raid6_recov.ko
lib/modules/6.12.0-xe/kernel/crypto/algif_rng.ko
lib/modules/6.12.0-xe/kernel/block/
lib/modules/6.12.0-xe/kernel/block/bfq.ko
lib/modules/6.12.0-xe/kernel/block/kyber-iosched.ko
lib/modules/6.12.0-xe/build
lib/modules/6.12.0-xe/modules.alias.bin
lib/modules/6.12.0-xe/modules.builtin
lib/modules/6.12.0-xe/modules.softdep
lib/modules/6.12.0-xe/modules.alias
lib/modules/6.12.0-xe/modules.order
lib/modules/6.12.0-xe/modules.symbols
lib/modules/6.12.0-xe/modules.dep.bin
+ mv kernel-nodebug.tar.gz ..
+ cd ..
+ rm -rf archive
++ date +%s
^[[0Ksection_end:1731937348:package_x86_64_nodebug
^[[0K
+ echo -e '\e[0Ksection_end:1731937348:package_x86_64_nodebug\r\e[0K'
+ sync
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ CI.Hooks: failure for Add support for EU stall sampling

[Patchwork]

== Series Details ==

Series: Add support for EU stall sampling
URL   : https://patchwork.freedesktop.org/series/141483/
State : failure

== Summary ==

run-parts: executing /workspace/ci/hooks/00-showenv
+ export
+ grep -Ei '(^|\W)CI_'
declare -x CI_KERNEL_BUILD_DIR="/workspace/kernel/build64-default"
declare -x CI_KERNEL_SRC_DIR="/workspace/kernel"
declare -x CI_TOOLS_SRC_DIR="/workspace/ci"
declare -x CI_WORKSPACE_DIR="/workspace"
run-parts: executing /workspace/ci/hooks/10-build-W1
+ SRC_DIR=/workspace/kernel
+ RESTORE_DISPLAY_CONFIG=0
+ '[' -n /workspace/kernel/build64-default ']'
+ BUILD_DIR=/workspace/kernel/build64-default
+ cd /workspace/kernel
++ nproc
+ make -j48 O=/workspace/kernel/build64-default modules_prepare
make[1]: Entering directory '/workspace/kernel/build64-default'
  GEN     Makefile
  UPD     include/config/kernel.release
mkdir -p /workspace/kernel/build64-default/tools/objtool && make O=/workspace/kernel/build64-default subdir=tools/objtool --no-print-directory -C objtool 
  UPD     include/generated/utsrelease.h
  CALL    ../scripts/checksyscalls.sh
  INSTALL libsubcmd_headers
  CC      /workspace/kernel/build64-default/tools/objtool/libsubcmd/exec-cmd.o
  CC      /workspace/kernel/build64-default/tools/objtool/libsubcmd/help.o
  CC      /workspace/kernel/build64-default/tools/objtool/libsubcmd/pager.o
  CC      /workspace/kernel/build64-default/tools/objtool/libsubcmd/parse-options.o
  CC      /workspace/kernel/build64-default/tools/objtool/libsubcmd/run-command.o
  CC      /workspace/kernel/build64-default/tools/objtool/libsubcmd/sigchain.o
  CC      /workspace/kernel/build64-default/tools/objtool/libsubcmd/subcmd-config.o
  LD      /workspace/kernel/build64-default/tools/objtool/libsubcmd/libsubcmd-in.o
  AR      /workspace/kernel/build64-default/tools/objtool/libsubcmd/libsubcmd.a
  CC      /workspace/kernel/build64-default/tools/objtool/weak.o
  CC      /workspace/kernel/build64-default/tools/objtool/check.o
  CC      /workspace/kernel/build64-default/tools/objtool/special.o
  CC      /workspace/kernel/build64-default/tools/objtool/builtin-check.o
  CC      /workspace/kernel/build64-default/tools/objtool/elf.o
  CC      /workspace/kernel/build64-default/tools/objtool/objtool.o
  CC      /workspace/kernel/build64-default/tools/objtool/orc_gen.o
  CC      /workspace/kernel/build64-default/tools/objtool/orc_dump.o
  CC      /workspace/kernel/build64-default/tools/objtool/libstring.o
  CC      /workspace/kernel/build64-default/tools/objtool/libctype.o
  CC      /workspace/kernel/build64-default/tools/objtool/str_error_r.o
  CC      /workspace/kernel/build64-default/tools/objtool/arch/x86/special.o
  CC      /workspace/kernel/build64-default/tools/objtool/librbtree.o
  CC      /workspace/kernel/build64-default/tools/objtool/arch/x86/decode.o
  CC      /workspace/kernel/build64-default/tools/objtool/arch/x86/orc.o
  LD      /workspace/kernel/build64-default/tools/objtool/arch/x86/objtool-in.o
  LD      /workspace/kernel/build64-default/tools/objtool/objtool-in.o
  LINK    /workspace/kernel/build64-default/tools/objtool/objtool
make[1]: Leaving directory '/workspace/kernel/build64-default'
++ nproc
+ make -j48 O=/workspace/kernel/build64-default W=1 drivers/gpu/drm/xe
make[1]: Entering directory '/workspace/kernel/build64-default'
make[2]: Nothing to be done for 'drivers/gpu/drm/xe'.
make[1]: Leaving directory '/workspace/kernel/build64-default'
run-parts: executing /workspace/ci/hooks/11-build-32b
+++ realpath /workspace/ci/hooks/11-build-32b
++ dirname /workspace/ci/hooks/11-build-32b
+ THIS_SCRIPT_DIR=/workspace/ci/hooks
+ SRC_DIR=/workspace/kernel
+ TOOLS_SRC_DIR=/workspace/ci
+ '[' -n /workspace/kernel/build64-default ']'
+ BUILD_DIR=/workspace/kernel/build64-default
+ BUILD_DIR=/workspace/kernel/build64-default/build32
+ cd /workspace/kernel
+ mkdir -p /workspace/kernel/build64-default/build32
++ nproc
+ make -j48 ARCH=i386 O=/workspace/kernel/build64-default/build32 defconfig
make[1]: Entering directory '/workspace/kernel/build64-default/build32'
  GEN     Makefile
  HOSTCC  scripts/basic/fixdep
  HOSTCC  scripts/kconfig/conf.o
  HOSTCC  scripts/kconfig/confdata.o
  HOSTCC  scripts/kconfig/expr.o
  LEX     scripts/kconfig/lexer.lex.c
  YACC    scripts/kconfig/parser.tab.[ch]
  HOSTCC  scripts/kconfig/menu.o
  HOSTCC  scripts/kconfig/preprocess.o
  HOSTCC  scripts/kconfig/symbol.o
  HOSTCC  scripts/kconfig/util.o
  HOSTCC  scripts/kconfig/lexer.lex.o
  HOSTCC  scripts/kconfig/parser.tab.o
  HOSTLD  scripts/kconfig/conf
*** Default configuration is based on 'i386_defconfig'
#
# configuration written to .config
#
make[1]: Leaving directory '/workspace/kernel/build64-default/build32'
+ cd /workspace/kernel/build64-default/build32
+ /workspace/kernel/scripts/kconfig/merge_config.sh .config /workspace/ci/kernel/10-xe.fragment
Using .config as base
Merging /workspace/ci/kernel/10-xe.fragment
The merge file '/workspace/ci/kernel/10-xe.fragment' does not exist.  Exit.
run-parts: /workspace/ci/hooks/11-build-32b exited with return code 1

✓ CI.checksparse: success for Add support for EU stall sampling

[Patchwork]

== Series Details ==

Series: Add support for EU stall sampling
URL   : https://patchwork.freedesktop.org/series/141483/
State : success

== Summary ==

+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast 90014f8026e31874d368834834253debd131268b
/root/linux/maintainer-tools/dim: line 2068: sparse: command not found
Sparse version: 
Fast mode used, each commit won't be checked separately.
Okay!

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ CI.BAT: success for Add support for EU stall sampling

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 6888 bytes --]

== Series Details ==

Series: Add support for EU stall sampling
URL   : https://patchwork.freedesktop.org/series/141483/
State : success

== Summary ==

CI Bug Log - changes from xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f_BAT -> xe-pw-141483v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (9 -> 9)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-141483v1_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_frontbuffer_tracking@basic:
    - bat-adlp-7:         [PASS][1] -> [DMESG-FAIL][2] ([Intel XE#1033])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/bat-adlp-7/igt@kms_frontbuffer_tracking@basic.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/bat-adlp-7/igt@kms_frontbuffer_tracking@basic.html

  * igt@xe_exec_balancer@twice-cm-virtual-userptr-rebind:
    - bat-adlp-vf:        [PASS][3] -> [DMESG-WARN][4] ([Intel XE#358])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/bat-adlp-vf/igt@xe_exec_balancer@twice-cm-virtual-userptr-rebind.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/bat-adlp-vf/igt@xe_exec_balancer@twice-cm-virtual-userptr-rebind.html

  * igt@xe_live_ktest@xe_migrate:
    - bat-adlp-vf:        [PASS][5] -> [SKIP][6] ([Intel XE#1192]) +1 other test skip
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/bat-adlp-vf/igt@xe_live_ktest@xe_migrate.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/bat-adlp-vf/igt@xe_live_ktest@xe_migrate.html

  
#### Possible fixes ####

  * igt@kms_flip@basic-flip-vs-wf_vblank:
    - bat-lnl-1:          [FAIL][7] ([Intel XE#886]) -> [PASS][8] +1 other test pass
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/bat-lnl-1/igt@kms_flip@basic-flip-vs-wf_vblank.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/bat-lnl-1/igt@kms_flip@basic-flip-vs-wf_vblank.html

  * igt@xe_exec_threads@threads-mixed-shared-vm-basic:
    - bat-pvc-2:          [DMESG-WARN][9] ([Intel XE#3371]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/bat-pvc-2/igt@xe_exec_threads@threads-mixed-shared-vm-basic.html
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/bat-pvc-2/igt@xe_exec_threads@threads-mixed-shared-vm-basic.html

  
#### Warnings ####

  * igt@xe_live_ktest@xe_bo:
    - bat-adlp-vf:        [SKIP][11] ([Intel XE#2229] / [Intel XE#455]) -> [SKIP][12] ([Intel XE#1192])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/bat-adlp-vf/igt@xe_live_ktest@xe_bo.html
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/bat-adlp-vf/igt@xe_live_ktest@xe_bo.html

  * igt@xe_pat@pat-index-xe2:
    - bat-atsm-2:         [SKIP][13] ([Intel XE#2839] / [Intel XE#977]) -> [SKIP][14] ([Intel XE#977])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/bat-atsm-2/igt@xe_pat@pat-index-xe2.html
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/bat-atsm-2/igt@xe_pat@pat-index-xe2.html
    - bat-adlp-vf:        [SKIP][15] ([Intel XE#2839] / [Intel XE#977]) -> [SKIP][16] ([Intel XE#977])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/bat-adlp-vf/igt@xe_pat@pat-index-xe2.html
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/bat-adlp-vf/igt@xe_pat@pat-index-xe2.html
    - bat-adlp-7:         [SKIP][17] ([Intel XE#2839] / [Intel XE#3443] / [Intel XE#977]) -> [SKIP][18] ([Intel XE#3443] / [Intel XE#977])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/bat-adlp-7/igt@xe_pat@pat-index-xe2.html
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/bat-adlp-7/igt@xe_pat@pat-index-xe2.html
    - bat-dg2-oem2:       [SKIP][19] ([Intel XE#2839] / [Intel XE#977]) -> [SKIP][20] ([Intel XE#977])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/bat-dg2-oem2/igt@xe_pat@pat-index-xe2.html
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/bat-dg2-oem2/igt@xe_pat@pat-index-xe2.html

  * igt@xe_pat@pat-index-xelp:
    - bat-bmg-2:          [SKIP][21] ([Intel XE#2237] / [Intel XE#2245]) -> [SKIP][22] ([Intel XE#2245])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/bat-bmg-2/igt@xe_pat@pat-index-xelp.html
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/bat-bmg-2/igt@xe_pat@pat-index-xelp.html
    - bat-bmg-1:          [SKIP][23] ([Intel XE#2237] / [Intel XE#2245]) -> [SKIP][24] ([Intel XE#2245])
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/bat-bmg-1/igt@xe_pat@pat-index-xelp.html
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/bat-bmg-1/igt@xe_pat@pat-index-xelp.html
    - bat-lnl-2:          [SKIP][25] ([Intel XE#2237] / [Intel XE#977]) -> [SKIP][26] ([Intel XE#977])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/bat-lnl-2/igt@xe_pat@pat-index-xelp.html
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/bat-lnl-2/igt@xe_pat@pat-index-xelp.html

  
  [Intel XE#1033]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1033
  [Intel XE#1192]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1192
  [Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229
  [Intel XE#2237]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2237
  [Intel XE#2245]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2245
  [Intel XE#2839]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2839
  [Intel XE#3371]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3371
  [Intel XE#3443]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3443
  [Intel XE#358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/358
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/886
  [Intel XE#977]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/977


Build changes
-------------

  * Linux: xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f -> xe-pw-141483v1

  IGT_8114: 8114
  xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f: 57639ceec0f66f06f4a8a8ac3b9551b7b493c33f
  xe-pw-141483v1: 141483v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/index.html

[-- Attachment #2: Type: text/html, Size: 8933 bytes --]

✗ CI.FULL: failure for Add support for EU stall sampling

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 117191 bytes --]

== Series Details ==

Series: Add support for EU stall sampling
URL   : https://patchwork.freedesktop.org/series/141483/
State : failure

== Summary ==

CI Bug Log - changes from xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f_full -> xe-pw-141483v1_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-141483v1_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-141483v1_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-141483v1_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [DMESG-WARN][1]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-436/igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-6.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-mc-ccs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][2]
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-mc-ccs.html

  * igt@kms_draw_crc@draw-method-mmap-wc@xrgb2101010-4tiled:
    - shard-bmg:          NOTRUN -> [DMESG-FAIL][3] +4 other tests dmesg-fail
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-7/igt@kms_draw_crc@draw-method-mmap-wc@xrgb2101010-4tiled.html

  * igt@xe_exec_reset@cm-gt-reset:
    - shard-bmg:          [PASS][4] -> [INCOMPLETE][5]
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-bmg-8/igt@xe_exec_reset@cm-gt-reset.html
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-1/igt@xe_exec_reset@cm-gt-reset.html

  * igt@xe_module_load@unload:
    - shard-dg2-set2:     [PASS][6] -> [DMESG-WARN][7]
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@xe_module_load@unload.html
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-433/igt@xe_module_load@unload.html

  * igt@xe_vm@large-userptr-binds-67108864:
    - shard-bmg:          [PASS][8] -> [DMESG-WARN][9] +3 other tests dmesg-warn
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-bmg-5/igt@xe_vm@large-userptr-binds-67108864.html
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-8/igt@xe_vm@large-userptr-binds-67108864.html

  * igt@xe_vm@shared-pde2-page:
    - shard-bmg:          NOTRUN -> [DMESG-WARN][10] +10 other tests dmesg-warn
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-4/igt@xe_vm@shared-pde2-page.html

  
#### Warnings ####

  * igt@core_hotunplug@hotunplug-rescan:
    - shard-bmg:          [INCOMPLETE][11] ([Intel XE#3468]) -> [INCOMPLETE][12]
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-bmg-2/igt@core_hotunplug@hotunplug-rescan.html
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-7/igt@core_hotunplug@hotunplug-rescan.html

  * igt@kms_big_fb@x-tiled-8bpp-rotate-0:
    - shard-dg2-set2:     [SKIP][13] ([Intel XE#2136]) -> [DMESG-WARN][14]
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-433/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs-cc:
    - shard-dg2-set2:     [SKIP][15] ([Intel XE#2136] / [Intel XE#2351]) -> [DMESG-WARN][16]
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs-cc.html
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-436/igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-dg2-set2:     [SKIP][17] ([Intel XE#3442]) -> [SKIP][18]
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-436/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs:
    - shard-dg2-set2:     [SKIP][19] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][20]
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-434/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs.html
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs.html

  * igt@kms_draw_crc@draw-method-mmap-wc@rgb565-4tiled:
    - shard-bmg:          [INCOMPLETE][21] ([Intel XE#3468]) -> [DMESG-FAIL][22]
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-bmg-4/igt@kms_draw_crc@draw-method-mmap-wc@rgb565-4tiled.html
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-7/igt@kms_draw_crc@draw-method-mmap-wc@rgb565-4tiled.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-dg2-set2:     [SKIP][23] ([Intel XE#3309]) -> [SKIP][24]
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-434/igt@kms_pm_dc@dc5-retention-flops.html
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@xe_exec_basic@multigpu-once-basic-defer-bind:
    - shard-dg2-set2:     [SKIP][25] ([Intel XE#1130]) -> [DMESG-WARN][26] +1 other test dmesg-warn
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@xe_exec_basic@multigpu-once-basic-defer-bind.html
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-436/igt@xe_exec_basic@multigpu-once-basic-defer-bind.html

  
Known issues
------------

  Here are the changes found in xe-pw-141483v1_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_getclient:
    - shard-dg2-set2:     [PASS][27] -> [SKIP][28] ([Intel XE#2423])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-464/igt@core_getclient.html
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@core_getclient.html

  * igt@core_hotunplug@hotreplug:
    - shard-dg2-set2:     [PASS][29] -> [SKIP][30] ([Intel XE#1885])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-436/igt@core_hotunplug@hotreplug.html
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@core_hotunplug@hotreplug.html

  * igt@core_setmaster@master-drop-set-root:
    - shard-dg2-set2:     [PASS][31] -> [FAIL][32] ([Intel XE#3130] / [Intel XE#3249])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-434/igt@core_setmaster@master-drop-set-root.html
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@core_setmaster@master-drop-set-root.html

  * igt@kms_atomic_transition@modeset-transition-nonblocking:
    - shard-lnl:          [PASS][33] -> [FAIL][34] ([Intel XE#1701]) +1 other test fail
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-lnl-7/igt@kms_atomic_transition@modeset-transition-nonblocking.html
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-lnl-1/igt@kms_atomic_transition@modeset-transition-nonblocking.html

  * igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1:
    - shard-adlp:         [PASS][35] -> [FAIL][36] ([Intel XE#1426]) +1 other test fail
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-adlp-2/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1.html
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-adlp-4/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][37] ([Intel XE#2327])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-3/igt@kms_big_fb@4-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
    - shard-adlp:         [PASS][38] -> [DMESG-WARN][39] ([Intel XE#1033])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-adlp-3/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-adlp-9/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@yf-tiled-64bpp-rotate-0:
    - shard-bmg:          NOTRUN -> [SKIP][40] ([Intel XE#1124]) +3 other tests skip
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-7/igt@kms_big_fb@yf-tiled-64bpp-rotate-0.html

  * igt@kms_bw@linear-tiling-3-displays-1920x1080p:
    - shard-bmg:          NOTRUN -> [SKIP][41] ([Intel XE#367])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-3/igt@kms_bw@linear-tiling-3-displays-1920x1080p.html

  * igt@kms_ccs@crc-primary-basic-yf-tiled-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#2887]) +2 other tests skip
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-1/igt@kms_ccs@crc-primary-basic-yf-tiled-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [SKIP][43] ([Intel XE#787]) +153 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-464/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-6.html

  * igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-d-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][44] ([Intel XE#455] / [Intel XE#787]) +21 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-433/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-d-dp-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
    - shard-dg2-set2:     [PASS][45] -> [INCOMPLETE][46] ([Intel XE#1195] / [Intel XE#1727])
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html

  * igt@kms_chamelium_edid@dp-edid-resolution-list:
    - shard-bmg:          NOTRUN -> [SKIP][47] ([Intel XE#2252]) +4 other tests skip
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-1/igt@kms_chamelium_edid@dp-edid-resolution-list.html

  * igt@kms_content_protection@lic-type-0@pipe-a-dp-4:
    - shard-dg2-set2:     NOTRUN -> [FAIL][48] ([Intel XE#3304])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-436/igt@kms_content_protection@lic-type-0@pipe-a-dp-4.html

  * igt@kms_content_protection@srm@pipe-a-dp-4:
    - shard-dg2-set2:     NOTRUN -> [FAIL][49] ([Intel XE#1178]) +2 other tests fail
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-463/igt@kms_content_protection@srm@pipe-a-dp-4.html

  * igt@kms_cursor_crc@cursor-offscreen-max-size:
    - shard-bmg:          NOTRUN -> [SKIP][50] ([Intel XE#2320]) +1 other test skip
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-1/igt@kms_cursor_crc@cursor-offscreen-max-size.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
    - shard-bmg:          NOTRUN -> [SKIP][51] ([Intel XE#2286]) +1 other test skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-3/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html

  * igt@kms_feature_discovery@dp-mst:
    - shard-bmg:          NOTRUN -> [SKIP][52] ([Intel XE#2375])
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-7/igt@kms_feature_discovery@dp-mst.html

  * igt@kms_flip@2x-flip-vs-expired-vblank@bd-dp2-hdmi-a3:
    - shard-bmg:          NOTRUN -> [FAIL][53] ([Intel XE#2882])
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-1/igt@kms_flip@2x-flip-vs-expired-vblank@bd-dp2-hdmi-a3.html

  * igt@kms_flip@2x-flip-vs-suspend-interruptible:
    - shard-dg2-set2:     [PASS][54] -> [INCOMPLETE][55] ([Intel XE#1195] / [Intel XE#2049] / [Intel XE#2597])
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-433/igt@kms_flip@2x-flip-vs-suspend-interruptible.html
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-463/igt@kms_flip@2x-flip-vs-suspend-interruptible.html

  * igt@kms_flip@flip-vs-suspend@a-hdmi-a6:
    - shard-dg2-set2:     NOTRUN -> [DMESG-WARN][56] ([Intel XE#3468]) +1 other test dmesg-warn
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-464/igt@kms_flip@flip-vs-suspend@a-hdmi-a6.html

  * igt@kms_flip@flip-vs-suspend@c-hdmi-a6:
    - shard-dg2-set2:     NOTRUN -> [DMESG-FAIL][57] ([Intel XE#3468]) +5 other tests dmesg-fail
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-464/igt@kms_flip@flip-vs-suspend@c-hdmi-a6.html

  * igt@kms_flip@plain-flip-ts-check:
    - shard-bmg:          [PASS][58] -> [FAIL][59] ([Intel XE#2882]) +1 other test fail
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-bmg-1/igt@kms_flip@plain-flip-ts-check.html
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-1/igt@kms_flip@plain-flip-ts-check.html

  * igt@kms_flip@plain-flip-ts-check-interruptible@d-hdmi-a3:
    - shard-bmg:          NOTRUN -> [DMESG-WARN][60] ([Intel XE#3468]) +10 other tests dmesg-warn
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-4/igt@kms_flip@plain-flip-ts-check-interruptible@d-hdmi-a3.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling:
    - shard-dg2-set2:     [PASS][61] -> [SKIP][62] ([Intel XE#2136]) +24 other tests skip
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-435/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling.html
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
    - shard-dg2-set2:     NOTRUN -> [SKIP][63] ([Intel XE#455]) +6 other tests skip
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-463/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][64] ([Intel XE#2311]) +12 other tests skip
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-1/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-fullscreen:
    - shard-dg2-set2:     NOTRUN -> [SKIP][65] ([Intel XE#2136] / [Intel XE#2351]) +7 other tests skip
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt:
    - shard-bmg:          NOTRUN -> [FAIL][66] ([Intel XE#2333])
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-rte:
    - shard-bmg:          NOTRUN -> [DMESG-FAIL][67] ([Intel XE#3468]) +5 other tests dmesg-fail
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-rte.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt:
    - shard-dg2-set2:     [PASS][68] -> [SKIP][69] ([Intel XE#2136] / [Intel XE#2351]) +14 other tests skip
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-464/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc:
    - shard-dg2-set2:     NOTRUN -> [SKIP][70] ([Intel XE#2136]) +27 other tests skip
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-y:
    - shard-bmg:          NOTRUN -> [SKIP][71] ([Intel XE#2352])
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][72] ([Intel XE#2313]) +9 other tests skip
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [PASS][73] -> [SKIP][74] ([Intel XE#1503])
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-bmg-2/igt@kms_hdr@invalid-hdr.html
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-1/igt@kms_hdr@invalid-hdr.html

  * igt@kms_hdr@static-toggle-dpms:
    - shard-dg2-set2:     [PASS][75] -> [INCOMPLETE][76] ([Intel XE#1195]) +3 other tests incomplete
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-436/igt@kms_hdr@static-toggle-dpms.html
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-435/igt@kms_hdr@static-toggle-dpms.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-b:
    - shard-dg2-set2:     NOTRUN -> [SKIP][77] ([Intel XE#2763]) +11 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-433/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-b.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-d:
    - shard-dg2-set2:     NOTRUN -> [SKIP][78] ([Intel XE#2763] / [Intel XE#455]) +3 other tests skip
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-436/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-d.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75:
    - shard-bmg:          NOTRUN -> [SKIP][79] ([Intel XE#2763]) +4 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-3/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75.html

  * igt@kms_pm_dc@deep-pkgc:
    - shard-lnl:          [PASS][80] -> [FAIL][81] ([Intel XE#2029])
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-lnl-3/igt@kms_pm_dc@deep-pkgc.html
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-lnl-8/igt@kms_pm_dc@deep-pkgc.html

  * igt@kms_pm_rpm@universal-planes:
    - shard-dg2-set2:     [PASS][82] -> [SKIP][83] ([Intel XE#2446]) +2 other tests skip
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-434/igt@kms_pm_rpm@universal-planes.html
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_pm_rpm@universal-planes.html

  * igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-bmg:          NOTRUN -> [SKIP][84] ([Intel XE#1489]) +1 other test skip
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-1/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr@fbc-psr-primary-page-flip:
    - shard-bmg:          NOTRUN -> [SKIP][85] ([Intel XE#2234] / [Intel XE#2850]) +3 other tests skip
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-3/igt@kms_psr@fbc-psr-primary-page-flip.html

  * igt@kms_rotation_crc@primary-rotation-270:
    - shard-bmg:          NOTRUN -> [SKIP][86] ([Intel XE#3414]) +1 other test skip
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-3/igt@kms_rotation_crc@primary-rotation-270.html

  * igt@kms_rotation_crc@sprite-rotation-180:
    - shard-dg2-set2:     [PASS][87] -> [SKIP][88] ([Intel XE#2423] / [i915#2575]) +80 other tests skip
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-434/igt@kms_rotation_crc@sprite-rotation-180.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_rotation_crc@sprite-rotation-180.html

  * igt@kms_universal_plane@cursor-fb-leak@pipe-c-edp-1:
    - shard-lnl:          [PASS][89] -> [FAIL][90] ([Intel XE#899]) +1 other test fail
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-lnl-6/igt@kms_universal_plane@cursor-fb-leak@pipe-c-edp-1.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-lnl-6/igt@kms_universal_plane@cursor-fb-leak@pipe-c-edp-1.html

  * igt@kms_vrr@flip-dpms:
    - shard-dg2-set2:     NOTRUN -> [SKIP][91] ([Intel XE#2423] / [i915#2575]) +26 other tests skip
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_vrr@flip-dpms.html

  * igt@xe_compute_preempt@compute-threadgroup-preempt@engine-drm_xe_engine_class_compute:
    - shard-dg2-set2:     NOTRUN -> [SKIP][92] ([Intel XE#1280] / [Intel XE#455])
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-464/igt@xe_compute_preempt@compute-threadgroup-preempt@engine-drm_xe_engine_class_compute.html

  * igt@xe_eudebug_online@set-breakpoint:
    - shard-bmg:          NOTRUN -> [SKIP][93] ([Intel XE#2905]) +1 other test skip
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-7/igt@xe_eudebug_online@set-breakpoint.html

  * igt@xe_exec_balancer@twice-virtual-basic:
    - shard-dg2-set2:     [PASS][94] -> [SKIP][95] ([Intel XE#1130]) +161 other tests skip
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-464/igt@xe_exec_balancer@twice-virtual-basic.html
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@xe_exec_balancer@twice-virtual-basic.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-basic-defer-mmap:
    - shard-bmg:          NOTRUN -> [SKIP][96] ([Intel XE#2322]) +3 other tests skip
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-3/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-basic-defer-mmap.html

  * igt@xe_exec_basic@once-userptr-invalidate-race:
    - shard-dg2-set2:     NOTRUN -> [SKIP][97] ([Intel XE#1130]) +39 other tests skip
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@xe_exec_basic@once-userptr-invalidate-race.html

  * igt@xe_exec_reset@cat-error:
    - shard-adlp:         [PASS][98] -> [DMESG-WARN][99] ([Intel XE#358])
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-adlp-3/igt@xe_exec_reset@cat-error.html
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-adlp-3/igt@xe_exec_reset@cat-error.html

  * igt@xe_exec_threads@threads-mixed-fd-userptr-invalidate-race:
    - shard-bmg:          [PASS][100] -> [DMESG-WARN][101] ([Intel XE#3468]) +3 other tests dmesg-warn
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-bmg-6/igt@xe_exec_threads@threads-mixed-fd-userptr-invalidate-race.html
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-4/igt@xe_exec_threads@threads-mixed-fd-userptr-invalidate-race.html

  * igt@xe_fault_injection@inject-fault-probe-function-xe_guc_relay_init:
    - shard-bmg:          NOTRUN -> [DMESG-WARN][102] ([Intel XE#3343])
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-1/igt@xe_fault_injection@inject-fault-probe-function-xe_guc_relay_init.html

  * igt@xe_gt_freq@freq_reset_multiple:
    - shard-lnl:          [PASS][103] -> [DMESG-WARN][104] ([Intel XE#3184])
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-lnl-4/igt@xe_gt_freq@freq_reset_multiple.html
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-lnl-2/igt@xe_gt_freq@freq_reset_multiple.html

  * igt@xe_live_ktest@xe_bo:
    - shard-dg2-set2:     [PASS][105] -> [TIMEOUT][106] ([Intel XE#2961] / [Intel XE#3191]) +1 other test timeout
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@xe_live_ktest@xe_bo.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-463/igt@xe_live_ktest@xe_bo.html

  * igt@xe_live_ktest@xe_mocs@xe_live_mocs_kernel_kunit:
    - shard-dg2-set2:     NOTRUN -> [FAIL][107] ([Intel XE#1999]) +2 other tests fail
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@xe_live_ktest@xe_mocs@xe_live_mocs_kernel_kunit.html

  * igt@xe_media_fill@media-fill:
    - shard-bmg:          NOTRUN -> [SKIP][108] ([Intel XE#2459] / [Intel XE#2596])
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-1/igt@xe_media_fill@media-fill.html

  * igt@xe_module_load@many-reload:
    - shard-dg2-set2:     NOTRUN -> [FAIL][109] ([Intel XE#2136])
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@xe_module_load@many-reload.html

  * igt@xe_oa@enable-disable@rcs-0:
    - shard-lnl:          NOTRUN -> [DMESG-WARN][110] ([Intel XE#3466])
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-lnl-5/igt@xe_oa@enable-disable@rcs-0.html

  * igt@xe_peer2peer@write@write-gpua-vram01-gpub-system-p2p:
    - shard-dg2-set2:     NOTRUN -> [FAIL][111] ([Intel XE#1173])
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-433/igt@xe_peer2peer@write@write-gpua-vram01-gpub-system-p2p.html

  * igt@xe_pm@s4-basic:
    - shard-adlp:         [PASS][112] -> [ABORT][113] ([Intel XE#1358] / [Intel XE#1607])
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-adlp-2/igt@xe_pm@s4-basic.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-adlp-9/igt@xe_pm@s4-basic.html

  * igt@xe_query@multigpu-query-mem-usage:
    - shard-bmg:          NOTRUN -> [SKIP][114] ([Intel XE#944])
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-4/igt@xe_query@multigpu-query-mem-usage.html

  
#### Possible fixes ####

  * igt@core_getstats:
    - shard-dg2-set2:     [SKIP][115] ([Intel XE#2423]) -> [PASS][116] +3 other tests pass
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@core_getstats.html
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-463/igt@core_getstats.html

  * igt@core_getversion@all-cards:
    - shard-dg2-set2:     [FAIL][117] ([Intel XE#3440]) -> [PASS][118]
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@core_getversion@all-cards.html
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-436/igt@core_getversion@all-cards.html

  * igt@core_setmaster@master-drop-set-user:
    - shard-dg2-set2:     [FAIL][119] ([Intel XE#3339]) -> [PASS][120]
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@core_setmaster@master-drop-set-user.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-464/igt@core_setmaster@master-drop-set-user.html

  * igt@fbdev@read:
    - shard-dg2-set2:     [SKIP][121] ([Intel XE#2134]) -> [PASS][122] +3 other tests pass
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@fbdev@read.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-433/igt@fbdev@read.html

  * igt@kms_atomic_transition@modeset-transition-nonblocking-fencing:
    - shard-dg2-set2:     [SKIP][123] ([Intel XE#2423] / [i915#2575]) -> [PASS][124] +109 other tests pass
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-463/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing.html

  * igt@kms_atomic_transition@plane-toggle-modeset-transition:
    - shard-adlp:         [FAIL][125] ([Intel XE#1426]) -> [PASS][126] +1 other test pass
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-adlp-1/igt@kms_atomic_transition@plane-toggle-modeset-transition.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-adlp-6/igt@kms_atomic_transition@plane-toggle-modeset-transition.html

  * igt@kms_color@degamma@pipe-a-dp-2:
    - shard-bmg:          [DMESG-WARN][127] -> [PASS][128] +10 other tests pass
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-bmg-6/igt@kms_color@degamma@pipe-a-dp-2.html
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-3/igt@kms_color@degamma@pipe-a-dp-2.html

  * igt@kms_cursor_edge_walk@64x64-top-edge:
    - shard-lnl:          [FAIL][129] ([Intel XE#2577] / [Intel XE#3106]) -> [PASS][130] +1 other test pass
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-lnl-3/igt@kms_cursor_edge_walk@64x64-top-edge.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-lnl-8/igt@kms_cursor_edge_walk@64x64-top-edge.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size:
    - shard-bmg:          [DMESG-WARN][131] ([Intel XE#877]) -> [PASS][132]
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-bmg-4/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-7/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic:
    - shard-bmg:          [DMESG-FAIL][133] ([Intel XE#3468]) -> [PASS][134] +10 other tests pass
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-bmg-6/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-3/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-dp2-hdmi-a3:
    - shard-bmg:          [FAIL][135] ([Intel XE#3486]) -> [PASS][136] +1 other test pass
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-bmg-2/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-dp2-hdmi-a3.html
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-7/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-dp2-hdmi-a3.html

  * igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
    - shard-bmg:          [FAIL][137] ([Intel XE#2882]) -> [PASS][138] +8 other tests pass
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-bmg-6/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-2/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank:
    - shard-lnl:          [FAIL][139] ([Intel XE#886]) -> [PASS][140] +1 other test pass
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-lnl-3/igt@kms_flip@flip-vs-absolute-wf_vblank.html
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-lnl-8/igt@kms_flip@flip-vs-absolute-wf_vblank.html

  * igt@kms_flip@flip-vs-suspend@b-hdmi-a1:
    - shard-adlp:         [DMESG-WARN][141] ([Intel XE#2953] / [Intel XE#3086]) -> [PASS][142] +5 other tests pass
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-adlp-8/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-adlp-3/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html

  * igt@kms_flip@flip-vs-suspend@c-dp2:
    - shard-bmg:          [DMESG-WARN][143] ([Intel XE#3451]) -> [PASS][144] +1 other test pass
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-bmg-6/igt@kms_flip@flip-vs-suspend@c-dp2.html
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-2/igt@kms_flip@flip-vs-suspend@c-dp2.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt:
    - shard-dg2-set2:     [SKIP][145] ([Intel XE#2136]) -> [PASS][146] +32 other tests pass
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt.html
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-464/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-dg2-set2:     [SKIP][147] ([Intel XE#2136] / [Intel XE#2351]) -> [PASS][148] +6 other tests pass
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc.html
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-464/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_plane_alpha_blend@alpha-7efc@pipe-a-dp-2:
    - shard-bmg:          [DMESG-FAIL][149] -> [PASS][150]
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-bmg-6/igt@kms_plane_alpha_blend@alpha-7efc@pipe-a-dp-2.html
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-3/igt@kms_plane_alpha_blend@alpha-7efc@pipe-a-dp-2.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-75-upscale-20x20:
    - shard-lnl:          [DMESG-WARN][151] ([Intel XE#2566]) -> [PASS][152]
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-lnl-3/igt@kms_plane_scaling@planes-downscale-factor-0-75-upscale-20x20.html
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-lnl-8/igt@kms_plane_scaling@planes-downscale-factor-0-75-upscale-20x20.html

  * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5:
    - shard-bmg:          [DMESG-WARN][153] ([Intel XE#2566]) -> [PASS][154]
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-bmg-6/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5.html
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-4/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5.html

  * igt@kms_plane_scaling@planes-upscale-20x20:
    - shard-adlp:         [DMESG-WARN][155] ([Intel XE#3086]) -> [PASS][156] +4 other tests pass
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-adlp-9/igt@kms_plane_scaling@planes-upscale-20x20.html
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-adlp-1/igt@kms_plane_scaling@planes-upscale-20x20.html

  * igt@kms_pm_rpm@cursor:
    - shard-lnl:          [DMESG-WARN][157] ([Intel XE#3184]) -> [PASS][158]
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-lnl-7/igt@kms_pm_rpm@cursor.html
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-lnl-1/igt@kms_pm_rpm@cursor.html

  * igt@kms_pm_rpm@cursor-dpms:
    - shard-dg2-set2:     [SKIP][159] ([Intel XE#2446]) -> [PASS][160] +3 other tests pass
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_pm_rpm@cursor-dpms.html
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-464/igt@kms_pm_rpm@cursor-dpms.html

  * igt@kms_pm_rpm@universal-planes:
    - shard-lnl:          [DMESG-WARN][161] ([Intel XE#2042]) -> [PASS][162]
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-lnl-3/igt@kms_pm_rpm@universal-planes.html
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-lnl-8/igt@kms_pm_rpm@universal-planes.html

  * igt@kms_rotation_crc@primary-x-tiled-reflect-x-180:
    - shard-lnl:          [DMESG-WARN][163] -> [PASS][164] +94 other tests pass
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-lnl-3/igt@kms_rotation_crc@primary-x-tiled-reflect-x-180.html
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-lnl-8/igt@kms_rotation_crc@primary-x-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@sprite-rotation-180:
    - shard-lnl:          [DMESG-WARN][165] ([Intel XE#3466]) -> [PASS][166]
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-lnl-3/igt@kms_rotation_crc@sprite-rotation-180.html
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-lnl-8/igt@kms_rotation_crc@sprite-rotation-180.html

  * igt@kms_vblank@wait-idle@pipe-a-dp-4:
    - shard-dg2-set2:     [FAIL][167] -> [PASS][168] +1 other test pass
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-463/igt@kms_vblank@wait-idle@pipe-a-dp-4.html
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-436/igt@kms_vblank@wait-idle@pipe-a-dp-4.html

  * igt@kms_vrr@cmrr@pipe-a-edp-1:
    - shard-lnl:          [FAIL][169] ([Intel XE#2159]) -> [PASS][170] +1 other test pass
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-lnl-5/igt@kms_vrr@cmrr@pipe-a-edp-1.html
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-lnl-3/igt@kms_vrr@cmrr@pipe-a-edp-1.html

  * igt@xe_drm_fdinfo@utilization-others-idle:
    - shard-bmg:          [INCOMPLETE][171] -> [PASS][172] +1 other test pass
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-bmg-1/igt@xe_drm_fdinfo@utilization-others-idle.html
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-1/igt@xe_drm_fdinfo@utilization-others-idle.html

  * igt@xe_exec_balancer@once-parallel-rebind:
    - shard-dg2-set2:     [SKIP][173] ([Intel XE#1130]) -> [PASS][174] +216 other tests pass
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@xe_exec_balancer@once-parallel-rebind.html
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-464/igt@xe_exec_balancer@once-parallel-rebind.html

  * igt@xe_exec_threads@threads-mixed-shared-vm-userptr-invalidate:
    - shard-adlp:         [DMESG-FAIL][175] ([Intel XE#3371]) -> [PASS][176]
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-adlp-8/igt@xe_exec_threads@threads-mixed-shared-vm-userptr-invalidate.html
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-adlp-1/igt@xe_exec_threads@threads-mixed-shared-vm-userptr-invalidate.html

  * igt@xe_fault_injection@vm-create-fail-xe_pt_create:
    - shard-bmg:          [DMESG-WARN][177] ([Intel XE#3467]) -> [PASS][178] +1 other test pass
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-bmg-6/igt@xe_fault_injection@vm-create-fail-xe_pt_create.html
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-3/igt@xe_fault_injection@vm-create-fail-xe_pt_create.html

  * igt@xe_live_ktest@xe_bo@xe_bo_evict_kunit:
    - shard-dg2-set2:     [SKIP][179] ([Intel XE#2229]) -> [PASS][180] +1 other test pass
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@xe_live_ktest@xe_bo@xe_bo_evict_kunit.html
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-463/igt@xe_live_ktest@xe_bo@xe_bo_evict_kunit.html

  * igt@xe_live_ktest@xe_bo@xe_bo_shrink_kunit:
    - shard-bmg:          [INCOMPLETE][181] ([Intel XE#2998]) -> [PASS][182] +1 other test pass
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-bmg-1/igt@xe_live_ktest@xe_bo@xe_bo_shrink_kunit.html
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-3/igt@xe_live_ktest@xe_bo@xe_bo_shrink_kunit.html

  * igt@xe_pm@s2idle-vm-bind-unbind-all:
    - shard-lnl:          [DMESG-WARN][183] ([Intel XE#1616]) -> [PASS][184]
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-lnl-3/igt@xe_pm@s2idle-vm-bind-unbind-all.html
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-lnl-8/igt@xe_pm@s2idle-vm-bind-unbind-all.html

  * igt@xe_pm_residency@toggle-gt-c6:
    - shard-adlp:         [FAIL][185] ([Intel XE#958]) -> [PASS][186]
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-adlp-9/igt@xe_pm_residency@toggle-gt-c6.html
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-adlp-8/igt@xe_pm_residency@toggle-gt-c6.html
    - shard-lnl:          [FAIL][187] ([Intel XE#958]) -> [PASS][188]
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-lnl-7/igt@xe_pm_residency@toggle-gt-c6.html
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-lnl-1/igt@xe_pm_residency@toggle-gt-c6.html

  * igt@xe_sriov_flr@flr-vf1-clear:
    - shard-adlp:         [FAIL][189] ([Intel XE#3507]) -> [PASS][190]
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-adlp-1/igt@xe_sriov_flr@flr-vf1-clear.html
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-adlp-6/igt@xe_sriov_flr@flr-vf1-clear.html

  * igt@xe_vm@large-userptr-split-misaligned-binds-67108864:
    - shard-bmg:          [DMESG-WARN][191] ([Intel XE#3468]) -> [PASS][192] +41 other tests pass
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-bmg-6/igt@xe_vm@large-userptr-split-misaligned-binds-67108864.html
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-3/igt@xe_vm@large-userptr-split-misaligned-binds-67108864.html

  
#### Warnings ####

  * igt@core_hotunplug@hotrebind-lateclose:
    - shard-dg2-set2:     [SKIP][193] ([Intel XE#1885]) -> [DMESG-WARN][194] ([Intel XE#3468])
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@core_hotunplug@hotrebind-lateclose.html
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-433/igt@core_hotunplug@hotrebind-lateclose.html

  * igt@core_hotunplug@unplug-rescan:
    - shard-dg2-set2:     [INCOMPLETE][195] ([Intel XE#1195]) -> [SKIP][196] ([Intel XE#1885])
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-436/igt@core_hotunplug@unplug-rescan.html
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@core_hotunplug@unplug-rescan.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - shard-dg2-set2:     [SKIP][197] ([Intel XE#623]) -> [SKIP][198] ([Intel XE#2423] / [i915#2575])
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-436/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1-linear:
    - shard-lnl:          [DMESG-FAIL][199] -> [FAIL][200] ([Intel XE#911]) +3 other tests fail
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-lnl-3/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1-linear.html
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-lnl-8/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-edp-1-linear.html

  * igt@kms_big_fb@4-tiled-16bpp-rotate-90:
    - shard-dg2-set2:     [SKIP][201] ([Intel XE#2136] / [Intel XE#2351]) -> [SKIP][202] ([Intel XE#316])
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_big_fb@4-tiled-16bpp-rotate-90.html
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-436/igt@kms_big_fb@4-tiled-16bpp-rotate-90.html

  * igt@kms_big_fb@linear-16bpp-rotate-90:
    - shard-dg2-set2:     [SKIP][203] ([Intel XE#316]) -> [SKIP][204] ([Intel XE#2136] / [Intel XE#2351]) +1 other test skip
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-434/igt@kms_big_fb@linear-16bpp-rotate-90.html
   [204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_big_fb@linear-16bpp-rotate-90.html

  * igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0:
    - shard-bmg:          [DMESG-WARN][205] ([Intel XE#3468]) -> [DMESG-FAIL][206] ([Intel XE#3468]) +1 other test dmesg-fail
   [205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-bmg-5/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0.html
   [206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-2/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0.html

  * igt@kms_big_fb@x-tiled-16bpp-rotate-270:
    - shard-dg2-set2:     [SKIP][207] ([Intel XE#2136]) -> [SKIP][208] ([Intel XE#316]) +5 other tests skip
   [207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html
   [208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-464/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-90:
    - shard-dg2-set2:     [SKIP][209] ([Intel XE#316]) -> [SKIP][210] ([Intel XE#2136])
   [209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-434/igt@kms_big_fb@x-tiled-32bpp-rotate-90.html
   [210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_big_fb@x-tiled-32bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-bmg:          [DMESG-FAIL][211] ([Intel XE#3468]) -> [DMESG-WARN][212] ([Intel XE#3468]) +2 other tests dmesg-warn
   [211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-bmg-6/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
   [212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-4/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0:
    - shard-adlp:         [DMESG-FAIL][213] ([Intel XE#1033]) -> [FAIL][214] ([Intel XE#1874])
   [213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-adlp-4/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0.html
   [214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-adlp-2/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-dg2-set2:     [SKIP][215] ([Intel XE#1124]) -> [SKIP][216] ([Intel XE#2136] / [Intel XE#2351]) +3 other tests skip
   [215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-434/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
   [216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@yf-tiled-32bpp-rotate-180:
    - shard-dg2-set2:     [SKIP][217] ([Intel XE#2136]) -> [SKIP][218] ([Intel XE#1124]) +6 other tests skip
   [217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_big_fb@yf-tiled-32bpp-rotate-180.html
   [218]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-463/igt@kms_big_fb@yf-tiled-32bpp-rotate-180.html

  * igt@kms_big_fb@yf-tiled-addfb:
    - shard-dg2-set2:     [SKIP][219] ([Intel XE#619]) -> [SKIP][220] ([Intel XE#2136] / [Intel XE#2351])
   [219]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-434/igt@kms_big_fb@yf-tiled-addfb.html
   [220]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_big_fb@yf-tiled-addfb.html

  * igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
    - shard-dg2-set2:     [SKIP][221] ([Intel XE#607]) -> [SKIP][222] ([Intel XE#2136])
   [221]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-436/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html
   [222]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@yf-tiled-addfb-size-overflow:
    - shard-dg2-set2:     [SKIP][223] ([Intel XE#2136]) -> [SKIP][224] ([Intel XE#610])
   [223]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html
   [224]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-436/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-dg2-set2:     [SKIP][225] ([Intel XE#2136] / [Intel XE#2351]) -> [SKIP][226] ([Intel XE#1124]) +5 other tests skip
   [225]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
   [226]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-463/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
    - shard-dg2-set2:     [SKIP][227] ([Intel XE#1124]) -> [SKIP][228] ([Intel XE#2136]) +5 other tests skip
   [227]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-434/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
   [228]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p:
    - shard-dg2-set2:     [SKIP][229] ([Intel XE#2423] / [i915#2575]) -> [SKIP][230] ([Intel XE#367]) +6 other tests skip
   [229]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html
   [230]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-464/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html

  * igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p:
    - shard-dg2-set2:     [SKIP][231] ([Intel XE#2423] / [i915#2575]) -> [SKIP][232] ([Intel XE#2191])
   [231]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p.html
   [232]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-436/igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p.html

  * igt@kms_bw@connected-linear-tiling-4-displays-1920x1080p:
    - shard-dg2-set2:     [SKIP][233] ([Intel XE#2191]) -> [SKIP][234] ([Intel XE#2423] / [i915#2575]) +1 other test skip
   [233]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-434/igt@kms_bw@connected-linear-tiling-4-displays-1920x1080p.html
   [234]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_bw@connected-linear-tiling-4-displays-1920x1080p.html

  * igt@kms_bw@linear-tiling-4-displays-2160x1440p:
    - shard-dg2-set2:     [SKIP][235] ([Intel XE#367]) -> [SKIP][236] ([Intel XE#2423] / [i915#2575]) +2 other tests skip
   [235]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-434/igt@kms_bw@linear-tiling-4-displays-2160x1440p.html
   [236]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_bw@linear-tiling-4-displays-2160x1440p.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs:
    - shard-dg2-set2:     [SKIP][237] ([Intel XE#2136]) -> [SKIP][238] ([Intel XE#2907])
   [237]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html
   [238]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-463/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html

  * igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs:
    - shard-dg2-set2:     [SKIP][239] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][240] ([Intel XE#2136] / [Intel XE#2351]) +2 other tests skip
   [239]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-436/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs.html
   [240]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc:
    - shard-dg2-set2:     [SKIP][241] ([Intel XE#2136] / [Intel XE#2351]) -> [SKIP][242] ([Intel XE#455] / [Intel XE#787]) +2 other tests skip
   [241]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc.html
   [242]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-464/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs:
    - shard-dg2-set2:     [SKIP][243] -> [SKIP][244] ([Intel XE#455] / [Intel XE#787])
   [243]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs.html
   [244]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-463/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs:
    - shard-dg2-set2:     [SKIP][245] ([Intel XE#2907]) -> [SKIP][246] ([Intel XE#2136]) +1 other test skip
   [245]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html
   [246]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs:
    - shard-dg2-set2:     [SKIP][247] ([Intel XE#2136]) -> [SKIP][248] ([Intel XE#455] / [Intel XE#787]) +17 other tests skip
   [247]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs.html
   [248]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs.html

  * igt@kms_ccs@random-ccs-data-y-tiled-gen12-mc-ccs:
    - shard-dg2-set2:     [SKIP][249] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][250] ([Intel XE#2136]) +9 other tests skip
   [249]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-436/igt@kms_ccs@random-ccs-data-y-tiled-gen12-mc-ccs.html
   [250]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_ccs@random-ccs-data-y-tiled-gen12-mc-ccs.html

  * igt@kms_chamelium_color@ctm-0-75:
    - shard-dg2-set2:     [SKIP][251] ([Intel XE#2423] / [i915#2575]) -> [SKIP][252] ([Intel XE#306]) +2 other tests skip
   [251]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_chamelium_color@ctm-0-75.html
   [252]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-463/igt@kms_chamelium_color@ctm-0-75.html

  * igt@kms_chamelium_color@degamma:
    - shard-dg2-set2:     [SKIP][253] ([Intel XE#306]) -> [SKIP][254] ([Intel XE#2423] / [i915#2575]) +1 other test skip
   [253]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-464/igt@kms_chamelium_color@degamma.html
   [254]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_chamelium_color@degamma.html

  * igt@kms_chamelium_hpd@hdmi-hpd-for-each-pipe:
    - shard-dg2-set2:     [SKIP][255] ([Intel XE#2423] / [i915#2575]) -> [SKIP][256] ([Intel XE#373]) +13 other tests skip
   [255]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_chamelium_hpd@hdmi-hpd-for-each-pipe.html
   [256]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-433/igt@kms_chamelium_hpd@hdmi-hpd-for-each-pipe.html

  * igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode:
    - shard-dg2-set2:     [SKIP][257] ([Intel XE#373]) -> [SKIP][258] ([Intel XE#2423] / [i915#2575]) +12 other tests skip
   [257]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-436/igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode.html
   [258]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode.html

  * igt@kms_content_protection@dp-mst-type-0:
    - shard-dg2-set2:     [SKIP][259] ([Intel XE#2423] / [i915#2575]) -> [SKIP][260] ([Intel XE#307]) +1 other test skip
   [259]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_content_protection@dp-mst-type-0.html
   [260]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-463/igt@kms_content_protection@dp-mst-type-0.html

  * igt@kms_content_protection@lic-type-0:
    - shard-dg2-set2:     [SKIP][261] ([Intel XE#2423] / [i915#2575]) -> [FAIL][262] ([Intel XE#1178]) +3 other tests fail
   [261]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_content_protection@lic-type-0.html
   [262]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-436/igt@kms_content_protection@lic-type-0.html

  * igt@kms_cursor_crc@cursor-offscreen-512x512:
    - shard-dg2-set2:     [SKIP][263] ([Intel XE#2423] / [i915#2575]) -> [SKIP][264] ([Intel XE#308]) +2 other tests skip
   [263]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_cursor_crc@cursor-offscreen-512x512.html
   [264]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-463/igt@kms_cursor_crc@cursor-offscreen-512x512.html

  * igt@kms_cursor_crc@cursor-offscreen-64x21:
    - shard-dg2-set2:     [INCOMPLETE][265] ([Intel XE#1195]) -> [SKIP][266] ([Intel XE#2423] / [i915#2575])
   [265]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-464/igt@kms_cursor_crc@cursor-offscreen-64x21.html
   [266]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_cursor_crc@cursor-offscreen-64x21.html

  * igt@kms_cursor_crc@cursor-onscreen-512x512:
    - shard-dg2-set2:     [SKIP][267] ([Intel XE#308]) -> [SKIP][268] ([Intel XE#2423] / [i915#2575]) +1 other test skip
   [267]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-434/igt@kms_cursor_crc@cursor-onscreen-512x512.html
   [268]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_cursor_crc@cursor-onscreen-512x512.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - shard-dg2-set2:     [SKIP][269] ([Intel XE#2423] / [i915#2575]) -> [SKIP][270] ([Intel XE#323]) +1 other test skip
   [269]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [270]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-464/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
    - shard-dg2-set2:     [SKIP][271] ([Intel XE#323]) -> [SKIP][272] ([Intel XE#2423] / [i915#2575])
   [271]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-464/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
   [272]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@torture-bo:
    - shard-dg2-set2:     [DMESG-WARN][273] ([Intel XE#3184]) -> [SKIP][274] ([Intel XE#2423] / [i915#2575])
   [273]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-434/igt@kms_cursor_legacy@torture-bo.html
   [274]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_cursor_legacy@torture-bo.html

  * igt@kms_draw_crc@draw-method-mmap-wc:
    - shard-bmg:          [INCOMPLETE][275] ([Intel XE#3468]) -> [DMESG-FAIL][276] ([Intel XE#3468])
   [275]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-bmg-4/igt@kms_draw_crc@draw-method-mmap-wc.html
   [276]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-7/igt@kms_draw_crc@draw-method-mmap-wc.html

  * igt@kms_dsc@dsc-with-output-formats-with-bpc:
    - shard-dg2-set2:     [SKIP][277] ([Intel XE#455]) -> [SKIP][278] ([Intel XE#2136]) +4 other tests skip
   [277]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-464/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
   [278]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_dsc@dsc-with-output-formats-with-bpc.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-dg2-set2:     [SKIP][279] ([Intel XE#2136]) -> [SKIP][280] ([Intel XE#776])
   [279]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_fbcon_fbt@psr-suspend.html
   [280]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-463/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_feature_discovery@display-3x:
    - shard-dg2-set2:     [SKIP][281] ([Intel XE#2423] / [i915#2575]) -> [SKIP][282] ([Intel XE#703])
   [281]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_feature_discovery@display-3x.html
   [282]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-463/igt@kms_feature_discovery@display-3x.html

  * igt@kms_feature_discovery@display-4x:
    - shard-dg2-set2:     [SKIP][283] ([Intel XE#2423] / [i915#2575]) -> [SKIP][284] ([Intel XE#1138])
   [283]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_feature_discovery@display-4x.html
   [284]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-464/igt@kms_feature_discovery@display-4x.html

  * igt@kms_feature_discovery@psr2:
    - shard-dg2-set2:     [SKIP][285] ([Intel XE#2423] / [i915#2575]) -> [SKIP][286] ([Intel XE#1135])
   [285]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_feature_discovery@psr2.html
   [286]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-436/igt@kms_feature_discovery@psr2.html

  * igt@kms_flip@2x-flip-vs-modeset-vs-hang:
    - shard-dg2-set2:     [DMESG-WARN][287] -> [SKIP][288] ([Intel XE#2423] / [i915#2575])
   [287]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-436/igt@kms_flip@2x-flip-vs-modeset-vs-hang.html
   [288]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_flip@2x-flip-vs-modeset-vs-hang.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-dg2-set2:     [SKIP][289] ([Intel XE#2423] / [i915#2575]) -> [DMESG-FAIL][290] ([Intel XE#3468])
   [289]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_flip@flip-vs-suspend.html
   [290]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-464/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-dg2-set2:     [INCOMPLETE][291] ([Intel XE#1195] / [Intel XE#2049] / [Intel XE#2597]) -> [SKIP][292] ([Intel XE#2423] / [i915#2575])
   [291]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-434/igt@kms_flip@flip-vs-suspend-interruptible.html
   [292]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling:
    - shard-dg2-set2:     [INCOMPLETE][293] ([Intel XE#1195]) -> [INCOMPLETE][294] ([Intel XE#1195] / [Intel XE#3468]) +2 other tests incomplete
   [293]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-433/igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling.html
   [294]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-434/igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling:
    - shard-dg2-set2:     [SKIP][295] ([Intel XE#2136]) -> [SKIP][296] ([Intel XE#455]) +6 other tests skip
   [295]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling.html
   [296]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-463/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
    - shard-dg2-set2:     [SKIP][297] ([Intel XE#2136] / [Intel XE#2351]) -> [SKIP][298] ([Intel XE#455]) +1 other test skip
   [297]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
   [298]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-433/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling:
    - shard-dg2-set2:     [SKIP][299] ([Intel XE#455]) -> [SKIP][300] ([Intel XE#2136] / [Intel XE#2351])
   [299]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-464/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html
   [300]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-render:
    - shard-dg2-set2:     [SKIP][301] ([Intel XE#2136]) -> [SKIP][302] ([Intel XE#651]) +34 other tests skip
   [301]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-render.html
   [302]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-464/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@drrs-indfb-scaledprimary:
    - shard-dg2-set2:     [SKIP][303] ([Intel XE#651]) -> [SKIP][304] ([Intel XE#2136]) +20 other tests skip
   [303]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-434/igt@kms_frontbuffer_tracking@drrs-indfb-scaledprimary.html
   [304]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_frontbuffer_tracking@drrs-indfb-scaledprimary.html

  * igt@kms_frontbuffer_tracking@drrs-suspend:
    - shard-dg2-set2:     [SKIP][305] ([Intel XE#2136] / [Intel XE#2351]) -> [SKIP][306] ([Intel XE#651]) +9 other tests skip
   [305]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_frontbuffer_tracking@drrs-suspend.html
   [306]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-463/igt@kms_frontbuffer_tracking@drrs-suspend.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move:
    - shard-bmg:          [DMESG-FAIL][307] ([Intel XE#3468]) -> [FAIL][308] ([Intel XE#2333]) +2 other tests fail
   [307]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html
   [308]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-y:
    - shard-dg2-set2:     [SKIP][309] ([Intel XE#2136] / [Intel XE#2351]) -> [SKIP][310] ([Intel XE#658]) +1 other test skip
   [309]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_frontbuffer_tracking@fbc-tiling-y.html
   [310]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-463/igt@kms_frontbuffer_tracking@fbc-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-render:
    - shard-dg2-set2:     [SKIP][311] ([Intel XE#651]) -> [SKIP][312] ([Intel XE#2136] / [Intel XE#2351]) +10 other tests skip
   [311]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-436/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-render.html
   [312]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-msflip-blt:
    - shard-dg2-set2:     [SKIP][313] ([Intel XE#2136]) -> [SKIP][314] ([Intel XE#653]) +36 other tests skip
   [313]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-msflip-blt.html
   [314]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
    - shard-dg2-set2:     [SKIP][315] ([Intel XE#653]) -> [SKIP][316] ([Intel XE#2136] / [Intel XE#2351]) +9 other tests skip
   [315]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-434/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
   [316]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt:
    - shard-dg2-set2:     [SKIP][317] ([Intel XE#653]) -> [SKIP][318] ([Intel XE#2136]) +24 other tests skip
   [317]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-436/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt.html
   [318]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-dg2-set2:     [SKIP][319] ([Intel XE#2136] / [Intel XE#2351]) -> [SKIP][320] ([Intel XE#653]) +9 other tests skip
   [319]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc.html
   [320]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-463/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_getfb@getfb-reject-ccs:
    - shard-dg2-set2:     [SKIP][321] ([Intel XE#2423] / [i915#2575]) -> [SKIP][322] ([Intel XE#605])
   [321]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_getfb@getfb-reject-ccs.html
   [322]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-464/igt@kms_getfb@getfb-reject-ccs.html

  * igt@kms_plane_cursor@primary:
    - shard-dg2-set2:     [FAIL][323] ([Intel XE#616]) -> [SKIP][324] ([Intel XE#2423] / [i915#2575])
   [323]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-436/igt@kms_plane_cursor@primary.html
   [324]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_plane_cursor@primary.html

  * igt@kms_plane_scaling@intel-max-src-size:
    - shard-dg2-set2:     [FAIL][325] ([Intel XE#361]) -> [SKIP][326] ([Intel XE#2423] / [i915#2575])
   [325]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-464/igt@kms_plane_scaling@intel-max-src-size.html
   [326]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_plane_scaling@intel-max-src-size.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling:
    - shard-dg2-set2:     [SKIP][327] ([Intel XE#2423] / [i915#2575]) -> [SKIP][328] ([Intel XE#2763] / [Intel XE#455]) +3 other tests skip
   [327]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling.html
   [328]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-464/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling.html

  * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25:
    - shard-dg2-set2:     [SKIP][329] ([Intel XE#2763] / [Intel XE#455]) -> [SKIP][330] ([Intel XE#2423] / [i915#2575])
   [329]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-435/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25.html
   [330]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25.html

  * igt@kms_pm_backlight@bad-brightness:
    - shard-dg2-set2:     [SKIP][331] ([Intel XE#2136]) -> [SKIP][332] ([Intel XE#870])
   [331]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_pm_backlight@bad-brightness.html
   [332]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-463/igt@kms_pm_backlight@bad-brightness.html

  * igt@kms_pm_backlight@brightness-with-dpms:
    - shard-dg2-set2:     [SKIP][333] ([Intel XE#2938]) -> [SKIP][334] ([Intel XE#2136])
   [333]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-464/igt@kms_pm_backlight@brightness-with-dpms.html
   [334]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_pm_backlight@brightness-with-dpms.html

  * igt@kms_pm_backlight@fade-with-suspend:
    - shard-dg2-set2:     [SKIP][335] ([Intel XE#870]) -> [SKIP][336] ([Intel XE#2136])
   [335]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-436/igt@kms_pm_backlight@fade-with-suspend.html
   [336]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_pm_backlight@fade-with-suspend.html

  * igt@kms_pm_dc@dc3co-vpb-simulation:
    - shard-dg2-set2:     [SKIP][337] ([Intel XE#2136] / [Intel XE#2351]) -> [SKIP][338] ([Intel XE#1122])
   [337]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_pm_dc@dc3co-vpb-simulation.html
   [338]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-433/igt@kms_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_pm_dc@deep-pkgc:
    - shard-dg2-set2:     [SKIP][339] ([Intel XE#908]) -> [SKIP][340] ([Intel XE#2136])
   [339]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-435/igt@kms_pm_dc@deep-pkgc.html
   [340]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_pm_dc@deep-pkgc.html

  * igt@kms_pm_rpm@basic-pci-d3-state:
    - shard-dg2-set2:     [DMESG-WARN][341] ([Intel XE#3468]) -> [ABORT][342] ([Intel XE#3468])
   [341]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-463/igt@kms_pm_rpm@basic-pci-d3-state.html
   [342]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-433/igt@kms_pm_rpm@basic-pci-d3-state.html

  * igt@kms_pm_rpm@dpms-non-lpsp:
    - shard-dg2-set2:     [SKIP][343] ([Intel XE#2446]) -> [ABORT][344] ([Intel XE#3468])
   [343]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_pm_rpm@dpms-non-lpsp.html
   [344]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-463/igt@kms_pm_rpm@dpms-non-lpsp.html

  * igt@kms_pm_rpm@drm-resources-equal:
    - shard-dg2-set2:     [ABORT][345] ([Intel XE#3468]) -> [SKIP][346] ([Intel XE#2446])
   [345]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-464/igt@kms_pm_rpm@drm-resources-equal.html
   [346]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_pm_rpm@drm-resources-equal.html

  * igt@kms_pm_rpm@legacy-planes-dpms:
    - shard-dg2-set2:     [DMESG-WARN][347] ([Intel XE#3468]) -> [SKIP][348] ([Intel XE#2446])
   [347]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-435/igt@kms_pm_rpm@legacy-planes-dpms.html
   [348]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_pm_rpm@legacy-planes-dpms.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-dg2-set2:     [SKIP][349] ([Intel XE#1489]) -> [SKIP][350] ([Intel XE#2136]) +9 other tests skip
   [349]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-435/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-fully-sf.html
   [350]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf:
    - shard-dg2-set2:     [SKIP][351] ([Intel XE#2136]) -> [SKIP][352] ([Intel XE#1489]) +8 other tests skip
   [351]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf.html
   [352]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-464/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-dg2-set2:     [SKIP][353] ([Intel XE#2136]) -> [SKIP][354] ([Intel XE#1122]) +1 other test skip
   [353]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_psr2_su@page_flip-p010.html
   [354]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-464/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_psr@fbc-psr-sprite-plane-move:
    - shard-dg2-set2:     [SKIP][355] ([Intel XE#2850] / [Intel XE#929]) -> [SKIP][356] ([Intel XE#2136] / [Intel XE#2351]) +4 other tests skip
   [355]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-436/igt@kms_psr@fbc-psr-sprite-plane-move.html
   [356]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_psr@fbc-psr-sprite-plane-move.html

  * igt@kms_psr@fbc-psr2-sprite-plane-move:
    - shard-dg2-set2:     [SKIP][357] ([Intel XE#2850] / [Intel XE#929]) -> [SKIP][358] ([Intel XE#2136]) +8 other tests skip
   [357]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-434/igt@kms_psr@fbc-psr2-sprite-plane-move.html
   [358]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_psr@fbc-psr2-sprite-plane-move.html

  * igt@kms_psr@psr-dpms:
    - shard-dg2-set2:     [SKIP][359] ([Intel XE#2136] / [Intel XE#2351]) -> [SKIP][360] ([Intel XE#2850] / [Intel XE#929]) +2 other tests skip
   [359]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_psr@psr-dpms.html
   [360]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-464/igt@kms_psr@psr-dpms.html

  * igt@kms_psr@psr-primary-page-flip:
    - shard-dg2-set2:     [SKIP][361] ([Intel XE#2850] / [Intel XE#929]) -> [SKIP][362] ([Intel XE#2351]) +1 other test skip
   [361]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-464/igt@kms_psr@psr-primary-page-flip.html
   [362]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_psr@psr-primary-page-flip.html

  * igt@kms_psr@psr2-basic:
    - shard-dg2-set2:     [SKIP][363] ([Intel XE#2136]) -> [SKIP][364] ([Intel XE#2850] / [Intel XE#929]) +17 other tests skip
   [363]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_psr@psr2-basic.html
   [364]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-463/igt@kms_psr@psr2-basic.html

  * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
    - shard-dg2-set2:     [SKIP][365] ([Intel XE#2136] / [Intel XE#2351]) -> [SKIP][366] ([Intel XE#2939])
   [365]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
   [366]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-463/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html

  * igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
    - shard-dg2-set2:     [SKIP][367] ([Intel XE#2136]) -> [SKIP][368] ([Intel XE#2939])
   [367]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
   [368]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-463/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html

  * igt@kms_rotation_crc@bad-pixel-format:
    - shard-dg2-set2:     [SKIP][369] ([Intel XE#3414]) -> [SKIP][370] ([Intel XE#2423] / [i915#2575])
   [369]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-434/igt@kms_rotation_crc@bad-pixel-format.html
   [370]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_rotation_crc@bad-pixel-format.html

  * igt@kms_rotation_crc@bad-tiling:
    - shard-dg2-set2:     [SKIP][371] ([Intel XE#2423] / [i915#2575]) -> [SKIP][372] ([Intel XE#3414]) +3 other tests skip
   [371]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_rotation_crc@bad-tiling.html
   [372]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-463/igt@kms_rotation_crc@bad-tiling.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
    - shard-dg2-set2:     [SKIP][373] ([Intel XE#2423] / [i915#2575]) -> [SKIP][374] ([Intel XE#1127])
   [373]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
   [374]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-464/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html

  * igt@kms_scaling_modes@scaling-mode-full-aspect:
    - shard-dg2-set2:     [SKIP][375] ([Intel XE#455]) -> [SKIP][376] ([Intel XE#2423] / [i915#2575]) +8 other tests skip
   [375]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-435/igt@kms_scaling_modes@scaling-mode-full-aspect.html
   [376]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_scaling_modes@scaling-mode-full-aspect.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-dg2-set2:     [SKIP][377] ([Intel XE#2423] / [i915#2575]) -> [FAIL][378] ([Intel XE#1729])
   [377]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_tiled_display@basic-test-pattern.html
   [378]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-436/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-dg2-set2:     [SKIP][379] ([Intel XE#2423] / [i915#2575]) -> [SKIP][380] ([Intel XE#1500])
   [379]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [380]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-433/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_vrr@cmrr:
    - shard-dg2-set2:     [SKIP][381] ([Intel XE#2423] / [i915#2575]) -> [SKIP][382] ([Intel XE#2168])
   [381]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_vrr@cmrr.html
   [382]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-433/igt@kms_vrr@cmrr.html

  * igt@kms_vrr@flipline:
    - shard-dg2-set2:     [SKIP][383] ([Intel XE#2423] / [i915#2575]) -> [SKIP][384] ([Intel XE#455]) +3 other tests skip
   [383]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_vrr@flipline.html
   [384]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-463/igt@kms_vrr@flipline.html

  * igt@kms_writeback@writeback-check-output:
    - shard-dg2-set2:     [SKIP][385] ([Intel XE#2423] / [i915#2575]) -> [SKIP][386] ([Intel XE#756])
   [385]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@kms_writeback@writeback-check-output.html
   [386]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-464/igt@kms_writeback@writeback-check-output.html

  * igt@kms_writeback@writeback-invalid-parameters:
    - shard-dg2-set2:     [SKIP][387] ([Intel XE#756]) -> [SKIP][388] ([Intel XE#2423] / [i915#2575]) +1 other test skip
   [387]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-464/igt@kms_writeback@writeback-invalid-parameters.html
   [388]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@kms_writeback@writeback-invalid-parameters.html

  * igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all:
    - shard-dg2-set2:     [SKIP][389] ([Intel XE#2423] / [i915#2575]) -> [SKIP][390] ([Intel XE#1091] / [Intel XE#2849])
   [389]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html
   [390]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-463/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html

  * igt@xe_compute_preempt@compute-threadgroup-preempt:
    - shard-dg2-set2:     [SKIP][391] ([Intel XE#1130]) -> [SKIP][392] ([Intel XE#1280] / [Intel XE#455])
   [391]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@xe_compute_preempt@compute-threadgroup-preempt.html
   [392]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-464/igt@xe_compute_preempt@compute-threadgroup-preempt.html

  * igt@xe_copy_basic@mem-set-linear-0x369:
    - shard-dg2-set2:     [SKIP][393] ([Intel XE#1130]) -> [SKIP][394] ([Intel XE#1126])
   [393]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@xe_copy_basic@mem-set-linear-0x369.html
   [394]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-433/igt@xe_copy_basic@mem-set-linear-0x369.html

  * igt@xe_copy_basic@mem-set-linear-0xfffe:
    - shard-dg2-set2:     [SKIP][395] ([Intel XE#1126]) -> [SKIP][396] ([Intel XE#1130])
   [395]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-434/igt@xe_copy_basic@mem-set-linear-0xfffe.html
   [396]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@xe_copy_basic@mem-set-linear-0xfffe.html

  * igt@xe_eudebug_online@debugger-reopen:
    - shard-dg2-set2:     [SKIP][397] ([Intel XE#1130]) -> [SKIP][398] ([Intel XE#2905]) +14 other tests skip
   [397]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@xe_eudebug_online@debugger-reopen.html
   [398]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-463/igt@xe_eudebug_online@debugger-reopen.html

  * igt@xe_evict@evict-beng-large-multi-vm-cm:
    - shard-dg2-set2:     [FAIL][399] ([Intel XE#1600]) -> [SKIP][400] ([Intel XE#1130])
   [399]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-435/igt@xe_evict@evict-beng-large-multi-vm-cm.html
   [400]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@xe_evict@evict-beng-large-multi-vm-cm.html

  * igt@xe_evict@evict-beng-mixed-many-threads-small:
    - shard-dg2-set2:     [SKIP][401] ([Intel XE#1130]) -> [TIMEOUT][402] ([Intel XE#1473] / [Intel XE#402])
   [401]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@xe_evict@evict-beng-mixed-many-threads-small.html
   [402]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-464/igt@xe_evict@evict-beng-mixed-many-threads-small.html

  * igt@xe_evict@evict-large-multi-vm-cm:
    - shard-dg2-set2:     [SKIP][403] ([Intel XE#1130]) -> [FAIL][404] ([Intel XE#1600])
   [403]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@xe_evict@evict-large-multi-vm-cm.html
   [404]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-464/igt@xe_evict@evict-large-multi-vm-cm.html

  * igt@xe_evict@evict-mixed-many-threads-small:
    - shard-bmg:          [INCOMPLETE][405] ([Intel XE#1473]) -> [DMESG-WARN][406] ([Intel XE#3468])
   [405]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-bmg-8/igt@xe_evict@evict-mixed-many-threads-small.html
   [406]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-bmg-7/igt@xe_evict@evict-mixed-many-threads-small.html

  * igt@xe_exec_fault_mode@many-userptr:
    - shard-dg2-set2:     [SKIP][407] ([Intel XE#288]) -> [SKIP][408] ([Intel XE#1130]) +27 other tests skip
   [407]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-464/igt@xe_exec_fault_mode@many-userptr.html
   [408]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@xe_exec_fault_mode@many-userptr.html

  * igt@xe_exec_fault_mode@twice-userptr-prefetch:
    - shard-dg2-set2:     [SKIP][409] ([Intel XE#1130]) -> [SKIP][410] ([Intel XE#288]) +34 other tests skip
   [409]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@xe_exec_fault_mode@twice-userptr-prefetch.html
   [410]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-463/igt@xe_exec_fault_mode@twice-userptr-prefetch.html

  * igt@xe_exec_mix_modes@exec-simple-batch-store-dma-fence:
    - shard-dg2-set2:     [SKIP][411] ([Intel XE#1130]) -> [SKIP][412] ([Intel XE#2360])
   [411]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@xe_exec_mix_modes@exec-simple-batch-store-dma-fence.html
   [412]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-464/igt@xe_exec_mix_modes@exec-simple-batch-store-dma-fence.html

  * igt@xe_exec_mix_modes@exec-spinner-interrupted-dma-fence:
    - shard-dg2-set2:     [SKIP][413] ([Intel XE#2360]) -> [SKIP][414] ([Intel XE#1130])
   [413]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-436/igt@xe_exec_mix_modes@exec-spinner-interrupted-dma-fence.html
   [414]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@xe_exec_mix_modes@exec-spinner-interrupted-dma-fence.html

  * igt@xe_exec_sip_eudebug@breakpoint-writesip:
    - shard-dg2-set2:     [SKIP][415] ([Intel XE#2905]) -> [SKIP][416] ([Intel XE#1130]) +8 other tests skip
   [415]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-464/igt@xe_exec_sip_eudebug@breakpoint-writesip.html
   [416]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@xe_exec_sip_eudebug@breakpoint-writesip.html

  * igt@xe_fault_injection@inject-fault-probe-function-xe_guc_relay_init:
    - shard-dg2-set2:     [DMESG-WARN][417] ([Intel XE#3343]) -> [SKIP][418] ([Intel XE#1130])
   [417]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-436/igt@xe_fault_injection@inject-fault-probe-function-xe_guc_relay_init.html
   [418]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@xe_fault_injection@inject-fault-probe-function-xe_guc_relay_init.html

  * igt@xe_fault_injection@inject-fault-probe-function-xe_wa_init:
    - shard-dg2-set2:     [DMESG-WARN][419] ([Intel XE#3467]) -> [SKIP][420] ([Intel XE#1130]) +2 other tests skip
   [419]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-464/igt@xe_fault_injection@inject-fault-probe-function-xe_wa_init.html
   [420]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@xe_fault_injection@inject-fault-probe-function-xe_wa_init.html

  * igt@xe_fault_injection@inject-fault-probe-function-xe_wopcm_init:
    - shard-adlp:         [DMESG-WARN][421] ([Intel XE#3343]) -> [DMESG-WARN][422] ([Intel XE#3086] / [Intel XE#3343])
   [421]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-adlp-8/igt@xe_fault_injection@inject-fault-probe-function-xe_wopcm_init.html
   [422]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-adlp-3/igt@xe_fault_injection@inject-fault-probe-function-xe_wopcm_init.html

  * igt@xe_fault_injection@vm-bind-fail-vm_bind_ioctl_ops_create:
    - shard-dg2-set2:     [SKIP][423] ([Intel XE#1130]) -> [DMESG-WARN][424] ([Intel XE#3467]) +2 other tests dmesg-warn
   [423]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@xe_fault_injection@vm-bind-fail-vm_bind_ioctl_ops_create.html
   [424]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-436/igt@xe_fault_injection@vm-bind-fail-vm_bind_ioctl_ops_create.html

  * igt@xe_huc_copy@huc_copy:
    - shard-dg2-set2:     [SKIP][425] ([Intel XE#1130]) -> [SKIP][426] ([Intel XE#255])
   [425]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@xe_huc_copy@huc_copy.html
   [426]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-464/igt@xe_huc_copy@huc_copy.html

  * igt@xe_live_ktest@xe_eudebug:
    - shard-lnl:          [SKIP][427] ([Intel XE#1192] / [Intel XE#3026]) -> [SKIP][428] ([Intel XE#2833])
   [427]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-lnl-3/igt@xe_live_ktest@xe_eudebug.html
   [428]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-lnl-8/igt@xe_live_ktest@xe_eudebug.html

  * igt@xe_media_fill@media-fill:
    - shard-dg2-set2:     [SKIP][429] ([Intel XE#560]) -> [SKIP][430] ([Intel XE#1130])
   [429]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-436/igt@xe_media_fill@media-fill.html
   [430]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@xe_media_fill@media-fill.html

  * igt@xe_oa@closed-fd-and-unmapped-access:
    - shard-dg2-set2:     [SKIP][431] ([Intel XE#2541]) -> [SKIP][432] ([Intel XE#1130]) +6 other tests skip
   [431]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-434/igt@xe_oa@closed-fd-and-unmapped-access.html
   [432]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@xe_oa@closed-fd-and-unmapped-access.html

  * igt@xe_oa@whitelisted-registers-userspace-config:
    - shard-dg2-set2:     [SKIP][433] ([Intel XE#1130]) -> [SKIP][434] ([Intel XE#2541]) +9 other tests skip
   [433]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@xe_oa@whitelisted-registers-userspace-config.html
   [434]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-464/igt@xe_oa@whitelisted-registers-userspace-config.html

  * igt@xe_peer2peer@read:
    - shard-dg2-set2:     [FAIL][435] ([Intel XE#1173]) -> [SKIP][436] ([Intel XE#1061])
   [435]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-436/igt@xe_peer2peer@read.html
   [436]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@xe_peer2peer@read.html

  * igt@xe_peer2peer@write:
    - shard-dg2-set2:     [SKIP][437] ([Intel XE#1061]) -> [FAIL][438] ([Intel XE#1173])
   [437]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@xe_peer2peer@write.html
   [438]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-433/igt@xe_peer2peer@write.html

  * igt@xe_pm@d3cold-basic-exec:
    - shard-dg2-set2:     [SKIP][439] ([Intel XE#1130]) -> [SKIP][440] ([Intel XE#2284] / [Intel XE#366]) +2 other tests skip
   [439]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@xe_pm@d3cold-basic-exec.html
   [440]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-464/igt@xe_pm@d3cold-basic-exec.html

  * igt@xe_pm@s3-basic-exec:
    - shard-dg2-set2:     [DMESG-WARN][441] ([Intel XE#569]) -> [SKIP][442] ([Intel XE#1130])
   [441]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-464/igt@xe_pm@s3-basic-exec.html
   [442]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@xe_pm@s3-basic-exec.html

  * igt@xe_pm@s3-d3cold-basic-exec:
    - shard-dg2-set2:     [SKIP][443] ([Intel XE#2284] / [Intel XE#366]) -> [SKIP][444] ([Intel XE#1130])
   [443]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-434/igt@xe_pm@s3-d3cold-basic-exec.html
   [444]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@xe_pm@s3-d3cold-basic-exec.html

  * igt@xe_pm@s4-exec-after:
    - shard-dg2-set2:     [DMESG-WARN][445] ([Intel XE#3468]) -> [SKIP][446] ([Intel XE#1130])
   [445]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-436/igt@xe_pm@s4-exec-after.html
   [446]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@xe_pm@s4-exec-after.html

  * igt@xe_pm@s4-multiple-execs:
    - shard-dg2-set2:     [SKIP][447] ([Intel XE#1130]) -> [DMESG-WARN][448] ([Intel XE#3468])
   [447]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@xe_pm@s4-multiple-execs.html
   [448]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-436/igt@xe_pm@s4-multiple-execs.html

  * igt@xe_pm@s4-vm-bind-unbind-all:
    - shard-dg2-set2:     [DMESG-WARN][449] ([Intel XE#2280]) -> [SKIP][450] ([Intel XE#1130])
   [449]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-435/igt@xe_pm@s4-vm-bind-unbind-all.html
   [450]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@xe_pm@s4-vm-bind-unbind-all.html

  * igt@xe_pm@s4-vm-bind-userptr:
    - shard-dg2-set2:     [SKIP][451] ([Intel XE#1130]) -> [DMESG-WARN][452] ([Intel XE#2280])
   [451]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@xe_pm@s4-vm-bind-userptr.html
   [452]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-464/igt@xe_pm@s4-vm-bind-userptr.html

  * igt@xe_pm_residency@gt-c6-freeze:
    - shard-dg2-set2:     [DMESG-WARN][453] ([Intel XE#3088]) -> [SKIP][454] ([Intel XE#1130])
   [453]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-436/igt@xe_pm_residency@gt-c6-freeze.html
   [454]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@xe_pm_residency@gt-c6-freeze.html

  * igt@xe_query@multigpu-query-config:
    - shard-dg2-set2:     [SKIP][455] ([Intel XE#1130]) -> [SKIP][456] ([Intel XE#944]) +2 other tests skip
   [455]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@xe_query@multigpu-query-config.html
   [456]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-464/igt@xe_query@multigpu-query-config.html

  * igt@xe_query@multigpu-query-oa-units:
    - shard-dg2-set2:     [SKIP][457] ([Intel XE#944]) -> [SKIP][458] ([Intel XE#1130]) +2 other tests skip
   [457]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-434/igt@xe_query@multigpu-query-oa-units.html
   [458]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@xe_query@multigpu-query-oa-units.html

  * igt@xe_sriov_flr@flr-vf1-clear:
    - shard-dg2-set2:     [SKIP][459] ([Intel XE#1130]) -> [SKIP][460] ([Intel XE#3342])
   [459]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@xe_sriov_flr@flr-vf1-clear.html
   [460]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-433/igt@xe_sriov_flr@flr-vf1-clear.html

  * igt@xe_vm@shared-pde2-page:
    - shard-dg2-set2:     [DMESG-WARN][461] -> [SKIP][462] ([Intel XE#1130])
   [461]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-464/igt@xe_vm@shared-pde2-page.html
   [462]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-466/igt@xe_vm@shared-pde2-page.html

  * igt@xe_wedged@wedged-mode-toggle:
    - shard-dg2-set2:     [SKIP][463] ([Intel XE#1130]) -> [ABORT][464] ([Intel XE#3075] / [Intel XE#3084])
   [463]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f/shard-dg2-466/igt@xe_wedged@wedged-mode-toggle.html
   [464]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/shard-dg2-433/igt@xe_wedged@wedged-mode-toggle.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1033]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1033
  [Intel XE#1061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1061
  [Intel XE#1091]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1091
  [Intel XE#1122]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1122
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1126
  [Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
  [Intel XE#1130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1130
  [Intel XE#1135]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1135
  [Intel XE#1138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1138
  [Intel XE#1173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1173
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1192]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1192
  [Intel XE#1195]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1195
  [Intel XE#1280]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1280
  [Intel XE#1358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1358
  [Intel XE#1426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1426
  [Intel XE#1473]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1473
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1500]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1500
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1600]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1600
  [Intel XE#1607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1607
  [Intel XE#1616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1616
  [Intel XE#1701]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1701
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#1874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1874
  [Intel XE#1885]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1885
  [Intel XE#1999]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1999
  [Intel XE#2029]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2029
  [Intel XE#2042]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2042
  [Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
  [Intel XE#2134]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2134
  [Intel XE#2136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2136
  [Intel XE#2159]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2159
  [Intel XE#2168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2168
  [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
  [Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2280]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2280
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2286]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2286
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2333]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2333
  [Intel XE#2351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2351
  [Intel XE#2352]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2352
  [Intel XE#2360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2360
  [Intel XE#2375]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2375
  [Intel XE#2423]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2423
  [Intel XE#2446]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2446
  [Intel XE#2459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2459
  [Intel XE#2541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2541
  [Intel XE#255]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/255
  [Intel XE#2566]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2566
  [Intel XE#2577]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2577
  [Intel XE#2596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2596
  [Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2833]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2833
  [Intel XE#2849]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2849
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2882]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2882
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2905
  [Intel XE#2907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2907
  [Intel XE#2938]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2938
  [Intel XE#2939]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2939
  [Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
  [Intel XE#2961]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2961
  [Intel XE#2998]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2998
  [Intel XE#3026]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3026
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
  [Intel XE#3075]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3075
  [Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
  [Intel XE#3084]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3084
  [Intel XE#3086]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3086
  [Intel XE#3088]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3088
  [Intel XE#3106]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3106
  [Intel XE#3130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3130
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#3184]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3184
  [Intel XE#3191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3191
  [Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
  [Intel XE#3249]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3249
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#3309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3309
  [Intel XE#3339]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3339
  [Intel XE#3342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3342
  [Intel XE#3343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3343
  [Intel XE#3371]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3371
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3440]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3440
  [Intel XE#3442]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3442
  [Intel XE#3451]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3451
  [Intel XE#3466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3466
  [Intel XE#3467]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3467
  [Intel XE#3468]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3468
  [Intel XE#3486]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3486
  [Intel XE#3507]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3507
  [Intel XE#358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/358
  [Intel XE#361]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/361
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#402]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/402
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#560]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/560
  [Intel XE#569]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/569
  [Intel XE#605]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/605
  [Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
  [Intel XE#610]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/610
  [Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616
  [Intel XE#619]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/619
  [Intel XE#623]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/623
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/658
  [Intel XE#703]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/703
  [Intel XE#756]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/756
  [Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#877]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/877
  [Intel XE#886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/886
  [Intel XE#899]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/899
  [Intel XE#908]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/908
  [Intel XE#911]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/911
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
  [Intel XE#958]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/958
  [i915#2575]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2575


Build changes
-------------

  * Linux: xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f -> xe-pw-141483v1

  IGT_8114: 8114
  xe-2245-57639ceec0f66f06f4a8a8ac3b9551b7b493c33f: 57639ceec0f66f06f4a8a8ac3b9551b7b493c33f
  xe-pw-141483v1: 141483v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-141483v1/index.html

[-- Attachment #2: Type: text/html, Size: 146671 bytes --]

Re: [PATCH v5 2/7] drm/xe/eustall: Introduce API for EU stall sampling

[Dixit, Ashutosh]

On Mon, 18 Nov 2024 01:07:14 -0800, Harish Chegondi wrote:

Hi Harish,

Once again reviewing only the uapi for now.

The patch title should contain uapi in it, so drm/xe/uapi, or
drm/xe/eustall/uapi.

Also, you are not recording version log for the patches. That needs to be
added too.

> diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
> index 4a8a4a63e99c..80aaa5b50c8a 100644
> --- a/include/uapi/drm/xe_drm.h
> +++ b/include/uapi/drm/xe_drm.h
> @@ -1397,6 +1397,8 @@ struct drm_xe_wait_user_fence {
>  enum drm_xe_observation_type {
>	/** @DRM_XE_OBSERVATION_TYPE_OA: OA observation stream type */
>	DRM_XE_OBSERVATION_TYPE_OA,
> +	/** @DRM_XE_OBSERVATION_TYPE_EU_STALL: EU stall sampling observation stream type */
> +	DRM_XE_OBSERVATION_TYPE_EU_STALL,
>  };
>
>  /**
> @@ -1713,6 +1715,43 @@ struct drm_xe_oa_stream_info {
>	__u64 reserved[3];
>  };
>
> +/**
> + * enum drm_xe_eu_stall_property_id - EU stall sampling input property ids.
> + *
> + * These properties are passed to the driver at open as a chain of
> + * @drm_xe_ext_set_property structures with @property set to these
> + * properties' enums and @value set to the corresponding values of these
> + * properties. @drm_xe_user_extension base.name should be set to
> + * @DRM_XE_EU_STALL_EXTENSION_SET_PROPERTY.
> + *
> + * With the file descriptor obtained from open, user space must enable
> + * the EU stall stream fd with @DRM_XE_OBSERVATION_IOCTL_ENABLE before
> + * calling read.

Good to add this. Maybe also add "EIO return from read() indicates buffer
overflow" since EIO return is part of uapi.

> + */
> +enum drm_xe_eu_stall_property_id {
> +#define DRM_XE_EU_STALL_EXTENSION_SET_PROPERTY		0
> +	/**
> +	 * @DRM_XE_EU_STALL_PROP_SAMPLE_RATE: Sampling rate
> +	 * in multiples of 251 cycles. Valid values are 1 to 7.
> +	 * If the value is 1, sampling interval is 251 cycles.
> +	 * If the value is 7, sampling interval is 7 x 251 cycles.
> +	 */
> +	DRM_XE_EU_STALL_PROP_SAMPLE_RATE = 1,

There is an unaddressed comment from Umesh about this (on the previous
version), we need to address it.

> +
> +	/**
> +	 * @DRM_XE_EU_STALL_PROP_EVENT_REPORT_COUNT: Minimum number of
> +	 * EU stall data rows to be present in the kernel buffer for
> +	 * poll() to set POLLIN (data present).
> +	 */
> +	DRM_XE_EU_STALL_PROP_EVENT_REPORT_COUNT,
> +
> +	/**
> +	 * @DRM_XE_EU_STALL_PROP_GT_ID: GT ID of the GT on which
> +	 * EU stall data will be captured.
> +	 */
> +	DRM_XE_EU_STALL_PROP_GT_ID,

Maybe a nit, but I would make this the first property.

> +};
> +
>  #if defined(__cplusplus)
>  }
>  #endif
> --
> 2.45.1
>

Thanks.
--
Ashutosh

Re: [PATCH v5 2/7] drm/xe/eustall: Introduce API for EU stall sampling

[Harish Chegondi]

On Mon, Nov 18, 2024 at 10:58:25AM -0800, Dixit, Ashutosh wrote:
> On Mon, 18 Nov 2024 01:07:14 -0800, Harish Chegondi wrote:
> 
Hi Ashutosh,
> Hi Harish,
> 
> Once again reviewing only the uapi for now.
> 
> The patch title should contain uapi in it, so drm/xe/uapi, or
> drm/xe/eustall/uapi.
Will change the title in the next version of the patch series.
> 
> Also, you are not recording version log for the patches. That needs to be
> added too.
I have been documenting the changes in the cover letter. In the next
patch series, I will move the change log to the individual patches.
> 
> > diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
> > index 4a8a4a63e99c..80aaa5b50c8a 100644
> > --- a/include/uapi/drm/xe_drm.h
> > +++ b/include/uapi/drm/xe_drm.h
> > @@ -1397,6 +1397,8 @@ struct drm_xe_wait_user_fence {
> >  enum drm_xe_observation_type {
> >	/** @DRM_XE_OBSERVATION_TYPE_OA: OA observation stream type */
> >	DRM_XE_OBSERVATION_TYPE_OA,
> > +	/** @DRM_XE_OBSERVATION_TYPE_EU_STALL: EU stall sampling observation stream type */
> > +	DRM_XE_OBSERVATION_TYPE_EU_STALL,
> >  };
> >
> >  /**
> > @@ -1713,6 +1715,43 @@ struct drm_xe_oa_stream_info {
> >	__u64 reserved[3];
> >  };
> >
> > +/**
> > + * enum drm_xe_eu_stall_property_id - EU stall sampling input property ids.
> > + *
> > + * These properties are passed to the driver at open as a chain of
> > + * @drm_xe_ext_set_property structures with @property set to these
> > + * properties' enums and @value set to the corresponding values of these
> > + * properties. @drm_xe_user_extension base.name should be set to
> > + * @DRM_XE_EU_STALL_EXTENSION_SET_PROPERTY.
> > + *
> > + * With the file descriptor obtained from open, user space must enable
> > + * the EU stall stream fd with @DRM_XE_OBSERVATION_IOCTL_ENABLE before
> > + * calling read.
> 
> Good to add this. Maybe also add "EIO return from read() indicates buffer
> overflow" since EIO return is part of uapi.
Can I add a comment block on EU stall sampling above the comment block
for this structure? While it is important to document read() returning
-EIO for buffer overflow, I am wondering if this is the correct place to
add the comment since it is unrelated to the below structure?
> 
> > + */
> > +enum drm_xe_eu_stall_property_id {
> > +#define DRM_XE_EU_STALL_EXTENSION_SET_PROPERTY		0
> > +	/**
> > +	 * @DRM_XE_EU_STALL_PROP_SAMPLE_RATE: Sampling rate
> > +	 * in multiples of 251 cycles. Valid values are 1 to 7.
> > +	 * If the value is 1, sampling interval is 251 cycles.
> > +	 * If the value is 7, sampling interval is 7 x 251 cycles.
> > +	 */
> > +	DRM_XE_EU_STALL_PROP_SAMPLE_RATE = 1,
> 
> There is an unaddressed comment from Umesh about this (on the previous
> version), we need to address it.
I am still working on the comment from Umesh and seeking feedback from
others including the user space folks. I think having this input as it
is in terms of cycles is more generic and more future proof as the clock
frequency can vary from GPU to GPU and even for a GPU it can vary from
time to time due to performance and power reasons? 
> 
> > +
> > +	/**
> > +	 * @DRM_XE_EU_STALL_PROP_EVENT_REPORT_COUNT: Minimum number of
> > +	 * EU stall data rows to be present in the kernel buffer for
> > +	 * poll() to set POLLIN (data present).
> > +	 */
> > +	DRM_XE_EU_STALL_PROP_EVENT_REPORT_COUNT,
> > +
> > +	/**
> > +	 * @DRM_XE_EU_STALL_PROP_GT_ID: GT ID of the GT on which
> > +	 * EU stall data will be captured.
> > +	 */
> > +	DRM_XE_EU_STALL_PROP_GT_ID,
> 
> Maybe a nit, but I would make this the first property.
> 
> > +};
> > +
> >  #if defined(__cplusplus)
> >  }
> >  #endif
> > --
> > 2.45.1
> >
> 
> Thanks.
> --
> Ashutosh


Thank You
Harish.

Re: [PATCH v5 2/7] drm/xe/eustall: Introduce API for EU stall sampling

[Dixit, Ashutosh]

On Tue, 19 Nov 2024 20:59:57 -0800, Harish Chegondi wrote:
>
> > > diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
> > > index 4a8a4a63e99c..80aaa5b50c8a 100644
> > > --- a/include/uapi/drm/xe_drm.h
> > > +++ b/include/uapi/drm/xe_drm.h
> > > @@ -1397,6 +1397,8 @@ struct drm_xe_wait_user_fence {
> > >  enum drm_xe_observation_type {
> > >	/** @DRM_XE_OBSERVATION_TYPE_OA: OA observation stream type */
> > >	DRM_XE_OBSERVATION_TYPE_OA,
> > > +	/** @DRM_XE_OBSERVATION_TYPE_EU_STALL: EU stall sampling observation stream type */
> > > +	DRM_XE_OBSERVATION_TYPE_EU_STALL,
> > >  };
> > >
> > >  /**
> > > @@ -1713,6 +1715,43 @@ struct drm_xe_oa_stream_info {
> > >	__u64 reserved[3];
> > >  };
> > >
> > > +/**
> > > + * enum drm_xe_eu_stall_property_id - EU stall sampling input property ids.
> > > + *
> > > + * These properties are passed to the driver at open as a chain of
> > > + * @drm_xe_ext_set_property structures with @property set to these
> > > + * properties' enums and @value set to the corresponding values of these
> > > + * properties. @drm_xe_user_extension base.name should be set to
> > > + * @DRM_XE_EU_STALL_EXTENSION_SET_PROPERTY.
> > > + *
> > > + * With the file descriptor obtained from open, user space must enable
> > > + * the EU stall stream fd with @DRM_XE_OBSERVATION_IOCTL_ENABLE before
> > > + * calling read.
> >
> > Good to add this. Maybe also add "EIO return from read() indicates buffer
> > overflow" since EIO return is part of uapi.
> Can I add a comment block on EU stall sampling above the comment block
> for this structure? While it is important to document read() returning
> -EIO for buffer overflow, I am wondering if this is the correct place to
> add the comment since it is unrelated to the below structure?

There don't seem to be any such comment blocks in this file. So no need to
overthink this, just add a line about EIO right here and be done with it.

> > > + */
> > > +enum drm_xe_eu_stall_property_id {
> > > +#define DRM_XE_EU_STALL_EXTENSION_SET_PROPERTY		0
> > > +	/**
> > > +	 * @DRM_XE_EU_STALL_PROP_SAMPLE_RATE: Sampling rate
> > > +	 * in multiples of 251 cycles. Valid values are 1 to 7.
> > > +	 * If the value is 1, sampling interval is 251 cycles.
> > > +	 * If the value is 7, sampling interval is 7 x 251 cycles.
> > > +	 */
> > > +	DRM_XE_EU_STALL_PROP_SAMPLE_RATE = 1,
> >
> > There is an unaddressed comment from Umesh about this (on the previous
> > version), we need to address it.
> I am still working on the comment from Umesh and seeking feedback from
> others including the user space folks. I think having this input as it
> is in terms of cycles is more generic and more future proof as the clock
> frequency can vary from GPU to GPU and even for a GPU it can vary from
> time to time due to performance and power reasons?

Will respond to this in the thread where Umesh's original comment is.

Ashutosh

Re: [PATCH v5 3/7] drm/xe/eustall: Implement EU stall sampling APIs for Xe_HPC

[Olson, Matthew]

Small suggestion down below:

On Mon, Nov 18, 2024 at 01:07:15AM -0800, Harish Chegondi wrote:
> Implement EU stall sampling APIs introduced in the previous patch for
> Xe_HPC (PVC). Add register definitions and the code that accesses these
> registers to the APIs.
> 
> Add initialization and clean up functions and their implementations,
> EU stall enable and disable functions, poll() and read() implementations.
> 
> A timer thread periodically polls the EU stall data buffer write pointer
> registers to look for any new data and caches the write pointer. The read
> function compares the cached read and write pointers and copies any new
> data to the user space.
> 
> Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_eu_stall_regs.h |  29 +
>  drivers/gpu/drm/xe/xe_eu_stall.c           | 748 ++++++++++++++++++++-
>  drivers/gpu/drm/xe/xe_eu_stall.h           |  43 ++
>  drivers/gpu/drm/xe/xe_gt.c                 |   6 +
>  drivers/gpu/drm/xe/xe_gt_types.h           |   3 +
>  drivers/gpu/drm/xe/xe_trace.h              |  33 +
>  6 files changed, 837 insertions(+), 25 deletions(-)
>  create mode 100644 drivers/gpu/drm/xe/regs/xe_eu_stall_regs.h
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_eu_stall_regs.h b/drivers/gpu/drm/xe/regs/xe_eu_stall_regs.h
> new file mode 100644
> index 000000000000..2b742890b283
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/regs/xe_eu_stall_regs.h
> @@ -0,0 +1,29 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2024 Intel Corporation
> + */
> +
> +#ifndef _XE_EU_STALL_REGS_H_
> +#define _XE_EU_STALL_REGS_H_
> +
> +#include "regs/xe_reg_defs.h"
> +
> +#define XEHPC_EUSTALL_BASE			XE_REG_MCR(0xe520)
> +#define   XEHPC_EUSTALL_BASE_BUF_ADDR		REG_GENMASK(31, 6)
> +#define   XEHPC_EUSTALL_BASE_XECORE_BUF_SZ	REG_GENMASK(5, 3)
> +#define   XEHPC_EUSTALL_BASE_ENABLE_SAMPLING	REG_BIT(1)
> +
> +#define XEHPC_EUSTALL_BASE_UPPER		XE_REG_MCR(0xe524)
> +
> +#define XEHPC_EUSTALL_REPORT			XE_REG_MCR(0xe528, XE_REG_OPTION_MASKED)
> +#define   XEHPC_EUSTALL_REPORT_WRITE_PTR_MASK	REG_GENMASK(15, 2)
> +#define   XEHPC_EUSTALL_REPORT_OVERFLOW_DROP	REG_BIT(1)
> +
> +#define XEHPC_EUSTALL_REPORT1			XE_REG_MCR(0xe52c, XE_REG_OPTION_MASKED)
> +#define   XEHPC_EUSTALL_REPORT1_READ_PTR_MASK	REG_GENMASK(15, 2)
> +
> +#define XEHPC_EUSTALL_CTRL			XE_REG_MCR(0xe53c, XE_REG_OPTION_MASKED)
> +#define   EUSTALL_MOCS				REG_GENMASK(9, 3)
> +#define   EUSTALL_SAMPLE_RATE			REG_GENMASK(2, 0)
> +
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_eu_stall.c b/drivers/gpu/drm/xe/xe_eu_stall.c
> index e9209fc0d917..5c69f68acb98 100644
> --- a/drivers/gpu/drm/xe/xe_eu_stall.c
> +++ b/drivers/gpu/drm/xe/xe_eu_stall.c
> @@ -8,15 +8,27 @@
>  #include <linux/poll.h>
>  #include <linux/fs.h>
>  
> +#include <drm/drm_drv.h>
>  #include <uapi/drm/xe_drm.h>
>  
> +#include "xe_bo.h"
> +#include "xe_pm.h"
> +#include "xe_trace.h"
>  #include "xe_macros.h"
>  #include "xe_device.h"
> +#include "xe_gt_mcr.h"
>  #include "xe_eu_stall.h"
>  #include "xe_gt_printk.h"
> +#include "xe_force_wake.h"
>  #include "xe_gt_topology.h"
>  #include "xe_observation.h"
>  
> +#include "regs/xe_gt_regs.h"
> +#include "regs/xe_eu_stall_regs.h"
> +
> +#define POLL_FREQUENCY_HZ 100
> +#define POLL_PERIOD_NS (NSEC_PER_SEC / POLL_FREQUENCY_HZ)
> +
>  /**
>   * struct eu_stall_open_properties - EU stall sampling properties received
>   *				     from user space at open.
> @@ -31,6 +43,48 @@ struct eu_stall_open_properties {
>  	struct xe_gt *gt;
>  };
>  
> +/**
> + * struct drm_xe_eu_stall_data_pvc - EU stall data format for PVC
> + *
> + * Bits		Field
> + * 0  to 28	IP (addr)
> + * 29 to 36	active count
> + * 37 to 44	other count
> + * 45 to 52	control count
> + * 53 to 60	pipestall count
> + * 61 to 68	send count
> + * 69 to 76	dist_acc count
> + * 77 to 84	sbid count
> + * 85 to 92	sync count
> + * 93 to 100	inst_fetch count
> + */
> +struct drm_xe_eu_stall_data_pvc {
> +	__u64 ip_addr:29;
> +	__u64 active_count:8;
> +	__u64 other_count:8;
> +	__u64 control_count:8;
> +	__u64 pipestall_count:8;
> +	__u64 send_count:8;
> +	__u64 dist_acc_count:8;
> +	__u64 sbid_count:8;
> +	__u64 sync_count:8;
> +	__u64 inst_fetch_count:8;
> +	__u64 unused_bits:27;
> +	__u64 unused[6];
> +} __packed;
> +
> +static unsigned long
> +xe_eu_stall_data_record_size(struct xe_device *xe)
> +{
> +	enum xe_platform platform = xe->info.platform;
> +	unsigned long record_size = 0;
> +
> +	if (platform == XE_PVC)
> +		record_size = sizeof(struct drm_xe_eu_stall_data_pvc);
> +
> +	return record_size;
> +}
> +
>  /**
>   * num_data_rows - Return the number of EU stall data rows of 64B each
>   *		   for a given data size.
> @@ -43,6 +97,36 @@ num_data_rows(u32 data_size)
>  	return (data_size >> 6);
>  }
>  
> +/**
> + * xe_eu_stall_init() - Allocate and initialize GT level EU stall data
> + *			structure xe_eu_stall_gt within struct xe_gt.
> + *
> + * @gt: GT being initialized.
> + *
> + * Returns: zero on success or a negative error code.
> + */
> +int xe_eu_stall_init(struct xe_gt *gt)
> +{
> +	gt->eu_stall = kzalloc(sizeof(*gt->eu_stall), GFP_KERNEL);
> +	if (!gt->eu_stall)
> +		return -ENOMEM;
> +
> +	mutex_init(&gt->eu_stall->lock);
> +	return 0;
> +}
> +
> +/**
> + * xe_eu_stall_fini() - Clean up the GT level EU stall data
> + *			structure xe_eu_stall_gt within struct xe_gt.
> + *
> + * @gt: GT being cleaned up.
> + */
> +void xe_eu_stall_fini(struct xe_gt *gt)
> +{
> +	mutex_destroy(&gt->eu_stall->lock);
> +	kfree(gt->eu_stall);
> +}
> +
>  static int set_prop_eu_stall_sampling_rate(struct xe_device *xe, u64 value,
>  					   struct eu_stall_open_properties *props)
>  {
> @@ -143,6 +227,235 @@ static int xe_eu_stall_user_extensions(struct xe_device *xe, u64 extension,
>  	return 0;
>  }
>  
> +/**
> + * buf_data_size - Calculate the number of bytes in a circular buffer
> + *		   given the read and write pointers and the size of
> + *		   the buffer.
> + *
> + * @buf_size: Size of the circular buffer
> + * @read_ptr: Read pointer with an additional overflow bit
> + * @write_ptr: Write pointer with an additional overflow bit
> + *
> + * Since the read and write pointers have an additional overflow bit,
> + * this function calculates the offsets from the pointers and use the
> + * offsets to calculate the data size in the buffer.
> + *
> + * Returns: number of bytes of data in the buffer
> + */
> +static u32
> +buf_data_size(size_t buf_size, u32 read_ptr, u32 write_ptr)
> +{
> +	u32 read_offset, write_offset, size = 0;
> +
> +	read_offset = read_ptr & (buf_size - 1);
> +	write_offset = write_ptr & (buf_size - 1);
> +
> +	if (write_offset > read_offset)
> +		size = write_offset - read_offset;
> +	else
> +		size = buf_size - read_offset + write_offset;
> +
> +	return size;
> +}
> +
> +/**
> + * eu_stall_data_buf_check - check for EU stall data in the buffer
> + *
> + * @stream: xe EU stall data stream instance
> + *
> + * Returns: true if the EU stall buffer contains minimum stall data as
> + *	    specified by the event report count, else false.
> + */
> +static bool
> +eu_stall_data_buf_check(struct xe_eu_stall_data_stream *stream)
> +{
> +	u32 read_ptr, write_ptr_reg, write_ptr, total_data = 0;
> +	u32 buf_size = stream->per_xecore_buf_size;
> +	struct xe_gt *gt = stream->gt;
> +	struct per_xecore_buf *xecore_buf;
> +	bool min_data_present;
> +	u16 group, instance;
> +	unsigned int xecore;
> +
> +	min_data_present = false;
> +	for_each_dss_steering(xecore, gt, group, instance) {
> +		xecore_buf = &stream->xecore_buf[xecore];
> +		mutex_lock(&xecore_buf->lock);
> +		read_ptr = xecore_buf->read;
> +		write_ptr_reg = xe_gt_mcr_unicast_read(gt, XEHPC_EUSTALL_REPORT,
> +						       group, instance);
> +		write_ptr = REG_FIELD_GET(XEHPC_EUSTALL_REPORT_WRITE_PTR_MASK, write_ptr_reg);
> +		write_ptr <<= 6;
> +		write_ptr &= ((buf_size << 1) - 1);
> +		if (write_ptr != read_ptr && !min_data_present) {
> +			total_data += buf_data_size(buf_size, read_ptr, write_ptr);
> +			/*
> +			 * Check if there are at least minimum number of stall data
> +			 * rows for poll() to indicate that the data is present.
> +			 * Each stall data row is 64B (cacheline size).
> +			 */
> +			if (num_data_rows(total_data) >= stream->event_report_count)
> +				min_data_present = true;
> +		}
> +		if (write_ptr_reg & XEHPC_EUSTALL_REPORT_OVERFLOW_DROP)
> +			set_bit(xecore, stream->data_drop.mask);
> +		xecore_buf->write = write_ptr;
> +		mutex_unlock(&xecore_buf->lock);
> +	}
> +	return min_data_present;
> +}
> +
> +static void
> +clear_dropped_eviction_line_bit(struct xe_gt *gt, u16 group, u16 instance)
> +{
> +	u32 write_ptr_reg;
> +
> +	/* On PVC, the overflow bit has to be cleared by writing 1 to it. */
> +	write_ptr_reg = _MASKED_BIT_ENABLE(XEHPC_EUSTALL_REPORT_OVERFLOW_DROP);
> +
> +	xe_gt_mcr_unicast_write(gt, XEHPC_EUSTALL_REPORT, write_ptr_reg, group, instance);
> +}
> +
> +static int
> +xe_eu_stall_data_buf_read(struct xe_eu_stall_data_stream *stream,
> +			  char __user *buf, size_t count,
> +			  size_t *total_size, struct xe_gt *gt,
> +			  u16 group, u16 instance, unsigned int xecore)
> +{
> +	u32 read_ptr_reg, read_ptr, write_ptr;
> +	u8 *xecore_start_vaddr, *read_vaddr;
> +	struct xe_device *xe = gt_to_xe(gt);
> +	struct per_xecore_buf *xecore_buf;
> +	size_t size, copy_size, buf_size;
> +	u32 read_offset, write_offset;
> +	unsigned long record_size;
> +
> +	/* Hardware increments the read and write pointers such that they can
> +	 * overflow into one additional bit. For example, a 256KB size buffer
> +	 * offset pointer needs 18 bits. But HW uses 19 bits for the read and
> +	 * write pointers. This technique avoids wasting a slot in the buffer.
> +	 * Read and write offsets are calculated from the pointers in order to
> +	 * check if the write pointer has wrapped around the array.
> +	 */
> +	xecore_buf = &stream->xecore_buf[xecore];
> +	mutex_lock(&xecore_buf->lock);
> +	xecore_start_vaddr = xecore_buf->vaddr;
> +	read_ptr = xecore_buf->read;
> +	write_ptr = xecore_buf->write;
> +	buf_size = stream->per_xecore_buf_size;
> +	read_offset = read_ptr & (buf_size - 1);
> +	write_offset = write_ptr & (buf_size - 1);
> +
> +	if (write_ptr == read_ptr) {
> +		mutex_unlock(&xecore_buf->lock);
> +		return 0;
> +	}
> +
> +	trace_xe_eu_stall_data_read(group, instance, read_ptr, write_ptr,
> +				    read_offset, write_offset, *total_size);
> +	/* If write pointer offset is less than the read pointer offset,
> +	 * it means, write pointer has wrapped around the array.
> +	 */
> +	if (write_offset > read_offset)
> +		size = write_offset - read_offset;
> +	else
> +		size = buf_size - read_offset + write_offset;
> +
> +	/* Read only the data that the user space buffer can accommodate */
> +	if ((*total_size + size) > count) {
> +		record_size = xe_eu_stall_data_record_size(xe);
> +		size = count - *total_size;
> +		size = (size / record_size) * record_size;
> +	}
> +
> +	if (size == 0) {
> +		mutex_unlock(&xecore_buf->lock);
> +		return 0;
> +	}
> +
> +	read_vaddr = xecore_start_vaddr + read_offset;
> +
> +	if (write_offset > read_offset) {
> +		if (copy_to_user((buf + *total_size), read_vaddr, size)) {
> +			mutex_unlock(&xecore_buf->lock);
> +			return -EFAULT;
> +		}
> +	} else {
> +		if (size >= (buf_size - read_offset))
> +			copy_size = buf_size - read_offset;
> +		else
> +			copy_size = size;
> +		if (copy_to_user((buf + *total_size), read_vaddr, copy_size)) {
> +			mutex_unlock(&xecore_buf->lock);
> +			return -EFAULT;
> +		}
> +		if (copy_to_user((buf + *total_size), xecore_start_vaddr, size - copy_size)) {
  
I think this should be `copy_to_user(buf + *total_size + copy_size, ...)`.
As it currently stands, this line will overwrite some of the bits written by the first
call to `copy_to_user`, and will result in userspace reading `size` bytes, but
this function only having written `copy_size` bytes.

We noticed in our userspace profiler that many of our stalls weren't related to any 
particular GPU shader, and so debugged it down to this line; with this change, we no longer
get 0x0 addresses and random-looking data in the stall buffer.
  
> +			mutex_unlock(&xecore_buf->lock);
> +			return -EFAULT;
> +		}
> +	}
> +
> +	*total_size += size;
> +	read_ptr += size;
> +
> +	/* Read pointer can overflow into one additional bit */
> +	read_ptr &= ((buf_size << 1) - 1);
> +	read_ptr_reg = REG_FIELD_PREP(XEHPC_EUSTALL_REPORT1_READ_PTR_MASK, (read_ptr >> 6));
> +	read_ptr_reg &= XEHPC_EUSTALL_REPORT1_READ_PTR_MASK;
> +	read_ptr_reg = _MASKED_FIELD(XEHPC_EUSTALL_REPORT1_READ_PTR_MASK, read_ptr_reg);
> +	xe_gt_mcr_unicast_write(gt, XEHPC_EUSTALL_REPORT1, read_ptr_reg, group, instance);
> +	if (test_bit(xecore, stream->data_drop.mask)) {
> +		clear_dropped_eviction_line_bit(gt, group, instance);
> +		clear_bit(xecore, stream->data_drop.mask);
> +	}
> +	xecore_buf->read = read_ptr;
> +	mutex_unlock(&xecore_buf->lock);
> +	trace_xe_eu_stall_data_read(group, instance, read_ptr, write_ptr,
> +				    read_offset, write_offset, *total_size);
> +	return 0;
> +}
> +
> +/**
> + * xe_eu_stall_stream_read_locked - copy EU stall counters data from the
> + *				    per xecore buffers to the userspace buffer
> + * @stream: A stream opened for EU stall count metrics
> + * @buf: destination buffer given by userspace
> + * @count: the number of bytes userspace wants to read
> + * @ppos: (inout) file seek position (unused)
> + *
> + * Returns: Number of bytes copied or a negative error code
> + * If we've successfully copied any data then reporting that takes
> + * precedence over any internal error status, so the data isn't lost.
> + */
> +static ssize_t
> +xe_eu_stall_stream_read_locked(struct xe_eu_stall_data_stream *stream,
> +			       struct file *file, char __user *buf,
> +			       size_t count, loff_t *ppos)
> +{
> +	struct xe_gt *gt = stream->gt;
> +	size_t total_size = 0;
> +	u16 group, instance;
> +	unsigned int xecore;
> +	int ret = 0;
> +
> +	if (count == 0)
> +		return -EINVAL;
> +
> +	for_each_dss_steering(xecore, gt, group, instance) {
> +		ret = xe_eu_stall_data_buf_read(stream, buf, count, &total_size,
> +						gt, group, instance, xecore);
> +		if (ret || count == total_size)
> +			goto exit;
> +	}
> +exit:
> +	if (total_size)
> +		return total_size;
> +	else if (ret)
> +		return ret;
> +	else
> +		return -EAGAIN;
> +}
> +
>  /**
>   * xe_eu_stall_stream_read - handles userspace read() of a EU stall data stream fd.
>   *
> @@ -159,11 +472,259 @@ static int xe_eu_stall_user_extensions(struct xe_device *xe, u64 extension,
>  static ssize_t xe_eu_stall_stream_read(struct file *file, char __user *buf,
>  				       size_t count, loff_t *ppos)
>  {
> -	ssize_t ret = 0;
> +	struct xe_eu_stall_data_stream *stream = file->private_data;
> +	struct xe_gt *gt = stream->gt;
> +	ssize_t ret;
> +
> +	if (!stream->enabled) {
> +		xe_gt_dbg(gt, "EU stall data stream not enabled to read\n");
> +		return -EINVAL;
> +	}
> +
> +	if (!(file->f_flags & O_NONBLOCK)) {
> +		do {
> +			if (!stream->pollin) {
> +				ret = wait_event_interruptible(stream->poll_wq, stream->pollin);
> +				if (ret)
> +					return -EINTR;
> +			}
> +
> +			mutex_lock(&gt->eu_stall->lock);
> +			ret = xe_eu_stall_stream_read_locked(stream, file, buf, count, ppos);
> +			mutex_unlock(&gt->eu_stall->lock);
> +		} while (ret == -EAGAIN);
> +	} else {
> +		mutex_lock(&gt->eu_stall->lock);
> +		ret = xe_eu_stall_stream_read_locked(stream, file, buf, count, ppos);
> +		mutex_unlock(&gt->eu_stall->lock);
> +	}
> +
> +	stream->pollin = false;
>  
>  	return ret;
>  }
>  
> +static void
> +free_eu_stall_data_buf(struct xe_eu_stall_data_stream *stream)
> +{
> +	if (stream->bo) {
> +		xe_bo_unpin_map_no_vm(stream->bo);
> +		stream->bo = NULL;
> +	}
> +	destroy_workqueue(stream->buf_check_wq);
> +}
> +
> +static int alloc_eu_stall_data_buf(struct xe_eu_stall_data_stream *stream,
> +				   u16 num_xecore)
> +{
> +	struct xe_tile *tile = stream->gt->tile;
> +	struct xe_bo *bo;
> +	u32 size;
> +
> +	size = stream->per_xecore_buf_size * num_xecore;
> +
> +	bo = xe_bo_create_pin_map(tile->xe, tile, NULL,
> +				  size, ttm_bo_type_kernel,
> +				  XE_BO_FLAG_SYSTEM |
> +				  XE_BO_FLAG_GGTT);
> +	if (IS_ERR(bo))
> +		return PTR_ERR(bo);
> +
> +	stream->bo = bo;
> +
> +	return 0;
> +}
> +
> +static u32
> +gen_eustall_base(struct xe_eu_stall_data_stream *stream, bool enable)
> +{
> +	u32 val = xe_bo_ggtt_addr(stream->bo);
> +	u32 sz;
> +
> +	XE_WARN_ON(!IS_ALIGNED(val, 64));
> +
> +	switch (stream->per_xecore_buf_size) {
> +	case SZ_128K:
> +		sz = 0;
> +		break;
> +	case SZ_256K:
> +		sz = 1;
> +		break;
> +	case SZ_512K:
> +		sz = 2;
> +		break;
> +	default:
> +		xe_gt_warn(stream->gt, "Missing case per XeCore buffer size == %lu)\n",
> +			   (long)(stream->per_xecore_buf_size));
> +		sz = 2;
> +	}
> +
> +	val |= REG_FIELD_PREP(XEHPC_EUSTALL_BASE_XECORE_BUF_SZ, sz);
> +	if (enable)
> +		val |= XEHPC_EUSTALL_BASE_ENABLE_SAMPLING;
> +
> +	return val;
> +}
> +
> +static void
> +xe_eu_stall_stream_enable(struct xe_eu_stall_data_stream *stream)
> +{
> +	struct xe_gt *gt = stream->gt;
> +	u32 reg_value;
> +
> +	/* Take runtime pm ref and forcewake to disable RC6 */
> +	xe_pm_runtime_get(gt_to_xe(gt));
> +	XE_WARN_ON(xe_force_wake_get(gt_to_fw(gt), XE_FW_RENDER));
> +
> +	reg_value = gen_eustall_base(stream, true);
> +	xe_gt_mcr_multicast_write(gt, XEHPC_EUSTALL_BASE, reg_value);
> +}
> +
> +static void
> +xe_eu_stall_stream_disable(struct xe_eu_stall_data_stream *stream)
> +{
> +	struct xe_gt *gt = stream->gt;
> +	u16 group, instance;
> +	unsigned int xecore;
> +	u32 reg_value;
> +
> +	/*
> +	 * Before disabling EU stall sampling, check if any of the
> +	 * XEHPC_EUSTALL_REPORT registers have the drop bit set. If set,
> +	 * clear the bit. If the user space application reads all the
> +	 * stall data, the drop bit would be cleared during the read.
> +	 * But if there is any unread data and the drop bit is set for
> +	 * any subslice, the drop bit would continue to be set even
> +	 * after disabling EU stall sampling and may cause erroneous
> +	 * stall data in the subsequent stall data sampling run.
> +	 */
> +	for_each_dss_steering(xecore, gt, group, instance) {
> +		reg_value = xe_gt_mcr_unicast_read(gt, XEHPC_EUSTALL_REPORT,
> +						   group, instance);
> +		if (reg_value & XEHPC_EUSTALL_REPORT_OVERFLOW_DROP)
> +			clear_dropped_eviction_line_bit(gt, group, instance);
> +	}
> +	reg_value = gen_eustall_base(stream, false);
> +	xe_gt_mcr_multicast_write(gt, XEHPC_EUSTALL_BASE, reg_value);
> +
> +	xe_force_wake_put(gt_to_fw(gt), XE_FW_RENDER);
> +	xe_pm_runtime_put(gt_to_xe(gt));
> +}
> +
> +static void eu_stall_buf_check_work_fn(struct work_struct *work)
> +{
> +	struct xe_eu_stall_data_stream *stream =
> +		container_of(work, typeof(*stream), buf_check_work);
> +
> +	if (eu_stall_data_buf_check(stream)) {
> +		stream->pollin = true;
> +		wake_up(&stream->poll_wq);
> +	}
> +}
> +
> +static enum
> +hrtimer_restart eu_stall_poll_check_timer_cb(struct hrtimer *hrtimer)
> +{
> +	struct xe_eu_stall_data_stream *stream =
> +		container_of(hrtimer, typeof(*stream), poll_check_timer);
> +
> +	queue_work(stream->buf_check_wq, &stream->buf_check_work);
> +	hrtimer_forward_now(hrtimer, ns_to_ktime(stream->poll_period));
> +
> +	return HRTIMER_RESTART;
> +}
> +
> +static int xe_eu_stall_stream_init(struct xe_eu_stall_data_stream *stream,
> +				   struct eu_stall_open_properties *props)
> +{
> +	u32 write_ptr_reg, write_ptr, read_ptr_reg;
> +	u32 vaddr_offset, base_reg_value;
> +	struct xe_gt *gt = stream->gt;
> +	struct per_xecore_buf *xecore_buf;
> +	u16 group, instance, num_xecore;
> +	xe_dss_mask_t all_xecore;
> +	int ret, xecore;
> +
> +	init_waitqueue_head(&stream->poll_wq);
> +	INIT_WORK(&stream->buf_check_work, eu_stall_buf_check_work_fn);
> +	stream->buf_check_wq = alloc_ordered_workqueue("xe_eustall", 0);
> +	if (!stream->buf_check_wq)
> +		return -ENOMEM;
> +	hrtimer_init(&stream->poll_check_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
> +	stream->poll_check_timer.function = eu_stall_poll_check_timer_cb;
> +	stream->event_report_count = props->event_report_count;
> +	stream->per_xecore_buf_size = SZ_512K;
> +	stream->poll_period = POLL_PERIOD_NS;
> +
> +	bitmap_or(all_xecore, gt->fuse_topo.g_dss_mask, gt->fuse_topo.c_dss_mask,
> +		  XE_MAX_DSS_FUSE_BITS);
> +	/*
> +	 * Enabled subslices can be discontiguous. Find the maximum number of subslices
> +	 * that are enabled.
> +	 */
> +	num_xecore = xe_gt_topology_mask_last_dss(all_xecore) + 1;
> +
> +	ret = alloc_eu_stall_data_buf(stream, num_xecore);
> +	if (ret)
> +		return ret;
> +
> +	stream->xecore_buf = kcalloc(num_xecore, sizeof(*stream->xecore_buf), GFP_KERNEL);
> +	if (!stream->xecore_buf)
> +		return -ENOMEM;
> +
> +	bitmap_zero(stream->data_drop.mask, XE_MAX_DSS_FUSE_BITS);
> +
> +	xe_pm_runtime_get(gt_to_xe(gt));
> +	XE_WARN_ON(xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL));
> +
> +	base_reg_value = gen_eustall_base(stream, false);
> +	xe_gt_mcr_multicast_write(gt, XEHPC_EUSTALL_BASE, base_reg_value);
> +	/* GGTT addresses can never be > 32 bits */
> +	xe_gt_mcr_multicast_write(gt, XEHPC_EUSTALL_BASE_UPPER, 0);
> +	base_reg_value = _MASKED_FIELD(EUSTALL_MOCS | EUSTALL_SAMPLE_RATE,
> +				       REG_FIELD_PREP(EUSTALL_MOCS, gt->mocs.uc_index << 1) |
> +				       REG_FIELD_PREP(EUSTALL_SAMPLE_RATE,
> +						      props->eu_stall_sampling_rate));
> +	xe_gt_mcr_multicast_write(gt, XEHPC_EUSTALL_CTRL, base_reg_value);
> +
> +	for_each_dss_steering(xecore, gt, group, instance) {
> +		write_ptr_reg = xe_gt_mcr_unicast_read(gt, XEHPC_EUSTALL_REPORT,
> +						       group, instance);
> +		write_ptr = REG_FIELD_GET(XEHPC_EUSTALL_REPORT_WRITE_PTR_MASK, write_ptr_reg);
> +		write_ptr <<= 6;
> +		write_ptr &= ((stream->per_xecore_buf_size << 1) - 1);
> +		read_ptr_reg = write_ptr >> 6;
> +		read_ptr_reg = REG_FIELD_PREP(XEHPC_EUSTALL_REPORT1_READ_PTR_MASK, write_ptr);
> +		read_ptr_reg &= XEHPC_EUSTALL_REPORT1_READ_PTR_MASK;
> +		read_ptr_reg = _MASKED_FIELD(XEHPC_EUSTALL_REPORT1_READ_PTR_MASK, read_ptr_reg);
> +		xe_gt_mcr_unicast_write(gt, XEHPC_EUSTALL_REPORT1,
> +					read_ptr_reg, group, instance);
> +		xecore_buf = &stream->xecore_buf[xecore];
> +		vaddr_offset = xecore * stream->per_xecore_buf_size;
> +		xecore_buf->vaddr = stream->bo->vmap.vaddr + vaddr_offset;
> +		xecore_buf->write = write_ptr;
> +		xecore_buf->read = write_ptr;
> +		mutex_init(&xecore_buf->lock);
> +	}
> +	xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL);
> +	xe_pm_runtime_put(gt_to_xe(gt));
> +	return 0;
> +}
> +
> +static __poll_t
> +xe_eu_stall_stream_poll_locked(struct xe_eu_stall_data_stream *stream,
> +			       struct file *file, poll_table *wait)
> +{
> +	__poll_t events = 0;
> +
> +	poll_wait(file, &stream->poll_wq, wait);
> +
> +	if (stream->pollin)
> +		events |= EPOLLIN;
> +
> +	return events;
> +}
> +
>  /**
>   * xe_eu_stall_stream_poll - handles userspace poll() of a EU stall data stream fd.
>   *
> @@ -175,11 +736,60 @@ static ssize_t xe_eu_stall_stream_read(struct file *file, char __user *buf,
>  static __poll_t
>  xe_eu_stall_stream_poll(struct file *file, poll_table *wait)
>  {
> -	__poll_t ret = 0;
> +	struct xe_eu_stall_data_stream *stream = file->private_data;
> +	struct xe_gt *gt = stream->gt;
> +	__poll_t ret;
> +
> +	mutex_lock(&gt->eu_stall->lock);
> +	ret = xe_eu_stall_stream_poll_locked(stream, file, wait);
> +	mutex_unlock(&gt->eu_stall->lock);
>  
>  	return ret;
>  }
>  
> +static void
> +xe_eu_stall_enable_locked(struct xe_eu_stall_data_stream *stream)
> +{
> +	if (stream->enabled)
> +		return;
> +
> +	stream->enabled = true;
> +
> +	xe_eu_stall_stream_enable(stream);
> +	hrtimer_start(&stream->poll_check_timer,
> +		      ns_to_ktime(stream->poll_period),
> +		      HRTIMER_MODE_REL);
> +}
> +
> +static void
> +xe_eu_stall_disable_locked(struct xe_eu_stall_data_stream *stream)
> +{
> +	if (!stream->enabled)
> +		return;
> +
> +	stream->enabled = false;
> +
> +	hrtimer_cancel(&stream->poll_check_timer);
> +	flush_workqueue(stream->buf_check_wq);
> +	xe_eu_stall_stream_disable(stream);
> +}
> +
> +static long
> +xe_eu_stall_stream_ioctl_locked(struct xe_eu_stall_data_stream *stream,
> +				unsigned int cmd, unsigned long arg)
> +{
> +	switch (cmd) {
> +	case DRM_XE_OBSERVATION_IOCTL_ENABLE:
> +		xe_eu_stall_enable_locked(stream);
> +		return 0;
> +	case DRM_XE_OBSERVATION_IOCTL_DISABLE:
> +		xe_eu_stall_disable_locked(stream);
> +		return 0;
> +	}
> +
> +	return -EINVAL;
> +}
> +
>  /**
>   * xe_eu_stall_stream_ioctl - support ioctl() of a xe EU stall data stream fd.
>   *
> @@ -194,14 +804,22 @@ static long xe_eu_stall_stream_ioctl(struct file *file,
>  				     unsigned int cmd,
>  				     unsigned long arg)
>  {
> -	switch (cmd) {
> -	case DRM_XE_OBSERVATION_IOCTL_ENABLE:
> -		return 0;
> -	case DRM_XE_OBSERVATION_IOCTL_DISABLE:
> -		return 0;
> -	}
> +	struct xe_eu_stall_data_stream *stream = file->private_data;
> +	struct xe_gt *gt = stream->gt;
> +	long ret;
>  
> -	return -EINVAL;
> +	mutex_lock(&gt->eu_stall->lock);
> +	ret = xe_eu_stall_stream_ioctl_locked(stream, cmd, arg);
> +	mutex_unlock(&gt->eu_stall->lock);
> +
> +	return ret;
> +}
> +
> +static void
> +xe_eu_stall_stream_close_locked(struct xe_eu_stall_data_stream *stream)
> +{
> +	xe_eu_stall_disable_locked(stream);
> +	free_eu_stall_data_buf(stream);
>  }
>  
>  /**
> @@ -214,6 +832,19 @@ static long xe_eu_stall_stream_ioctl(struct file *file,
>   */
>  static int xe_eu_stall_stream_close(struct inode *inode, struct file *file)
>  {
> +	struct xe_eu_stall_data_stream *stream = file->private_data;
> +	struct xe_gt *gt = stream->gt;
> +
> +	mutex_lock(&gt->eu_stall->lock);
> +	xe_eu_stall_stream_close_locked(stream);
> +	kfree(stream->xecore_buf);
> +	kfree(stream);
> +	gt->eu_stall->stream = NULL;
> +	mutex_unlock(&gt->eu_stall->lock);
> +
> +	/* Release the reference the EU stall stream kept on the driver */
> +	drm_dev_put(&gt->tile->xe->drm);
> +
>  	return 0;
>  }
>  
> @@ -229,7 +860,79 @@ static const struct file_operations fops_eu_stall = {
>  
>  static inline bool has_eu_stall_sampling_support(struct xe_device *xe)
>  {
> -	return false;
> +	return ((xe->info.platform == XE_PVC) ? true : false);
> +}
> +
> +/**
> + * xe_eu_stall_stream_open_locked - Open a EU stall data stream FD.
> + * @dev: drm device instance
> + * @props: individually validated u64 property value pairs
> + * @file: drm file
> + *
> + * Returns: zero on success or a negative error code.
> + */
> +static int
> +xe_eu_stall_stream_open_locked(struct drm_device *dev,
> +			       struct eu_stall_open_properties *props,
> +			       struct drm_file *file)
> +{
> +	struct xe_device *xe = to_xe_device(dev);
> +	struct xe_eu_stall_data_stream *stream;
> +	struct xe_gt *gt = props->gt;
> +	unsigned long f_flags = 0;
> +	int ret, stream_fd;
> +
> +	if (!has_eu_stall_sampling_support(xe)) {
> +		xe_gt_dbg(gt, "EU stall monitoring is not supported on this platform\n");
> +		return -EPERM;
> +	}
> +
> +	if (xe_observation_paranoid && !perfmon_capable()) {
> +		xe_gt_dbg(gt, "Insufficient privileges for EU stall monitoring\n");
> +		return -EACCES;
> +	}
> +
> +	/* Only one session can be active at any time */
> +	if (gt->eu_stall->stream) {
> +		xe_gt_dbg(gt, "EU stall sampling session already active\n");
> +		return -EBUSY;
> +	}
> +
> +	stream = kzalloc(sizeof(*stream), GFP_KERNEL);
> +	if (!stream)
> +		return -ENOMEM;
> +
> +	gt->eu_stall->stream = stream;
> +	stream->gt = gt;
> +
> +	ret = xe_eu_stall_stream_init(stream, props);
> +	if (ret) {
> +		xe_gt_dbg(gt, "EU stall stream init failed : %d\n", ret);
> +		goto err_alloc;
> +	}
> +
> +	stream_fd = anon_inode_getfd("[xe_eu_stall]", &fops_eu_stall,
> +				     stream, f_flags);
> +	if (stream_fd < 0) {
> +		ret = stream_fd;
> +		xe_gt_dbg(gt, "EU stall inode get fd failed : %d\n", ret);
> +		goto err_open;
> +	}
> +
> +	/* Take a reference on the driver that will be kept with stream_fd
> +	 * until its release.
> +	 */
> +	drm_dev_get(&gt->tile->xe->drm);
> +
> +	return stream_fd;
> +
> +err_open:
> +	free_eu_stall_data_buf(stream);
> +err_alloc:
> +	gt->eu_stall->stream = NULL;
> +	kfree(stream->xecore_buf);
> +	kfree(stream);
> +	return ret;
>  }
>  
>  /**
> @@ -251,10 +954,15 @@ int xe_eu_stall_stream_open(struct drm_device *dev,
>  {
>  	struct xe_device *xe = to_xe_device(dev);
>  	struct eu_stall_open_properties props;
> -	int ret, stream_fd;
> +	int ret;
>  
>  	memset(&props, 0, sizeof(struct eu_stall_open_properties));
>  
> +	/* Set default values */
> +	props.gt = NULL;
> +	props.eu_stall_sampling_rate = 4;
> +	props.event_report_count = 1;
> +
>  	ret = xe_eu_stall_user_extensions(xe, data, &props);
>  	if (ret)
>  		return ret;
> @@ -264,19 +972,9 @@ int xe_eu_stall_stream_open(struct drm_device *dev,
>  		return -EINVAL;
>  	}
>  
> -	if (xe_observation_paranoid && !perfmon_capable()) {
> -		xe_gt_dbg(props.gt, "Insufficient privileges for EU stall monitoring\n");
> -		return -EACCES;
> -	}
> +	mutex_lock(&props.gt->eu_stall->lock);
> +	ret = xe_eu_stall_stream_open_locked(dev, &props, file);
> +	mutex_unlock(&props.gt->eu_stall->lock);
>  
> -	if (!has_eu_stall_sampling_support(xe)) {
> -		xe_gt_dbg(props.gt, "EU stall monitoring is not supported on this platform\n");
> -		return -EPERM;
> -	}
> -	stream_fd = anon_inode_getfd("[xe_eu_stall]", &fops_eu_stall,
> -				     NULL, 0);
> -	if (stream_fd < 0)
> -		xe_gt_dbg(props.gt, "EU stall inode get fd failed : %d\n", stream_fd);
> -
> -	return stream_fd;
> +	return ret;
>  }
> diff --git a/drivers/gpu/drm/xe/xe_eu_stall.h b/drivers/gpu/drm/xe/xe_eu_stall.h
> index 70fc89480df2..00896812db41 100644
> --- a/drivers/gpu/drm/xe/xe_eu_stall.h
> +++ b/drivers/gpu/drm/xe/xe_eu_stall.h
> @@ -6,6 +6,49 @@
>  #ifndef __XE_EU_STALL_H__
>  #define __XE_EU_STALL_H__
>  
> +#include "xe_gt_types.h"
> +
> +struct per_xecore_buf {
> +	u8 *vaddr;
> +	u32 write;
> +	u32 read;
> +	/* lock to protect read and write pointers */
> +	struct mutex lock;
> +};
> +
> +/**
> + * struct xe_eu_stall_data_stream - state of EU stall data stream FD
> + */
> +struct xe_eu_stall_data_stream {
> +	bool pollin;
> +	bool enabled;
> +	u64 poll_period;
> +	u32 event_report_count;
> +	size_t per_xecore_buf_size;
> +	wait_queue_head_t poll_wq;
> +
> +	struct xe_gt *gt;
> +	struct xe_bo *bo;
> +	struct per_xecore_buf *xecore_buf;
> +	struct {
> +		xe_dss_mask_t mask;
> +	} data_drop;
> +	struct hrtimer poll_check_timer;
> +	struct work_struct buf_check_work;
> +	struct workqueue_struct *buf_check_wq;
> +};
> +
> +struct xe_eu_stall_gt {
> +	/* Lock to protect stream */
> +	struct mutex lock;
> +
> +	/* Execution Unit (EU) stall data stream */
> +	struct xe_eu_stall_data_stream *stream;
> +};
> +
> +int xe_eu_stall_init(struct xe_gt *gt);
> +void xe_eu_stall_fini(struct xe_gt *gt);
> +
>  int xe_eu_stall_stream_open(struct drm_device *dev,
>  			    u64 data,
>  			    struct drm_file *file);
> diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
> index d6744be01a68..6e9598ddabd7 100644
> --- a/drivers/gpu/drm/xe/xe_gt.c
> +++ b/drivers/gpu/drm/xe/xe_gt.c
> @@ -59,6 +59,7 @@
>  #include "xe_vm.h"
>  #include "xe_wa.h"
>  #include "xe_wopcm.h"
> +#include "xe_eu_stall.h"
>  
>  static void gt_fini(struct drm_device *drm, void *arg)
>  {
> @@ -158,6 +159,7 @@ void xe_gt_remove(struct xe_gt *gt)
>  		xe_hw_fence_irq_finish(&gt->fence_irq[i]);
>  
>  	xe_gt_disable_host_l2_vram(gt);
> +	xe_eu_stall_fini(gt);
>  }
>  
>  static void gt_reset_worker(struct work_struct *w);
> @@ -622,6 +624,10 @@ int xe_gt_init(struct xe_gt *gt)
>  
>  	xe_gt_record_user_engines(gt);
>  
> +	err = xe_eu_stall_init(gt);
> +	if (err)
> +		return err;
> +
>  	return 0;
>  }
>  
> diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
> index 6e66bf0e8b3f..833a1a67e9ae 100644
> --- a/drivers/gpu/drm/xe/xe_gt_types.h
> +++ b/drivers/gpu/drm/xe/xe_gt_types.h
> @@ -430,6 +430,9 @@ struct xe_gt {
>  
>  	/** @oa: oa observation subsystem per gt info */
>  	struct xe_oa_gt oa;
> +
> +	/** @eu_stall: EU stall counters subsystem per gt info */
> +	struct xe_eu_stall_gt *eu_stall;
>  };
>  
>  #endif
> diff --git a/drivers/gpu/drm/xe/xe_trace.h b/drivers/gpu/drm/xe/xe_trace.h
> index de682978c4bf..bcc34e47808a 100644
> --- a/drivers/gpu/drm/xe/xe_trace.h
> +++ b/drivers/gpu/drm/xe/xe_trace.h
> @@ -424,6 +424,39 @@ DEFINE_EVENT(xe_pm_runtime, xe_pm_runtime_get_ioctl,
>  	     TP_ARGS(xe, caller)
>  );
>  
> +TRACE_EVENT(xe_eu_stall_data_read,
> +	    TP_PROTO(u8 slice, u8 subslice,
> +		     u32 read_ptr, u32 write_ptr,
> +		     u32 read_offset, u32 write_offset,
> +		     size_t total_size),
> +	    TP_ARGS(slice, subslice, read_ptr, write_ptr,
> +		    read_offset, write_offset, total_size),
> +
> +	    TP_STRUCT__entry(__field(u8, slice)
> +			     __field(u8, subslice)
> +			     __field(u32, read_ptr)
> +			     __field(u32, write_ptr)
> +			     __field(u32, read_offset)
> +			     __field(u32, write_offset)
> +			     __field(size_t, total_size)
> +			     ),
> +
> +	    TP_fast_assign(__entry->slice = slice;
> +			   __entry->subslice = subslice;
> +			   __entry->read_ptr = read_ptr;
> +			   __entry->write_ptr = write_ptr;
> +			   __entry->read_offset = read_offset;
> +			   __entry->write_offset = write_offset;
> +			   __entry->total_size = total_size;
> +			   ),
> +
> +	    TP_printk("slice:%u subslice:%u readptr:0x%x writeptr:0x%x read off:%u write off:%u size:%zu ",
> +		      __entry->slice, __entry->subslice,
> +		      __entry->read_ptr, __entry->write_ptr,
> +		      __entry->read_offset, __entry->write_offset,
> +		      __entry->total_size)
> +);
> +
>  #endif
>  
>  /* This part must be outside protection */
> -- 
> 2.45.1
> 

Re: [PATCH v5 3/7] drm/xe/eustall: Implement EU stall sampling APIs for Xe_HPC

[Harish Chegondi]

On Thu, Nov 21, 2024 at 09:10:45AM -0600, Olson, Matthew wrote:
> Small suggestion down below:
> 
> On Mon, Nov 18, 2024 at 01:07:15AM -0800, Harish Chegondi wrote:
> > Implement EU stall sampling APIs introduced in the previous patch for
> > Xe_HPC (PVC). Add register definitions and the code that accesses these
> > registers to the APIs.
> > 
> > Add initialization and clean up functions and their implementations,
> > EU stall enable and disable functions, poll() and read() implementations.
> > 
> > A timer thread periodically polls the EU stall data buffer write pointer
> > registers to look for any new data and caches the write pointer. The read
> > function compares the cached read and write pointers and copies any new
> > data to the user space.
> > 
> > Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
> > ---
> >  drivers/gpu/drm/xe/regs/xe_eu_stall_regs.h |  29 +
> >  drivers/gpu/drm/xe/xe_eu_stall.c           | 748 ++++++++++++++++++++-
> >  drivers/gpu/drm/xe/xe_eu_stall.h           |  43 ++
> >  drivers/gpu/drm/xe/xe_gt.c                 |   6 +
> >  drivers/gpu/drm/xe/xe_gt_types.h           |   3 +
> >  drivers/gpu/drm/xe/xe_trace.h              |  33 +
> >  6 files changed, 837 insertions(+), 25 deletions(-)
> >  create mode 100644 drivers/gpu/drm/xe/regs/xe_eu_stall_regs.h
> > 
> > diff --git a/drivers/gpu/drm/xe/regs/xe_eu_stall_regs.h b/drivers/gpu/drm/xe/regs/xe_eu_stall_regs.h
> > new file mode 100644
> > index 000000000000..2b742890b283
> > --- /dev/null
> > +++ b/drivers/gpu/drm/xe/regs/xe_eu_stall_regs.h
> > @@ -0,0 +1,29 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/*
> > + * Copyright © 2024 Intel Corporation
> > + */
> > +
> > +#ifndef _XE_EU_STALL_REGS_H_
> > +#define _XE_EU_STALL_REGS_H_
> > +
> > +#include "regs/xe_reg_defs.h"
> > +
> > +#define XEHPC_EUSTALL_BASE			XE_REG_MCR(0xe520)
> > +#define   XEHPC_EUSTALL_BASE_BUF_ADDR		REG_GENMASK(31, 6)
> > +#define   XEHPC_EUSTALL_BASE_XECORE_BUF_SZ	REG_GENMASK(5, 3)
> > +#define   XEHPC_EUSTALL_BASE_ENABLE_SAMPLING	REG_BIT(1)
> > +
> > +#define XEHPC_EUSTALL_BASE_UPPER		XE_REG_MCR(0xe524)
> > +
> > +#define XEHPC_EUSTALL_REPORT			XE_REG_MCR(0xe528, XE_REG_OPTION_MASKED)
> > +#define   XEHPC_EUSTALL_REPORT_WRITE_PTR_MASK	REG_GENMASK(15, 2)
> > +#define   XEHPC_EUSTALL_REPORT_OVERFLOW_DROP	REG_BIT(1)
> > +
> > +#define XEHPC_EUSTALL_REPORT1			XE_REG_MCR(0xe52c, XE_REG_OPTION_MASKED)
> > +#define   XEHPC_EUSTALL_REPORT1_READ_PTR_MASK	REG_GENMASK(15, 2)
> > +
> > +#define XEHPC_EUSTALL_CTRL			XE_REG_MCR(0xe53c, XE_REG_OPTION_MASKED)
> > +#define   EUSTALL_MOCS				REG_GENMASK(9, 3)
> > +#define   EUSTALL_SAMPLE_RATE			REG_GENMASK(2, 0)
> > +
> > +#endif
> > diff --git a/drivers/gpu/drm/xe/xe_eu_stall.c b/drivers/gpu/drm/xe/xe_eu_stall.c
> > index e9209fc0d917..5c69f68acb98 100644
> > --- a/drivers/gpu/drm/xe/xe_eu_stall.c
> > +++ b/drivers/gpu/drm/xe/xe_eu_stall.c
> > @@ -8,15 +8,27 @@
> >  #include <linux/poll.h>
> >  #include <linux/fs.h>
> >  
> > +#include <drm/drm_drv.h>
> >  #include <uapi/drm/xe_drm.h>
> >  
> > +#include "xe_bo.h"
> > +#include "xe_pm.h"
> > +#include "xe_trace.h"
> >  #include "xe_macros.h"
> >  #include "xe_device.h"
> > +#include "xe_gt_mcr.h"
> >  #include "xe_eu_stall.h"
> >  #include "xe_gt_printk.h"
> > +#include "xe_force_wake.h"
> >  #include "xe_gt_topology.h"
> >  #include "xe_observation.h"
> >  
> > +#include "regs/xe_gt_regs.h"
> > +#include "regs/xe_eu_stall_regs.h"
> > +
> > +#define POLL_FREQUENCY_HZ 100
> > +#define POLL_PERIOD_NS (NSEC_PER_SEC / POLL_FREQUENCY_HZ)
> > +
> >  /**
> >   * struct eu_stall_open_properties - EU stall sampling properties received
> >   *				     from user space at open.
> > @@ -31,6 +43,48 @@ struct eu_stall_open_properties {
> >  	struct xe_gt *gt;
> >  };
> >  
> > +/**
> > + * struct drm_xe_eu_stall_data_pvc - EU stall data format for PVC
> > + *
> > + * Bits		Field
> > + * 0  to 28	IP (addr)
> > + * 29 to 36	active count
> > + * 37 to 44	other count
> > + * 45 to 52	control count
> > + * 53 to 60	pipestall count
> > + * 61 to 68	send count
> > + * 69 to 76	dist_acc count
> > + * 77 to 84	sbid count
> > + * 85 to 92	sync count
> > + * 93 to 100	inst_fetch count
> > + */
> > +struct drm_xe_eu_stall_data_pvc {
> > +	__u64 ip_addr:29;
> > +	__u64 active_count:8;
> > +	__u64 other_count:8;
> > +	__u64 control_count:8;
> > +	__u64 pipestall_count:8;
> > +	__u64 send_count:8;
> > +	__u64 dist_acc_count:8;
> > +	__u64 sbid_count:8;
> > +	__u64 sync_count:8;
> > +	__u64 inst_fetch_count:8;
> > +	__u64 unused_bits:27;
> > +	__u64 unused[6];
> > +} __packed;
> > +
> > +static unsigned long
> > +xe_eu_stall_data_record_size(struct xe_device *xe)
> > +{
> > +	enum xe_platform platform = xe->info.platform;
> > +	unsigned long record_size = 0;
> > +
> > +	if (platform == XE_PVC)
> > +		record_size = sizeof(struct drm_xe_eu_stall_data_pvc);
> > +
> > +	return record_size;
> > +}
> > +
> >  /**
> >   * num_data_rows - Return the number of EU stall data rows of 64B each
> >   *		   for a given data size.
> > @@ -43,6 +97,36 @@ num_data_rows(u32 data_size)
> >  	return (data_size >> 6);
> >  }
> >  
> > +/**
> > + * xe_eu_stall_init() - Allocate and initialize GT level EU stall data
> > + *			structure xe_eu_stall_gt within struct xe_gt.
> > + *
> > + * @gt: GT being initialized.
> > + *
> > + * Returns: zero on success or a negative error code.
> > + */
> > +int xe_eu_stall_init(struct xe_gt *gt)
> > +{
> > +	gt->eu_stall = kzalloc(sizeof(*gt->eu_stall), GFP_KERNEL);
> > +	if (!gt->eu_stall)
> > +		return -ENOMEM;
> > +
> > +	mutex_init(&gt->eu_stall->lock);
> > +	return 0;
> > +}
> > +
> > +/**
> > + * xe_eu_stall_fini() - Clean up the GT level EU stall data
> > + *			structure xe_eu_stall_gt within struct xe_gt.
> > + *
> > + * @gt: GT being cleaned up.
> > + */
> > +void xe_eu_stall_fini(struct xe_gt *gt)
> > +{
> > +	mutex_destroy(&gt->eu_stall->lock);
> > +	kfree(gt->eu_stall);
> > +}
> > +
> >  static int set_prop_eu_stall_sampling_rate(struct xe_device *xe, u64 value,
> >  					   struct eu_stall_open_properties *props)
> >  {
> > @@ -143,6 +227,235 @@ static int xe_eu_stall_user_extensions(struct xe_device *xe, u64 extension,
> >  	return 0;
> >  }
> >  
> > +/**
> > + * buf_data_size - Calculate the number of bytes in a circular buffer
> > + *		   given the read and write pointers and the size of
> > + *		   the buffer.
> > + *
> > + * @buf_size: Size of the circular buffer
> > + * @read_ptr: Read pointer with an additional overflow bit
> > + * @write_ptr: Write pointer with an additional overflow bit
> > + *
> > + * Since the read and write pointers have an additional overflow bit,
> > + * this function calculates the offsets from the pointers and use the
> > + * offsets to calculate the data size in the buffer.
> > + *
> > + * Returns: number of bytes of data in the buffer
> > + */
> > +static u32
> > +buf_data_size(size_t buf_size, u32 read_ptr, u32 write_ptr)
> > +{
> > +	u32 read_offset, write_offset, size = 0;
> > +
> > +	read_offset = read_ptr & (buf_size - 1);
> > +	write_offset = write_ptr & (buf_size - 1);
> > +
> > +	if (write_offset > read_offset)
> > +		size = write_offset - read_offset;
> > +	else
> > +		size = buf_size - read_offset + write_offset;
> > +
> > +	return size;
> > +}
> > +
> > +/**
> > + * eu_stall_data_buf_check - check for EU stall data in the buffer
> > + *
> > + * @stream: xe EU stall data stream instance
> > + *
> > + * Returns: true if the EU stall buffer contains minimum stall data as
> > + *	    specified by the event report count, else false.
> > + */
> > +static bool
> > +eu_stall_data_buf_check(struct xe_eu_stall_data_stream *stream)
> > +{
> > +	u32 read_ptr, write_ptr_reg, write_ptr, total_data = 0;
> > +	u32 buf_size = stream->per_xecore_buf_size;
> > +	struct xe_gt *gt = stream->gt;
> > +	struct per_xecore_buf *xecore_buf;
> > +	bool min_data_present;
> > +	u16 group, instance;
> > +	unsigned int xecore;
> > +
> > +	min_data_present = false;
> > +	for_each_dss_steering(xecore, gt, group, instance) {
> > +		xecore_buf = &stream->xecore_buf[xecore];
> > +		mutex_lock(&xecore_buf->lock);
> > +		read_ptr = xecore_buf->read;
> > +		write_ptr_reg = xe_gt_mcr_unicast_read(gt, XEHPC_EUSTALL_REPORT,
> > +						       group, instance);
> > +		write_ptr = REG_FIELD_GET(XEHPC_EUSTALL_REPORT_WRITE_PTR_MASK, write_ptr_reg);
> > +		write_ptr <<= 6;
> > +		write_ptr &= ((buf_size << 1) - 1);
> > +		if (write_ptr != read_ptr && !min_data_present) {
> > +			total_data += buf_data_size(buf_size, read_ptr, write_ptr);
> > +			/*
> > +			 * Check if there are at least minimum number of stall data
> > +			 * rows for poll() to indicate that the data is present.
> > +			 * Each stall data row is 64B (cacheline size).
> > +			 */
> > +			if (num_data_rows(total_data) >= stream->event_report_count)
> > +				min_data_present = true;
> > +		}
> > +		if (write_ptr_reg & XEHPC_EUSTALL_REPORT_OVERFLOW_DROP)
> > +			set_bit(xecore, stream->data_drop.mask);
> > +		xecore_buf->write = write_ptr;
> > +		mutex_unlock(&xecore_buf->lock);
> > +	}
> > +	return min_data_present;
> > +}
> > +
> > +static void
> > +clear_dropped_eviction_line_bit(struct xe_gt *gt, u16 group, u16 instance)
> > +{
> > +	u32 write_ptr_reg;
> > +
> > +	/* On PVC, the overflow bit has to be cleared by writing 1 to it. */
> > +	write_ptr_reg = _MASKED_BIT_ENABLE(XEHPC_EUSTALL_REPORT_OVERFLOW_DROP);
> > +
> > +	xe_gt_mcr_unicast_write(gt, XEHPC_EUSTALL_REPORT, write_ptr_reg, group, instance);
> > +}
> > +
> > +static int
> > +xe_eu_stall_data_buf_read(struct xe_eu_stall_data_stream *stream,
> > +			  char __user *buf, size_t count,
> > +			  size_t *total_size, struct xe_gt *gt,
> > +			  u16 group, u16 instance, unsigned int xecore)
> > +{
> > +	u32 read_ptr_reg, read_ptr, write_ptr;
> > +	u8 *xecore_start_vaddr, *read_vaddr;
> > +	struct xe_device *xe = gt_to_xe(gt);
> > +	struct per_xecore_buf *xecore_buf;
> > +	size_t size, copy_size, buf_size;
> > +	u32 read_offset, write_offset;
> > +	unsigned long record_size;
> > +
> > +	/* Hardware increments the read and write pointers such that they can
> > +	 * overflow into one additional bit. For example, a 256KB size buffer
> > +	 * offset pointer needs 18 bits. But HW uses 19 bits for the read and
> > +	 * write pointers. This technique avoids wasting a slot in the buffer.
> > +	 * Read and write offsets are calculated from the pointers in order to
> > +	 * check if the write pointer has wrapped around the array.
> > +	 */
> > +	xecore_buf = &stream->xecore_buf[xecore];
> > +	mutex_lock(&xecore_buf->lock);
> > +	xecore_start_vaddr = xecore_buf->vaddr;
> > +	read_ptr = xecore_buf->read;
> > +	write_ptr = xecore_buf->write;
> > +	buf_size = stream->per_xecore_buf_size;
> > +	read_offset = read_ptr & (buf_size - 1);
> > +	write_offset = write_ptr & (buf_size - 1);
> > +
> > +	if (write_ptr == read_ptr) {
> > +		mutex_unlock(&xecore_buf->lock);
> > +		return 0;
> > +	}
> > +
> > +	trace_xe_eu_stall_data_read(group, instance, read_ptr, write_ptr,
> > +				    read_offset, write_offset, *total_size);
> > +	/* If write pointer offset is less than the read pointer offset,
> > +	 * it means, write pointer has wrapped around the array.
> > +	 */
> > +	if (write_offset > read_offset)
> > +		size = write_offset - read_offset;
> > +	else
> > +		size = buf_size - read_offset + write_offset;
> > +
> > +	/* Read only the data that the user space buffer can accommodate */
> > +	if ((*total_size + size) > count) {
> > +		record_size = xe_eu_stall_data_record_size(xe);
> > +		size = count - *total_size;
> > +		size = (size / record_size) * record_size;
> > +	}
> > +
> > +	if (size == 0) {
> > +		mutex_unlock(&xecore_buf->lock);
> > +		return 0;
> > +	}
> > +
> > +	read_vaddr = xecore_start_vaddr + read_offset;
> > +
> > +	if (write_offset > read_offset) {
> > +		if (copy_to_user((buf + *total_size), read_vaddr, size)) {
> > +			mutex_unlock(&xecore_buf->lock);
> > +			return -EFAULT;
> > +		}
> > +	} else {
> > +		if (size >= (buf_size - read_offset))
> > +			copy_size = buf_size - read_offset;
> > +		else
> > +			copy_size = size;
> > +		if (copy_to_user((buf + *total_size), read_vaddr, copy_size)) {
> > +			mutex_unlock(&xecore_buf->lock);
> > +			return -EFAULT;
> > +		}
> > +		if (copy_to_user((buf + *total_size), xecore_start_vaddr, size - copy_size)) {
>   
> I think this should be `copy_to_user(buf + *total_size + copy_size, ...)`.
> As it currently stands, this line will overwrite some of the bits written by the first
> call to `copy_to_user`, and will result in userspace reading `size` bytes, but
> this function only having written `copy_size` bytes.
> 
> We noticed in our userspace profiler that many of our stalls weren't related to any 
> particular GPU shader, and so debugged it down to this line; with this change, we no longer
> get 0x0 addresses and random-looking data in the stall buffer.


Thanks for finding this bug. I am incorporating this fix in the next
version of the patch series.

Thank You
Harish.

>   
> > +			mutex_unlock(&xecore_buf->lock);
> > +			return -EFAULT;
> > +		}
> > +	}
> > +
> > +	*total_size += size;
> > +	read_ptr += size;
> > +
> > +	/* Read pointer can overflow into one additional bit */
> > +	read_ptr &= ((buf_size << 1) - 1);
> > +	read_ptr_reg = REG_FIELD_PREP(XEHPC_EUSTALL_REPORT1_READ_PTR_MASK, (read_ptr >> 6));
> > +	read_ptr_reg &= XEHPC_EUSTALL_REPORT1_READ_PTR_MASK;
> > +	read_ptr_reg = _MASKED_FIELD(XEHPC_EUSTALL_REPORT1_READ_PTR_MASK, read_ptr_reg);
> > +	xe_gt_mcr_unicast_write(gt, XEHPC_EUSTALL_REPORT1, read_ptr_reg, group, instance);
> > +	if (test_bit(xecore, stream->data_drop.mask)) {
> > +		clear_dropped_eviction_line_bit(gt, group, instance);
> > +		clear_bit(xecore, stream->data_drop.mask);
> > +	}
> > +	xecore_buf->read = read_ptr;
> > +	mutex_unlock(&xecore_buf->lock);
> > +	trace_xe_eu_stall_data_read(group, instance, read_ptr, write_ptr,
> > +				    read_offset, write_offset, *total_size);
> > +	return 0;
> > +}
> > +
> > +/**
> > + * xe_eu_stall_stream_read_locked - copy EU stall counters data from the
> > + *				    per xecore buffers to the userspace buffer
> > + * @stream: A stream opened for EU stall count metrics
> > + * @buf: destination buffer given by userspace
> > + * @count: the number of bytes userspace wants to read
> > + * @ppos: (inout) file seek position (unused)
> > + *
> > + * Returns: Number of bytes copied or a negative error code
> > + * If we've successfully copied any data then reporting that takes
> > + * precedence over any internal error status, so the data isn't lost.
> > + */
> > +static ssize_t
> > +xe_eu_stall_stream_read_locked(struct xe_eu_stall_data_stream *stream,
> > +			       struct file *file, char __user *buf,
> > +			       size_t count, loff_t *ppos)
> > +{
> > +	struct xe_gt *gt = stream->gt;
> > +	size_t total_size = 0;
> > +	u16 group, instance;
> > +	unsigned int xecore;
> > +	int ret = 0;
> > +
> > +	if (count == 0)
> > +		return -EINVAL;
> > +
> > +	for_each_dss_steering(xecore, gt, group, instance) {
> > +		ret = xe_eu_stall_data_buf_read(stream, buf, count, &total_size,
> > +						gt, group, instance, xecore);
> > +		if (ret || count == total_size)
> > +			goto exit;
> > +	}
> > +exit:
> > +	if (total_size)
> > +		return total_size;
> > +	else if (ret)
> > +		return ret;
> > +	else
> > +		return -EAGAIN;
> > +}
> > +
> >  /**
> >   * xe_eu_stall_stream_read - handles userspace read() of a EU stall data stream fd.
> >   *
> > @@ -159,11 +472,259 @@ static int xe_eu_stall_user_extensions(struct xe_device *xe, u64 extension,
> >  static ssize_t xe_eu_stall_stream_read(struct file *file, char __user *buf,
> >  				       size_t count, loff_t *ppos)
> >  {
> > -	ssize_t ret = 0;
> > +	struct xe_eu_stall_data_stream *stream = file->private_data;
> > +	struct xe_gt *gt = stream->gt;
> > +	ssize_t ret;
> > +
> > +	if (!stream->enabled) {
> > +		xe_gt_dbg(gt, "EU stall data stream not enabled to read\n");
> > +		return -EINVAL;
> > +	}
> > +
> > +	if (!(file->f_flags & O_NONBLOCK)) {
> > +		do {
> > +			if (!stream->pollin) {
> > +				ret = wait_event_interruptible(stream->poll_wq, stream->pollin);
> > +				if (ret)
> > +					return -EINTR;
> > +			}
> > +
> > +			mutex_lock(&gt->eu_stall->lock);
> > +			ret = xe_eu_stall_stream_read_locked(stream, file, buf, count, ppos);
> > +			mutex_unlock(&gt->eu_stall->lock);
> > +		} while (ret == -EAGAIN);
> > +	} else {
> > +		mutex_lock(&gt->eu_stall->lock);
> > +		ret = xe_eu_stall_stream_read_locked(stream, file, buf, count, ppos);
> > +		mutex_unlock(&gt->eu_stall->lock);
> > +	}
> > +
> > +	stream->pollin = false;
> >  
> >  	return ret;
> >  }
> >  
> > +static void
> > +free_eu_stall_data_buf(struct xe_eu_stall_data_stream *stream)
> > +{
> > +	if (stream->bo) {
> > +		xe_bo_unpin_map_no_vm(stream->bo);
> > +		stream->bo = NULL;
> > +	}
> > +	destroy_workqueue(stream->buf_check_wq);
> > +}
> > +
> > +static int alloc_eu_stall_data_buf(struct xe_eu_stall_data_stream *stream,
> > +				   u16 num_xecore)
> > +{
> > +	struct xe_tile *tile = stream->gt->tile;
> > +	struct xe_bo *bo;
> > +	u32 size;
> > +
> > +	size = stream->per_xecore_buf_size * num_xecore;
> > +
> > +	bo = xe_bo_create_pin_map(tile->xe, tile, NULL,
> > +				  size, ttm_bo_type_kernel,
> > +				  XE_BO_FLAG_SYSTEM |
> > +				  XE_BO_FLAG_GGTT);
> > +	if (IS_ERR(bo))
> > +		return PTR_ERR(bo);
> > +
> > +	stream->bo = bo;
> > +
> > +	return 0;
> > +}
> > +
> > +static u32
> > +gen_eustall_base(struct xe_eu_stall_data_stream *stream, bool enable)
> > +{
> > +	u32 val = xe_bo_ggtt_addr(stream->bo);
> > +	u32 sz;
> > +
> > +	XE_WARN_ON(!IS_ALIGNED(val, 64));
> > +
> > +	switch (stream->per_xecore_buf_size) {
> > +	case SZ_128K:
> > +		sz = 0;
> > +		break;
> > +	case SZ_256K:
> > +		sz = 1;
> > +		break;
> > +	case SZ_512K:
> > +		sz = 2;
> > +		break;
> > +	default:
> > +		xe_gt_warn(stream->gt, "Missing case per XeCore buffer size == %lu)\n",
> > +			   (long)(stream->per_xecore_buf_size));
> > +		sz = 2;
> > +	}
> > +
> > +	val |= REG_FIELD_PREP(XEHPC_EUSTALL_BASE_XECORE_BUF_SZ, sz);
> > +	if (enable)
> > +		val |= XEHPC_EUSTALL_BASE_ENABLE_SAMPLING;
> > +
> > +	return val;
> > +}
> > +
> > +static void
> > +xe_eu_stall_stream_enable(struct xe_eu_stall_data_stream *stream)
> > +{
> > +	struct xe_gt *gt = stream->gt;
> > +	u32 reg_value;
> > +
> > +	/* Take runtime pm ref and forcewake to disable RC6 */
> > +	xe_pm_runtime_get(gt_to_xe(gt));
> > +	XE_WARN_ON(xe_force_wake_get(gt_to_fw(gt), XE_FW_RENDER));
> > +
> > +	reg_value = gen_eustall_base(stream, true);
> > +	xe_gt_mcr_multicast_write(gt, XEHPC_EUSTALL_BASE, reg_value);
> > +}
> > +
> > +static void
> > +xe_eu_stall_stream_disable(struct xe_eu_stall_data_stream *stream)
> > +{
> > +	struct xe_gt *gt = stream->gt;
> > +	u16 group, instance;
> > +	unsigned int xecore;
> > +	u32 reg_value;
> > +
> > +	/*
> > +	 * Before disabling EU stall sampling, check if any of the
> > +	 * XEHPC_EUSTALL_REPORT registers have the drop bit set. If set,
> > +	 * clear the bit. If the user space application reads all the
> > +	 * stall data, the drop bit would be cleared during the read.
> > +	 * But if there is any unread data and the drop bit is set for
> > +	 * any subslice, the drop bit would continue to be set even
> > +	 * after disabling EU stall sampling and may cause erroneous
> > +	 * stall data in the subsequent stall data sampling run.
> > +	 */
> > +	for_each_dss_steering(xecore, gt, group, instance) {
> > +		reg_value = xe_gt_mcr_unicast_read(gt, XEHPC_EUSTALL_REPORT,
> > +						   group, instance);
> > +		if (reg_value & XEHPC_EUSTALL_REPORT_OVERFLOW_DROP)
> > +			clear_dropped_eviction_line_bit(gt, group, instance);
> > +	}
> > +	reg_value = gen_eustall_base(stream, false);
> > +	xe_gt_mcr_multicast_write(gt, XEHPC_EUSTALL_BASE, reg_value);
> > +
> > +	xe_force_wake_put(gt_to_fw(gt), XE_FW_RENDER);
> > +	xe_pm_runtime_put(gt_to_xe(gt));
> > +}
> > +
> > +static void eu_stall_buf_check_work_fn(struct work_struct *work)
> > +{
> > +	struct xe_eu_stall_data_stream *stream =
> > +		container_of(work, typeof(*stream), buf_check_work);
> > +
> > +	if (eu_stall_data_buf_check(stream)) {
> > +		stream->pollin = true;
> > +		wake_up(&stream->poll_wq);
> > +	}
> > +}
> > +
> > +static enum
> > +hrtimer_restart eu_stall_poll_check_timer_cb(struct hrtimer *hrtimer)
> > +{
> > +	struct xe_eu_stall_data_stream *stream =
> > +		container_of(hrtimer, typeof(*stream), poll_check_timer);
> > +
> > +	queue_work(stream->buf_check_wq, &stream->buf_check_work);
> > +	hrtimer_forward_now(hrtimer, ns_to_ktime(stream->poll_period));
> > +
> > +	return HRTIMER_RESTART;
> > +}
> > +
> > +static int xe_eu_stall_stream_init(struct xe_eu_stall_data_stream *stream,
> > +				   struct eu_stall_open_properties *props)
> > +{
> > +	u32 write_ptr_reg, write_ptr, read_ptr_reg;
> > +	u32 vaddr_offset, base_reg_value;
> > +	struct xe_gt *gt = stream->gt;
> > +	struct per_xecore_buf *xecore_buf;
> > +	u16 group, instance, num_xecore;
> > +	xe_dss_mask_t all_xecore;
> > +	int ret, xecore;
> > +
> > +	init_waitqueue_head(&stream->poll_wq);
> > +	INIT_WORK(&stream->buf_check_work, eu_stall_buf_check_work_fn);
> > +	stream->buf_check_wq = alloc_ordered_workqueue("xe_eustall", 0);
> > +	if (!stream->buf_check_wq)
> > +		return -ENOMEM;
> > +	hrtimer_init(&stream->poll_check_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
> > +	stream->poll_check_timer.function = eu_stall_poll_check_timer_cb;
> > +	stream->event_report_count = props->event_report_count;
> > +	stream->per_xecore_buf_size = SZ_512K;
> > +	stream->poll_period = POLL_PERIOD_NS;
> > +
> > +	bitmap_or(all_xecore, gt->fuse_topo.g_dss_mask, gt->fuse_topo.c_dss_mask,
> > +		  XE_MAX_DSS_FUSE_BITS);
> > +	/*
> > +	 * Enabled subslices can be discontiguous. Find the maximum number of subslices
> > +	 * that are enabled.
> > +	 */
> > +	num_xecore = xe_gt_topology_mask_last_dss(all_xecore) + 1;
> > +
> > +	ret = alloc_eu_stall_data_buf(stream, num_xecore);
> > +	if (ret)
> > +		return ret;
> > +
> > +	stream->xecore_buf = kcalloc(num_xecore, sizeof(*stream->xecore_buf), GFP_KERNEL);
> > +	if (!stream->xecore_buf)
> > +		return -ENOMEM;
> > +
> > +	bitmap_zero(stream->data_drop.mask, XE_MAX_DSS_FUSE_BITS);
> > +
> > +	xe_pm_runtime_get(gt_to_xe(gt));
> > +	XE_WARN_ON(xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL));
> > +
> > +	base_reg_value = gen_eustall_base(stream, false);
> > +	xe_gt_mcr_multicast_write(gt, XEHPC_EUSTALL_BASE, base_reg_value);
> > +	/* GGTT addresses can never be > 32 bits */
> > +	xe_gt_mcr_multicast_write(gt, XEHPC_EUSTALL_BASE_UPPER, 0);
> > +	base_reg_value = _MASKED_FIELD(EUSTALL_MOCS | EUSTALL_SAMPLE_RATE,
> > +				       REG_FIELD_PREP(EUSTALL_MOCS, gt->mocs.uc_index << 1) |
> > +				       REG_FIELD_PREP(EUSTALL_SAMPLE_RATE,
> > +						      props->eu_stall_sampling_rate));
> > +	xe_gt_mcr_multicast_write(gt, XEHPC_EUSTALL_CTRL, base_reg_value);
> > +
> > +	for_each_dss_steering(xecore, gt, group, instance) {
> > +		write_ptr_reg = xe_gt_mcr_unicast_read(gt, XEHPC_EUSTALL_REPORT,
> > +						       group, instance);
> > +		write_ptr = REG_FIELD_GET(XEHPC_EUSTALL_REPORT_WRITE_PTR_MASK, write_ptr_reg);
> > +		write_ptr <<= 6;
> > +		write_ptr &= ((stream->per_xecore_buf_size << 1) - 1);
> > +		read_ptr_reg = write_ptr >> 6;
> > +		read_ptr_reg = REG_FIELD_PREP(XEHPC_EUSTALL_REPORT1_READ_PTR_MASK, write_ptr);
> > +		read_ptr_reg &= XEHPC_EUSTALL_REPORT1_READ_PTR_MASK;
> > +		read_ptr_reg = _MASKED_FIELD(XEHPC_EUSTALL_REPORT1_READ_PTR_MASK, read_ptr_reg);
> > +		xe_gt_mcr_unicast_write(gt, XEHPC_EUSTALL_REPORT1,
> > +					read_ptr_reg, group, instance);
> > +		xecore_buf = &stream->xecore_buf[xecore];
> > +		vaddr_offset = xecore * stream->per_xecore_buf_size;
> > +		xecore_buf->vaddr = stream->bo->vmap.vaddr + vaddr_offset;
> > +		xecore_buf->write = write_ptr;
> > +		xecore_buf->read = write_ptr;
> > +		mutex_init(&xecore_buf->lock);
> > +	}
> > +	xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL);
> > +	xe_pm_runtime_put(gt_to_xe(gt));
> > +	return 0;
> > +}
> > +
> > +static __poll_t
> > +xe_eu_stall_stream_poll_locked(struct xe_eu_stall_data_stream *stream,
> > +			       struct file *file, poll_table *wait)
> > +{
> > +	__poll_t events = 0;
> > +
> > +	poll_wait(file, &stream->poll_wq, wait);
> > +
> > +	if (stream->pollin)
> > +		events |= EPOLLIN;
> > +
> > +	return events;
> > +}
> > +
> >  /**
> >   * xe_eu_stall_stream_poll - handles userspace poll() of a EU stall data stream fd.
> >   *
> > @@ -175,11 +736,60 @@ static ssize_t xe_eu_stall_stream_read(struct file *file, char __user *buf,
> >  static __poll_t
> >  xe_eu_stall_stream_poll(struct file *file, poll_table *wait)
> >  {
> > -	__poll_t ret = 0;
> > +	struct xe_eu_stall_data_stream *stream = file->private_data;
> > +	struct xe_gt *gt = stream->gt;
> > +	__poll_t ret;
> > +
> > +	mutex_lock(&gt->eu_stall->lock);
> > +	ret = xe_eu_stall_stream_poll_locked(stream, file, wait);
> > +	mutex_unlock(&gt->eu_stall->lock);
> >  
> >  	return ret;
> >  }
> >  
> > +static void
> > +xe_eu_stall_enable_locked(struct xe_eu_stall_data_stream *stream)
> > +{
> > +	if (stream->enabled)
> > +		return;
> > +
> > +	stream->enabled = true;
> > +
> > +	xe_eu_stall_stream_enable(stream);
> > +	hrtimer_start(&stream->poll_check_timer,
> > +		      ns_to_ktime(stream->poll_period),
> > +		      HRTIMER_MODE_REL);
> > +}
> > +
> > +static void
> > +xe_eu_stall_disable_locked(struct xe_eu_stall_data_stream *stream)
> > +{
> > +	if (!stream->enabled)
> > +		return;
> > +
> > +	stream->enabled = false;
> > +
> > +	hrtimer_cancel(&stream->poll_check_timer);
> > +	flush_workqueue(stream->buf_check_wq);
> > +	xe_eu_stall_stream_disable(stream);
> > +}
> > +
> > +static long
> > +xe_eu_stall_stream_ioctl_locked(struct xe_eu_stall_data_stream *stream,
> > +				unsigned int cmd, unsigned long arg)
> > +{
> > +	switch (cmd) {
> > +	case DRM_XE_OBSERVATION_IOCTL_ENABLE:
> > +		xe_eu_stall_enable_locked(stream);
> > +		return 0;
> > +	case DRM_XE_OBSERVATION_IOCTL_DISABLE:
> > +		xe_eu_stall_disable_locked(stream);
> > +		return 0;
> > +	}
> > +
> > +	return -EINVAL;
> > +}
> > +
> >  /**
> >   * xe_eu_stall_stream_ioctl - support ioctl() of a xe EU stall data stream fd.
> >   *
> > @@ -194,14 +804,22 @@ static long xe_eu_stall_stream_ioctl(struct file *file,
> >  				     unsigned int cmd,
> >  				     unsigned long arg)
> >  {
> > -	switch (cmd) {
> > -	case DRM_XE_OBSERVATION_IOCTL_ENABLE:
> > -		return 0;
> > -	case DRM_XE_OBSERVATION_IOCTL_DISABLE:
> > -		return 0;
> > -	}
> > +	struct xe_eu_stall_data_stream *stream = file->private_data;
> > +	struct xe_gt *gt = stream->gt;
> > +	long ret;
> >  
> > -	return -EINVAL;
> > +	mutex_lock(&gt->eu_stall->lock);
> > +	ret = xe_eu_stall_stream_ioctl_locked(stream, cmd, arg);
> > +	mutex_unlock(&gt->eu_stall->lock);
> > +
> > +	return ret;
> > +}
> > +
> > +static void
> > +xe_eu_stall_stream_close_locked(struct xe_eu_stall_data_stream *stream)
> > +{
> > +	xe_eu_stall_disable_locked(stream);
> > +	free_eu_stall_data_buf(stream);
> >  }
> >  
> >  /**
> > @@ -214,6 +832,19 @@ static long xe_eu_stall_stream_ioctl(struct file *file,
> >   */
> >  static int xe_eu_stall_stream_close(struct inode *inode, struct file *file)
> >  {
> > +	struct xe_eu_stall_data_stream *stream = file->private_data;
> > +	struct xe_gt *gt = stream->gt;
> > +
> > +	mutex_lock(&gt->eu_stall->lock);
> > +	xe_eu_stall_stream_close_locked(stream);
> > +	kfree(stream->xecore_buf);
> > +	kfree(stream);
> > +	gt->eu_stall->stream = NULL;
> > +	mutex_unlock(&gt->eu_stall->lock);
> > +
> > +	/* Release the reference the EU stall stream kept on the driver */
> > +	drm_dev_put(&gt->tile->xe->drm);
> > +
> >  	return 0;
> >  }
> >  
> > @@ -229,7 +860,79 @@ static const struct file_operations fops_eu_stall = {
> >  
> >  static inline bool has_eu_stall_sampling_support(struct xe_device *xe)
> >  {
> > -	return false;
> > +	return ((xe->info.platform == XE_PVC) ? true : false);
> > +}
> > +
> > +/**
> > + * xe_eu_stall_stream_open_locked - Open a EU stall data stream FD.
> > + * @dev: drm device instance
> > + * @props: individually validated u64 property value pairs
> > + * @file: drm file
> > + *
> > + * Returns: zero on success or a negative error code.
> > + */
> > +static int
> > +xe_eu_stall_stream_open_locked(struct drm_device *dev,
> > +			       struct eu_stall_open_properties *props,
> > +			       struct drm_file *file)
> > +{
> > +	struct xe_device *xe = to_xe_device(dev);
> > +	struct xe_eu_stall_data_stream *stream;
> > +	struct xe_gt *gt = props->gt;
> > +	unsigned long f_flags = 0;
> > +	int ret, stream_fd;
> > +
> > +	if (!has_eu_stall_sampling_support(xe)) {
> > +		xe_gt_dbg(gt, "EU stall monitoring is not supported on this platform\n");
> > +		return -EPERM;
> > +	}
> > +
> > +	if (xe_observation_paranoid && !perfmon_capable()) {
> > +		xe_gt_dbg(gt, "Insufficient privileges for EU stall monitoring\n");
> > +		return -EACCES;
> > +	}
> > +
> > +	/* Only one session can be active at any time */
> > +	if (gt->eu_stall->stream) {
> > +		xe_gt_dbg(gt, "EU stall sampling session already active\n");
> > +		return -EBUSY;
> > +	}
> > +
> > +	stream = kzalloc(sizeof(*stream), GFP_KERNEL);
> > +	if (!stream)
> > +		return -ENOMEM;
> > +
> > +	gt->eu_stall->stream = stream;
> > +	stream->gt = gt;
> > +
> > +	ret = xe_eu_stall_stream_init(stream, props);
> > +	if (ret) {
> > +		xe_gt_dbg(gt, "EU stall stream init failed : %d\n", ret);
> > +		goto err_alloc;
> > +	}
> > +
> > +	stream_fd = anon_inode_getfd("[xe_eu_stall]", &fops_eu_stall,
> > +				     stream, f_flags);
> > +	if (stream_fd < 0) {
> > +		ret = stream_fd;
> > +		xe_gt_dbg(gt, "EU stall inode get fd failed : %d\n", ret);
> > +		goto err_open;
> > +	}
> > +
> > +	/* Take a reference on the driver that will be kept with stream_fd
> > +	 * until its release.
> > +	 */
> > +	drm_dev_get(&gt->tile->xe->drm);
> > +
> > +	return stream_fd;
> > +
> > +err_open:
> > +	free_eu_stall_data_buf(stream);
> > +err_alloc:
> > +	gt->eu_stall->stream = NULL;
> > +	kfree(stream->xecore_buf);
> > +	kfree(stream);
> > +	return ret;
> >  }
> >  
> >  /**
> > @@ -251,10 +954,15 @@ int xe_eu_stall_stream_open(struct drm_device *dev,
> >  {
> >  	struct xe_device *xe = to_xe_device(dev);
> >  	struct eu_stall_open_properties props;
> > -	int ret, stream_fd;
> > +	int ret;
> >  
> >  	memset(&props, 0, sizeof(struct eu_stall_open_properties));
> >  
> > +	/* Set default values */
> > +	props.gt = NULL;
> > +	props.eu_stall_sampling_rate = 4;
> > +	props.event_report_count = 1;
> > +
> >  	ret = xe_eu_stall_user_extensions(xe, data, &props);
> >  	if (ret)
> >  		return ret;
> > @@ -264,19 +972,9 @@ int xe_eu_stall_stream_open(struct drm_device *dev,
> >  		return -EINVAL;
> >  	}
> >  
> > -	if (xe_observation_paranoid && !perfmon_capable()) {
> > -		xe_gt_dbg(props.gt, "Insufficient privileges for EU stall monitoring\n");
> > -		return -EACCES;
> > -	}
> > +	mutex_lock(&props.gt->eu_stall->lock);
> > +	ret = xe_eu_stall_stream_open_locked(dev, &props, file);
> > +	mutex_unlock(&props.gt->eu_stall->lock);
> >  
> > -	if (!has_eu_stall_sampling_support(xe)) {
> > -		xe_gt_dbg(props.gt, "EU stall monitoring is not supported on this platform\n");
> > -		return -EPERM;
> > -	}
> > -	stream_fd = anon_inode_getfd("[xe_eu_stall]", &fops_eu_stall,
> > -				     NULL, 0);
> > -	if (stream_fd < 0)
> > -		xe_gt_dbg(props.gt, "EU stall inode get fd failed : %d\n", stream_fd);
> > -
> > -	return stream_fd;
> > +	return ret;
> >  }
> > diff --git a/drivers/gpu/drm/xe/xe_eu_stall.h b/drivers/gpu/drm/xe/xe_eu_stall.h
> > index 70fc89480df2..00896812db41 100644
> > --- a/drivers/gpu/drm/xe/xe_eu_stall.h
> > +++ b/drivers/gpu/drm/xe/xe_eu_stall.h
> > @@ -6,6 +6,49 @@
> >  #ifndef __XE_EU_STALL_H__
> >  #define __XE_EU_STALL_H__
> >  
> > +#include "xe_gt_types.h"
> > +
> > +struct per_xecore_buf {
> > +	u8 *vaddr;
> > +	u32 write;
> > +	u32 read;
> > +	/* lock to protect read and write pointers */
> > +	struct mutex lock;
> > +};
> > +
> > +/**
> > + * struct xe_eu_stall_data_stream - state of EU stall data stream FD
> > + */
> > +struct xe_eu_stall_data_stream {
> > +	bool pollin;
> > +	bool enabled;
> > +	u64 poll_period;
> > +	u32 event_report_count;
> > +	size_t per_xecore_buf_size;
> > +	wait_queue_head_t poll_wq;
> > +
> > +	struct xe_gt *gt;
> > +	struct xe_bo *bo;
> > +	struct per_xecore_buf *xecore_buf;
> > +	struct {
> > +		xe_dss_mask_t mask;
> > +	} data_drop;
> > +	struct hrtimer poll_check_timer;
> > +	struct work_struct buf_check_work;
> > +	struct workqueue_struct *buf_check_wq;
> > +};
> > +
> > +struct xe_eu_stall_gt {
> > +	/* Lock to protect stream */
> > +	struct mutex lock;
> > +
> > +	/* Execution Unit (EU) stall data stream */
> > +	struct xe_eu_stall_data_stream *stream;
> > +};
> > +
> > +int xe_eu_stall_init(struct xe_gt *gt);
> > +void xe_eu_stall_fini(struct xe_gt *gt);
> > +
> >  int xe_eu_stall_stream_open(struct drm_device *dev,
> >  			    u64 data,
> >  			    struct drm_file *file);
> > diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
> > index d6744be01a68..6e9598ddabd7 100644
> > --- a/drivers/gpu/drm/xe/xe_gt.c
> > +++ b/drivers/gpu/drm/xe/xe_gt.c
> > @@ -59,6 +59,7 @@
> >  #include "xe_vm.h"
> >  #include "xe_wa.h"
> >  #include "xe_wopcm.h"
> > +#include "xe_eu_stall.h"
> >  
> >  static void gt_fini(struct drm_device *drm, void *arg)
> >  {
> > @@ -158,6 +159,7 @@ void xe_gt_remove(struct xe_gt *gt)
> >  		xe_hw_fence_irq_finish(&gt->fence_irq[i]);
> >  
> >  	xe_gt_disable_host_l2_vram(gt);
> > +	xe_eu_stall_fini(gt);
> >  }
> >  
> >  static void gt_reset_worker(struct work_struct *w);
> > @@ -622,6 +624,10 @@ int xe_gt_init(struct xe_gt *gt)
> >  
> >  	xe_gt_record_user_engines(gt);
> >  
> > +	err = xe_eu_stall_init(gt);
> > +	if (err)
> > +		return err;
> > +
> >  	return 0;
> >  }
> >  
> > diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
> > index 6e66bf0e8b3f..833a1a67e9ae 100644
> > --- a/drivers/gpu/drm/xe/xe_gt_types.h
> > +++ b/drivers/gpu/drm/xe/xe_gt_types.h
> > @@ -430,6 +430,9 @@ struct xe_gt {
> >  
> >  	/** @oa: oa observation subsystem per gt info */
> >  	struct xe_oa_gt oa;
> > +
> > +	/** @eu_stall: EU stall counters subsystem per gt info */
> > +	struct xe_eu_stall_gt *eu_stall;
> >  };
> >  
> >  #endif
> > diff --git a/drivers/gpu/drm/xe/xe_trace.h b/drivers/gpu/drm/xe/xe_trace.h
> > index de682978c4bf..bcc34e47808a 100644
> > --- a/drivers/gpu/drm/xe/xe_trace.h
> > +++ b/drivers/gpu/drm/xe/xe_trace.h
> > @@ -424,6 +424,39 @@ DEFINE_EVENT(xe_pm_runtime, xe_pm_runtime_get_ioctl,
> >  	     TP_ARGS(xe, caller)
> >  );
> >  
> > +TRACE_EVENT(xe_eu_stall_data_read,
> > +	    TP_PROTO(u8 slice, u8 subslice,
> > +		     u32 read_ptr, u32 write_ptr,
> > +		     u32 read_offset, u32 write_offset,
> > +		     size_t total_size),
> > +	    TP_ARGS(slice, subslice, read_ptr, write_ptr,
> > +		    read_offset, write_offset, total_size),
> > +
> > +	    TP_STRUCT__entry(__field(u8, slice)
> > +			     __field(u8, subslice)
> > +			     __field(u32, read_ptr)
> > +			     __field(u32, write_ptr)
> > +			     __field(u32, read_offset)
> > +			     __field(u32, write_offset)
> > +			     __field(size_t, total_size)
> > +			     ),
> > +
> > +	    TP_fast_assign(__entry->slice = slice;
> > +			   __entry->subslice = subslice;
> > +			   __entry->read_ptr = read_ptr;
> > +			   __entry->write_ptr = write_ptr;
> > +			   __entry->read_offset = read_offset;
> > +			   __entry->write_offset = write_offset;
> > +			   __entry->total_size = total_size;
> > +			   ),
> > +
> > +	    TP_printk("slice:%u subslice:%u readptr:0x%x writeptr:0x%x read off:%u write off:%u size:%zu ",
> > +		      __entry->slice, __entry->subslice,
> > +		      __entry->read_ptr, __entry->write_ptr,
> > +		      __entry->read_offset, __entry->write_offset,
> > +		      __entry->total_size)
> > +);
> > +
> >  #endif
> >  
> >  /* This part must be outside protection */
> > -- 
> > 2.45.1
> >