* [PATCH v2 0/3] drm/i915: i915_reg.h display split
@ 2025-04-15 10:51 Jani Nikula
2025-04-15 10:51 ` [PATCH v2 1/3] drm/i915/reg: use REG_BIT and friends to define DP registers Jani Nikula
` (10 more replies)
0 siblings, 11 replies; 13+ messages in thread
From: Jani Nikula @ 2025-04-15 10:51 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala, Suraj Kandpal
v2 of https://lore.kernel.org/r/cover.1738935286.git.jani.nikula@intel.com
Jani Nikula (3):
drm/i915/reg: use REG_BIT and friends to define DP registers
drm/i915/reg: Add/remove some extra blank lines
drm/i915: split out display register macros to a separate file
drivers/gpu/drm/i915/display/g4x_dp.c | 24 +-
drivers/gpu/drm/i915/display/g4x_hdmi.c | 1 +
drivers/gpu/drm/i915/display/hsw_ips.c | 1 +
.../gpu/drm/i915/display/i9xx_display_sr.c | 1 +
drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +
drivers/gpu/drm/i915/display/i9xx_wm.c | 1 +
drivers/gpu/drm/i915/display/icl_dsi.c | 1 +
.../gpu/drm/i915/display/intel_backlight.c | 2 +-
drivers/gpu/drm/i915/display/intel_bw.c | 3 +-
drivers/gpu/drm/i915/display/intel_cdclk.c | 1 +
drivers/gpu/drm/i915/display/intel_cmtg.c | 3 +-
.../gpu/drm/i915/display/intel_combo_phy.c | 1 +
drivers/gpu/drm/i915/display/intel_crt.c | 1 +
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 3 +-
.../drm/i915/display/intel_display_debugfs.c | 1 +
.../drm/i915/display/intel_display_device.c | 6 +-
.../gpu/drm/i915/display/intel_display_irq.c | 2 +
.../drm/i915/display/intel_display_power.c | 1 +
.../i915/display/intel_display_power_map.c | 1 +
.../i915/display/intel_display_power_well.c | 1 +
.../gpu/drm/i915/display/intel_display_regs.h | 2878 ++++++++++++++++
.../gpu/drm/i915/display/intel_display_wa.c | 1 +
drivers/gpu/drm/i915/display/intel_dmc.c | 3 +-
drivers/gpu/drm/i915/display/intel_dmc_wl.c | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 4 +-
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 1 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 1 +
drivers/gpu/drm/i915/display/intel_dp_test.c | 1 +
drivers/gpu/drm/i915/display/intel_dpio_phy.c | 1 +
drivers/gpu/drm/i915/display/intel_dpll.c | 1 +
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 +
.../gpu/drm/i915/display/intel_dpt_common.c | 1 +
drivers/gpu/drm/i915/display/intel_drrs.c | 1 +
drivers/gpu/drm/i915/display/intel_dsb.c | 1 +
drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 3 +-
drivers/gpu/drm/i915/display/intel_dvo.c | 1 +
drivers/gpu/drm/i915/display/intel_fbc.c | 3 +
drivers/gpu/drm/i915/display/intel_fdi.c | 3 +-
.../drm/i915/display/intel_fifo_underrun.c | 1 +
drivers/gpu/drm/i915/display/intel_gmbus.c | 1 +
drivers/gpu/drm/i915/display/intel_hdcp.c | 1 +
drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
.../gpu/drm/i915/display/intel_hotplug_irq.c | 1 +
drivers/gpu/drm/i915/display/intel_lspcon.c | 1 +
.../drm/i915/display/intel_modeset_setup.c | 3 +-
drivers/gpu/drm/i915/display/intel_overlay.c | 2 +
.../gpu/drm/i915/display/intel_pch_display.c | 1 +
.../gpu/drm/i915/display/intel_pch_refclk.c | 1 +
drivers/gpu/drm/i915/display/intel_pfit.c | 1 +
drivers/gpu/drm/i915/display/intel_pipe_crc.c | 1 +
drivers/gpu/drm/i915/display/intel_pmdemand.c | 1 +
drivers/gpu/drm/i915/display/intel_pps.c | 1 +
drivers/gpu/drm/i915/display/intel_psr.c | 1 +
drivers/gpu/drm/i915/display/intel_sdvo.c | 1 +
drivers/gpu/drm/i915/display/intel_snps_phy.c | 1 +
drivers/gpu/drm/i915/display/intel_tc.c | 1 +
drivers/gpu/drm/i915/display/intel_vblank.c | 1 +
drivers/gpu/drm/i915/display/intel_vga.c | 2 +
drivers/gpu/drm/i915/display/intel_vrr.c | 1 +
drivers/gpu/drm/i915/display/skl_scaler.c | 1 +
.../drm/i915/display/skl_universal_plane.c | 4 +-
drivers/gpu/drm/i915/display/skl_watermark.c | 1 +
drivers/gpu/drm/i915/display/vlv_dsi.c | 1 +
drivers/gpu/drm/i915/gvt/cmd_parser.c | 1 +
drivers/gpu/drm/i915/gvt/display.c | 1 +
drivers/gpu/drm/i915/gvt/fb_decoder.c | 1 +
drivers/gpu/drm/i915/gvt/handlers.c | 1 +
drivers/gpu/drm/i915/gvt/interrupt.c | 1 +
drivers/gpu/drm/i915/gvt/mmio.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 2911 +----------------
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1 +
drivers/gpu/drm/xe/display/xe_plane_initial.c | 1 +
73 files changed, 2980 insertions(+), 2936 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_display_regs.h
--
2.39.5
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 1/3] drm/i915/reg: use REG_BIT and friends to define DP registers
2025-04-15 10:51 [PATCH v2 0/3] drm/i915: i915_reg.h display split Jani Nikula
@ 2025-04-15 10:51 ` Jani Nikula
2025-04-15 10:51 ` [PATCH v2 2/3] drm/i915/reg: Add/remove some extra blank lines Jani Nikula
` (9 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Jani Nikula @ 2025-04-15 10:51 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala, Suraj Kandpal
Define the DP register contents using the REG_BIT, REG_GENMASK,
etc. macros. Ditch the unhelpful comments. Rename eDP related register
content macros to have EDP_ prefix.
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/g4x_dp.c | 23 +++--
drivers/gpu/drm/i915/i915_reg.h | 124 +++++++++-----------------
2 files changed, 54 insertions(+), 93 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
index 18e51799d2a6..9b6792c701d1 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -182,7 +182,7 @@ static void assert_dp_port(struct intel_dp *intel_dp, bool state)
static void assert_edp_pll(struct intel_display *display, bool state)
{
- bool cur_state = intel_de_read(display, DP_A) & DP_PLL_ENABLE;
+ bool cur_state = intel_de_read(display, DP_A) & EDP_PLL_ENABLE;
INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
"eDP PLL state assertion failure (expected %s, current %s)\n",
@@ -204,12 +204,12 @@ static void ilk_edp_pll_on(struct intel_dp *intel_dp,
drm_dbg_kms(display->drm, "enabling eDP PLL for clock %d\n",
pipe_config->port_clock);
- intel_dp->DP &= ~DP_PLL_FREQ_MASK;
+ intel_dp->DP &= ~EDP_PLL_FREQ_MASK;
if (pipe_config->port_clock == 162000)
- intel_dp->DP |= DP_PLL_FREQ_162MHZ;
+ intel_dp->DP |= EDP_PLL_FREQ_162MHZ;
else
- intel_dp->DP |= DP_PLL_FREQ_270MHZ;
+ intel_dp->DP |= EDP_PLL_FREQ_270MHZ;
intel_de_write(display, DP_A, intel_dp->DP);
intel_de_posting_read(display, DP_A);
@@ -224,7 +224,7 @@ static void ilk_edp_pll_on(struct intel_dp *intel_dp,
if (display->platform.ironlake)
intel_wait_for_vblank_if_active(display, !crtc->pipe);
- intel_dp->DP |= DP_PLL_ENABLE;
+ intel_dp->DP |= EDP_PLL_ENABLE;
intel_de_write(display, DP_A, intel_dp->DP);
intel_de_posting_read(display, DP_A);
@@ -242,7 +242,7 @@ static void ilk_edp_pll_off(struct intel_dp *intel_dp,
drm_dbg_kms(display->drm, "disabling eDP PLL\n");
- intel_dp->DP &= ~DP_PLL_ENABLE;
+ intel_dp->DP &= ~EDP_PLL_ENABLE;
intel_de_write(display, DP_A, intel_dp->DP);
intel_de_posting_read(display, DP_A);
@@ -286,13 +286,13 @@ bool g4x_dp_port_enabled(struct intel_display *display,
/* asserts want to know the pipe even if the port is disabled */
if (display->platform.ivybridge && port == PORT_A)
- *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
+ *pipe = REG_FIELD_GET(DP_PIPE_SEL_MASK_IVB, val);
else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
ret &= cpt_dp_port_selected(display, port, pipe);
else if (display->platform.cherryview)
- *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
+ *pipe = REG_FIELD_GET(DP_PIPE_SEL_MASK_CHV, val);
else
- *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
+ *pipe = REG_FIELD_GET(DP_PIPE_SEL_MASK, val);
return ret;
}
@@ -388,13 +388,12 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
if (display->platform.g4x && tmp & DP_COLOR_RANGE_16_235)
pipe_config->limited_color_range = true;
- pipe_config->lane_count =
- ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
+ pipe_config->lane_count = REG_FIELD_GET(DP_PORT_WIDTH_MASK, tmp) + 1;
g4x_dp_get_m_n(pipe_config);
if (port == PORT_A) {
- if ((intel_de_read(display, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
+ if ((intel_de_read(display, DP_A) & EDP_PLL_FREQ_MASK) == EDP_PLL_FREQ_162MHZ)
pipe_config->port_clock = 162000;
else
pipe_config->port_clock = 270000;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 49beab8e324d..43a5b17e2b20 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1397,88 +1397,50 @@
#define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100)
#define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200)
#define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300)
-#define DP_PORT_EN (1 << 31)
-#define DP_PIPE_SEL_SHIFT 30
-#define DP_PIPE_SEL_MASK (1 << 30)
-#define DP_PIPE_SEL(pipe) ((pipe) << 30)
-#define DP_PIPE_SEL_SHIFT_IVB 29
-#define DP_PIPE_SEL_MASK_IVB (3 << 29)
-#define DP_PIPE_SEL_IVB(pipe) ((pipe) << 29)
+#define DP_PORT_EN REG_BIT(31)
+#define DP_PIPE_SEL_MASK REG_GENMASK(30, 30)
+#define DP_PIPE_SEL(pipe) REG_FIELD_PREP(DP_PIPE_SEL_MASK, (pipe))
+#define DP_PIPE_SEL_MASK_IVB REG_GENMASK(30, 29)
+#define DP_PIPE_SEL_IVB(pipe) REG_FIELD_PREP(DP_PIPE_SEL_MASK_IVB, (pipe))
#define DP_PIPE_SEL_SHIFT_CHV 16
-#define DP_PIPE_SEL_MASK_CHV (3 << 16)
-#define DP_PIPE_SEL_CHV(pipe) ((pipe) << 16)
-
-/* Link training mode - select a suitable mode for each stage */
-#define DP_LINK_TRAIN_PAT_1 (0 << 28)
-#define DP_LINK_TRAIN_PAT_2 (1 << 28)
-#define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
-#define DP_LINK_TRAIN_OFF (3 << 28)
-#define DP_LINK_TRAIN_MASK (3 << 28)
-#define DP_LINK_TRAIN_SHIFT 28
-
-/* CPT Link training mode */
-#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
-#define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
-#define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
-#define DP_LINK_TRAIN_OFF_CPT (3 << 8)
-#define DP_LINK_TRAIN_MASK_CPT (7 << 8)
-#define DP_LINK_TRAIN_SHIFT_CPT 8
-
-/* Signal voltages. These are mostly controlled by the other end */
-#define DP_VOLTAGE_0_4 (0 << 25)
-#define DP_VOLTAGE_0_6 (1 << 25)
-#define DP_VOLTAGE_0_8 (2 << 25)
-#define DP_VOLTAGE_1_2 (3 << 25)
-#define DP_VOLTAGE_MASK (7 << 25)
-#define DP_VOLTAGE_SHIFT 25
-
-/* Signal pre-emphasis levels, like voltages, the other end tells us what
- * they want
- */
-#define DP_PRE_EMPHASIS_0 (0 << 22)
-#define DP_PRE_EMPHASIS_3_5 (1 << 22)
-#define DP_PRE_EMPHASIS_6 (2 << 22)
-#define DP_PRE_EMPHASIS_9_5 (3 << 22)
-#define DP_PRE_EMPHASIS_MASK (7 << 22)
-#define DP_PRE_EMPHASIS_SHIFT 22
-
-/* How many wires to use. I guess 3 was too hard */
-#define DP_PORT_WIDTH(width) (((width) - 1) << 19)
-#define DP_PORT_WIDTH_MASK (7 << 19)
-#define DP_PORT_WIDTH_SHIFT 19
-
-/* Mystic DPCD version 1.1 special mode */
-#define DP_ENHANCED_FRAMING (1 << 18)
-
-/* eDP */
-#define DP_PLL_FREQ_270MHZ (0 << 16)
-#define DP_PLL_FREQ_162MHZ (1 << 16)
-#define DP_PLL_FREQ_MASK (3 << 16)
-
-/* locked once port is enabled */
-#define DP_PORT_REVERSAL (1 << 15)
-
-/* eDP */
-#define DP_PLL_ENABLE (1 << 14)
-
-/* sends the clock on lane 15 of the PEG for debug */
-#define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
-
-#define DP_SCRAMBLING_DISABLE (1 << 12)
-#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
-
-/* limit RGB values to avoid confusing TVs */
-#define DP_COLOR_RANGE_16_235 (1 << 8)
-
-/* Turn on the audio link */
-#define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
-
-/* vs and hs sync polarity */
-#define DP_SYNC_VS_HIGH (1 << 4)
-#define DP_SYNC_HS_HIGH (1 << 3)
-
-/* A fantasy */
-#define DP_DETECTED (1 << 2)
+#define DP_PIPE_SEL_MASK_CHV REG_GENMASK(17, 16)
+#define DP_PIPE_SEL_CHV(pipe) REG_FIELD_PREP(DP_PIPE_SEL_MASK_CHV, (pipe))
+#define DP_LINK_TRAIN_MASK REG_GENMASK(29, 28)
+#define DP_LINK_TRAIN_PAT_1 REG_FIELD_PREP(DP_LINK_TRAIN_MASK, 0)
+#define DP_LINK_TRAIN_PAT_2 REG_FIELD_PREP(DP_LINK_TRAIN_MASK, 1)
+#define DP_LINK_TRAIN_PAT_IDLE REG_FIELD_PREP(DP_LINK_TRAIN_MASK, 2)
+#define DP_LINK_TRAIN_OFF REG_FIELD_PREP(DP_LINK_TRAIN_MASK, 3)
+#define DP_LINK_TRAIN_MASK_CPT REG_GENMASK(10, 8)
+#define DP_LINK_TRAIN_PAT_1_CPT REG_FIELD_PREP(DP_LINK_TRAIN_MASK_CPT, 0)
+#define DP_LINK_TRAIN_PAT_2_CPT REG_FIELD_PREP(DP_LINK_TRAIN_MASK_CPT, 1)
+#define DP_LINK_TRAIN_PAT_IDLE_CPT REG_FIELD_PREP(DP_LINK_TRAIN_MASK_CPT, 2)
+#define DP_LINK_TRAIN_OFF_CPT REG_FIELD_PREP(DP_LINK_TRAIN_MASK_CPT, 3)
+#define DP_VOLTAGE_MASK REG_GENMASK(27, 25)
+#define DP_VOLTAGE_0_4 REG_FIELD_PREP(DP_VOLTAGE_MASK, 0)
+#define DP_VOLTAGE_0_6 REG_FIELD_PREP(DP_VOLTAGE_MASK, 1)
+#define DP_VOLTAGE_0_8 REG_FIELD_PREP(DP_VOLTAGE_MASK, 2)
+#define DP_VOLTAGE_1_2 REG_FIELD_PREP(DP_VOLTAGE_MASK, 3)
+#define DP_PRE_EMPHASIS_MASK REG_GENMASK(24, 22)
+#define DP_PRE_EMPHASIS_0 REG_FIELD_PREP(DP_PRE_EMPHASIS_MASK, 0)
+#define DP_PRE_EMPHASIS_3_5 REG_FIELD_PREP(DP_PRE_EMPHASIS_MASK, 1)
+#define DP_PRE_EMPHASIS_6 REG_FIELD_PREP(DP_PRE_EMPHASIS_MASK, 2)
+#define DP_PRE_EMPHASIS_9_5 REG_FIELD_PREP(DP_PRE_EMPHASIS_MASK, 3)
+#define DP_PORT_WIDTH_MASK REG_GENMASK(21, 19)
+#define DP_PORT_WIDTH(width) REG_FIELD_PREP(DP_PORT_WIDTH_MASK, (width) - 1)
+#define DP_ENHANCED_FRAMING REG_BIT(18)
+#define EDP_PLL_FREQ_MASK REG_GENMASK(17, 16)
+#define EDP_PLL_FREQ_270MHZ REG_FIELD_PREP(EDP_PLL_FREQ_MASK, 0)
+#define EDP_PLL_FREQ_162MHZ REG_FIELD_PREP(EDP_PLL_FREQ_MASK, 1)
+#define DP_PORT_REVERSAL REG_BIT(15)
+#define EDP_PLL_ENABLE REG_BIT(14)
+#define DP_CLOCK_OUTPUT_ENABLE REG_BIT(13)
+#define DP_SCRAMBLING_DISABLE REG_BIT(12)
+#define DP_SCRAMBLING_DISABLE_ILK REG_BIT(7)
+#define DP_COLOR_RANGE_16_235 REG_BIT(8)
+#define DP_AUDIO_OUTPUT_ENABLE REG_BIT(6)
+#define DP_SYNC_VS_HIGH REG_BIT(4)
+#define DP_SYNC_HS_HIGH REG_BIT(3)
+#define DP_DETECTED REG_BIT(2)
/*
* Computing GMCH M and N values for the Display Port link
--
2.39.5
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 2/3] drm/i915/reg: Add/remove some extra blank lines
2025-04-15 10:51 [PATCH v2 0/3] drm/i915: i915_reg.h display split Jani Nikula
2025-04-15 10:51 ` [PATCH v2 1/3] drm/i915/reg: use REG_BIT and friends to define DP registers Jani Nikula
@ 2025-04-15 10:51 ` Jani Nikula
2025-04-15 10:51 ` [PATCH v2 3/3] drm/i915: split out display register macros to a separate file Jani Nikula
` (8 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Jani Nikula @ 2025-04-15 10:51 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala, Suraj Kandpal
Add/remove some blank lines to/from i915_reg.h primarily to help the
scripted refactoring coming up, separating unrelated registers and
keeping the comments together.
v2: Also add some extra blank lines
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> # v1
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 43a5b17e2b20..88c46a7c948f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -866,6 +866,7 @@
#define FP_M2_DIV_MASK 0x0000003f
#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
#define FP_M2_DIV_SHIFT 0
+
#define DPLL_TEST _MMIO(0x606c)
#define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
#define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
@@ -877,11 +878,13 @@
#define DPLLA_TEST_N_BYPASS (1 << 3)
#define DPLLA_TEST_M_BYPASS (1 << 2)
#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
+
#define D_STATE _MMIO(0x6104)
#define DSTATE_GFX_RESET_I830 (1 << 6)
#define DSTATE_PLL_D3_OFF (1 << 3)
#define DSTATE_GFX_CLOCK_GATING (1 << 1)
#define DSTATE_DOT_CLOCK_GATING (1 << 0)
+
#define DSPCLK_GATE_D(__i915) _MMIO(DISPLAY_MMIO_BASE(__i915) + 0x6200)
# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
@@ -1050,7 +1053,6 @@
/*
* Overlay regs
*/
-
#define OVADD _MMIO(0x30000)
#define DOVSTA _MMIO(0x30008)
#define OC_BUF (0x3 << 20)
@@ -1106,7 +1108,6 @@
/*
* Display engine regs
*/
-
/* Pipe/transcoder A timing regs */
#define _TRANS_HTOTAL_A 0x60000
#define _TRANS_HTOTAL_B 0x61000
@@ -2746,7 +2747,6 @@
* functionality covered in PCH_PORT_HOTPLUG is split into
* SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
*/
-
#define SHOTPLUG_CTL_DDI _MMIO(0xc4030)
#define SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin) (0x8 << (_HPD_PIN_DDI(hpd_pin) * 4))
#define SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(hpd_pin) (0x4 << (_HPD_PIN_DDI(hpd_pin) * 4))
@@ -2826,7 +2826,6 @@
#define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3))
/* transcoder */
-
#define _PCH_TRANS_HTOTAL_A 0xe0000
#define _PCH_TRANS_HTOTAL_B 0xe1000
#define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
@@ -3757,7 +3756,6 @@ enum skl_power_gate {
/*
* SKL Clocks
*/
-
/* CDCLK_CTL */
#define CDCLK_CTL _MMIO(0x46000)
#define CDCLK_FREQ_SEL_MASK REG_GENMASK(27, 26)
--
2.39.5
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 3/3] drm/i915: split out display register macros to a separate file
2025-04-15 10:51 [PATCH v2 0/3] drm/i915: i915_reg.h display split Jani Nikula
2025-04-15 10:51 ` [PATCH v2 1/3] drm/i915/reg: use REG_BIT and friends to define DP registers Jani Nikula
2025-04-15 10:51 ` [PATCH v2 2/3] drm/i915/reg: Add/remove some extra blank lines Jani Nikula
@ 2025-04-15 10:51 ` Jani Nikula
2025-04-17 8:33 ` Kandpal, Suraj
2025-04-15 11:42 ` ✓ CI.Patch_applied: success for drm/i915: i915_reg.h display split (rev2) Patchwork
` (7 subsequent siblings)
10 siblings, 1 reply; 13+ messages in thread
From: Jani Nikula @ 2025-04-15 10:51 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala, Suraj Kandpal
This is a scripted split of the display related register macros from
i915_reg.h to display/intel_display_regs.h. As a starting point, move
all the macros that are only used in display code (or GVT). If there are
users in core i915 code or soc/, or no users anywhere, keep the macros
in i915_reg.h. This is done in groups of macros separated by blank
lines, moving the comments along with the groups.
Some manually picked macro groups are kept/moved regardless of the
heuristics above.
This is obviously a very crude approach. It's not perfect. But there are
4.2k lines in i915_reg.h, and its refactoring has ground to a halt. This
is the big hammer that splits the file to two, and enables further
cleanup.
Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
All moved lines are moved verbatim, with no additional changes, so 'git
show --color-moved' will be helpful for review.
I've added a way to manually indicate register macro groups that should
be moved or kept. I've added some to the list. I hope the end result is
better than last time. It's trivial to amend those move/keep lists and
re-run this if you spot something that's not right.
---
drivers/gpu/drm/i915/display/g4x_dp.c | 1 +
drivers/gpu/drm/i915/display/g4x_hdmi.c | 1 +
drivers/gpu/drm/i915/display/hsw_ips.c | 1 +
.../gpu/drm/i915/display/i9xx_display_sr.c | 1 +
drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +
drivers/gpu/drm/i915/display/i9xx_wm.c | 1 +
drivers/gpu/drm/i915/display/icl_dsi.c | 1 +
.../gpu/drm/i915/display/intel_backlight.c | 2 +-
drivers/gpu/drm/i915/display/intel_bw.c | 3 +-
drivers/gpu/drm/i915/display/intel_cdclk.c | 1 +
drivers/gpu/drm/i915/display/intel_cmtg.c | 3 +-
.../gpu/drm/i915/display/intel_combo_phy.c | 1 +
drivers/gpu/drm/i915/display/intel_crt.c | 1 +
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 3 +-
.../drm/i915/display/intel_display_debugfs.c | 1 +
.../drm/i915/display/intel_display_device.c | 6 +-
.../gpu/drm/i915/display/intel_display_irq.c | 2 +
.../drm/i915/display/intel_display_power.c | 1 +
.../i915/display/intel_display_power_map.c | 1 +
.../i915/display/intel_display_power_well.c | 1 +
.../gpu/drm/i915/display/intel_display_regs.h | 2878 +++++++++++++++++
.../gpu/drm/i915/display/intel_display_wa.c | 1 +
drivers/gpu/drm/i915/display/intel_dmc.c | 3 +-
drivers/gpu/drm/i915/display/intel_dmc_wl.c | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 4 +-
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 1 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 1 +
drivers/gpu/drm/i915/display/intel_dp_test.c | 1 +
drivers/gpu/drm/i915/display/intel_dpio_phy.c | 1 +
drivers/gpu/drm/i915/display/intel_dpll.c | 1 +
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 +
.../gpu/drm/i915/display/intel_dpt_common.c | 1 +
drivers/gpu/drm/i915/display/intel_drrs.c | 1 +
drivers/gpu/drm/i915/display/intel_dsb.c | 1 +
drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 3 +-
drivers/gpu/drm/i915/display/intel_dvo.c | 1 +
drivers/gpu/drm/i915/display/intel_fbc.c | 3 +
drivers/gpu/drm/i915/display/intel_fdi.c | 3 +-
.../drm/i915/display/intel_fifo_underrun.c | 1 +
drivers/gpu/drm/i915/display/intel_gmbus.c | 1 +
drivers/gpu/drm/i915/display/intel_hdcp.c | 1 +
drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
.../gpu/drm/i915/display/intel_hotplug_irq.c | 1 +
drivers/gpu/drm/i915/display/intel_lspcon.c | 1 +
.../drm/i915/display/intel_modeset_setup.c | 3 +-
drivers/gpu/drm/i915/display/intel_overlay.c | 2 +
.../gpu/drm/i915/display/intel_pch_display.c | 1 +
.../gpu/drm/i915/display/intel_pch_refclk.c | 1 +
drivers/gpu/drm/i915/display/intel_pfit.c | 1 +
drivers/gpu/drm/i915/display/intel_pipe_crc.c | 1 +
drivers/gpu/drm/i915/display/intel_pmdemand.c | 1 +
drivers/gpu/drm/i915/display/intel_pps.c | 1 +
drivers/gpu/drm/i915/display/intel_psr.c | 1 +
drivers/gpu/drm/i915/display/intel_sdvo.c | 1 +
drivers/gpu/drm/i915/display/intel_snps_phy.c | 1 +
drivers/gpu/drm/i915/display/intel_tc.c | 1 +
drivers/gpu/drm/i915/display/intel_vblank.c | 1 +
drivers/gpu/drm/i915/display/intel_vga.c | 2 +
drivers/gpu/drm/i915/display/intel_vrr.c | 1 +
drivers/gpu/drm/i915/display/skl_scaler.c | 1 +
.../drm/i915/display/skl_universal_plane.c | 4 +-
drivers/gpu/drm/i915/display/skl_watermark.c | 1 +
drivers/gpu/drm/i915/display/vlv_dsi.c | 1 +
drivers/gpu/drm/i915/gvt/cmd_parser.c | 1 +
drivers/gpu/drm/i915/gvt/display.c | 1 +
drivers/gpu/drm/i915/gvt/fb_decoder.c | 1 +
drivers/gpu/drm/i915/gvt/handlers.c | 1 +
drivers/gpu/drm/i915/gvt/interrupt.c | 1 +
drivers/gpu/drm/i915/gvt/mmio.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 2867 ----------------
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1 +
drivers/gpu/drm/xe/display/xe_plane_initial.c | 1 +
73 files changed, 2967 insertions(+), 2882 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_display_regs.h
diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
index 9b6792c701d1..646ff7d1c53b 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -16,6 +16,7 @@
#include "intel_crtc.h"
#include "intel_de.h"
#include "intel_display_power.h"
+#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_dp.h"
#include "intel_dp_aux.h"
diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c b/drivers/gpu/drm/i915/display/g4x_hdmi.c
index 21b5db2fa203..863fea23dd08 100644
--- a/drivers/gpu/drm/i915/display/g4x_hdmi.c
+++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c
@@ -14,6 +14,7 @@
#include "intel_crtc.h"
#include "intel_de.h"
#include "intel_display_power.h"
+#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_dp_aux.h"
#include "intel_dpio_phy.h"
diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c b/drivers/gpu/drm/i915/display/hsw_ips.c
index 4307e2ed03d9..0d33782f11be 100644
--- a/drivers/gpu/drm/i915/display/hsw_ips.c
+++ b/drivers/gpu/drm/i915/display/hsw_ips.c
@@ -10,6 +10,7 @@
#include "i915_reg.h"
#include "intel_color_regs.h"
#include "intel_de.h"
+#include "intel_display_regs.h"
#include "intel_display_rpm.h"
#include "intel_display_types.h"
#include "intel_pcode.h"
diff --git a/drivers/gpu/drm/i915/display/i9xx_display_sr.c b/drivers/gpu/drm/i915/display/i9xx_display_sr.c
index 32abe9743014..357212f09a0f 100644
--- a/drivers/gpu/drm/i915/display/i9xx_display_sr.c
+++ b/drivers/gpu/drm/i915/display/i9xx_display_sr.c
@@ -9,6 +9,7 @@
#include "i9xx_display_sr.h"
#include "i9xx_wm_regs.h"
#include "intel_de.h"
+#include "intel_display_regs.h"
#include "intel_gmbus.h"
#include "intel_pci_config.h"
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 5e8344fdfc28..b7248ae98ad1 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -2,6 +2,7 @@
/*
* Copyright © 2020 Intel Corporation
*/
+
#include <linux/kernel.h>
#include <drm/drm_atomic_helper.h>
@@ -16,6 +17,7 @@
#include "intel_atomic_plane.h"
#include "intel_de.h"
#include "intel_display_irq.h"
+#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_fb.h"
#include "intel_fbc.h"
diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
index 40751f1547b7..9f0509a5d2c1 100644
--- a/drivers/gpu/drm/i915/display/i9xx_wm.c
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
@@ -11,6 +11,7 @@
#include "intel_bo.h"
#include "intel_de.h"
#include "intel_display.h"
+#include "intel_display_regs.h"
#include "intel_display_trace.h"
#include "intel_fb.h"
#include "intel_mchbar_regs.h"
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index ca7033251e91..c62e97e494c2 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -45,6 +45,7 @@
#include "intel_crtc.h"
#include "intel_ddi.h"
#include "intel_de.h"
+#include "intel_display_regs.h"
#include "intel_dsi.h"
#include "intel_dsi_vbt.h"
#include "intel_panel.h"
diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c b/drivers/gpu/drm/i915/display/intel_backlight.c
index 4f3fa966c537..3e9e0b2b4a53 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -7,7 +7,6 @@
#include <linux/kernel.h>
#include <linux/pwm.h>
#include <linux/string_helpers.h>
-
#include <acpi/video.h>
#include "i915_drv.h"
@@ -16,6 +15,7 @@
#include "intel_backlight_regs.h"
#include "intel_connector.h"
#include "intel_de.h"
+#include "intel_display_regs.h"
#include "intel_display_rpm.h"
#include "intel_display_types.h"
#include "intel_dp_aux_backlight.h"
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index a5dd2932b852..23712f38d368 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -12,10 +12,11 @@
#include "intel_bw.h"
#include "intel_cdclk.h"
#include "intel_display_core.h"
+#include "intel_display_regs.h"
#include "intel_display_types.h"
-#include "skl_watermark.h"
#include "intel_mchbar_regs.h"
#include "intel_pcode.h"
+#include "skl_watermark.h"
/* Parameters for Qclk Geyserville (QGV) */
struct intel_qgv_point {
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 6830950aae3f..e9f315f6a5a1 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -38,6 +38,7 @@
#include "intel_cdclk.h"
#include "intel_crtc.h"
#include "intel_de.h"
+#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_mchbar_regs.h"
#include "intel_pci_config.h"
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index 07d7f4e8f60f..e9d03daec80d 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -11,12 +11,13 @@
#include "i915_drv.h"
#include "i915_reg.h"
-#include "intel_crtc.h"
#include "intel_cmtg.h"
#include "intel_cmtg_regs.h"
+#include "intel_crtc.h"
#include "intel_de.h"
#include "intel_display_device.h"
#include "intel_display_power.h"
+#include "intel_display_regs.h"
/**
* DOC: Common Primary Timing Generator (CMTG)
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index f5cc38dbe559..b1bff2f0b020 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -10,6 +10,7 @@
#include "intel_combo_phy.h"
#include "intel_combo_phy_regs.h"
#include "intel_de.h"
+#include "intel_display_regs.h"
#include "intel_display_types.h"
#define for_each_combo_phy(__display, __phy) \
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index cca22d2402e8..20eafd2a48fd 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -44,6 +44,7 @@
#include "intel_ddi_buf_trans.h"
#include "intel_de.h"
#include "intel_display_driver.h"
+#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_fdi.h"
#include "intel_fdi_regs.h"
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index b48ed5df7a96..def7ce928782 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -48,6 +48,7 @@
#include "intel_ddi_buf_trans.h"
#include "intel_de.h"
#include "intel_display_power.h"
+#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_dkl_phy.h"
#include "intel_dkl_phy_regs.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index db524d01e574..dfe9972f602e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -66,13 +66,14 @@
#include "intel_crt.h"
#include "intel_crtc.h"
#include "intel_crtc_state_dump.h"
+#include "intel_cursor.h"
#include "intel_cursor_regs.h"
#include "intel_cx0_phy.h"
-#include "intel_cursor.h"
#include "intel_ddi.h"
#include "intel_de.h"
#include "intel_display_driver.h"
#include "intel_display_power.h"
+#include "intel_display_regs.h"
#include "intel_display_rpm.h"
#include "intel_display_types.h"
#include "intel_dmc.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 3f7c605d47d3..7d70918903e3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -24,6 +24,7 @@
#include "intel_display_debugfs_params.h"
#include "intel_display_power.h"
#include "intel_display_power_well.h"
+#include "intel_display_regs.h"
#include "intel_display_rpm.h"
#include "intel_display_types.h"
#include "intel_dmc.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index 738ae522c8f4..cf4ab425984b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -3,10 +3,11 @@
* Copyright © 2023 Intel Corporation
*/
-#include <drm/intel/pciids.h>
-#include <drm/drm_color_mgmt.h>
#include <linux/pci.h>
+#include <drm/drm_color_mgmt.h>
+#include <drm/intel/pciids.h>
+
#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_cx0_phy_regs.h"
@@ -16,6 +17,7 @@
#include "intel_display_params.h"
#include "intel_display_power.h"
#include "intel_display_reg_defs.h"
+#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_fbc.h"
#include "intel_step.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 5d07b6a9e59e..30bf80bb576b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -6,6 +6,7 @@
#include <drm/drm_vblank.h>
#include "gt/intel_rps.h"
+
#include "i915_drv.h"
#include "i915_irq.h"
#include "i915_reg.h"
@@ -14,6 +15,7 @@
#include "intel_crtc.h"
#include "intel_de.h"
#include "intel_display_irq.h"
+#include "intel_display_regs.h"
#include "intel_display_rpm.h"
#include "intel_display_trace.h"
#include "intel_display_types.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index c78315eb44fa..592f6d0cce97 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -16,6 +16,7 @@
#include "intel_display_power.h"
#include "intel_display_power_map.h"
#include "intel_display_power_well.h"
+#include "intel_display_regs.h"
#include "intel_display_rpm.h"
#include "intel_display_types.h"
#include "intel_dmc.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index ab1163744bc5..adbe321cb70b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -9,6 +9,7 @@
#include "intel_display_core.h"
#include "intel_display_power_map.h"
#include "intel_display_power_well.h"
+#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "vlv_sideband_reg.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index b9b4359751cc..c360d8365c84 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -13,6 +13,7 @@
#include "intel_de.h"
#include "intel_display_irq.h"
#include "intel_display_power_well.h"
+#include "intel_display_regs.h"
#include "intel_display_rpm.h"
#include "intel_display_types.h"
#include "intel_dkl_phy.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
new file mode 100644
index 000000000000..19c02a2e3198
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -0,0 +1,2878 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright © 2025 Intel Corporation */
+
+#ifndef __INTEL_DISPLAY_REGS_H__
+#define __INTEL_DISPLAY_REGS_H__
+
+#include "intel_display_reg_defs.h"
+
+#define _GEN7_PIPEA_DE_LOAD_SL 0x70068
+#define _GEN7_PIPEB_DE_LOAD_SL 0x71068
+#define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
+
+#define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110)
+#define DPIO_MODSEL1 (1 << 3) /* if ref clk b == 27 */
+#define DPIO_MODSEL0 (1 << 2) /* if ref clk a == 27 */
+#define DPIO_SFR_BYPASS (1 << 1)
+#define DPIO_CMNRST (1 << 0)
+
+#define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090)
+#define MIPIO_RST_CTRL (1 << 2)
+
+#define _BXT_PHY_CTL_DDI_A 0x64C00
+#define _BXT_PHY_CTL_DDI_B 0x64C10
+#define _BXT_PHY_CTL_DDI_C 0x64C20
+#define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10)
+#define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9)
+#define BXT_PHY_LANE_ENABLED (1 << 8)
+#define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \
+ _BXT_PHY_CTL_DDI_B)
+
+#define _PHY_CTL_FAMILY_DDI 0x64C90
+#define _PHY_CTL_FAMILY_EDP 0x64C80
+#define _PHY_CTL_FAMILY_DDI_C 0x64CA0
+#define COMMON_RESET_DIS (1 << 31)
+#define BXT_PHY_CTL_FAMILY(phy) \
+ _MMIO(_PICK_EVEN_2RANGES(phy, 1, \
+ _PHY_CTL_FAMILY_DDI, _PHY_CTL_FAMILY_DDI, \
+ _PHY_CTL_FAMILY_EDP, _PHY_CTL_FAMILY_DDI_C))
+
+/* UAIMI scratch pad register 1 */
+#define UAIMI_SPR1 _MMIO(0x4F074)
+/* SKL VccIO mask */
+#define SKL_VCCIO_MASK 0x1
+/* SKL balance leg register */
+#define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C)
+/* I_boost values */
+#define BALANCE_LEG_SHIFT(port) (8 + 3 * (port))
+#define BALANCE_LEG_MASK(port) (7 << (8 + 3 * (port)))
+/* Balance leg disable bits */
+#define BALANCE_LEG_DISABLE_SHIFT 23
+#define BALANCE_LEG_DISABLE(port) (1 << (23 + (port)))
+
+#define ILK_GTT_FAULT _MMIO(0x44040) /* ilk/snb */
+#define GTT_FAULT_INVALID_GTT_PTE (1 << 7)
+#define GTT_FAULT_INVALID_PTE_DATA (1 << 6)
+#define GTT_FAULT_CURSOR_B_FAULT (1 << 5)
+#define GTT_FAULT_CURSOR_A_FAULT (1 << 4)
+#define GTT_FAULT_SPRITE_B_FAULT (1 << 3)
+#define GTT_FAULT_SPRITE_A_FAULT (1 << 2)
+#define GTT_FAULT_PRIMARY_B_FAULT (1 << 1)
+#define GTT_FAULT_PRIMARY_A_FAULT (1 << 0)
+
+#define VLV_IRQ_REGS I915_IRQ_REGS(VLV_IMR, \
+ VLV_IER, \
+ VLV_IIR)
+
+#define VLV_EIR _MMIO(VLV_DISPLAY_BASE + 0x20b0)
+#define VLV_EMR _MMIO(VLV_DISPLAY_BASE + 0x20b4)
+#define VLV_ESR _MMIO(VLV_DISPLAY_BASE + 0x20b8)
+#define VLV_ERROR_GUNIT_TLB_DATA (1 << 6)
+#define VLV_ERROR_GUNIT_TLB_PTE (1 << 5)
+#define VLV_ERROR_PAGE_TABLE (1 << 4)
+#define VLV_ERROR_CLAIM (1 << 0)
+
+#define VLV_ERROR_REGS I915_ERROR_REGS(VLV_EMR, VLV_EIR)
+
+#define _MBUS_ABOX0_CTL 0x45038
+#define _MBUS_ABOX1_CTL 0x45048
+#define _MBUS_ABOX2_CTL 0x4504C
+#define MBUS_ABOX_CTL(x) \
+ _MMIO(_PICK_EVEN_2RANGES(x, 2, \
+ _MBUS_ABOX0_CTL, _MBUS_ABOX1_CTL, \
+ _MBUS_ABOX2_CTL, _MBUS_ABOX2_CTL))
+
+#define MBUS_ABOX_BW_CREDIT_MASK (3 << 20)
+#define MBUS_ABOX_BW_CREDIT(x) ((x) << 20)
+#define MBUS_ABOX_B_CREDIT_MASK (0xF << 16)
+#define MBUS_ABOX_B_CREDIT(x) ((x) << 16)
+#define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8)
+#define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8)
+#define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0)
+#define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0)
+
+#define IPS_CTL _MMIO(0x43408)
+#define IPS_ENABLE REG_BIT(31)
+#define IPS_FALSE_COLOR REG_BIT(4)
+
+/*
+ * Clock control & power management
+ */
+#define _DPLL_A 0x6014
+#define _DPLL_B 0x6018
+#define _CHV_DPLL_C 0x6030
+#define DPLL(dev_priv, pipe) _MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \
+ (pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
+
+#define VGA0 _MMIO(0x6000)
+#define VGA1 _MMIO(0x6004)
+#define VGA_PD _MMIO(0x6010)
+#define VGA0_PD_P2_DIV_4 (1 << 7)
+#define VGA0_PD_P1_DIV_2 (1 << 5)
+#define VGA0_PD_P1_SHIFT 0
+#define VGA0_PD_P1_MASK (0x1f << 0)
+#define VGA1_PD_P2_DIV_4 (1 << 15)
+#define VGA1_PD_P1_DIV_2 (1 << 13)
+#define VGA1_PD_P1_SHIFT 8
+#define VGA1_PD_P1_MASK (0x1f << 8)
+#define DPLL_VCO_ENABLE (1 << 31)
+#define DPLL_SDVO_HIGH_SPEED (1 << 30)
+#define DPLL_DVO_2X_MODE (1 << 30)
+#define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
+#define DPLL_SYNCLOCK_ENABLE (1 << 29)
+#define DPLL_REF_CLK_ENABLE_VLV (1 << 29)
+#define DPLL_VGA_MODE_DIS (1 << 28)
+#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
+#define DPLLB_MODE_LVDS (2 << 26) /* i915 */
+#define DPLL_MODE_MASK (3 << 26)
+#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
+#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
+#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
+#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
+#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
+#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
+#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
+#define DPLL_LOCK_VLV (1 << 15)
+#define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14)
+#define DPLL_INTEGRATED_REF_CLK_VLV (1 << 13)
+#define DPLL_SSC_REF_CLK_CHV (1 << 13)
+#define DPLL_PORTC_READY_MASK (0xf << 4)
+#define DPLL_PORTB_READY_MASK (0xf)
+
+#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
+
+/* Additional CHV pll/phy registers */
+#define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240)
+#define DPLL_PORTD_READY_MASK (0xf)
+#define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
+#define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2 * (phy) + (ch) + 27))
+#define PHY_LDO_DELAY_0NS 0x0
+#define PHY_LDO_DELAY_200NS 0x1
+#define PHY_LDO_DELAY_600NS 0x2
+#define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2 * (phy) + 23))
+#define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 * (phy) + 4 * (ch) + 11))
+#define PHY_CH_SU_PSR 0x1
+#define PHY_CH_DEEP_PSR 0x7
+#define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6 * (phy) + 3 * (ch) + 2))
+#define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))
+#define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
+#define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30))
+#define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch))))
+#define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline))))
+
+/*
+ * The i830 generation, in LVDS mode, defines P1 as the bit number set within
+ * this field (only one bit may be set).
+ */
+#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
+#define DPLL_FPA01_P1_POST_DIV_SHIFT 16
+#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
+/* i830, required in DVO non-gang */
+#define PLL_P2_DIVIDE_BY_4 (1 << 23)
+#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
+#define PLL_REF_INPUT_DREFCLK (0 << 13)
+#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
+#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
+#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
+#define PLL_REF_INPUT_MASK (3 << 13)
+#define PLL_LOAD_PULSE_PHASE_SHIFT 9
+/* Ironlake */
+# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
+# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
+# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9)
+# define DPLL_FPA1_P1_POST_DIV_SHIFT 0
+# define DPLL_FPA1_P1_POST_DIV_MASK 0xff
+
+/*
+ * Parallel to Serial Load Pulse phase selection.
+ * Selects the phase for the 10X DPLL clock for the PCIe
+ * digital display port. The range is 4 to 13; 10 or more
+ * is just a flip delay. The default is 6
+ */
+#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
+#define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
+/*
+ * SDVO multiplier for 945G/GM. Not used on 965.
+ */
+#define SDVO_MULTIPLIER_MASK 0x000000ff
+#define SDVO_MULTIPLIER_SHIFT_HIRES 4
+#define SDVO_MULTIPLIER_SHIFT_VGA 0
+
+#define _DPLL_A_MD 0x601c
+#define _DPLL_B_MD 0x6020
+#define _CHV_DPLL_C_MD 0x603c
+#define DPLL_MD(dev_priv, pipe) _MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \
+ (pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
+
+/*
+ * UDI pixel divider, controlling how many pixels are stuffed into a packet.
+ *
+ * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
+ */
+#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
+#define DPLL_MD_UDI_DIVIDER_SHIFT 24
+/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
+#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
+#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
+/*
+ * SDVO/UDI pixel multiplier.
+ *
+ * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
+ * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
+ * modes, the bus rate would be below the limits, so SDVO allows for stuffing
+ * dummy bytes in the datastream at an increased clock rate, with both sides of
+ * the link knowing how many bytes are fill.
+ *
+ * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
+ * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
+ * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
+ * through an SDVO command.
+ *
+ * This register field has values of multiplication factor minus 1, with
+ * a maximum multiplier of 5 for SDVO.
+ */
+#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
+#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
+/*
+ * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
+ * This best be set to the default value (3) or the CRT won't work. No,
+ * I don't entirely understand what this does...
+ */
+#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
+#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
+
+#define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024)
+
+#define _FPA0 0x6040
+#define _FPA1 0x6044
+#define _FPB0 0x6048
+#define _FPB1 0x604c
+#define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0)
+#define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1)
+#define FP_N_DIV_MASK 0x003f0000
+#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
+#define FP_N_DIV_SHIFT 16
+#define FP_M1_DIV_MASK 0x00003f00
+#define FP_M1_DIV_SHIFT 8
+#define FP_M2_DIV_MASK 0x0000003f
+#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
+#define FP_M2_DIV_SHIFT 0
+
+#define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500)
+#define FW_CSPWRDWNEN (1 << 15)
+
+#define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)
+
+#define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508)
+#define CDCLK_FREQ_SHIFT 4
+#define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT)
+#define CZCLK_FREQ_MASK 0xf
+
+#define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C)
+#define PFI_CREDIT_63 (9 << 28) /* chv only */
+#define PFI_CREDIT_31 (8 << 28) /* chv only */
+#define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */
+#define PFI_CREDIT_RESEND (1 << 27)
+#define VGA_FAST_MODE_DISABLE (1 << 14)
+
+#define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510)
+
+#define PEG_BAND_GAP_DATA _MMIO(0x14d68)
+
+/*
+ * Overlay regs
+ */
+#define OVADD _MMIO(0x30000)
+#define DOVSTA _MMIO(0x30008)
+#define OC_BUF (0x3 << 20)
+#define OGAMC5 _MMIO(0x30010)
+#define OGAMC4 _MMIO(0x30014)
+#define OGAMC3 _MMIO(0x30018)
+#define OGAMC2 _MMIO(0x3001c)
+#define OGAMC1 _MMIO(0x30020)
+#define OGAMC0 _MMIO(0x30024)
+
+#define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
+#define BXT_GMBUS_GATING_DIS (1 << 14)
+#define DG2_DPFC_GATING_DIS REG_BIT(31)
+
+#define GEN9_CLKGATE_DIS_5 _MMIO(0x46540)
+#define DPCE_GATING_DIS REG_BIT(17)
+
+#define _CLKGATE_DIS_PSL_A 0x46520
+#define _CLKGATE_DIS_PSL_B 0x46524
+#define _CLKGATE_DIS_PSL_C 0x46528
+#define DUPS1_GATING_DIS (1 << 15)
+#define DUPS2_GATING_DIS (1 << 19)
+#define DUPS3_GATING_DIS (1 << 23)
+#define CURSOR_GATING_DIS REG_BIT(28)
+#define DPF_GATING_DIS (1 << 10)
+#define DPF_RAM_GATING_DIS (1 << 9)
+#define DPFR_GATING_DIS (1 << 8)
+
+#define CLKGATE_DIS_PSL(pipe) \
+ _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B)
+
+#define _CLKGATE_DIS_PSL_EXT_A 0x4654C
+#define _CLKGATE_DIS_PSL_EXT_B 0x46550
+#define PIPEDMC_GATING_DIS REG_BIT(12)
+
+#define CLKGATE_DIS_PSL_EXT(pipe) \
+ _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_EXT_A, _CLKGATE_DIS_PSL_EXT_B)
+
+/*
+ * Display engine regs
+ */
+/* Pipe/transcoder A timing regs */
+#define _TRANS_HTOTAL_A 0x60000
+#define _TRANS_HTOTAL_B 0x61000
+#define TRANS_HTOTAL(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HTOTAL_A)
+#define HTOTAL_MASK REG_GENMASK(31, 16)
+#define HTOTAL(htotal) REG_FIELD_PREP(HTOTAL_MASK, (htotal))
+#define HACTIVE_MASK REG_GENMASK(15, 0)
+#define HACTIVE(hdisplay) REG_FIELD_PREP(HACTIVE_MASK, (hdisplay))
+
+#define _TRANS_HBLANK_A 0x60004
+#define _TRANS_HBLANK_B 0x61004
+#define TRANS_HBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HBLANK_A)
+#define HBLANK_END_MASK REG_GENMASK(31, 16)
+#define HBLANK_END(hblank_end) REG_FIELD_PREP(HBLANK_END_MASK, (hblank_end))
+#define HBLANK_START_MASK REG_GENMASK(15, 0)
+#define HBLANK_START(hblank_start) REG_FIELD_PREP(HBLANK_START_MASK, (hblank_start))
+
+#define _TRANS_HSYNC_A 0x60008
+#define _TRANS_HSYNC_B 0x61008
+#define TRANS_HSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A)
+#define HSYNC_END_MASK REG_GENMASK(31, 16)
+#define HSYNC_END(hsync_end) REG_FIELD_PREP(HSYNC_END_MASK, (hsync_end))
+#define HSYNC_START_MASK REG_GENMASK(15, 0)
+#define HSYNC_START(hsync_start) REG_FIELD_PREP(HSYNC_START_MASK, (hsync_start))
+
+#define _TRANS_VTOTAL_A 0x6000c
+#define _TRANS_VTOTAL_B 0x6100c
+#define TRANS_VTOTAL(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A)
+#define VTOTAL_MASK REG_GENMASK(31, 16)
+#define VTOTAL(vtotal) REG_FIELD_PREP(VTOTAL_MASK, (vtotal))
+#define VACTIVE_MASK REG_GENMASK(15, 0)
+#define VACTIVE(vdisplay) REG_FIELD_PREP(VACTIVE_MASK, (vdisplay))
+
+#define _TRANS_VBLANK_A 0x60010
+#define _TRANS_VBLANK_B 0x61010
+#define TRANS_VBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A)
+#define VBLANK_END_MASK REG_GENMASK(31, 16)
+#define VBLANK_END(vblank_end) REG_FIELD_PREP(VBLANK_END_MASK, (vblank_end))
+#define VBLANK_START_MASK REG_GENMASK(15, 0)
+#define VBLANK_START(vblank_start) REG_FIELD_PREP(VBLANK_START_MASK, (vblank_start))
+
+#define _TRANS_VSYNC_A 0x60014
+#define _TRANS_VSYNC_B 0x61014
+#define TRANS_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A)
+#define VSYNC_END_MASK REG_GENMASK(31, 16)
+#define VSYNC_END(vsync_end) REG_FIELD_PREP(VSYNC_END_MASK, (vsync_end))
+#define VSYNC_START_MASK REG_GENMASK(15, 0)
+#define VSYNC_START(vsync_start) REG_FIELD_PREP(VSYNC_START_MASK, (vsync_start))
+
+#define _PIPEASRC 0x6001c
+#define _PIPEBSRC 0x6101c
+#define PIPESRC(dev_priv, pipe) _MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC)
+#define PIPESRC_WIDTH_MASK REG_GENMASK(31, 16)
+#define PIPESRC_WIDTH(w) REG_FIELD_PREP(PIPESRC_WIDTH_MASK, (w))
+#define PIPESRC_HEIGHT_MASK REG_GENMASK(15, 0)
+#define PIPESRC_HEIGHT(h) REG_FIELD_PREP(PIPESRC_HEIGHT_MASK, (h))
+
+#define _BCLRPAT_A 0x60020
+#define _BCLRPAT_B 0x61020
+#define BCLRPAT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A)
+
+#define _TRANS_VSYNCSHIFT_A 0x60028
+#define _TRANS_VSYNCSHIFT_B 0x61028
+#define TRANS_VSYNCSHIFT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A)
+
+#define _TRANS_MULT_A 0x6002c
+#define _TRANS_MULT_B 0x6102c
+#define TRANS_MULT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A)
+
+/* Hotplug control (945+ only) */
+#define PORT_HOTPLUG_EN(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
+#define PORTB_HOTPLUG_INT_EN (1 << 29)
+#define PORTC_HOTPLUG_INT_EN (1 << 28)
+#define PORTD_HOTPLUG_INT_EN (1 << 27)
+#define SDVOB_HOTPLUG_INT_EN (1 << 26)
+#define SDVOC_HOTPLUG_INT_EN (1 << 25)
+#define TV_HOTPLUG_INT_EN (1 << 18)
+#define CRT_HOTPLUG_INT_EN (1 << 9)
+#define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \
+ PORTC_HOTPLUG_INT_EN | \
+ PORTD_HOTPLUG_INT_EN | \
+ SDVOC_HOTPLUG_INT_EN | \
+ SDVOB_HOTPLUG_INT_EN | \
+ CRT_HOTPLUG_INT_EN)
+#define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
+#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
+/* must use period 64 on GM45 according to docs */
+#define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
+#define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
+#define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
+#define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
+#define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
+#define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
+#define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
+#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
+#define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
+#define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
+#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
+#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
+
+#define PORT_HOTPLUG_STAT(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114)
+/* HDMI/DP bits are g4x+ */
+#define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27)
+#define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28)
+#define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29)
+#define PORTD_HOTPLUG_INT_STATUS (3 << 21)
+#define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21)
+#define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21)
+#define PORTC_HOTPLUG_INT_STATUS (3 << 19)
+#define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19)
+#define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19)
+#define PORTB_HOTPLUG_INT_STATUS (3 << 17)
+#define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17)
+#define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17)
+/* CRT/TV common between gen3+ */
+#define CRT_HOTPLUG_INT_STATUS (1 << 11)
+#define TV_HOTPLUG_INT_STATUS (1 << 10)
+#define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
+#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
+#define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
+#define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
+#define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6)
+#define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5)
+#define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4)
+#define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4)
+
+/* SDVO is different across gen3/4 */
+#define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
+#define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
+/*
+ * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
+ * since reality corrobates that they're the same as on gen3. But keep these
+ * bits here (and the comment!) to help any other lost wanderers back onto the
+ * right tracks.
+ */
+#define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
+#define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
+#define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
+#define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
+#define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \
+ SDVOB_HOTPLUG_INT_STATUS_G4X | \
+ SDVOC_HOTPLUG_INT_STATUS_G4X | \
+ PORTB_HOTPLUG_INT_STATUS | \
+ PORTC_HOTPLUG_INT_STATUS | \
+ PORTD_HOTPLUG_INT_STATUS)
+
+#define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \
+ SDVOB_HOTPLUG_INT_STATUS_I915 | \
+ SDVOC_HOTPLUG_INT_STATUS_I915 | \
+ PORTB_HOTPLUG_INT_STATUS | \
+ PORTC_HOTPLUG_INT_STATUS | \
+ PORTD_HOTPLUG_INT_STATUS)
+
+/* SDVO and HDMI port control.
+ * The same register may be used for SDVO or HDMI */
+#define _GEN3_SDVOB 0x61140
+#define _GEN3_SDVOC 0x61160
+#define GEN3_SDVOB _MMIO(_GEN3_SDVOB)
+#define GEN3_SDVOC _MMIO(_GEN3_SDVOC)
+#define GEN4_HDMIB GEN3_SDVOB
+#define GEN4_HDMIC GEN3_SDVOC
+#define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140)
+#define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160)
+#define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C)
+#define PCH_SDVOB _MMIO(0xe1140)
+#define PCH_HDMIB PCH_SDVOB
+#define PCH_HDMIC _MMIO(0xe1150)
+#define PCH_HDMID _MMIO(0xe1160)
+
+#define PORT_DFT_I9XX _MMIO(0x61150)
+#define DC_BALANCE_RESET (1 << 25)
+#define PORT_DFT2_G4X(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154)
+#define DC_BALANCE_RESET_VLV (1 << 31)
+#define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0))
+#define PIPE_C_SCRAMBLE_RESET REG_BIT(14) /* chv */
+#define PIPE_B_SCRAMBLE_RESET REG_BIT(1)
+#define PIPE_A_SCRAMBLE_RESET REG_BIT(0)
+
+/* Gen 3 SDVO bits: */
+#define SDVO_ENABLE (1 << 31)
+#define SDVO_PIPE_SEL_SHIFT 30
+#define SDVO_PIPE_SEL_MASK (1 << 30)
+#define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
+#define SDVO_STALL_SELECT (1 << 29)
+#define SDVO_INTERRUPT_ENABLE (1 << 26)
+/*
+ * 915G/GM SDVO pixel multiplier.
+ * Programmed value is multiplier - 1, up to 5x.
+ * \sa DPLL_MD_UDI_MULTIPLIER_MASK
+ */
+#define SDVO_PORT_MULTIPLY_MASK (7 << 23)
+#define SDVO_PORT_MULTIPLY_SHIFT 23
+#define SDVO_PHASE_SELECT_MASK (15 << 19)
+#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
+#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
+#define SDVOC_GANG_MODE (1 << 16) /* Port C only */
+#define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */
+#define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */
+#define SDVO_DETECTED (1 << 2)
+/* Bits to be preserved when writing */
+#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
+ SDVO_INTERRUPT_ENABLE)
+#define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
+
+/* Gen 4 SDVO/HDMI bits: */
+#define SDVO_COLOR_FORMAT_8bpc (0 << 26)
+#define SDVO_COLOR_FORMAT_MASK (7 << 26)
+#define SDVO_ENCODING_SDVO (0 << 10)
+#define SDVO_ENCODING_HDMI (2 << 10)
+#define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */
+#define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */
+#define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */
+#define HDMI_AUDIO_ENABLE (1 << 6) /* HDMI only */
+/* VSYNC/HSYNC bits new with 965, default is to be set */
+#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
+#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
+
+/* Gen 5 (IBX) SDVO/HDMI bits: */
+#define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */
+#define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */
+
+/* Gen 6 (CPT) SDVO/HDMI bits: */
+#define SDVO_PIPE_SEL_SHIFT_CPT 29
+#define SDVO_PIPE_SEL_MASK_CPT (3 << 29)
+#define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
+
+/* CHV SDVO/HDMI bits: */
+#define SDVO_PIPE_SEL_SHIFT_CHV 24
+#define SDVO_PIPE_SEL_MASK_CHV (3 << 24)
+#define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24)
+
+/* Video Data Island Packet control */
+#define VIDEO_DIP_DATA _MMIO(0x61178)
+/* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC
+ * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
+ * of the infoframe structure specified by CEA-861. */
+#define VIDEO_DIP_DATA_SIZE 32
+#define VIDEO_DIP_ASYNC_DATA_SIZE 36
+#define VIDEO_DIP_GMP_DATA_SIZE 36
+#define VIDEO_DIP_VSC_DATA_SIZE 36
+#define VIDEO_DIP_PPS_DATA_SIZE 132
+#define VIDEO_DIP_CTL _MMIO(0x61170)
+/* Pre HSW: */
+#define VIDEO_DIP_ENABLE (1 << 31)
+#define VIDEO_DIP_PORT(port) ((port) << 29)
+#define VIDEO_DIP_PORT_MASK (3 << 29)
+#define VIDEO_DIP_ENABLE_GCP (1 << 25) /* ilk+ */
+#define VIDEO_DIP_ENABLE_AVI (1 << 21)
+#define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
+#define VIDEO_DIP_ENABLE_GAMUT (4 << 21) /* ilk+ */
+#define VIDEO_DIP_ENABLE_SPD (8 << 21)
+#define VIDEO_DIP_SELECT_AVI (0 << 19)
+#define VIDEO_DIP_SELECT_VENDOR (1 << 19)
+#define VIDEO_DIP_SELECT_GAMUT (2 << 19)
+#define VIDEO_DIP_SELECT_SPD (3 << 19)
+#define VIDEO_DIP_SELECT_MASK (3 << 19)
+#define VIDEO_DIP_FREQ_ONCE (0 << 16)
+#define VIDEO_DIP_FREQ_VSYNC (1 << 16)
+#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
+#define VIDEO_DIP_FREQ_MASK (3 << 16)
+/* HSW and later: */
+#define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28)
+#define PSR_VSC_BIT_7_SET (1 << 27)
+#define VSC_SELECT_MASK (0x3 << 25)
+#define VSC_SELECT_SHIFT 25
+#define VSC_DIP_HW_HEA_DATA (0 << 25)
+#define VSC_DIP_HW_HEA_SW_DATA (1 << 25)
+#define VSC_DIP_HW_DATA_SW_HEA (2 << 25)
+#define VSC_DIP_SW_HEA_DATA (3 << 25)
+#define VDIP_ENABLE_PPS (1 << 24)
+#define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
+#define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
+#define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
+#define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
+#define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
+#define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
+/* ADL and later: */
+#define VIDEO_DIP_ENABLE_AS_ADL REG_BIT(23)
+
+#define PCH_GTC_CTL _MMIO(0xe7000)
+#define PCH_GTC_ENABLE (1 << 31)
+
+/* Display Port */
+#define DP_A _MMIO(0x64000) /* eDP */
+#define DP_B _MMIO(0x64100)
+#define DP_C _MMIO(0x64200)
+#define DP_D _MMIO(0x64300)
+#define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100)
+#define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200)
+#define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300)
+#define DP_PORT_EN REG_BIT(31)
+#define DP_PIPE_SEL_MASK REG_GENMASK(30, 30)
+#define DP_PIPE_SEL(pipe) REG_FIELD_PREP(DP_PIPE_SEL_MASK, (pipe))
+#define DP_PIPE_SEL_MASK_IVB REG_GENMASK(30, 29)
+#define DP_PIPE_SEL_IVB(pipe) REG_FIELD_PREP(DP_PIPE_SEL_MASK_IVB, (pipe))
+#define DP_PIPE_SEL_SHIFT_CHV 16
+#define DP_PIPE_SEL_MASK_CHV REG_GENMASK(17, 16)
+#define DP_PIPE_SEL_CHV(pipe) REG_FIELD_PREP(DP_PIPE_SEL_MASK_CHV, (pipe))
+#define DP_LINK_TRAIN_MASK REG_GENMASK(29, 28)
+#define DP_LINK_TRAIN_PAT_1 REG_FIELD_PREP(DP_LINK_TRAIN_MASK, 0)
+#define DP_LINK_TRAIN_PAT_2 REG_FIELD_PREP(DP_LINK_TRAIN_MASK, 1)
+#define DP_LINK_TRAIN_PAT_IDLE REG_FIELD_PREP(DP_LINK_TRAIN_MASK, 2)
+#define DP_LINK_TRAIN_OFF REG_FIELD_PREP(DP_LINK_TRAIN_MASK, 3)
+#define DP_LINK_TRAIN_MASK_CPT REG_GENMASK(10, 8)
+#define DP_LINK_TRAIN_PAT_1_CPT REG_FIELD_PREP(DP_LINK_TRAIN_MASK_CPT, 0)
+#define DP_LINK_TRAIN_PAT_2_CPT REG_FIELD_PREP(DP_LINK_TRAIN_MASK_CPT, 1)
+#define DP_LINK_TRAIN_PAT_IDLE_CPT REG_FIELD_PREP(DP_LINK_TRAIN_MASK_CPT, 2)
+#define DP_LINK_TRAIN_OFF_CPT REG_FIELD_PREP(DP_LINK_TRAIN_MASK_CPT, 3)
+#define DP_VOLTAGE_MASK REG_GENMASK(27, 25)
+#define DP_VOLTAGE_0_4 REG_FIELD_PREP(DP_VOLTAGE_MASK, 0)
+#define DP_VOLTAGE_0_6 REG_FIELD_PREP(DP_VOLTAGE_MASK, 1)
+#define DP_VOLTAGE_0_8 REG_FIELD_PREP(DP_VOLTAGE_MASK, 2)
+#define DP_VOLTAGE_1_2 REG_FIELD_PREP(DP_VOLTAGE_MASK, 3)
+#define DP_PRE_EMPHASIS_MASK REG_GENMASK(24, 22)
+#define DP_PRE_EMPHASIS_0 REG_FIELD_PREP(DP_PRE_EMPHASIS_MASK, 0)
+#define DP_PRE_EMPHASIS_3_5 REG_FIELD_PREP(DP_PRE_EMPHASIS_MASK, 1)
+#define DP_PRE_EMPHASIS_6 REG_FIELD_PREP(DP_PRE_EMPHASIS_MASK, 2)
+#define DP_PRE_EMPHASIS_9_5 REG_FIELD_PREP(DP_PRE_EMPHASIS_MASK, 3)
+#define DP_PORT_WIDTH_MASK REG_GENMASK(21, 19)
+#define DP_PORT_WIDTH(width) REG_FIELD_PREP(DP_PORT_WIDTH_MASK, (width) - 1)
+#define DP_ENHANCED_FRAMING REG_BIT(18)
+#define EDP_PLL_FREQ_MASK REG_GENMASK(17, 16)
+#define EDP_PLL_FREQ_270MHZ REG_FIELD_PREP(EDP_PLL_FREQ_MASK, 0)
+#define EDP_PLL_FREQ_162MHZ REG_FIELD_PREP(EDP_PLL_FREQ_MASK, 1)
+#define DP_PORT_REVERSAL REG_BIT(15)
+#define EDP_PLL_ENABLE REG_BIT(14)
+#define DP_CLOCK_OUTPUT_ENABLE REG_BIT(13)
+#define DP_SCRAMBLING_DISABLE REG_BIT(12)
+#define DP_SCRAMBLING_DISABLE_ILK REG_BIT(7)
+#define DP_COLOR_RANGE_16_235 REG_BIT(8)
+#define DP_AUDIO_OUTPUT_ENABLE REG_BIT(6)
+#define DP_SYNC_VS_HIGH REG_BIT(4)
+#define DP_SYNC_HS_HIGH REG_BIT(3)
+#define DP_DETECTED REG_BIT(2)
+
+/*
+ * Computing GMCH M and N values for the Display Port link
+ *
+ * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
+ *
+ * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
+ *
+ * The GMCH value is used internally
+ *
+ * bytes_per_pixel is the number of bytes coming out of the plane,
+ * which is after the LUTs, so we want the bytes for our color format.
+ * For our current usage, this is always 3, one byte for R, G and B.
+ */
+#define _PIPEA_DATA_M_G4X 0x70050
+#define _PIPEB_DATA_M_G4X 0x71050
+#define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
+/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
+#define TU_SIZE_MASK REG_GENMASK(30, 25)
+#define TU_SIZE(x) REG_FIELD_PREP(TU_SIZE_MASK, (x) - 1) /* default size 64 */
+#define DATA_LINK_M_N_MASK REG_GENMASK(23, 0)
+#define DATA_LINK_N_MAX (0x800000)
+
+#define _PIPEA_DATA_N_G4X 0x70054
+#define _PIPEB_DATA_N_G4X 0x71054
+#define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
+
+/*
+ * Computing Link M and N values for the Display Port link
+ *
+ * Link M / N = pixel_clock / ls_clk
+ *
+ * (the DP spec calls pixel_clock the 'strm_clk')
+ *
+ * The Link value is transmitted in the Main Stream
+ * Attributes and VB-ID.
+ */
+#define _PIPEA_LINK_M_G4X 0x70060
+#define _PIPEB_LINK_M_G4X 0x71060
+#define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
+
+#define _PIPEA_LINK_N_G4X 0x70064
+#define _PIPEB_LINK_N_G4X 0x71064
+#define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
+
+/* Pipe A */
+#define _PIPEADSL 0x70000
+#define PIPEDSL(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEADSL)
+#define PIPEDSL_CURR_FIELD REG_BIT(31) /* ctg+ */
+#define PIPEDSL_LINE_MASK REG_GENMASK(19, 0)
+
+#define _TRANSACONF 0x70008
+#define TRANSCONF(dev_priv, trans) _MMIO_PIPE2(dev_priv, (trans), _TRANSACONF)
+#define TRANSCONF_ENABLE REG_BIT(31)
+#define TRANSCONF_DOUBLE_WIDE REG_BIT(30) /* pre-i965 */
+#define TRANSCONF_STATE_ENABLE REG_BIT(30) /* i965+ */
+#define TRANSCONF_DSI_PLL_LOCKED REG_BIT(29) /* vlv & pipe A only */
+#define TRANSCONF_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* pre-hsw */
+#define TRANSCONF_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANSCONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */
+#define TRANSCONF_PIPE_LOCKED REG_BIT(25)
+#define TRANSCONF_FORCE_BORDER REG_BIT(25)
+#define TRANSCONF_GAMMA_MODE_MASK_I9XX REG_BIT(24) /* gmch */
+#define TRANSCONF_GAMMA_MODE_MASK_ILK REG_GENMASK(25, 24) /* ilk-ivb */
+#define TRANSCONF_GAMMA_MODE_8BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 0)
+#define TRANSCONF_GAMMA_MODE_10BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 1)
+#define TRANSCONF_GAMMA_MODE_12BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */
+#define TRANSCONF_GAMMA_MODE_SPLIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 3) /* ivb */
+#define TRANSCONF_GAMMA_MODE(x) REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, (x)) /* pass in GAMMA_MODE_MODE_* */
+#define TRANSCONF_INTERLACE_MASK REG_GENMASK(23, 21) /* gen3+ */
+#define TRANSCONF_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 0)
+#define TRANSCONF_INTERLACE_W_SYNC_SHIFT_PANEL REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 4) /* gen4 only */
+#define TRANSCONF_INTERLACE_W_SYNC_SHIFT REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 5) /* gen4 only */
+#define TRANSCONF_INTERLACE_W_FIELD_INDICATION REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 6)
+#define TRANSCONF_INTERLACE_FIELD_0_ONLY REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 7) /* gen3 only */
+/*
+ * ilk+: PF/D=progressive fetch/display, IF/D=interlaced fetch/display,
+ * DBL=power saving pixel doubling, PF-ID* requires panel fitter
+ */
+#define TRANSCONF_INTERLACE_MASK_ILK REG_GENMASK(23, 21) /* ilk+ */
+#define TRANSCONF_INTERLACE_MASK_HSW REG_GENMASK(22, 21) /* hsw+ */
+#define TRANSCONF_INTERLACE_PF_PD_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 0)
+#define TRANSCONF_INTERLACE_PF_ID_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 1)
+#define TRANSCONF_INTERLACE_IF_ID_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 3)
+#define TRANSCONF_INTERLACE_IF_ID_DBL_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 4) /* ilk/snb only */
+#define TRANSCONF_INTERLACE_PF_ID_DBL_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 5) /* ilk/snb only */
+#define TRANSCONF_REFRESH_RATE_ALT_ILK REG_BIT(20)
+#define TRANSCONF_MSA_TIMING_DELAY_MASK REG_GENMASK(19, 18) /* ilk/snb/ivb */
+#define TRANSCONF_MSA_TIMING_DELAY(x) REG_FIELD_PREP(TRANSCONF_MSA_TIMING_DELAY_MASK, (x))
+#define TRANSCONF_CXSR_DOWNCLOCK REG_BIT(16)
+#define TRANSCONF_WGC_ENABLE REG_BIT(15) /* vlv/chv only */
+#define TRANSCONF_REFRESH_RATE_ALT_VLV REG_BIT(14)
+#define TRANSCONF_COLOR_RANGE_SELECT REG_BIT(13)
+#define TRANSCONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12, 11) /* ilk-ivb */
+#define TRANSCONF_OUTPUT_COLORSPACE_RGB REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */
+#define TRANSCONF_OUTPUT_COLORSPACE_YUV601 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */
+#define TRANSCONF_OUTPUT_COLORSPACE_YUV709 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */
+#define TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW REG_BIT(11) /* hsw only */
+#define TRANSCONF_BPC_MASK REG_GENMASK(7, 5) /* ctg-ivb */
+#define TRANSCONF_BPC_8 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 0)
+#define TRANSCONF_BPC_10 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 1)
+#define TRANSCONF_BPC_6 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 2)
+#define TRANSCONF_BPC_12 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 3)
+#define TRANSCONF_DITHER_EN REG_BIT(4)
+#define TRANSCONF_DITHER_TYPE_MASK REG_GENMASK(3, 2)
+#define TRANSCONF_DITHER_TYPE_SP REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 0)
+#define TRANSCONF_DITHER_TYPE_ST1 REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 1)
+#define TRANSCONF_DITHER_TYPE_ST2 REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 2)
+#define TRANSCONF_DITHER_TYPE_TEMP REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 3)
+#define TRANSCONF_PIXEL_COUNT_SCALING_MASK REG_GENMASK(1, 0)
+#define TRANSCONF_PIXEL_COUNT_SCALING_X4 1
+
+#define _PIPE_ARB_CTL_A 0x70028 /* icl+ */
+#define PIPE_ARB_CTL(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPE_ARB_CTL_A)
+#define PIPE_ARB_USE_PROG_SLOTS REG_BIT(13)
+
+#define _PIPE_MISC_A 0x70030
+#define _PIPE_MISC_B 0x71030
+#define PIPE_MISC(pipe) _MMIO_PIPE(pipe, _PIPE_MISC_A, _PIPE_MISC_B)
+#define PIPE_MISC_YUV420_ENABLE REG_BIT(27) /* glk+ */
+#define PIPE_MISC_YUV420_MODE_FULL_BLEND REG_BIT(26) /* glk+ */
+#define PIPE_MISC_HDR_MODE_PRECISION REG_BIT(23) /* icl+ */
+#define PIPE_MISC_PSR_MASK_PRIMARY_FLIP REG_BIT(23) /* bdw */
+#define PIPE_MISC_PSR_MASK_SPRITE_ENABLE REG_BIT(22) /* bdw */
+#define PIPE_MISC_PSR_MASK_PIPE_REG_WRITE REG_BIT(21) /* skl+ */
+#define PIPE_MISC_PSR_MASK_CURSOR_MOVE REG_BIT(21) /* bdw */
+#define PIPE_MISC_PSR_MASK_VBLANK_VSYNC_INT REG_BIT(20)
+#define PIPE_MISC_OUTPUT_COLORSPACE_YUV REG_BIT(11)
+#define PIPE_MISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */
+/*
+ * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with
+ * valid values of: 6, 8, 10 BPC.
+ * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of:
+ * 6, 8, 10, 12 BPC.
+ */
+#define PIPE_MISC_BPC_MASK REG_GENMASK(7, 5)
+#define PIPE_MISC_BPC_8 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 0)
+#define PIPE_MISC_BPC_10 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 1)
+#define PIPE_MISC_BPC_6 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 2)
+#define PIPE_MISC_BPC_12_ADLP REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 4) /* adlp+ */
+#define PIPE_MISC_DITHER_ENABLE REG_BIT(4)
+#define PIPE_MISC_DITHER_TYPE_MASK REG_GENMASK(3, 2)
+#define PIPE_MISC_DITHER_TYPE_SP REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 0)
+#define PIPE_MISC_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 1)
+#define PIPE_MISC_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 2)
+#define PIPE_MISC_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 3)
+
+#define _PIPE_MISC2_A 0x7002C
+#define _PIPE_MISC2_B 0x7102C
+#define PIPE_MISC2(pipe) _MMIO_PIPE(pipe, _PIPE_MISC2_A, _PIPE_MISC2_B)
+#define PIPE_MISC2_BUBBLE_COUNTER_MASK REG_GENMASK(31, 24)
+#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 80)
+#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 20)
+#define PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK REG_GENMASK(2, 0) /* tgl+ */
+#define PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id) REG_FIELD_PREP(PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK, (plane_id))
+
+#define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
+#define DPINVGTT_EN_MASK_CHV REG_GENMASK(27, 16)
+#define DPINVGTT_EN_MASK_VLV REG_GENMASK(23, 16)
+#define SPRITEF_INVALID_GTT_INT_EN REG_BIT(27)
+#define SPRITEE_INVALID_GTT_INT_EN REG_BIT(26)
+#define PLANEC_INVALID_GTT_INT_EN REG_BIT(25)
+#define CURSORC_INVALID_GTT_INT_EN REG_BIT(24)
+#define CURSORB_INVALID_GTT_INT_EN REG_BIT(23)
+#define CURSORA_INVALID_GTT_INT_EN REG_BIT(22)
+#define SPRITED_INVALID_GTT_INT_EN REG_BIT(21)
+#define SPRITEC_INVALID_GTT_INT_EN REG_BIT(20)
+#define PLANEB_INVALID_GTT_INT_EN REG_BIT(19)
+#define SPRITEB_INVALID_GTT_INT_EN REG_BIT(18)
+#define SPRITEA_INVALID_GTT_INT_EN REG_BIT(17)
+#define PLANEA_INVALID_GTT_INT_EN REG_BIT(16)
+#define DPINVGTT_STATUS_MASK_CHV REG_GENMASK(11, 0)
+#define DPINVGTT_STATUS_MASK_VLV REG_GENMASK(7, 0)
+#define SPRITEF_INVALID_GTT_STATUS REG_BIT(11)
+#define SPRITEE_INVALID_GTT_STATUS REG_BIT(10)
+#define PLANEC_INVALID_GTT_STATUS REG_BIT(9)
+#define CURSORC_INVALID_GTT_STATUS REG_BIT(8)
+#define CURSORB_INVALID_GTT_STATUS REG_BIT(7)
+#define CURSORA_INVALID_GTT_STATUS REG_BIT(6)
+#define SPRITED_INVALID_GTT_STATUS REG_BIT(5)
+#define SPRITEC_INVALID_GTT_STATUS REG_BIT(4)
+#define PLANEB_INVALID_GTT_STATUS REG_BIT(3)
+#define SPRITEB_INVALID_GTT_STATUS REG_BIT(2)
+#define SPRITEA_INVALID_GTT_STATUS REG_BIT(1)
+#define PLANEA_INVALID_GTT_STATUS REG_BIT(0)
+
+#define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400)
+#define CBR_PND_DEADLINE_DISABLE (1 << 31)
+#define CBR_PWM_CLOCK_MUX_SELECT (1 << 30)
+
+#define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450)
+#define CBR_DPLLBMD_PIPE(pipe) (1 << (7 + (pipe) * 11)) /* pipes B and C */
+
+/*
+ * The two pipe frame counter registers are not synchronized, so
+ * reading a stable value is somewhat tricky. The following code
+ * should work:
+ *
+ * do {
+ * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
+ * PIPE_FRAME_HIGH_SHIFT;
+ * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
+ * PIPE_FRAME_LOW_SHIFT);
+ * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
+ * PIPE_FRAME_HIGH_SHIFT);
+ * } while (high1 != high2);
+ * frame = (high1 << 8) | low1;
+ */
+#define _PIPEAFRAMEHIGH 0x70040
+#define PIPEFRAME(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEHIGH)
+#define PIPE_FRAME_HIGH_MASK 0x0000ffff
+#define PIPE_FRAME_HIGH_SHIFT 0
+
+#define _PIPEAFRAMEPIXEL 0x70044
+#define PIPEFRAMEPIXEL(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEPIXEL)
+#define PIPE_FRAME_LOW_MASK 0xff000000
+#define PIPE_FRAME_LOW_SHIFT 24
+#define PIPE_PIXEL_MASK 0x00ffffff
+#define PIPE_PIXEL_SHIFT 0
+
+/* GM45+ just has to be different */
+#define _PIPEA_FRMCOUNT_G4X 0x70040
+#define PIPE_FRMCOUNT_G4X(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FRMCOUNT_G4X)
+
+#define _PIPEA_FLIPCOUNT_G4X 0x70044
+#define PIPE_FLIPCOUNT_G4X(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FLIPCOUNT_G4X)
+
+/* CHV pipe B blender */
+#define _CHV_BLEND_A 0x60a00
+#define CHV_BLEND(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _CHV_BLEND_A)
+#define CHV_BLEND_MASK REG_GENMASK(31, 30)
+#define CHV_BLEND_LEGACY REG_FIELD_PREP(CHV_BLEND_MASK, 0)
+#define CHV_BLEND_ANDROID REG_FIELD_PREP(CHV_BLEND_MASK, 1)
+#define CHV_BLEND_MPO REG_FIELD_PREP(CHV_BLEND_MASK, 2)
+
+#define _CHV_CANVAS_A 0x60a04
+#define CHV_CANVAS(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _CHV_CANVAS_A)
+#define CHV_CANVAS_RED_MASK REG_GENMASK(29, 20)
+#define CHV_CANVAS_GREEN_MASK REG_GENMASK(19, 10)
+#define CHV_CANVAS_BLUE_MASK REG_GENMASK(9, 0)
+
+/* Display/Sprite base address macros */
+#define DISP_BASEADDR_MASK (0xfffff000)
+#define I915_LO_DISPBASE(val) ((val) & ~DISP_BASEADDR_MASK)
+#define I915_HI_DISPBASE(val) ((val) & DISP_BASEADDR_MASK)
+
+/*
+ * VBIOS flags
+ * gen2:
+ * [00:06] alm,mgm
+ * [10:16] all
+ * [30:32] alm,mgm
+ * gen3+:
+ * [00:0f] all
+ * [10:1f] all
+ * [30:32] all
+ */
+#define SWF0(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4)
+#define SWF1(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4)
+#define SWF3(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
+#define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)
+
+/* VBIOS regs */
+#define VGACNTRL _MMIO(0x71400)
+# define VGA_DISP_DISABLE (1 << 31)
+# define VGA_2X_MODE (1 << 30)
+# define VGA_PIPE_B_SELECT (1 << 29)
+
+#define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400)
+
+#define CPU_VGACNTRL _MMIO(0x41000)
+
+#define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030)
+#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
+#define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */
+#define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */
+#define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */
+#define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */
+#define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */
+#define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0)
+#define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0)
+#define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0)
+#define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0)
+
+/* refresh rate hardware control */
+#define RR_HW_CTL _MMIO(0x45300)
+#define RR_HW_LOW_POWER_FRAMES_MASK 0xff
+#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
+
+#define _PIPEA_DATA_M1 0x60030
+#define _PIPEB_DATA_M1 0x61030
+#define PIPE_DATA_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M1)
+
+#define _PIPEA_DATA_N1 0x60034
+#define _PIPEB_DATA_N1 0x61034
+#define PIPE_DATA_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N1)
+
+#define _PIPEA_DATA_M2 0x60038
+#define _PIPEB_DATA_M2 0x61038
+#define PIPE_DATA_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M2)
+
+#define _PIPEA_DATA_N2 0x6003c
+#define _PIPEB_DATA_N2 0x6103c
+#define PIPE_DATA_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2)
+
+#define _PIPEA_LINK_M1 0x60040
+#define _PIPEB_LINK_M1 0x61040
+#define PIPE_LINK_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1)
+
+#define _PIPEA_LINK_N1 0x60044
+#define _PIPEB_LINK_N1 0x61044
+#define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1)
+
+#define _PIPEA_LINK_M2 0x60048
+#define _PIPEB_LINK_M2 0x61048
+#define PIPE_LINK_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M2)
+
+#define _PIPEA_LINK_N2 0x6004c
+#define _PIPEB_LINK_N2 0x6104c
+#define PIPE_LINK_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N2)
+
+/*
+ * Skylake scalers
+ */
+#define _ID(id, a, b) _PICK_EVEN(id, a, b)
+#define _PS_1A_CTRL 0x68180
+#define _PS_2A_CTRL 0x68280
+#define _PS_1B_CTRL 0x68980
+#define _PS_2B_CTRL 0x68A80
+#define _PS_1C_CTRL 0x69180
+#define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \
+ _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \
+ _ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
+#define PS_SCALER_EN REG_BIT(31)
+#define PS_SCALER_TYPE_MASK REG_BIT(30) /* icl+ */
+#define PS_SCALER_TYPE_NON_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 0)
+#define PS_SCALER_TYPE_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 1)
+#define SKL_PS_SCALER_MODE_MASK REG_GENMASK(29, 28) /* skl/bxt */
+#define SKL_PS_SCALER_MODE_DYN REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 0)
+#define SKL_PS_SCALER_MODE_HQ REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 1)
+#define SKL_PS_SCALER_MODE_NV12 REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 2)
+#define PS_SCALER_MODE_MASK REG_BIT(29) /* glk-tgl */
+#define PS_SCALER_MODE_NORMAL REG_FIELD_PREP(PS_SCALER_MODE_MASK, 0)
+#define PS_SCALER_MODE_PLANAR REG_FIELD_PREP(PS_SCALER_MODE_MASK, 1)
+#define PS_ADAPTIVE_FILTERING_EN REG_BIT(28) /* icl+ */
+#define PS_BINDING_MASK REG_GENMASK(27, 25)
+#define PS_BINDING_PIPE REG_FIELD_PREP(PS_BINDING_MASK, 0)
+#define PS_BINDING_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_MASK, (plane_id) + 1)
+#define PS_FILTER_MASK REG_GENMASK(24, 23)
+#define PS_FILTER_MEDIUM REG_FIELD_PREP(PS_FILTER_MASK, 0)
+#define PS_FILTER_PROGRAMMED REG_FIELD_PREP(PS_FILTER_MASK, 1)
+#define PS_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_FILTER_MASK, 2)
+#define PS_FILTER_BILINEAR REG_FIELD_PREP(PS_FILTER_MASK, 3)
+#define PS_ADAPTIVE_FILTER_MASK REG_BIT(22) /* icl+ */
+#define PS_ADAPTIVE_FILTER_MEDIUM REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 0)
+#define PS_ADAPTIVE_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 1)
+#define PS_PIPE_SCALER_LOC_MASK REG_BIT(21) /* icl+ */
+#define PS_PIPE_SCALER_LOC_AFTER_OUTPUT_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 0) /* non-linear */
+#define PS_PIPE_SCALER_LOC_AFTER_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 1) /* linear */
+#define PS_VERT3TAP REG_BIT(21) /* skl/bxt */
+#define PS_VERT_INT_INVERT_FIELD REG_BIT(20)
+#define PS_PROG_SCALE_FACTOR REG_BIT(19) /* tgl+ */
+#define PS_PWRUP_PROGRESS REG_BIT(17)
+#define PS_V_FILTER_BYPASS REG_BIT(8)
+#define PS_VADAPT_EN REG_BIT(7) /* skl/bxt */
+#define PS_VADAPT_MODE_MASK REG_GENMASK(6, 5) /* skl/bxt */
+#define PS_VADAPT_MODE_LEAST_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 0)
+#define PS_VADAPT_MODE_MOD_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 1)
+#define PS_VADAPT_MODE_MOST_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 3)
+#define PS_BINDING_Y_MASK REG_GENMASK(7, 5) /* icl-tgl */
+#define PS_BINDING_Y_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_Y_MASK, (plane_id) + 1)
+#define PS_Y_VERT_FILTER_SELECT_MASK REG_BIT(4) /* glk+ */
+#define PS_Y_VERT_FILTER_SELECT(set) REG_FIELD_PREP(PS_Y_VERT_FILTER_SELECT_MASK, (set))
+#define PS_Y_HORZ_FILTER_SELECT_MASK REG_BIT(3) /* glk+ */
+#define PS_Y_HORZ_FILTER_SELECT(set) REG_FIELD_PREP(PS_Y_HORZ_FILTER_SELECT_MASK, (set))
+#define PS_UV_VERT_FILTER_SELECT_MASK REG_BIT(2) /* glk+ */
+#define PS_UV_VERT_FILTER_SELECT(set) REG_FIELD_PREP(PS_UV_VERT_FILTER_SELECT_MASK, (set))
+#define PS_UV_HORZ_FILTER_SELECT_MASK REG_BIT(1) /* glk+ */
+#define PS_UV_HORZ_FILTER_SELECT(set) REG_FIELD_PREP(PS_UV_HORZ_FILTER_SELECT_MASK, (set))
+
+#define _PS_PWR_GATE_1A 0x68160
+#define _PS_PWR_GATE_2A 0x68260
+#define _PS_PWR_GATE_1B 0x68960
+#define _PS_PWR_GATE_2B 0x68A60
+#define _PS_PWR_GATE_1C 0x69160
+#define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \
+ _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \
+ _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))
+#define PS_PWR_GATE_DIS_OVERRIDE REG_BIT(31)
+#define PS_PWR_GATE_SETTLING_TIME_MASK REG_GENMASK(4, 3)
+#define PS_PWR_GATE_SETTLING_TIME_32 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 0)
+#define PS_PWR_GATE_SETTLING_TIME_64 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 1)
+#define PS_PWR_GATE_SETTLING_TIME_96 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 2)
+#define PS_PWR_GATE_SETTLING_TIME_128 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 3)
+#define PS_PWR_GATE_SLPEN_MASK REG_GENMASK(1, 0)
+#define PS_PWR_GATE_SLPEN_8 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 0)
+#define PS_PWR_GATE_SLPEN_16 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 1)
+#define PS_PWR_GATE_SLPEN_24 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 2)
+#define PS_PWR_GATE_SLPEN_32 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 3)
+
+#define _PS_WIN_POS_1A 0x68170
+#define _PS_WIN_POS_2A 0x68270
+#define _PS_WIN_POS_1B 0x68970
+#define _PS_WIN_POS_2B 0x68A70
+#define _PS_WIN_POS_1C 0x69170
+#define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \
+ _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \
+ _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))
+#define PS_WIN_XPOS_MASK REG_GENMASK(31, 16)
+#define PS_WIN_XPOS(x) REG_FIELD_PREP(PS_WIN_XPOS_MASK, (x))
+#define PS_WIN_YPOS_MASK REG_GENMASK(15, 0)
+#define PS_WIN_YPOS(y) REG_FIELD_PREP(PS_WIN_YPOS_MASK, (y))
+
+#define _PS_WIN_SZ_1A 0x68174
+#define _PS_WIN_SZ_2A 0x68274
+#define _PS_WIN_SZ_1B 0x68974
+#define _PS_WIN_SZ_2B 0x68A74
+#define _PS_WIN_SZ_1C 0x69174
+#define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \
+ _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \
+ _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))
+#define PS_WIN_XSIZE_MASK REG_GENMASK(31, 16)
+#define PS_WIN_XSIZE(w) REG_FIELD_PREP(PS_WIN_XSIZE_MASK, (w))
+#define PS_WIN_YSIZE_MASK REG_GENMASK(15, 0)
+#define PS_WIN_YSIZE(h) REG_FIELD_PREP(PS_WIN_YSIZE_MASK, (h))
+
+#define _PS_VSCALE_1A 0x68184
+#define _PS_VSCALE_2A 0x68284
+#define _PS_VSCALE_1B 0x68984
+#define _PS_VSCALE_2B 0x68A84
+#define _PS_VSCALE_1C 0x69184
+#define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \
+ _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \
+ _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))
+
+#define _PS_HSCALE_1A 0x68190
+#define _PS_HSCALE_2A 0x68290
+#define _PS_HSCALE_1B 0x68990
+#define _PS_HSCALE_2B 0x68A90
+#define _PS_HSCALE_1C 0x69190
+#define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \
+ _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \
+ _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))
+
+#define _PS_VPHASE_1A 0x68188
+#define _PS_VPHASE_2A 0x68288
+#define _PS_VPHASE_1B 0x68988
+#define _PS_VPHASE_2B 0x68A88
+#define _PS_VPHASE_1C 0x69188
+#define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \
+ _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \
+ _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))
+#define PS_Y_PHASE_MASK REG_GENMASK(31, 16)
+#define PS_Y_PHASE(x) REG_FIELD_PREP(PS_Y_PHASE_MASK, (x))
+#define PS_UV_RGB_PHASE_MASK REG_GENMASK(15, 0)
+#define PS_UV_RGB_PHASE(x) REG_FIELD_PREP(PS_UV_RGB_PHASE_MASK, (x))
+#define PS_PHASE_MASK (0x7fff << 1) /* u2.13 */
+#define PS_PHASE_TRIP (1 << 0)
+
+#define _PS_HPHASE_1A 0x68194
+#define _PS_HPHASE_2A 0x68294
+#define _PS_HPHASE_1B 0x68994
+#define _PS_HPHASE_2B 0x68A94
+#define _PS_HPHASE_1C 0x69194
+#define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \
+ _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \
+ _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))
+
+#define _PS_ECC_STAT_1A 0x681D0
+#define _PS_ECC_STAT_2A 0x682D0
+#define _PS_ECC_STAT_1B 0x689D0
+#define _PS_ECC_STAT_2B 0x68AD0
+#define _PS_ECC_STAT_1C 0x691D0
+#define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \
+ _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
+ _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
+
+#define _PS_COEF_SET0_INDEX_1A 0x68198
+#define _PS_COEF_SET0_INDEX_2A 0x68298
+#define _PS_COEF_SET0_INDEX_1B 0x68998
+#define _PS_COEF_SET0_INDEX_2B 0x68A98
+#define GLK_PS_COEF_INDEX_SET(pipe, id, set) _MMIO_PIPE(pipe, \
+ _ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A) + (set) * 8, \
+ _ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B) + (set) * 8)
+#define PS_COEF_INDEX_AUTO_INC REG_BIT(10)
+
+#define _PS_COEF_SET0_DATA_1A 0x6819C
+#define _PS_COEF_SET0_DATA_2A 0x6829C
+#define _PS_COEF_SET0_DATA_1B 0x6899C
+#define _PS_COEF_SET0_DATA_2B 0x68A9C
+#define GLK_PS_COEF_DATA_SET(pipe, id, set) _MMIO_PIPE(pipe, \
+ _ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + (set) * 8, \
+ _ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + (set) * 8)
+
+/* More Ivybridge lolz */
+#define DE_ERR_INT_IVB (1 << 30)
+#define DE_GSE_IVB (1 << 29)
+#define DE_PCH_EVENT_IVB (1 << 28)
+#define DE_DP_A_HOTPLUG_IVB (1 << 27)
+#define DE_AUX_CHANNEL_A_IVB (1 << 26)
+#define DE_EDP_PSR_INT_HSW (1 << 19)
+#define DE_SPRITEC_FLIP_DONE_IVB (1 << 14)
+#define DE_PLANEC_FLIP_DONE_IVB (1 << 13)
+#define DE_PIPEC_VBLANK_IVB (1 << 10)
+#define DE_SPRITEB_FLIP_DONE_IVB (1 << 9)
+#define DE_PLANEB_FLIP_DONE_IVB (1 << 8)
+#define DE_PIPEB_VBLANK_IVB (1 << 5)
+#define DE_SPRITEA_FLIP_DONE_IVB (1 << 4)
+#define DE_PLANEA_FLIP_DONE_IVB (1 << 3)
+#define DE_PLANE_FLIP_DONE_IVB(plane) (1 << (3 + 5 * (plane)))
+#define DE_PIPEA_VBLANK_IVB (1 << 0)
+#define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5))
+
+#define XELPD_DISPLAY_ERR_FATAL_MASK _MMIO(0x4421c)
+
+#define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))
+#define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))
+#define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))
+#define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))
+#define GEN8_PIPE_FIFO_UNDERRUN REG_BIT(31)
+#define GEN8_PIPE_CDCLK_CRC_ERROR REG_BIT(29)
+#define GEN8_PIPE_CDCLK_CRC_DONE REG_BIT(28)
+#define GEN12_PIPEDMC_INTERRUPT REG_BIT(26) /* tgl+ */
+#define GEN12_PIPEDMC_FAULT REG_BIT(25) /* tgl+ */
+#define MTL_PIPEDMC_ATS_FAULT REG_BIT(24) /* mtl+ */
+#define GEN11_PIPE_PLANE7_FAULT REG_BIT(22) /* icl/tgl */
+#define GEN11_PIPE_PLANE6_FAULT REG_BIT(21) /* icl/tgl */
+#define GEN11_PIPE_PLANE5_FAULT REG_BIT(20) /* icl+ */
+#define GEN12_PIPE_VBLANK_UNMOD REG_BIT(19) /* tgl+ */
+#define MTL_PLANE_ATS_FAULT REG_BIT(18) /* mtl+ */
+#define GEN11_PIPE_PLANE7_FLIP_DONE REG_BIT(18) /* icl/tgl */
+#define GEN11_PIPE_PLANE6_FLIP_DONE REG_BIT(17) /* icl/tgl */
+#define GEN11_PIPE_PLANE5_FLIP_DONE REG_BIT(16) /* icl+ */
+#define GEN12_DSB_2_INT REG_BIT(15) /* tgl+ */
+#define GEN12_DSB_1_INT REG_BIT(14) /* tgl+ */
+#define GEN12_DSB_0_INT REG_BIT(13) /* tgl+ */
+#define GEN12_DSB_INT(dsb_id) REG_BIT(13 + (dsb_id))
+#define GEN9_PIPE_CURSOR_FAULT REG_BIT(11) /* skl+ */
+#define GEN9_PIPE_PLANE4_FAULT REG_BIT(10) /* skl+ */
+#define GEN8_PIPE_CURSOR_FAULT REG_BIT(10) /* bdw */
+#define GEN9_PIPE_PLANE3_FAULT REG_BIT(9) /* skl+ */
+#define GEN8_PIPE_SPRITE_FAULT REG_BIT(9) /* bdw */
+#define GEN9_PIPE_PLANE2_FAULT REG_BIT(8) /* skl+ */
+#define GEN8_PIPE_PRIMARY_FAULT REG_BIT(8) /* bdw */
+#define GEN9_PIPE_PLANE1_FAULT REG_BIT(7) /* skl+ */
+#define GEN9_PIPE_PLANE4_FLIP_DONE REG_BIT(6) /* skl+ */
+#define GEN9_PIPE_PLANE3_FLIP_DONE REG_BIT(5) /* skl+ */
+#define GEN8_PIPE_SPRITE_FLIP_DONE REG_BIT(5) /* bdw */
+#define GEN9_PIPE_PLANE2_FLIP_DONE REG_BIT(4) /* skl+ */
+#define GEN8_PIPE_PRIMARY_FLIP_DONE REG_BIT(4) /* bdw */
+#define GEN9_PIPE_PLANE1_FLIP_DONE REG_BIT(3) /* skl+ */
+#define GEN9_PIPE_PLANE_FLIP_DONE(plane_id) \
+ REG_BIT(((plane_id) >= PLANE_5 ? 16 - PLANE_5 : 3 - PLANE_1) + (plane_id)) /* skl+ */
+#define GEN8_PIPE_SCAN_LINE_EVENT REG_BIT(2)
+#define GEN8_PIPE_VSYNC REG_BIT(1)
+#define GEN8_PIPE_VBLANK REG_BIT(0)
+
+#define GEN8_DE_PIPE_IRQ_REGS(pipe) I915_IRQ_REGS(GEN8_DE_PIPE_IMR(pipe), \
+ GEN8_DE_PIPE_IER(pipe), \
+ GEN8_DE_PIPE_IIR(pipe))
+
+#define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A)
+#define _HPD_PIN_TC(hpd_pin) ((hpd_pin) - HPD_PORT_TC1)
+
+#define GEN8_DE_PORT_ISR _MMIO(0x44440)
+#define GEN8_DE_PORT_IMR _MMIO(0x44444)
+#define GEN8_DE_PORT_IIR _MMIO(0x44448)
+#define GEN8_DE_PORT_IER _MMIO(0x4444c)
+#define DSI1_NON_TE (1 << 31)
+#define DSI0_NON_TE (1 << 30)
+#define ICL_AUX_CHANNEL_E (1 << 29)
+#define ICL_AUX_CHANNEL_F (1 << 28)
+#define GEN9_AUX_CHANNEL_D (1 << 27)
+#define GEN9_AUX_CHANNEL_C (1 << 26)
+#define GEN9_AUX_CHANNEL_B (1 << 25)
+#define DSI1_TE (1 << 24)
+#define DSI0_TE (1 << 23)
+#define GEN8_DE_PORT_HOTPLUG(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))
+#define BXT_DE_PORT_HOTPLUG_MASK (GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \
+ GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \
+ GEN8_DE_PORT_HOTPLUG(HPD_PORT_C))
+#define BDW_DE_PORT_HOTPLUG_MASK GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)
+#define BXT_DE_PORT_GMBUS (1 << 1)
+#define GEN8_AUX_CHANNEL_A (1 << 0)
+#define TGL_DE_PORT_AUX_USBC6 REG_BIT(13)
+#define XELPD_DE_PORT_AUX_DDIE REG_BIT(13)
+#define TGL_DE_PORT_AUX_USBC5 REG_BIT(12)
+#define XELPD_DE_PORT_AUX_DDID REG_BIT(12)
+#define TGL_DE_PORT_AUX_USBC4 REG_BIT(11)
+#define TGL_DE_PORT_AUX_USBC3 REG_BIT(10)
+#define TGL_DE_PORT_AUX_USBC2 REG_BIT(9)
+#define TGL_DE_PORT_AUX_USBC1 REG_BIT(8)
+#define TGL_DE_PORT_AUX_DDIC REG_BIT(2)
+#define TGL_DE_PORT_AUX_DDIB REG_BIT(1)
+#define TGL_DE_PORT_AUX_DDIA REG_BIT(0)
+
+#define GEN8_DE_PORT_IRQ_REGS I915_IRQ_REGS(GEN8_DE_PORT_IMR, \
+ GEN8_DE_PORT_IER, \
+ GEN8_DE_PORT_IIR)
+
+#define GEN8_DE_MISC_IRQ_REGS I915_IRQ_REGS(GEN8_DE_MISC_IMR, \
+ GEN8_DE_MISC_IER, \
+ GEN8_DE_MISC_IIR)
+
+#define GEN11_DISPLAY_INT_CTL _MMIO(0x44200)
+#define GEN11_DISPLAY_IRQ_ENABLE (1 << 31)
+#define GEN11_AUDIO_CODEC_IRQ (1 << 24)
+#define GEN11_DE_PCH_IRQ (1 << 23)
+#define GEN11_DE_MISC_IRQ (1 << 22)
+#define GEN11_DE_HPD_IRQ (1 << 21)
+#define GEN11_DE_PORT_IRQ (1 << 20)
+#define GEN11_DE_PIPE_C (1 << 18)
+#define GEN11_DE_PIPE_B (1 << 17)
+#define GEN11_DE_PIPE_A (1 << 16)
+
+#define GEN11_DE_HPD_ISR _MMIO(0x44470)
+#define GEN11_DE_HPD_IMR _MMIO(0x44474)
+#define GEN11_DE_HPD_IIR _MMIO(0x44478)
+#define GEN11_DE_HPD_IER _MMIO(0x4447c)
+#define GEN11_TC_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin))
+#define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(HPD_PORT_TC6) | \
+ GEN11_TC_HOTPLUG(HPD_PORT_TC5) | \
+ GEN11_TC_HOTPLUG(HPD_PORT_TC4) | \
+ GEN11_TC_HOTPLUG(HPD_PORT_TC3) | \
+ GEN11_TC_HOTPLUG(HPD_PORT_TC2) | \
+ GEN11_TC_HOTPLUG(HPD_PORT_TC1))
+#define GEN11_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin))
+#define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(HPD_PORT_TC6) | \
+ GEN11_TBT_HOTPLUG(HPD_PORT_TC5) | \
+ GEN11_TBT_HOTPLUG(HPD_PORT_TC4) | \
+ GEN11_TBT_HOTPLUG(HPD_PORT_TC3) | \
+ GEN11_TBT_HOTPLUG(HPD_PORT_TC2) | \
+ GEN11_TBT_HOTPLUG(HPD_PORT_TC1))
+
+#define GEN11_DE_HPD_IRQ_REGS I915_IRQ_REGS(GEN11_DE_HPD_IMR, \
+ GEN11_DE_HPD_IER, \
+ GEN11_DE_HPD_IIR)
+
+#define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030)
+#define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038)
+#define GEN11_HOTPLUG_CTL_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4))
+#define GEN11_HOTPLUG_CTL_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4))
+#define GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4))
+#define GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin) (0 << (_HPD_PIN_TC(hpd_pin) * 4))
+
+#define PICAINTERRUPT_ISR _MMIO(0x16FE50)
+#define PICAINTERRUPT_IMR _MMIO(0x16FE54)
+#define PICAINTERRUPT_IIR _MMIO(0x16FE58)
+#define PICAINTERRUPT_IER _MMIO(0x16FE5C)
+#define XELPDP_DP_ALT_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin))
+#define XELPDP_DP_ALT_HOTPLUG_MASK REG_GENMASK(19, 16)
+#define XELPDP_AUX_TC(hpd_pin) REG_BIT(8 + _HPD_PIN_TC(hpd_pin))
+#define XELPDP_AUX_TC_MASK REG_GENMASK(11, 8)
+#define XE2LPD_AUX_DDI(hpd_pin) REG_BIT(6 + _HPD_PIN_DDI(hpd_pin))
+#define XE2LPD_AUX_DDI_MASK REG_GENMASK(7, 6)
+#define XELPDP_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin))
+#define XELPDP_TBT_HOTPLUG_MASK REG_GENMASK(3, 0)
+
+#define PICAINTERRUPT_IRQ_REGS I915_IRQ_REGS(PICAINTERRUPT_IMR, \
+ PICAINTERRUPT_IER, \
+ PICAINTERRUPT_IIR)
+
+#define XELPDP_PORT_HOTPLUG_CTL(hpd_pin) _MMIO(0x16F270 + (_HPD_PIN_TC(hpd_pin) * 0x200))
+#define XELPDP_TBT_HOTPLUG_ENABLE REG_BIT(6)
+#define XELPDP_TBT_HPD_LONG_DETECT REG_BIT(5)
+#define XELPDP_TBT_HPD_SHORT_DETECT REG_BIT(4)
+#define XELPDP_DP_ALT_HOTPLUG_ENABLE REG_BIT(2)
+#define XELPDP_DP_ALT_HPD_LONG_DETECT REG_BIT(1)
+#define XELPDP_DP_ALT_HPD_SHORT_DETECT REG_BIT(0)
+
+#define XELPDP_INITIATE_PMDEMAND_REQUEST(dword) _MMIO(0x45230 + 4 * (dword))
+#define XELPDP_PMDEMAND_QCLK_GV_BW_MASK REG_GENMASK(31, 16)
+#define XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK REG_GENMASK(14, 12)
+#define XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK REG_GENMASK(11, 8)
+#define XE3_PMDEMAND_PIPES_MASK REG_GENMASK(7, 4)
+#define XELPDP_PMDEMAND_PIPES_MASK REG_GENMASK(7, 6)
+#define XELPDP_PMDEMAND_DBUFS_MASK REG_GENMASK(5, 4)
+#define XELPDP_PMDEMAND_PHYS_MASK REG_GENMASK(2, 0)
+
+#define XELPDP_PMDEMAND_REQ_ENABLE REG_BIT(31)
+#define XELPDP_PMDEMAND_CDCLK_FREQ_MASK REG_GENMASK(30, 20)
+#define XELPDP_PMDEMAND_DDICLK_FREQ_MASK REG_GENMASK(18, 8)
+#define XELPDP_PMDEMAND_SCALERS_MASK REG_GENMASK(6, 4)
+#define XELPDP_PMDEMAND_PLLS_MASK REG_GENMASK(2, 0)
+
+#define GEN12_DCPR_STATUS_1 _MMIO(0x46440)
+#define XELPDP_PMDEMAND_INFLIGHT_STATUS REG_BIT(26)
+
+#define FUSE_STRAP _MMIO(0x42014)
+#define ILK_INTERNAL_GRAPHICS_DISABLE REG_BIT(31)
+#define ILK_INTERNAL_DISPLAY_DISABLE REG_BIT(30)
+#define ILK_DISPLAY_DEBUG_DISABLE REG_BIT(29)
+#define IVB_PIPE_C_DISABLE REG_BIT(28)
+#define ILK_HDCP_DISABLE REG_BIT(25)
+#define ILK_eDP_A_DISABLE REG_BIT(24)
+#define HSW_CDCLK_LIMIT REG_BIT(24)
+#define ILK_DESKTOP REG_BIT(23)
+#define HSW_CPU_SSC_ENABLE REG_BIT(21)
+
+#define FUSE_STRAP3 _MMIO(0x42020)
+#define HSW_REF_CLK_SELECT REG_BIT(1)
+
+#define CHICKEN_MISC_2 _MMIO(0x42084)
+#define CHICKEN_MISC_DISABLE_DPT REG_BIT(30) /* adl,dg2 */
+#define BMG_DARB_HALF_BLK_END_BURST REG_BIT(27)
+#define KBL_ARB_FILL_SPARE_14 REG_BIT(14)
+#define KBL_ARB_FILL_SPARE_13 REG_BIT(13)
+#define GLK_CL2_PWR_DOWN REG_BIT(12)
+#define GLK_CL1_PWR_DOWN REG_BIT(11)
+#define GLK_CL0_PWR_DOWN REG_BIT(10)
+
+#define CHICKEN_MISC_3 _MMIO(0x42088)
+#define DP_MST_DPT_DPTP_ALIGN_WA(trans) REG_BIT(9 + (trans) - TRANSCODER_A)
+#define DP_MST_SHORT_HBLANK_WA(trans) REG_BIT(5 + (trans) - TRANSCODER_A)
+#define DP_MST_FEC_BS_JITTER_WA(trans) REG_BIT(0 + (trans) - TRANSCODER_A)
+
+#define CHICKEN_MISC_4 _MMIO(0x4208c)
+#define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13)
+#define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0)
+#define CHICKEN_FBC_STRIDE(x) REG_FIELD_PREP(CHICKEN_FBC_STRIDE_MASK, (x))
+
+#define _CHICKEN_TRANS_A 0x420c0
+#define _CHICKEN_TRANS_B 0x420c4
+#define _CHICKEN_TRANS_C 0x420c8
+#define _CHICKEN_TRANS_EDP 0x420cc
+#define _CHICKEN_TRANS_D 0x420d8
+#define _CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \
+ [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \
+ [TRANSCODER_A] = _CHICKEN_TRANS_A, \
+ [TRANSCODER_B] = _CHICKEN_TRANS_B, \
+ [TRANSCODER_C] = _CHICKEN_TRANS_C, \
+ [TRANSCODER_D] = _CHICKEN_TRANS_D))
+#define _MTL_CHICKEN_TRANS_A 0x604e0
+#define _MTL_CHICKEN_TRANS_B 0x614e0
+#define _MTL_CHICKEN_TRANS(trans) _MMIO_TRANS((trans), \
+ _MTL_CHICKEN_TRANS_A, \
+ _MTL_CHICKEN_TRANS_B)
+#define CHICKEN_TRANS(display, trans) (DISPLAY_VER(display) >= 14 ? _MTL_CHICKEN_TRANS(trans) : _CHICKEN_TRANS(trans))
+#define PIPE_VBLANK_WITH_DELAY REG_BIT(31) /* tgl+ */
+#define SKL_UNMASK_VBL_TO_PIPE_IN_SRD REG_BIT(30) /* skl+ */
+#define HSW_FRAME_START_DELAY_MASK REG_GENMASK(28, 27)
+#define HSW_FRAME_START_DELAY(x) REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x)
+#define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */
+#define FECSTALL_DIS_DPTSTREAM_DPTTG REG_BIT(23)
+#define DDI_TRAINING_OVERRIDE_ENABLE REG_BIT(19)
+#define ADLP_1_BASED_X_GRANULARITY REG_BIT(18)
+#define DDI_TRAINING_OVERRIDE_VALUE REG_BIT(18)
+#define DDIE_TRAINING_OVERRIDE_ENABLE REG_BIT(17) /* CHICKEN_TRANS_A only */
+#define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /* CHICKEN_TRANS_A only */
+#define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15)
+#define DP_FEC_BS_JITTER_WA REG_BIT(15)
+#define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12)
+#define DP_DSC_INSERT_SF_AT_EOL_WA REG_BIT(4)
+#define HDCP_LINE_REKEY_DISABLE REG_BIT(0)
+
+#define DISP_ARB_CTL2 _MMIO(0x45004)
+#define DISP_DATA_PARTITION_5_6 REG_BIT(6)
+#define DISP_IPC_ENABLE REG_BIT(3)
+
+#define GEN7_MSG_CTL _MMIO(0x45010)
+#define WAIT_FOR_PCH_RESET_ACK (1 << 1)
+#define WAIT_FOR_PCH_FLR_ACK (1 << 0)
+
+#define _BW_BUDDY0_CTL 0x45130
+#define _BW_BUDDY1_CTL 0x45140
+#define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \
+ _BW_BUDDY0_CTL, \
+ _BW_BUDDY1_CTL))
+#define BW_BUDDY_DISABLE REG_BIT(31)
+#define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16)
+#define BW_BUDDY_TLB_REQ_TIMER(x) REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, x)
+
+#define _BW_BUDDY0_PAGE_MASK 0x45134
+#define _BW_BUDDY1_PAGE_MASK 0x45144
+#define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \
+ _BW_BUDDY0_PAGE_MASK, \
+ _BW_BUDDY1_PAGE_MASK))
+
+#define HSW_NDE_RSTWRN_OPT _MMIO(0x46408)
+#define MTL_RESET_PICA_HANDSHAKE_EN REG_BIT(6)
+#define RESET_PCH_HANDSHAKE_ENABLE REG_BIT(4)
+
+#define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434)
+#define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27)
+#define DCPR_MASK_LPMODE REG_BIT(26)
+#define DCPR_SEND_RESP_IMM REG_BIT(25)
+#define DCPR_CLEAR_MEMSTAT_DIS REG_BIT(24)
+
+#define XELPD_CHICKEN_DCPR_3 _MMIO(0x46438)
+#define DMD_RSP_TIMEOUT_DISABLE REG_BIT(19)
+
+#define SKL_DFSM _MMIO(0x51000)
+#define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27)
+#define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25)
+#define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
+#define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
+#define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
+#define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
+#define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
+#define ICL_DFSM_DMC_DISABLE (1 << 23)
+#define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
+#define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
+#define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
+#define TGL_DFSM_PIPE_D_DISABLE (1 << 22)
+#define GLK_DFSM_DISPLAY_DSC_DISABLE (1 << 7)
+#define XE2LPD_DFSM_DBUF_OVERLAP_DISABLE (1 << 3)
+
+#define XE2LPD_DE_CAP _MMIO(0x41100)
+#define XE2LPD_DE_CAP_3DLUT_MASK REG_GENMASK(31, 30)
+#define XE2LPD_DE_CAP_DSC_MASK REG_GENMASK(29, 28)
+#define XE2LPD_DE_CAP_DSC_REMOVED 1
+#define XE2LPD_DE_CAP_SCALER_MASK REG_GENMASK(27, 26)
+#define XE2LPD_DE_CAP_SCALER_SINGLE 1
+
+#define SKL_DSSM _MMIO(0x51004)
+#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29)
+#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29)
+#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29)
+#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29)
+
+/*GEN11 chicken */
+#define _PIPEA_CHICKEN 0x70038
+#define _PIPEB_CHICKEN 0x71038
+#define _PIPEC_CHICKEN 0x72038
+#define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\
+ _PIPEB_CHICKEN)
+#define UNDERRUN_RECOVERY_DISABLE_ADLP REG_BIT(30)
+#define UNDERRUN_RECOVERY_ENABLE_DG2 REG_BIT(30)
+#define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU REG_BIT(15)
+#define DG2_RENDER_CCSTAG_4_3_EN REG_BIT(12)
+#define PER_PIXEL_ALPHA_BYPASS_EN REG_BIT(7)
+
+#define PCH_DISPLAY_BASE 0xc0000u
+
+/* south display engine interrupt: IBX */
+#define SDE_AUDIO_POWER_D (1 << 27)
+#define SDE_AUDIO_POWER_C (1 << 26)
+#define SDE_AUDIO_POWER_B (1 << 25)
+#define SDE_AUDIO_POWER_SHIFT (25)
+#define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
+#define SDE_GMBUS (1 << 24)
+#define SDE_AUDIO_HDCP_TRANSB (1 << 23)
+#define SDE_AUDIO_HDCP_TRANSA (1 << 22)
+#define SDE_AUDIO_HDCP_MASK (3 << 22)
+#define SDE_AUDIO_TRANSB (1 << 21)
+#define SDE_AUDIO_TRANSA (1 << 20)
+#define SDE_AUDIO_TRANS_MASK (3 << 20)
+#define SDE_POISON (1 << 19)
+/* 18 reserved */
+#define SDE_FDI_RXB (1 << 17)
+#define SDE_FDI_RXA (1 << 16)
+#define SDE_FDI_MASK (3 << 16)
+#define SDE_AUXD (1 << 15)
+#define SDE_AUXC (1 << 14)
+#define SDE_AUXB (1 << 13)
+#define SDE_AUX_MASK (7 << 13)
+/* 12 reserved */
+#define SDE_CRT_HOTPLUG (1 << 11)
+#define SDE_PORTD_HOTPLUG (1 << 10)
+#define SDE_PORTC_HOTPLUG (1 << 9)
+#define SDE_PORTB_HOTPLUG (1 << 8)
+#define SDE_SDVOB_HOTPLUG (1 << 6)
+#define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \
+ SDE_SDVOB_HOTPLUG | \
+ SDE_PORTB_HOTPLUG | \
+ SDE_PORTC_HOTPLUG | \
+ SDE_PORTD_HOTPLUG)
+#define SDE_TRANSB_CRC_DONE (1 << 5)
+#define SDE_TRANSB_CRC_ERR (1 << 4)
+#define SDE_TRANSB_FIFO_UNDER (1 << 3)
+#define SDE_TRANSA_CRC_DONE (1 << 2)
+#define SDE_TRANSA_CRC_ERR (1 << 1)
+#define SDE_TRANSA_FIFO_UNDER (1 << 0)
+#define SDE_TRANS_MASK (0x3f)
+
+/* south display engine interrupt: CPT - CNP */
+#define SDE_AUDIO_POWER_D_CPT (1 << 31)
+#define SDE_AUDIO_POWER_C_CPT (1 << 30)
+#define SDE_AUDIO_POWER_B_CPT (1 << 29)
+#define SDE_AUDIO_POWER_SHIFT_CPT 29
+#define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
+#define SDE_AUXD_CPT (1 << 27)
+#define SDE_AUXC_CPT (1 << 26)
+#define SDE_AUXB_CPT (1 << 25)
+#define SDE_AUX_MASK_CPT (7 << 25)
+#define SDE_PORTE_HOTPLUG_SPT (1 << 25)
+#define SDE_PORTA_HOTPLUG_SPT (1 << 24)
+#define SDE_PORTD_HOTPLUG_CPT (1 << 23)
+#define SDE_PORTC_HOTPLUG_CPT (1 << 22)
+#define SDE_PORTB_HOTPLUG_CPT (1 << 21)
+#define SDE_CRT_HOTPLUG_CPT (1 << 19)
+#define SDE_SDVOB_HOTPLUG_CPT (1 << 18)
+#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
+ SDE_SDVOB_HOTPLUG_CPT | \
+ SDE_PORTD_HOTPLUG_CPT | \
+ SDE_PORTC_HOTPLUG_CPT | \
+ SDE_PORTB_HOTPLUG_CPT)
+#define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \
+ SDE_PORTD_HOTPLUG_CPT | \
+ SDE_PORTC_HOTPLUG_CPT | \
+ SDE_PORTB_HOTPLUG_CPT | \
+ SDE_PORTA_HOTPLUG_SPT)
+#define SDE_GMBUS_CPT (1 << 17)
+#define SDE_ERROR_CPT (1 << 16)
+#define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
+#define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
+#define SDE_FDI_RXC_CPT (1 << 8)
+#define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
+#define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
+#define SDE_FDI_RXB_CPT (1 << 4)
+#define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
+#define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
+#define SDE_FDI_RXA_CPT (1 << 0)
+#define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
+ SDE_AUDIO_CP_REQ_B_CPT | \
+ SDE_AUDIO_CP_REQ_A_CPT)
+#define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
+ SDE_AUDIO_CP_CHG_B_CPT | \
+ SDE_AUDIO_CP_CHG_A_CPT)
+#define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
+ SDE_FDI_RXB_CPT | \
+ SDE_FDI_RXA_CPT)
+
+/* south display engine interrupt: ICP/TGP/MTP */
+#define SDE_PICAINTERRUPT REG_BIT(31)
+#define SDE_GMBUS_ICP (1 << 23)
+#define SDE_TC_HOTPLUG_ICP(hpd_pin) REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
+#define SDE_TC_HOTPLUG_DG2(hpd_pin) REG_BIT(25 + _HPD_PIN_TC(hpd_pin)) /* sigh */
+#define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
+#define SDE_DDI_HOTPLUG_MASK_ICP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \
+ SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
+ SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
+ SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
+#define SDE_TC_HOTPLUG_MASK_ICP (SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \
+ SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \
+ SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \
+ SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \
+ SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \
+ SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))
+
+/* digital port hotplug */
+#define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */
+#define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */
+#define BXT_DDIA_HPD_INVERT (1 << 27)
+#define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */
+#define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */
+#define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */
+#define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */
+#define PORTD_HOTPLUG_ENABLE (1 << 20)
+#define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */
+#define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */
+#define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */
+#define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */
+#define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */
+#define PORTD_HOTPLUG_STATUS_MASK (3 << 16)
+#define PORTD_HOTPLUG_NO_DETECT (0 << 16)
+#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
+#define PORTD_HOTPLUG_LONG_DETECT (2 << 16)
+#define PORTC_HOTPLUG_ENABLE (1 << 12)
+#define BXT_DDIC_HPD_INVERT (1 << 11)
+#define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */
+#define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */
+#define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */
+#define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */
+#define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */
+#define PORTC_HOTPLUG_STATUS_MASK (3 << 8)
+#define PORTC_HOTPLUG_NO_DETECT (0 << 8)
+#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
+#define PORTC_HOTPLUG_LONG_DETECT (2 << 8)
+#define PORTB_HOTPLUG_ENABLE (1 << 4)
+#define BXT_DDIB_HPD_INVERT (1 << 3)
+#define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */
+#define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */
+#define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */
+#define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */
+#define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */
+#define PORTB_HOTPLUG_STATUS_MASK (3 << 0)
+#define PORTB_HOTPLUG_NO_DETECT (0 << 0)
+#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
+#define PORTB_HOTPLUG_LONG_DETECT (2 << 0)
+#define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \
+ BXT_DDIB_HPD_INVERT | \
+ BXT_DDIC_HPD_INVERT)
+
+#define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */
+#define PORTE_HOTPLUG_ENABLE (1 << 4)
+#define PORTE_HOTPLUG_STATUS_MASK (3 << 0)
+#define PORTE_HOTPLUG_NO_DETECT (0 << 0)
+#define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)
+#define PORTE_HOTPLUG_LONG_DETECT (2 << 0)
+
+/* This register is a reuse of PCH_PORT_HOTPLUG register. The
+ * functionality covered in PCH_PORT_HOTPLUG is split into
+ * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
+ */
+#define SHOTPLUG_CTL_DDI _MMIO(0xc4030)
+#define SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin) (0x8 << (_HPD_PIN_DDI(hpd_pin) * 4))
+#define SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(hpd_pin) (0x4 << (_HPD_PIN_DDI(hpd_pin) * 4))
+#define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
+#define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin) (0x0 << (_HPD_PIN_DDI(hpd_pin) * 4))
+#define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin) (0x1 << (_HPD_PIN_DDI(hpd_pin) * 4))
+#define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(hpd_pin) (0x2 << (_HPD_PIN_DDI(hpd_pin) * 4))
+#define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
+
+#define SHOTPLUG_CTL_TC _MMIO(0xc4034)
+#define ICP_TC_HPD_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4))
+#define ICP_TC_HPD_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4))
+#define ICP_TC_HPD_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4))
+
+#define SHPD_FILTER_CNT _MMIO(0xc4038)
+#define SHPD_FILTER_CNT_500_ADJ 0x001D9
+#define SHPD_FILTER_CNT_250 0x000F8
+
+#define _PCH_DPLL_A 0xc6014
+#define _PCH_DPLL_B 0xc6018
+#define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
+
+#define _PCH_FPA0 0xc6040
+#define _PCH_FPB0 0xc6048
+#define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0)
+#define FP_CB_TUNE (0x3 << 22)
+
+#define _PCH_FPA1 0xc6044
+#define _PCH_FPB1 0xc604c
+#define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1)
+
+#define PCH_DPLL_TEST _MMIO(0xc606c)
+
+#define PCH_DREF_CONTROL _MMIO(0xC6200)
+#define DREF_CONTROL_MASK 0x7fc3
+#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13)
+#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13)
+#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13)
+#define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13)
+#define DREF_SSC_SOURCE_DISABLE (0 << 11)
+#define DREF_SSC_SOURCE_ENABLE (2 << 11)
+#define DREF_SSC_SOURCE_MASK (3 << 11)
+#define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9)
+#define DREF_NONSPREAD_CK505_ENABLE (1 << 9)
+#define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9)
+#define DREF_NONSPREAD_SOURCE_MASK (3 << 9)
+#define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7)
+#define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7)
+#define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7)
+#define DREF_SSC4_DOWNSPREAD (0 << 6)
+#define DREF_SSC4_CENTERSPREAD (1 << 6)
+#define DREF_SSC1_DISABLE (0 << 1)
+#define DREF_SSC1_ENABLE (1 << 1)
+#define DREF_SSC4_DISABLE (0)
+#define DREF_SSC4_ENABLE (1)
+
+#define PCH_RAWCLK_FREQ _MMIO(0xc6204)
+#define FDL_TP1_TIMER_SHIFT 12
+#define FDL_TP1_TIMER_MASK (3 << 12)
+#define FDL_TP2_TIMER_SHIFT 10
+#define FDL_TP2_TIMER_MASK (3 << 10)
+#define RAWCLK_FREQ_MASK 0x3ff
+#define CNP_RAWCLK_DIV_MASK (0x3ff << 16)
+#define CNP_RAWCLK_DIV(div) ((div) << 16)
+#define CNP_RAWCLK_FRAC_MASK (0xf << 26)
+#define CNP_RAWCLK_DEN(den) ((den) << 26)
+#define ICP_RAWCLK_NUM(num) ((num) << 11)
+
+#define PCH_DPLL_TMR_CFG _MMIO(0xc6208)
+
+#define PCH_SSC4_PARMS _MMIO(0xc6210)
+#define PCH_SSC4_AUX_PARMS _MMIO(0xc6214)
+
+#define PCH_DPLL_SEL _MMIO(0xc7000)
+#define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4))
+#define TRANS_DPLLA_SEL(pipe) 0
+#define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3))
+
+/* transcoder */
+#define _PCH_TRANS_HTOTAL_A 0xe0000
+#define _PCH_TRANS_HTOTAL_B 0xe1000
+#define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
+#define TRANS_HTOTAL_SHIFT 16
+#define TRANS_HACTIVE_SHIFT 0
+
+#define _PCH_TRANS_HBLANK_A 0xe0004
+#define _PCH_TRANS_HBLANK_B 0xe1004
+#define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
+#define TRANS_HBLANK_END_SHIFT 16
+#define TRANS_HBLANK_START_SHIFT 0
+
+#define _PCH_TRANS_HSYNC_A 0xe0008
+#define _PCH_TRANS_HSYNC_B 0xe1008
+#define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
+#define TRANS_HSYNC_END_SHIFT 16
+#define TRANS_HSYNC_START_SHIFT 0
+
+#define _PCH_TRANS_VTOTAL_A 0xe000c
+#define _PCH_TRANS_VTOTAL_B 0xe100c
+#define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
+#define TRANS_VTOTAL_SHIFT 16
+#define TRANS_VACTIVE_SHIFT 0
+
+#define _PCH_TRANS_VBLANK_A 0xe0010
+#define _PCH_TRANS_VBLANK_B 0xe1010
+#define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
+#define TRANS_VBLANK_END_SHIFT 16
+#define TRANS_VBLANK_START_SHIFT 0
+
+#define _PCH_TRANS_VSYNC_A 0xe0014
+#define _PCH_TRANS_VSYNC_B 0xe1014
+#define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
+#define TRANS_VSYNC_END_SHIFT 16
+#define TRANS_VSYNC_START_SHIFT 0
+
+#define _PCH_TRANS_VSYNCSHIFT_A 0xe0028
+#define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
+#define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)
+
+#define _PCH_TRANSA_DATA_M1 0xe0030
+#define _PCH_TRANSB_DATA_M1 0xe1030
+#define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
+
+#define _PCH_TRANSA_DATA_N1 0xe0034
+#define _PCH_TRANSB_DATA_N1 0xe1034
+#define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
+
+#define _PCH_TRANSA_DATA_M2 0xe0038
+#define _PCH_TRANSB_DATA_M2 0xe1038
+#define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
+
+#define _PCH_TRANSA_DATA_N2 0xe003c
+#define _PCH_TRANSB_DATA_N2 0xe103c
+#define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
+
+#define _PCH_TRANSA_LINK_M1 0xe0040
+#define _PCH_TRANSB_LINK_M1 0xe1040
+#define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
+
+#define _PCH_TRANSA_LINK_N1 0xe0044
+#define _PCH_TRANSB_LINK_N1 0xe1044
+#define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
+
+#define _PCH_TRANSA_LINK_M2 0xe0048
+#define _PCH_TRANSB_LINK_M2 0xe1048
+#define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
+
+#define _PCH_TRANSA_LINK_N2 0xe004c
+#define _PCH_TRANSB_LINK_N2 0xe104c
+#define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
+
+/* Per-transcoder DIP controls (PCH) */
+#define _VIDEO_DIP_CTL_A 0xe0200
+#define _VIDEO_DIP_CTL_B 0xe1200
+#define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
+
+#define _VIDEO_DIP_DATA_A 0xe0208
+#define _VIDEO_DIP_DATA_B 0xe1208
+#define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
+
+#define _VIDEO_DIP_GCP_A 0xe0210
+#define _VIDEO_DIP_GCP_B 0xe1210
+#define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
+#define GCP_COLOR_INDICATION (1 << 2)
+#define GCP_DEFAULT_PHASE_ENABLE (1 << 1)
+#define GCP_AV_MUTE (1 << 0)
+
+/* Per-transcoder DIP controls (VLV) */
+#define _VLV_VIDEO_DIP_CTL_A 0x60200
+#define _VLV_VIDEO_DIP_CTL_B 0x61170
+#define _CHV_VIDEO_DIP_CTL_C 0x611f0
+#define VLV_TVIDEO_DIP_CTL(pipe) _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \
+ _VLV_VIDEO_DIP_CTL_A, \
+ _VLV_VIDEO_DIP_CTL_B, \
+ _CHV_VIDEO_DIP_CTL_C)
+
+#define _VLV_VIDEO_DIP_DATA_A 0x60208
+#define _VLV_VIDEO_DIP_DATA_B 0x61174
+#define _CHV_VIDEO_DIP_DATA_C 0x611f4
+#define VLV_TVIDEO_DIP_DATA(pipe) _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \
+ _VLV_VIDEO_DIP_DATA_A, \
+ _VLV_VIDEO_DIP_DATA_B, \
+ _CHV_VIDEO_DIP_DATA_C)
+
+#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A 0x60210
+#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B 0x61178
+#define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C 0x611f8
+#define VLV_TVIDEO_DIP_GCP(pipe) _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \
+ _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
+ _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, \
+ _CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
+
+/* Haswell DIP controls */
+#define _HSW_VIDEO_DIP_CTL_A 0x60200
+#define _HSW_VIDEO_DIP_CTL_B 0x61200
+#define HSW_TVIDEO_DIP_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_CTL_A)
+
+#define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220
+#define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220
+#define HSW_TVIDEO_DIP_AVI_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
+
+#define _HSW_VIDEO_DIP_VS_DATA_A 0x60260
+#define _HSW_VIDEO_DIP_VS_DATA_B 0x61260
+#define HSW_TVIDEO_DIP_VS_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
+
+#define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
+#define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
+#define HSW_TVIDEO_DIP_SPD_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
+
+#define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
+#define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
+#define HSW_TVIDEO_DIP_GMP_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4)
+
+#define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320
+#define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320
+#define HSW_TVIDEO_DIP_VSC_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
+
+/*ADLP and later: */
+#define _ADL_VIDEO_DIP_AS_DATA_A 0x60484
+#define _ADL_VIDEO_DIP_AS_DATA_B 0x61484
+#define ADL_TVIDEO_DIP_AS_SDP_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans,\
+ _ADL_VIDEO_DIP_AS_DATA_A + (i) * 4)
+
+#define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440
+#define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440
+#define GLK_TVIDEO_DIP_DRM_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4)
+
+#define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240
+#define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240
+#define _HSW_VIDEO_DIP_VS_ECC_A 0x60280
+#define _HSW_VIDEO_DIP_VS_ECC_B 0x61280
+#define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
+#define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
+#define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300
+#define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300
+#define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344
+#define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344
+
+#define _HSW_VIDEO_DIP_GCP_A 0x60210
+#define _HSW_VIDEO_DIP_GCP_B 0x61210
+#define HSW_TVIDEO_DIP_GCP(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GCP_A)
+
+#define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350
+#define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350
+#define ICL_VIDEO_DIP_PPS_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
+
+#define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4
+#define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4
+#define ICL_VIDEO_DIP_PPS_ECC(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
+
+#define _HSW_STEREO_3D_CTL_A 0x70020
+#define _HSW_STEREO_3D_CTL_B 0x71020
+#define HSW_STEREO_3D_CTL(dev_priv, trans) _MMIO_PIPE2(dev_priv, trans, _HSW_STEREO_3D_CTL_A)
+#define S3D_ENABLE (1 << 31)
+
+#define _PCH_TRANSACONF 0xf0008
+#define _PCH_TRANSBCONF 0xf1008
+#define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
+#define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */
+#define TRANS_ENABLE REG_BIT(31)
+#define TRANS_STATE_ENABLE REG_BIT(30)
+#define TRANS_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* ibx */
+#define TRANS_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */
+#define TRANS_INTERLACE_MASK REG_GENMASK(23, 21)
+#define TRANS_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANS_INTERLACE_MASK, 0)
+#define TRANS_INTERLACE_LEGACY_VSYNC_IBX REG_FIELD_PREP(TRANS_INTERLACE_MASK, 2) /* ibx */
+#define TRANS_INTERLACE_INTERLACED REG_FIELD_PREP(TRANS_INTERLACE_MASK, 3)
+#define TRANS_BPC_MASK REG_GENMASK(7, 5) /* ibx */
+#define TRANS_BPC_8 REG_FIELD_PREP(TRANS_BPC_MASK, 0)
+#define TRANS_BPC_10 REG_FIELD_PREP(TRANS_BPC_MASK, 1)
+#define TRANS_BPC_6 REG_FIELD_PREP(TRANS_BPC_MASK, 2)
+#define TRANS_BPC_12 REG_FIELD_PREP(TRANS_BPC_MASK, 3)
+
+#define PCH_DP_B _MMIO(0xe4100)
+#define PCH_DP_C _MMIO(0xe4200)
+#define PCH_DP_D _MMIO(0xe4300)
+
+/* CPT */
+#define _TRANS_DP_CTL_A 0xe0300
+#define _TRANS_DP_CTL_B 0xe1300
+#define _TRANS_DP_CTL_C 0xe2300
+#define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
+#define TRANS_DP_OUTPUT_ENABLE REG_BIT(31)
+#define TRANS_DP_PORT_SEL_MASK REG_GENMASK(30, 29)
+#define TRANS_DP_PORT_SEL_NONE REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, 3)
+#define TRANS_DP_PORT_SEL(port) REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, (port) - PORT_B)
+#define TRANS_DP_AUDIO_ONLY REG_BIT(26)
+#define TRANS_DP_ENH_FRAMING REG_BIT(18)
+#define TRANS_DP_BPC_MASK REG_GENMASK(10, 9)
+#define TRANS_DP_BPC_8 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 0)
+#define TRANS_DP_BPC_10 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 1)
+#define TRANS_DP_BPC_6 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 2)
+#define TRANS_DP_BPC_12 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 3)
+#define TRANS_DP_VSYNC_ACTIVE_HIGH REG_BIT(4)
+#define TRANS_DP_HSYNC_ACTIVE_HIGH REG_BIT(3)
+
+#define _TRANS_DP2_CTL_A 0x600a0
+#define _TRANS_DP2_CTL_B 0x610a0
+#define _TRANS_DP2_CTL_C 0x620a0
+#define _TRANS_DP2_CTL_D 0x630a0
+#define TRANS_DP2_CTL(trans) _MMIO_TRANS(trans, _TRANS_DP2_CTL_A, _TRANS_DP2_CTL_B)
+#define TRANS_DP2_128B132B_CHANNEL_CODING REG_BIT(31)
+#define TRANS_DP2_PANEL_REPLAY_ENABLE REG_BIT(30)
+#define TRANS_DP2_DEBUG_ENABLE REG_BIT(23)
+
+#define _TRANS_DP2_VFREQHIGH_A 0x600a4
+#define _TRANS_DP2_VFREQHIGH_B 0x610a4
+#define _TRANS_DP2_VFREQHIGH_C 0x620a4
+#define _TRANS_DP2_VFREQHIGH_D 0x630a4
+#define TRANS_DP2_VFREQHIGH(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQHIGH_A, _TRANS_DP2_VFREQHIGH_B)
+#define TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK REG_GENMASK(31, 8)
+#define TRANS_DP2_VFREQ_PIXEL_CLOCK(clk_hz) REG_FIELD_PREP(TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK, (clk_hz))
+
+#define _TRANS_DP2_VFREQLOW_A 0x600a8
+#define _TRANS_DP2_VFREQLOW_B 0x610a8
+#define _TRANS_DP2_VFREQLOW_C 0x620a8
+#define _TRANS_DP2_VFREQLOW_D 0x630a8
+#define TRANS_DP2_VFREQLOW(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQLOW_A, _TRANS_DP2_VFREQLOW_B)
+
+#define _DP_MIN_HBLANK_CTL_A 0x600ac
+#define _DP_MIN_HBLANK_CTL_B 0x610ac
+#define DP_MIN_HBLANK_CTL(trans) _MMIO_TRANS(trans, _DP_MIN_HBLANK_CTL_A, _DP_MIN_HBLANK_CTL_B)
+
+/* SNB eDP training params */
+/* SNB A-stepping */
+#define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22)
+#define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22)
+#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22)
+#define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22)
+/* SNB B-stepping */
+#define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0 << 22)
+#define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1 << 22)
+#define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a << 22)
+#define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39 << 22)
+#define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38 << 22)
+#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f << 22)
+
+/* IVB */
+#define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 << 22)
+#define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a << 22)
+#define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f << 22)
+#define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 << 22)
+#define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 << 22)
+#define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 << 22)
+#define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e << 22)
+
+/* legacy values */
+#define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 << 22)
+#define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 << 22)
+#define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 << 22)
+#define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 << 22)
+#define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 << 22)
+
+#define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f << 22)
+
+#define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C)
+#define PIXEL_OVERLAP_CNT_MASK (3 << 30)
+#define PIXEL_OVERLAP_CNT_SHIFT 30
+
+/*
+ * HSW - ICL power wells
+ *
+ * Platforms have up to 3 power well control register sets, each set
+ * controlling up to 16 power wells via a request/status HW flag tuple:
+ * - main (HSW_PWR_WELL_CTL[1-4])
+ * - AUX (ICL_PWR_WELL_CTL_AUX[1-4])
+ * - DDI (ICL_PWR_WELL_CTL_DDI[1-4])
+ * Each control register set consists of up to 4 registers used by different
+ * sources that can request a power well to be enabled:
+ * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1)
+ * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2)
+ * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set)
+ * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4)
+ */
+#define HSW_PWR_WELL_CTL1 _MMIO(0x45400)
+#define HSW_PWR_WELL_CTL2 _MMIO(0x45404)
+#define HSW_PWR_WELL_CTL3 _MMIO(0x45408)
+#define HSW_PWR_WELL_CTL4 _MMIO(0x4540C)
+#define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2))
+#define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2))
+
+/* HSW/BDW power well */
+#define HSW_PW_CTL_IDX_GLOBAL 15
+
+/* SKL/BXT/GLK power wells */
+#define SKL_PW_CTL_IDX_PW_2 15
+#define SKL_PW_CTL_IDX_PW_1 14
+#define GLK_PW_CTL_IDX_AUX_C 10
+#define GLK_PW_CTL_IDX_AUX_B 9
+#define GLK_PW_CTL_IDX_AUX_A 8
+#define SKL_PW_CTL_IDX_DDI_D 4
+#define SKL_PW_CTL_IDX_DDI_C 3
+#define SKL_PW_CTL_IDX_DDI_B 2
+#define SKL_PW_CTL_IDX_DDI_A_E 1
+#define GLK_PW_CTL_IDX_DDI_A 1
+#define SKL_PW_CTL_IDX_MISC_IO 0
+
+/* ICL/TGL - power wells */
+#define TGL_PW_CTL_IDX_PW_5 4
+#define ICL_PW_CTL_IDX_PW_4 3
+#define ICL_PW_CTL_IDX_PW_3 2
+#define ICL_PW_CTL_IDX_PW_2 1
+#define ICL_PW_CTL_IDX_PW_1 0
+
+/* XE_LPD - power wells */
+#define XELPD_PW_CTL_IDX_PW_D 8
+#define XELPD_PW_CTL_IDX_PW_C 7
+#define XELPD_PW_CTL_IDX_PW_B 6
+#define XELPD_PW_CTL_IDX_PW_A 5
+
+#define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440)
+#define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444)
+#define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C)
+#define TGL_PW_CTL_IDX_AUX_TBT6 14
+#define TGL_PW_CTL_IDX_AUX_TBT5 13
+#define TGL_PW_CTL_IDX_AUX_TBT4 12
+#define ICL_PW_CTL_IDX_AUX_TBT4 11
+#define TGL_PW_CTL_IDX_AUX_TBT3 11
+#define ICL_PW_CTL_IDX_AUX_TBT3 10
+#define TGL_PW_CTL_IDX_AUX_TBT2 10
+#define ICL_PW_CTL_IDX_AUX_TBT2 9
+#define TGL_PW_CTL_IDX_AUX_TBT1 9
+#define ICL_PW_CTL_IDX_AUX_TBT1 8
+#define TGL_PW_CTL_IDX_AUX_TC6 8
+#define XELPD_PW_CTL_IDX_AUX_E 8
+#define TGL_PW_CTL_IDX_AUX_TC5 7
+#define XELPD_PW_CTL_IDX_AUX_D 7
+#define TGL_PW_CTL_IDX_AUX_TC4 6
+#define ICL_PW_CTL_IDX_AUX_F 5
+#define TGL_PW_CTL_IDX_AUX_TC3 5
+#define ICL_PW_CTL_IDX_AUX_E 4
+#define TGL_PW_CTL_IDX_AUX_TC2 4
+#define ICL_PW_CTL_IDX_AUX_D 3
+#define TGL_PW_CTL_IDX_AUX_TC1 3
+#define ICL_PW_CTL_IDX_AUX_C 2
+#define ICL_PW_CTL_IDX_AUX_B 1
+#define ICL_PW_CTL_IDX_AUX_A 0
+
+#define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450)
+#define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454)
+#define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C)
+#define XELPD_PW_CTL_IDX_DDI_E 8
+#define TGL_PW_CTL_IDX_DDI_TC6 8
+#define XELPD_PW_CTL_IDX_DDI_D 7
+#define TGL_PW_CTL_IDX_DDI_TC5 7
+#define TGL_PW_CTL_IDX_DDI_TC4 6
+#define ICL_PW_CTL_IDX_DDI_F 5
+#define TGL_PW_CTL_IDX_DDI_TC3 5
+#define ICL_PW_CTL_IDX_DDI_E 4
+#define TGL_PW_CTL_IDX_DDI_TC2 4
+#define ICL_PW_CTL_IDX_DDI_D 3
+#define TGL_PW_CTL_IDX_DDI_TC1 3
+#define ICL_PW_CTL_IDX_DDI_C 2
+#define ICL_PW_CTL_IDX_DDI_B 1
+#define ICL_PW_CTL_IDX_DDI_A 0
+
+/* HSW - power well misc debug registers */
+#define HSW_PWR_WELL_CTL5 _MMIO(0x45410)
+#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31)
+#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20)
+#define HSW_PWR_WELL_FORCE_ON (1 << 19)
+#define HSW_PWR_WELL_CTL6 _MMIO(0x45414)
+
+#define SKL_FUSE_STATUS _MMIO(0x42000)
+#define SKL_FUSE_DOWNLOAD_STATUS (1 << 31)
+/*
+ * PG0 is HW controlled, so doesn't have a corresponding power well control knob
+ * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2
+ */
+#define SKL_PW_CTL_IDX_TO_PG(pw_idx) \
+ ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1)
+/*
+ * PG0 is HW controlled, so doesn't have a corresponding power well control knob
+ * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4
+ */
+#define ICL_PW_CTL_IDX_TO_PG(pw_idx) \
+ ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1)
+#define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
+
+/* Per-pipe DDI Function Control */
+#define _TRANS_DDI_FUNC_CTL_A 0x60400
+#define _TRANS_DDI_FUNC_CTL_B 0x61400
+#define _TRANS_DDI_FUNC_CTL_C 0x62400
+#define _TRANS_DDI_FUNC_CTL_D 0x63400
+#define _TRANS_DDI_FUNC_CTL_EDP 0x6F400
+#define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400
+#define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00
+#define TRANS_DDI_FUNC_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_DDI_FUNC_CTL_A)
+
+#define TRANS_DDI_FUNC_ENABLE (1 << 31)
+/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
+#define TRANS_DDI_PORT_SHIFT 28
+#define TGL_TRANS_DDI_PORT_SHIFT 27
+#define TRANS_DDI_PORT_MASK (7 << TRANS_DDI_PORT_SHIFT)
+#define TGL_TRANS_DDI_PORT_MASK (0xf << TGL_TRANS_DDI_PORT_SHIFT)
+#define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT)
+#define TGL_TRANS_DDI_SELECT_PORT(x) (((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT)
+#define TRANS_DDI_MODE_SELECT_MASK (7 << 24)
+#define TRANS_DDI_MODE_SELECT_HDMI (0 << 24)
+#define TRANS_DDI_MODE_SELECT_DVI (1 << 24)
+#define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24)
+#define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24)
+#define TRANS_DDI_MODE_SELECT_FDI_OR_128B132B (4 << 24)
+#define TRANS_DDI_BPC_MASK (7 << 20)
+#define TRANS_DDI_BPC_8 (0 << 20)
+#define TRANS_DDI_BPC_10 (1 << 20)
+#define TRANS_DDI_BPC_6 (2 << 20)
+#define TRANS_DDI_BPC_12 (3 << 20)
+#define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK REG_GENMASK(19, 18)
+#define TRANS_DDI_PORT_SYNC_MASTER_SELECT(x) REG_FIELD_PREP(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, (x))
+#define TRANS_DDI_PVSYNC (1 << 17)
+#define TRANS_DDI_PHSYNC (1 << 16)
+#define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15)
+#define XE3_TRANS_DDI_HDCP_LINE_REKEY_DISABLE REG_BIT(15)
+#define TRANS_DDI_EDP_INPUT_MASK (7 << 12)
+#define TRANS_DDI_EDP_INPUT_A_ON (0 << 12)
+#define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12)
+#define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12)
+#define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12)
+#define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12)
+#define TRANS_DDI_HDCP_LINE_REKEY_DISABLE REG_BIT(12)
+#define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10)
+#define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \
+ REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans)
+#define TRANS_DDI_HDCP_SIGNALLING (1 << 9)
+#define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8)
+#define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7)
+#define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6)
+#define TRANS_DDI_HDCP_SELECT REG_BIT(5)
+#define TRANS_DDI_BFI_ENABLE (1 << 4)
+#define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4)
+#define TRANS_DDI_PORT_WIDTH_MASK REG_GENMASK(3, 1)
+#define TRANS_DDI_PORT_WIDTH(width) REG_FIELD_PREP(TRANS_DDI_PORT_WIDTH_MASK, (width) - 1)
+#define TRANS_DDI_HDMI_SCRAMBLING (1 << 0)
+#define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \
+ | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \
+ | TRANS_DDI_HDMI_SCRAMBLING)
+
+#define _TRANS_DDI_FUNC_CTL2_A 0x60404
+#define _TRANS_DDI_FUNC_CTL2_B 0x61404
+#define _TRANS_DDI_FUNC_CTL2_C 0x62404
+#define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404
+#define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404
+#define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04
+#define TRANS_DDI_FUNC_CTL2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_DDI_FUNC_CTL2_A)
+#define PORT_SYNC_MODE_ENABLE REG_BIT(4)
+#define CMTG_SECONDARY_MODE REG_BIT(3)
+#define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0)
+#define PORT_SYNC_MODE_MASTER_SELECT(x) REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x))
+
+#define TRANS_CMTG_CHICKEN _MMIO(0x6fa90)
+#define DISABLE_DPT_CLK_GATING REG_BIT(1)
+
+/* DisplayPort Transport Control */
+#define _DP_TP_CTL_A 0x64040
+#define _DP_TP_CTL_B 0x64140
+#define _TGL_DP_TP_CTL_A 0x60540
+#define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
+#define TGL_DP_TP_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_CTL_A)
+#define DP_TP_CTL_ENABLE REG_BIT(31)
+#define DP_TP_CTL_FEC_ENABLE REG_BIT(30)
+#define DP_TP_CTL_MODE_MASK REG_BIT(27)
+#define DP_TP_CTL_MODE_SST REG_FIELD_PREP(DP_TP_CTL_MODE_MASK, 0)
+#define DP_TP_CTL_MODE_MST REG_FIELD_PREP(DP_TP_CTL_MODE_MASK, 1)
+#define DP_TP_CTL_FORCE_ACT REG_BIT(25)
+#define DP_TP_CTL_TRAIN_PAT4_SEL_MASK REG_GENMASK(20, 19)
+#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4A REG_FIELD_PREP(DP_TP_CTL_TRAIN_PAT4_SEL_MASK, 0)
+#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4B REG_FIELD_PREP(DP_TP_CTL_TRAIN_PAT4_SEL_MASK, 1)
+#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4C REG_FIELD_PREP(DP_TP_CTL_TRAIN_PAT4_SEL_MASK, 2)
+#define DP_TP_CTL_ENHANCED_FRAME_ENABLE REG_BIT(18)
+#define DP_TP_CTL_FDI_AUTOTRAIN REG_BIT(15)
+#define DP_TP_CTL_LINK_TRAIN_MASK REG_GENMASK(10, 8)
+#define DP_TP_CTL_LINK_TRAIN_PAT1 REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 0)
+#define DP_TP_CTL_LINK_TRAIN_PAT2 REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 1)
+#define DP_TP_CTL_LINK_TRAIN_PAT3 REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 4)
+#define DP_TP_CTL_LINK_TRAIN_PAT4 REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 5)
+#define DP_TP_CTL_LINK_TRAIN_IDLE REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 2)
+#define DP_TP_CTL_LINK_TRAIN_NORMAL REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 3)
+#define DP_TP_CTL_SCRAMBLE_DISABLE REG_BIT(7)
+
+/* DisplayPort Transport Status */
+#define _DP_TP_STATUS_A 0x64044
+#define _DP_TP_STATUS_B 0x64144
+#define _TGL_DP_TP_STATUS_A 0x60544
+#define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
+#define TGL_DP_TP_STATUS(dev_priv, tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_STATUS_A)
+#define DP_TP_STATUS_FEC_ENABLE_LIVE REG_BIT(28)
+#define DP_TP_STATUS_IDLE_DONE REG_BIT(25)
+#define DP_TP_STATUS_ACT_SENT REG_BIT(24)
+#define DP_TP_STATUS_MODE_STATUS_MST REG_BIT(23)
+#define DP_TP_STATUS_STREAMS_ENABLED_MASK REG_GENMASK(18, 16) /* 17:16 on hsw but bit 18 mbz */
+#define DP_TP_STATUS_AUTOTRAIN_DONE REG_BIT(12)
+#define DP_TP_STATUS_PAYLOAD_MAPPING_VC2_MASK REG_GENMASK(9, 8)
+#define DP_TP_STATUS_PAYLOAD_MAPPING_VC1_MASK REG_GENMASK(5, 4)
+#define DP_TP_STATUS_PAYLOAD_MAPPING_VC0_MASK REG_GENMASK(1, 0)
+
+/* DDI Buffer Control */
+#define _DDI_BUF_CTL_A 0x64000
+#define _DDI_BUF_CTL_B 0x64100
+/* Known as DDI_CTL_DE in MTL+ */
+#define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
+#define DDI_BUF_CTL_ENABLE REG_BIT(31)
+#define XE2LPD_DDI_BUF_D2D_LINK_ENABLE REG_BIT(29)
+#define XE2LPD_DDI_BUF_D2D_LINK_STATE REG_BIT(28)
+#define DDI_BUF_EMP_MASK REG_GENMASK(27, 24)
+#define DDI_BUF_TRANS_SELECT(n) REG_FIELD_PREP(DDI_BUF_EMP_MASK, (n))
+#define DDI_BUF_PHY_LINK_RATE_MASK REG_GENMASK(23, 20)
+#define DDI_BUF_PHY_LINK_RATE(r) REG_FIELD_PREP(DDI_BUF_PHY_LINK_RATE_MASK, (r))
+#define DDI_BUF_PORT_DATA_MASK REG_GENMASK(19, 18)
+#define DDI_BUF_PORT_DATA_10BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 0)
+#define DDI_BUF_PORT_DATA_20BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 1)
+#define DDI_BUF_PORT_DATA_40BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 2)
+#define DDI_BUF_PORT_REVERSAL REG_BIT(16)
+#define DDI_BUF_LANE_STAGGER_DELAY_MASK REG_GENMASK(15, 8)
+#define DDI_BUF_LANE_STAGGER_DELAY(symbols) REG_FIELD_PREP(DDI_BUF_LANE_STAGGER_DELAY_MASK, \
+ (symbols))
+#define DDI_BUF_IS_IDLE REG_BIT(7)
+#define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6)
+#define DDI_A_4_LANES REG_BIT(4)
+#define DDI_PORT_WIDTH_MASK REG_GENMASK(3, 1)
+#define DDI_PORT_WIDTH(width) REG_FIELD_PREP(DDI_PORT_WIDTH_MASK, \
+ ((width) == 3 ? 4 : (width) - 1))
+#define DDI_PORT_WIDTH_SHIFT 1
+#define DDI_INIT_DISPLAY_DETECTED REG_BIT(0)
+
+/* DDI Buffer Translations */
+#define _DDI_BUF_TRANS_A 0x64E00
+#define _DDI_BUF_TRANS_B 0x64E60
+#define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)
+#define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
+#define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
+
+/* DDI DP Compliance Control */
+#define _DDI_DP_COMP_CTL_A 0x605F0
+#define _DDI_DP_COMP_CTL_B 0x615F0
+#define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B)
+#define DDI_DP_COMP_CTL_ENABLE (1 << 31)
+#define DDI_DP_COMP_CTL_D10_2 (0 << 28)
+#define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28)
+#define DDI_DP_COMP_CTL_PRBS7 (2 << 28)
+#define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28)
+#define DDI_DP_COMP_CTL_HBR2 (4 << 28)
+#define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28)
+#define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0)
+
+/* DDI DP Compliance Pattern */
+#define _DDI_DP_COMP_PAT_A 0x605F4
+#define _DDI_DP_COMP_PAT_B 0x615F4
+#define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4)
+
+/* SBI offsets */
+#define SBI_SSCDIVINTPHASE 0x0200
+#define SBI_SSCDIVINTPHASE6 0x0600
+#define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1
+#define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1)
+#define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1)
+#define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8
+#define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8)
+#define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8)
+#define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15)
+#define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0)
+#define SBI_SSCDITHPHASE 0x0204
+#define SBI_SSCCTL 0x020c
+#define SBI_SSCCTL6 0x060C
+#define SBI_SSCCTL_PATHALT (1 << 3)
+#define SBI_SSCCTL_DISABLE (1 << 0)
+#define SBI_SSCAUXDIV6 0x0610
+#define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4
+#define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4)
+#define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4)
+#define SBI_DBUFF0 0x2a00
+#define SBI_GEN0 0x1f00
+#define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0)
+
+/* LPT PIXCLK_GATE */
+#define PIXCLK_GATE _MMIO(0xC6020)
+#define PIXCLK_GATE_UNGATE (1 << 0)
+#define PIXCLK_GATE_GATE (0 << 0)
+
+/* SPLL */
+#define SPLL_CTL _MMIO(0x46020)
+#define SPLL_PLL_ENABLE (1 << 31)
+#define SPLL_REF_BCLK (0 << 28)
+#define SPLL_REF_MUXED_SSC (1 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
+#define SPLL_REF_NON_SSC_HSW (2 << 28)
+#define SPLL_REF_PCH_SSC_BDW (2 << 28)
+#define SPLL_REF_LCPLL (3 << 28)
+#define SPLL_REF_MASK (3 << 28)
+#define SPLL_FREQ_810MHz (0 << 26)
+#define SPLL_FREQ_1350MHz (1 << 26)
+#define SPLL_FREQ_2700MHz (2 << 26)
+#define SPLL_FREQ_MASK (3 << 26)
+
+/* WRPLL */
+#define _WRPLL_CTL1 0x46040
+#define _WRPLL_CTL2 0x46060
+#define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2)
+#define WRPLL_PLL_ENABLE (1 << 31)
+#define WRPLL_REF_BCLK (0 << 28)
+#define WRPLL_REF_PCH_SSC (1 << 28)
+#define WRPLL_REF_MUXED_SSC_BDW (2 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
+#define WRPLL_REF_SPECIAL_HSW (2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */
+#define WRPLL_REF_LCPLL (3 << 28)
+#define WRPLL_REF_MASK (3 << 28)
+/* WRPLL divider programming */
+#define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0)
+#define WRPLL_DIVIDER_REF_MASK (0xff)
+#define WRPLL_DIVIDER_POST(x) ((x) << 8)
+#define WRPLL_DIVIDER_POST_MASK (0x3f << 8)
+#define WRPLL_DIVIDER_POST_SHIFT 8
+#define WRPLL_DIVIDER_FEEDBACK(x) ((x) << 16)
+#define WRPLL_DIVIDER_FB_SHIFT 16
+#define WRPLL_DIVIDER_FB_MASK (0xff << 16)
+
+/* Port clock selection */
+#define _PORT_CLK_SEL_A 0x46100
+#define _PORT_CLK_SEL_B 0x46104
+#define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B)
+#define PORT_CLK_SEL_MASK REG_GENMASK(31, 29)
+#define PORT_CLK_SEL_LCPLL_2700 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 0)
+#define PORT_CLK_SEL_LCPLL_1350 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 1)
+#define PORT_CLK_SEL_LCPLL_810 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 2)
+#define PORT_CLK_SEL_SPLL REG_FIELD_PREP(PORT_CLK_SEL_MASK, 3)
+#define PORT_CLK_SEL_WRPLL(pll) REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4 + (pll))
+#define PORT_CLK_SEL_WRPLL1 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4)
+#define PORT_CLK_SEL_WRPLL2 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 5)
+#define PORT_CLK_SEL_NONE REG_FIELD_PREP(PORT_CLK_SEL_MASK, 7)
+
+/* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */
+#define DDI_CLK_SEL(port) PORT_CLK_SEL(port)
+#define DDI_CLK_SEL_MASK REG_GENMASK(31, 28)
+#define DDI_CLK_SEL_NONE REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x0)
+#define DDI_CLK_SEL_MG REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x8)
+#define DDI_CLK_SEL_TBT_162 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xC)
+#define DDI_CLK_SEL_TBT_270 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xD)
+#define DDI_CLK_SEL_TBT_540 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xE)
+#define DDI_CLK_SEL_TBT_810 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xF)
+
+/* Transcoder clock selection */
+#define _TRANS_CLK_SEL_A 0x46140
+#define _TRANS_CLK_SEL_B 0x46144
+#define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B)
+/* For each transcoder, we need to select the corresponding port clock */
+#define TRANS_CLK_SEL_DISABLED (0x0 << 29)
+#define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29)
+#define TGL_TRANS_CLK_SEL_DISABLED (0x0 << 28)
+#define TGL_TRANS_CLK_SEL_PORT(x) (((x) + 1) << 28)
+
+#define CDCLK_FREQ _MMIO(0x46200)
+
+#define _TRANSA_MSA_MISC 0x60410
+#define _TRANSB_MSA_MISC 0x61410
+#define _TRANSC_MSA_MISC 0x62410
+#define _TRANS_EDP_MSA_MISC 0x6f410
+#define TRANS_MSA_MISC(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANSA_MSA_MISC)
+/* See DP_MSA_MISC_* for the bit definitions */
+
+#define _TRANS_A_SET_CONTEXT_LATENCY 0x6007C
+#define _TRANS_B_SET_CONTEXT_LATENCY 0x6107C
+#define _TRANS_C_SET_CONTEXT_LATENCY 0x6207C
+#define _TRANS_D_SET_CONTEXT_LATENCY 0x6307C
+#define TRANS_SET_CONTEXT_LATENCY(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_A_SET_CONTEXT_LATENCY)
+#define TRANS_SET_CONTEXT_LATENCY_MASK REG_GENMASK(15, 0)
+#define TRANS_SET_CONTEXT_LATENCY_VALUE(x) REG_FIELD_PREP(TRANS_SET_CONTEXT_LATENCY_MASK, (x))
+
+/* LCPLL Control */
+#define LCPLL_CTL _MMIO(0x130040)
+#define LCPLL_PLL_DISABLE (1 << 31)
+#define LCPLL_PLL_LOCK (1 << 30)
+#define LCPLL_REF_NON_SSC (0 << 28)
+#define LCPLL_REF_BCLK (2 << 28)
+#define LCPLL_REF_PCH_SSC (3 << 28)
+#define LCPLL_REF_MASK (3 << 28)
+#define LCPLL_CLK_FREQ_MASK (3 << 26)
+#define LCPLL_CLK_FREQ_450 (0 << 26)
+#define LCPLL_CLK_FREQ_54O_BDW (1 << 26)
+#define LCPLL_CLK_FREQ_337_5_BDW (2 << 26)
+#define LCPLL_CLK_FREQ_675_BDW (3 << 26)
+#define LCPLL_CD_CLOCK_DISABLE (1 << 25)
+#define LCPLL_ROOT_CD_CLOCK_DISABLE (1 << 24)
+#define LCPLL_CD2X_CLOCK_DISABLE (1 << 23)
+#define LCPLL_POWER_DOWN_ALLOW (1 << 22)
+#define LCPLL_CD_SOURCE_FCLK (1 << 21)
+#define LCPLL_CD_SOURCE_FCLK_DONE (1 << 19)
+
+/*
+ * SKL Clocks
+ */
+/* CDCLK_CTL */
+#define CDCLK_CTL _MMIO(0x46000)
+#define CDCLK_FREQ_SEL_MASK REG_GENMASK(27, 26)
+#define CDCLK_FREQ_450_432 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 0)
+#define CDCLK_FREQ_540 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1)
+#define CDCLK_FREQ_337_308 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2)
+#define CDCLK_FREQ_675_617 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3)
+#define MDCLK_SOURCE_SEL_MASK REG_GENMASK(25, 25)
+#define MDCLK_SOURCE_SEL_CD2XCLK REG_FIELD_PREP(MDCLK_SOURCE_SEL_MASK, 0)
+#define MDCLK_SOURCE_SEL_CDCLK_PLL REG_FIELD_PREP(MDCLK_SOURCE_SEL_MASK, 1)
+#define BXT_CDCLK_CD2X_DIV_SEL_MASK REG_GENMASK(23, 22)
+#define BXT_CDCLK_CD2X_DIV_SEL_1 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0)
+#define BXT_CDCLK_CD2X_DIV_SEL_1_5 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1)
+#define BXT_CDCLK_CD2X_DIV_SEL_2 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 2)
+#define BXT_CDCLK_CD2X_DIV_SEL_4 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 3)
+#define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20)
+#define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19)
+#define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
+#define ICL_CDCLK_CD2X_PIPE(pipe) (_PICK(pipe, 0, 2, 6) << 19)
+#define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19)
+#define TGL_CDCLK_CD2X_PIPE(pipe) BXT_CDCLK_CD2X_PIPE(pipe)
+#define TGL_CDCLK_CD2X_PIPE_NONE ICL_CDCLK_CD2X_PIPE_NONE
+#define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16)
+#define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
+
+/* CDCLK_SQUASH_CTL */
+#define CDCLK_SQUASH_CTL _MMIO(0x46008)
+#define CDCLK_SQUASH_ENABLE REG_BIT(31)
+#define CDCLK_SQUASH_WINDOW_SIZE_MASK REG_GENMASK(27, 24)
+#define CDCLK_SQUASH_WINDOW_SIZE(x) REG_FIELD_PREP(CDCLK_SQUASH_WINDOW_SIZE_MASK, (x))
+#define CDCLK_SQUASH_WAVEFORM_MASK REG_GENMASK(15, 0)
+#define CDCLK_SQUASH_WAVEFORM(x) REG_FIELD_PREP(CDCLK_SQUASH_WAVEFORM_MASK, (x))
+
+/* LCPLL_CTL */
+#define LCPLL1_CTL _MMIO(0x46010)
+#define LCPLL2_CTL _MMIO(0x46014)
+#define LCPLL_PLL_ENABLE (1 << 31)
+
+/* DPLL control1 */
+#define DPLL_CTRL1 _MMIO(0x6C058)
+#define DPLL_CTRL1_HDMI_MODE(id) (1 << ((id) * 6 + 5))
+#define DPLL_CTRL1_SSC(id) (1 << ((id) * 6 + 4))
+#define DPLL_CTRL1_LINK_RATE_MASK(id) (7 << ((id) * 6 + 1))
+#define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id) * 6 + 1)
+#define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate) << ((id) * 6 + 1))
+#define DPLL_CTRL1_OVERRIDE(id) (1 << ((id) * 6))
+#define DPLL_CTRL1_LINK_RATE_2700 0
+#define DPLL_CTRL1_LINK_RATE_1350 1
+#define DPLL_CTRL1_LINK_RATE_810 2
+#define DPLL_CTRL1_LINK_RATE_1620 3
+#define DPLL_CTRL1_LINK_RATE_1080 4
+#define DPLL_CTRL1_LINK_RATE_2160 5
+
+/* DPLL control2 */
+#define DPLL_CTRL2 _MMIO(0x6C05C)
+#define DPLL_CTRL2_DDI_CLK_OFF(port) (1 << ((port) + 15))
+#define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3 << ((port) * 3 + 1))
+#define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port) * 3 + 1)
+#define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk) << ((port) * 3 + 1))
+#define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1 << ((port) * 3))
+
+/* DPLL Status */
+#define DPLL_STATUS _MMIO(0x6C060)
+#define DPLL_LOCK(id) (1 << ((id) * 8))
+
+/* DPLL cfg */
+#define _DPLL1_CFGCR1 0x6C040
+#define _DPLL2_CFGCR1 0x6C048
+#define _DPLL3_CFGCR1 0x6C050
+#define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
+#define DPLL_CFGCR1_FREQ_ENABLE (1 << 31)
+#define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff << 9)
+#define DPLL_CFGCR1_DCO_FRACTION(x) ((x) << 9)
+#define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff)
+
+#define _DPLL1_CFGCR2 0x6C044
+#define _DPLL2_CFGCR2 0x6C04C
+#define _DPLL3_CFGCR2 0x6C054
+#define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
+#define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff << 8)
+#define DPLL_CFGCR2_QDIV_RATIO(x) ((x) << 8)
+#define DPLL_CFGCR2_QDIV_MODE(x) ((x) << 7)
+#define DPLL_CFGCR2_KDIV_MASK (3 << 5)
+#define DPLL_CFGCR2_KDIV(x) ((x) << 5)
+#define DPLL_CFGCR2_KDIV_5 (0 << 5)
+#define DPLL_CFGCR2_KDIV_2 (1 << 5)
+#define DPLL_CFGCR2_KDIV_3 (2 << 5)
+#define DPLL_CFGCR2_KDIV_1 (3 << 5)
+#define DPLL_CFGCR2_PDIV_MASK (7 << 2)
+#define DPLL_CFGCR2_PDIV(x) ((x) << 2)
+#define DPLL_CFGCR2_PDIV_1 (0 << 2)
+#define DPLL_CFGCR2_PDIV_2 (1 << 2)
+#define DPLL_CFGCR2_PDIV_3 (2 << 2)
+#define DPLL_CFGCR2_PDIV_7 (4 << 2)
+#define DPLL_CFGCR2_PDIV_7_INVALID (5 << 2)
+#define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
+
+/* ICL Clocks */
+#define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
+#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24, 4, 5))
+#define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10)
+#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_4 ? \
+ (tc_port) + 12 : \
+ (tc_port) - TC_PORT_4 + 21))
+#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2)
+#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
+#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
+#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27)
+#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \
+ (3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
+#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \
+ ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
+
+/*
+ * DG1 Clocks
+ * First registers controls the first A and B, while the second register
+ * controls the phy C and D. The bits on these registers are the
+ * same, but refer to different phys
+ */
+#define _DG1_DPCLKA_CFGCR0 0x164280
+#define _DG1_DPCLKA1_CFGCR0 0x16C280
+#define _DG1_DPCLKA_PHY_IDX(phy) ((phy) % 2)
+#define _DG1_DPCLKA_PLL_IDX(pll) ((pll) % 2)
+#define DG1_DPCLKA_CFGCR0(phy) _MMIO_PHY((phy) / 2, \
+ _DG1_DPCLKA_CFGCR0, \
+ _DG1_DPCLKA1_CFGCR0)
+#define DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT(_DG1_DPCLKA_PHY_IDX(phy) + 10)
+#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) (_DG1_DPCLKA_PHY_IDX(phy) * 2)
+#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) (_DG1_DPCLKA_PLL_IDX(pll) << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
+#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (0x3 << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
+
+/* ADLS Clocks */
+#define _ADLS_DPCLKA_CFGCR0 0x164280
+#define _ADLS_DPCLKA_CFGCR1 0x1642BC
+#define ADLS_DPCLKA_CFGCR(phy) _MMIO_PHY((phy) / 3, \
+ _ADLS_DPCLKA_CFGCR0, \
+ _ADLS_DPCLKA_CFGCR1)
+#define ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy) (((phy) % 3) * 2)
+/* ADLS DPCLKA_CFGCR0 DDI mask */
+#define ADLS_DPCLKA_DDII_SEL_MASK REG_GENMASK(5, 4)
+#define ADLS_DPCLKA_DDIB_SEL_MASK REG_GENMASK(3, 2)
+#define ADLS_DPCLKA_DDIA_SEL_MASK REG_GENMASK(1, 0)
+/* ADLS DPCLKA_CFGCR1 DDI mask */
+#define ADLS_DPCLKA_DDIK_SEL_MASK REG_GENMASK(3, 2)
+#define ADLS_DPCLKA_DDIJ_SEL_MASK REG_GENMASK(1, 0)
+#define ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy) _PICK((phy), \
+ ADLS_DPCLKA_DDIA_SEL_MASK, \
+ ADLS_DPCLKA_DDIB_SEL_MASK, \
+ ADLS_DPCLKA_DDII_SEL_MASK, \
+ ADLS_DPCLKA_DDIJ_SEL_MASK, \
+ ADLS_DPCLKA_DDIK_SEL_MASK)
+
+/* ICL PLL */
+#define _DPLL0_ENABLE 0x46010
+#define _DPLL1_ENABLE 0x46014
+#define _ADLS_DPLL2_ENABLE 0x46018
+#define _ADLS_DPLL3_ENABLE 0x46030
+#define PLL_ENABLE REG_BIT(31)
+#define PLL_LOCK REG_BIT(30)
+#define PLL_POWER_ENABLE REG_BIT(27)
+#define PLL_POWER_STATE REG_BIT(26)
+#define ICL_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \
+ _DPLL0_ENABLE, _DPLL1_ENABLE, \
+ _ADLS_DPLL3_ENABLE, _ADLS_DPLL3_ENABLE))
+
+#define _DG2_PLL3_ENABLE 0x4601C
+
+#define DG2_PLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \
+ _DPLL0_ENABLE, _DPLL1_ENABLE, \
+ _DG2_PLL3_ENABLE, _DG2_PLL3_ENABLE))
+
+#define TBT_PLL_ENABLE _MMIO(0x46020)
+
+#define _MG_PLL1_ENABLE 0x46030
+#define _MG_PLL2_ENABLE 0x46034
+#define _MG_PLL3_ENABLE 0x46038
+#define _MG_PLL4_ENABLE 0x4603C
+/* Bits are the same as _DPLL0_ENABLE */
+#define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \
+ _MG_PLL2_ENABLE)
+
+/* DG1 PLL */
+#define DG1_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
+ _DPLL0_ENABLE, _DPLL1_ENABLE, \
+ _MG_PLL1_ENABLE, _MG_PLL2_ENABLE))
+
+/* ADL-P Type C PLL */
+#define PORTTC1_PLL_ENABLE 0x46038
+#define PORTTC2_PLL_ENABLE 0x46040
+#define ADLP_PORTTC_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), \
+ PORTTC1_PLL_ENABLE, \
+ PORTTC2_PLL_ENABLE)
+
+#define _ICL_DPLL0_CFGCR0 0x164000
+#define _ICL_DPLL1_CFGCR0 0x164080
+#define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \
+ _ICL_DPLL1_CFGCR0)
+#define DPLL_CFGCR0_HDMI_MODE (1 << 30)
+#define DPLL_CFGCR0_SSC_ENABLE (1 << 29)
+#define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25)
+#define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25)
+#define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25)
+#define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25)
+#define DPLL_CFGCR0_LINK_RATE_810 (2 << 25)
+#define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25)
+#define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25)
+#define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25)
+#define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25)
+#define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25)
+#define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10)
+#define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10)
+#define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10)
+#define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff)
+
+#define _ICL_DPLL0_CFGCR1 0x164004
+#define _ICL_DPLL1_CFGCR1 0x164084
+#define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \
+ _ICL_DPLL1_CFGCR1)
+#define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10)
+#define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10)
+#define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10)
+#define DPLL_CFGCR1_QDIV_MODE_SHIFT (9)
+#define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9)
+#define DPLL_CFGCR1_KDIV_MASK (7 << 6)
+#define DPLL_CFGCR1_KDIV_SHIFT (6)
+#define DPLL_CFGCR1_KDIV(x) ((x) << 6)
+#define DPLL_CFGCR1_KDIV_1 (1 << 6)
+#define DPLL_CFGCR1_KDIV_2 (2 << 6)
+#define DPLL_CFGCR1_KDIV_3 (4 << 6)
+#define DPLL_CFGCR1_PDIV_MASK (0xf << 2)
+#define DPLL_CFGCR1_PDIV_SHIFT (2)
+#define DPLL_CFGCR1_PDIV(x) ((x) << 2)
+#define DPLL_CFGCR1_PDIV_2 (1 << 2)
+#define DPLL_CFGCR1_PDIV_3 (2 << 2)
+#define DPLL_CFGCR1_PDIV_5 (4 << 2)
+#define DPLL_CFGCR1_PDIV_7 (8 << 2)
+#define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0)
+#define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0)
+#define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0)
+
+#define _TGL_DPLL0_CFGCR0 0x164284
+#define _TGL_DPLL1_CFGCR0 0x16428C
+#define _TGL_TBTPLL_CFGCR0 0x16429C
+#define TGL_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
+ _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \
+ _TGL_TBTPLL_CFGCR0, _TGL_TBTPLL_CFGCR0))
+#define RKL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \
+ _TGL_DPLL1_CFGCR0)
+
+#define _TGL_DPLL0_DIV0 0x164B00
+#define _TGL_DPLL1_DIV0 0x164C00
+#define TGL_DPLL0_DIV0(pll) _MMIO_PLL(pll, _TGL_DPLL0_DIV0, _TGL_DPLL1_DIV0)
+#define TGL_DPLL0_DIV0_AFC_STARTUP_MASK REG_GENMASK(27, 25)
+#define TGL_DPLL0_DIV0_AFC_STARTUP(val) REG_FIELD_PREP(TGL_DPLL0_DIV0_AFC_STARTUP_MASK, (val))
+
+#define _TGL_DPLL0_CFGCR1 0x164288
+#define _TGL_DPLL1_CFGCR1 0x164290
+#define _TGL_TBTPLL_CFGCR1 0x1642A0
+#define TGL_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
+ _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \
+ _TGL_TBTPLL_CFGCR1, _TGL_TBTPLL_CFGCR1))
+#define RKL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \
+ _TGL_DPLL1_CFGCR1)
+
+#define _DG1_DPLL2_CFGCR0 0x16C284
+#define _DG1_DPLL3_CFGCR0 0x16C28C
+#define DG1_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
+ _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \
+ _DG1_DPLL2_CFGCR0, _DG1_DPLL3_CFGCR0))
+
+#define _DG1_DPLL2_CFGCR1 0x16C288
+#define _DG1_DPLL3_CFGCR1 0x16C290
+#define DG1_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
+ _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \
+ _DG1_DPLL2_CFGCR1, _DG1_DPLL3_CFGCR1))
+
+/* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */
+#define _ADLS_DPLL4_CFGCR0 0x164294
+#define _ADLS_DPLL3_CFGCR0 0x1642C0
+#define ADLS_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
+ _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \
+ _ADLS_DPLL4_CFGCR0, _ADLS_DPLL3_CFGCR0))
+
+#define _ADLS_DPLL4_CFGCR1 0x164298
+#define _ADLS_DPLL3_CFGCR1 0x1642C4
+#define ADLS_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
+ _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \
+ _ADLS_DPLL4_CFGCR1, _ADLS_DPLL3_CFGCR1))
+
+/* BXT display engine PLL */
+#define BXT_DE_PLL_CTL _MMIO(0x6d000)
+#define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */
+#define BXT_DE_PLL_RATIO_MASK 0xff
+
+#define BXT_DE_PLL_ENABLE _MMIO(0x46070)
+#define BXT_DE_PLL_PLL_ENABLE (1 << 31)
+#define BXT_DE_PLL_LOCK (1 << 30)
+#define BXT_DE_PLL_FREQ_REQ (1 << 23)
+#define BXT_DE_PLL_FREQ_REQ_ACK (1 << 22)
+#define ICL_CDCLK_PLL_RATIO(x) (x)
+#define ICL_CDCLK_PLL_RATIO_MASK 0xff
+
+/* GEN9 DC */
+#define DC_STATE_EN _MMIO(0x45504)
+#define DC_STATE_DISABLE 0
+#define DC_STATE_EN_DC3CO REG_BIT(30)
+#define DC_STATE_DC3CO_STATUS REG_BIT(29)
+#define HOLD_PHY_CLKREQ_PG1_LATCH REG_BIT(21)
+#define HOLD_PHY_PG1_LATCH REG_BIT(20)
+#define DC_STATE_EN_UPTO_DC5 (1 << 0)
+#define DC_STATE_EN_DC9 (1 << 3)
+#define DC_STATE_EN_UPTO_DC6 (2 << 0)
+#define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3
+
+#define DC_STATE_DEBUG _MMIO(0x45520)
+#define DC_STATE_DEBUG_MASK_CORES (1 << 0)
+#define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1)
+
+#define D_COMP_BDW _MMIO(0x138144)
+
+/* Pipe WM_LINETIME - watermark line time */
+#define _WM_LINETIME_A 0x45270
+#define _WM_LINETIME_B 0x45274
+#define WM_LINETIME(pipe) _MMIO_PIPE(pipe, _WM_LINETIME_A, _WM_LINETIME_B)
+#define HSW_LINETIME_MASK REG_GENMASK(8, 0)
+#define HSW_LINETIME(x) REG_FIELD_PREP(HSW_LINETIME_MASK, (x))
+#define HSW_IPS_LINETIME_MASK REG_GENMASK(24, 16)
+#define HSW_IPS_LINETIME(x) REG_FIELD_PREP(HSW_IPS_LINETIME_MASK, (x))
+
+/* SFUSE_STRAP */
+#define SFUSE_STRAP _MMIO(0xc2014)
+#define SFUSE_STRAP_FUSE_LOCK (1 << 13)
+#define SFUSE_STRAP_RAW_FREQUENCY (1 << 8)
+#define SFUSE_STRAP_DISPLAY_DISABLED (1 << 7)
+#define SFUSE_STRAP_CRT_DISABLED (1 << 6)
+#define SFUSE_STRAP_DDIF_DETECTED (1 << 3)
+#define SFUSE_STRAP_DDIB_DETECTED (1 << 2)
+#define SFUSE_STRAP_DDIC_DETECTED (1 << 1)
+#define SFUSE_STRAP_DDID_DETECTED (1 << 0)
+
+/* Gen4+ Timestamp and Pipe Frame time stamp registers */
+#define GEN4_TIMESTAMP _MMIO(0x2358)
+#define ILK_TIMESTAMP_HI _MMIO(0x70070)
+#define IVB_TIMESTAMP_CTR _MMIO(0x44070)
+
+/* g4x+, except vlv/chv! */
+#define _PIPE_FRMTMSTMP_A 0x70048
+#define _PIPE_FRMTMSTMP_B 0x71048
+#define PIPE_FRMTMSTMP(pipe) \
+ _MMIO_PIPE(pipe, _PIPE_FRMTMSTMP_A, _PIPE_FRMTMSTMP_B)
+
+/* g4x+, except vlv/chv! */
+#define _PIPE_FLIPTMSTMP_A 0x7004C
+#define _PIPE_FLIPTMSTMP_B 0x7104C
+#define PIPE_FLIPTMSTMP(pipe) \
+ _MMIO_PIPE(pipe, _PIPE_FLIPTMSTMP_A, _PIPE_FLIPTMSTMP_B)
+
+/* tgl+ */
+#define _PIPE_FLIPDONETMSTMP_A 0x70054
+#define _PIPE_FLIPDONETMSTMP_B 0x71054
+#define PIPE_FLIPDONETIMSTMP(pipe) \
+ _MMIO_PIPE(pipe, _PIPE_FLIPDONETMSTMP_A, _PIPE_FLIPDONETMSTMP_B)
+
+#define _VLV_PIPE_MSA_MISC_A 0x70048
+#define VLV_PIPE_MSA_MISC(__display, pipe) \
+ _MMIO_PIPE2(__display, pipe, _VLV_PIPE_MSA_MISC_A)
+#define VLV_MSA_MISC1_HW_ENABLE REG_BIT(31)
+#define VLV_MSA_MISC1_SW_S3D_MASK REG_GENMASK(2, 0) /* MSA MISC1 3:1 */
+
+#define _ICL_PHY_MISC_A 0x64C00
+#define _ICL_PHY_MISC_B 0x64C04
+#define _DG2_PHY_MISC_TC1 0x64C14 /* TC1="PHY E" but offset as if "PHY F" */
+#define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, _ICL_PHY_MISC_B)
+#define DG2_PHY_MISC(port) ((port) == PHY_E ? _MMIO(_DG2_PHY_MISC_TC1) : \
+ ICL_PHY_MISC(port))
+#define ICL_PHY_MISC_MUX_DDID (1 << 28)
+#define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
+#define DG2_PHY_DP_TX_ACK_MASK REG_GENMASK(23, 20)
+
+#define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0)
+#define MODULAR_FIA_MASK (1 << 4)
+#define TC_LIVE_STATE_TBT(idx) (1 << ((idx) * 8 + 6))
+#define TC_LIVE_STATE_TC(idx) (1 << ((idx) * 8 + 5))
+#define DP_LANE_ASSIGNMENT_SHIFT(idx) ((idx) * 8)
+#define DP_LANE_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 8))
+#define DP_LANE_ASSIGNMENT(idx, x) ((x) << ((idx) * 8))
+
+#define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia), 0x00890)
+#define DP_PHY_MODE_STATUS_COMPLETED(idx) (1 << (idx))
+
+#define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894)
+#define DP_PHY_MODE_STATUS_NOT_SAFE(idx) (1 << (idx))
+
+#define PORT_TX_DFLEXPA1(fia) _MMIO_FIA((fia), 0x00880)
+#define DP_PIN_ASSIGNMENT_SHIFT(idx) ((idx) * 4)
+#define DP_PIN_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 4))
+#define DP_PIN_ASSIGNMENT(idx, x) ((x) << ((idx) * 4))
+
+#define _TCSS_DDI_STATUS_1 0x161500
+#define _TCSS_DDI_STATUS_2 0x161504
+#define TCSS_DDI_STATUS(tc) _MMIO(_PICK_EVEN(tc, \
+ _TCSS_DDI_STATUS_1, \
+ _TCSS_DDI_STATUS_2))
+#define TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK REG_GENMASK(28, 25)
+#define TCSS_DDI_STATUS_READY REG_BIT(2)
+#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1)
+#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0)
+
+#define CLKREQ_POLICY _MMIO(0x101038)
+#define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1)
+
+#define CLKGATE_DIS_MISC _MMIO(0x46534)
+#define CLKGATE_DIS_MISC_DMASC_GATING_DIS REG_BIT(21)
+
+#define _MTL_CLKGATE_DIS_TRANS_A 0x604E8
+#define _MTL_CLKGATE_DIS_TRANS_B 0x614E8
+#define MTL_CLKGATE_DIS_TRANS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _MTL_CLKGATE_DIS_TRANS_A)
+#define MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS REG_BIT(7)
+
+#define _MTL_PIPE_CLKGATE_DIS2_A 0x60114
+#define _MTL_PIPE_CLKGATE_DIS2_B 0x61114
+#define MTL_PIPE_CLKGATE_DIS2(pipe) _MMIO_PIPE(pipe, _MTL_PIPE_CLKGATE_DIS2_A, _MTL_PIPE_CLKGATE_DIS2_B)
+#define MTL_DPFC_GATING_DIS REG_BIT(6)
+
+#define MTL_MEM_SS_INFO_QGV_POINT_OFFSET 0x45710
+#define MTL_MEM_SS_INFO_QGV_POINT_LOW(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8)
+#define MTL_TRCD_MASK REG_GENMASK(31, 24)
+#define MTL_TRP_MASK REG_GENMASK(23, 16)
+#define MTL_DCLK_MASK REG_GENMASK(15, 0)
+
+#define MTL_MEM_SS_INFO_QGV_POINT_HIGH(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8 + 4)
+#define MTL_TRAS_MASK REG_GENMASK(16, 8)
+#define MTL_TRDPRE_MASK REG_GENMASK(7, 0)
+
+
+
+#endif /* __INTEL_DISPLAY_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c b/drivers/gpu/drm/i915/display/intel_display_wa.c
index da429c332914..f57280e9d041 100644
--- a/drivers/gpu/drm/i915/display/intel_display_wa.c
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
@@ -6,6 +6,7 @@
#include "i915_reg.h"
#include "intel_de.h"
#include "intel_display_core.h"
+#include "intel_display_regs.h"
#include "intel_display_wa.h"
static void gen11_display_wa_apply(struct intel_display *display)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 98f80a6c63e8..e516104ee069 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -28,8 +28,9 @@
#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_de.h"
-#include "intel_display_rpm.h"
#include "intel_display_power_well.h"
+#include "intel_display_regs.h"
+#include "intel_display_rpm.h"
#include "intel_dmc.h"
#include "intel_dmc_regs.h"
#include "intel_step.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
index 7e2ce0c2f6c3..082cb5597c1a 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
@@ -10,6 +10,7 @@
#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_de.h"
+#include "intel_display_regs.h"
#include "intel_dmc_regs.h"
#include "intel_dmc_wl.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index d7a30d0992b7..56224d9ffdc0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -34,7 +34,6 @@
#include <linux/string_helpers.h>
#include <linux/timekeeping.h>
#include <linux/types.h>
-
#include <asm/byteorder.h>
#include <drm/display/drm_dp_helper.h>
@@ -58,10 +57,12 @@
#include "intel_combo_phy_regs.h"
#include "intel_connector.h"
#include "intel_crtc.h"
+#include "intel_crtc_state_dump.h"
#include "intel_cx0_phy.h"
#include "intel_ddi.h"
#include "intel_de.h"
#include "intel_display_driver.h"
+#include "intel_display_regs.h"
#include "intel_display_rpm.h"
#include "intel_display_types.h"
#include "intel_dp.h"
@@ -92,7 +93,6 @@
#include "intel_tc.h"
#include "intel_vdsc.h"
#include "intel_vrr.h"
-#include "intel_crtc_state_dump.h"
/* DP DSC throughput values used for slice count calculations KPixels/s */
#define DP_DSC_PEAK_PIXEL_RATE 2720000
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index cc312596fb77..23ea94ba4c6c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -14,6 +14,7 @@
#include "i915_reg.h"
#include "intel_ddi.h"
#include "intel_de.h"
+#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_dp.h"
#include "intel_dp_hdcp.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 4c15dcb103aa..94064cb7be28 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -38,6 +38,7 @@
#include "intel_ddi.h"
#include "intel_de.h"
#include "intel_display_driver.h"
+#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_dp.h"
#include "intel_dp_hdcp.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dp_test.c b/drivers/gpu/drm/i915/display/intel_dp_test.c
index bd61f3c3ec91..82b74f109315 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_test.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_test.c
@@ -13,6 +13,7 @@
#include "i915_reg.h"
#include "intel_ddi.h"
#include "intel_de.h"
+#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_dp.h"
#include "intel_dp_link_training.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index 1e1af7150723..ce6ccc14d093 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -28,6 +28,7 @@
#include "intel_ddi_buf_trans.h"
#include "intel_de.h"
#include "intel_display_power_well.h"
+#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_dp.h"
#include "intel_dpio_phy.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 0481b1365b85..c694be9521ae 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -13,6 +13,7 @@
#include "intel_cx0_phy.h"
#include "intel_de.h"
#include "intel_display.h"
+#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_dpio_phy.h"
#include "intel_dpll.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 84df41086a89..18b79485b9dd 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -29,6 +29,7 @@
#include "i915_reg.h"
#include "intel_cx0_phy.h"
#include "intel_de.h"
+#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_dkl_phy.h"
#include "intel_dkl_phy_regs.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dpt_common.c b/drivers/gpu/drm/i915/display/intel_dpt_common.c
index d2dede0a5229..4e05558d6b64 100644
--- a/drivers/gpu/drm/i915/display/intel_dpt_common.c
+++ b/drivers/gpu/drm/i915/display/intel_dpt_common.c
@@ -6,6 +6,7 @@
#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_de.h"
+#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_dpt_common.h"
#include "skl_universal_plane_regs.h"
diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c
index 05cd0f6e6d71..09ee2b157e2f 100644
--- a/drivers/gpu/drm/i915/display/intel_drrs.c
+++ b/drivers/gpu/drm/i915/display/intel_drrs.c
@@ -9,6 +9,7 @@
#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_de.h"
+#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_drrs.h"
#include "intel_frontbuffer.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index 72fe390c5af2..f6123081b6bd 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -11,6 +11,7 @@
#include "i915_reg.h"
#include "intel_crtc.h"
#include "intel_de.h"
+#include "intel_display_regs.h"
#include "intel_display_rpm.h"
#include "intel_display_types.h"
#include "intel_dsb.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
index 4e92504f5c14..ecebc3946cbb 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
@@ -31,17 +31,16 @@
#include <linux/pinctrl/machine.h>
#include <linux/slab.h>
#include <linux/string_helpers.h>
-
#include <linux/unaligned.h>
#include <drm/drm_crtc.h>
#include <drm/drm_edid.h>
-
#include <video/mipi_display.h>
#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_de.h"
+#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_dsi.h"
#include "intel_dsi_vbt.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
index b61520353c92..7cf3fb9163f4 100644
--- a/drivers/gpu/drm/i915/display/intel_dvo.c
+++ b/drivers/gpu/drm/i915/display/intel_dvo.c
@@ -39,6 +39,7 @@
#include "intel_connector.h"
#include "intel_de.h"
#include "intel_display_driver.h"
+#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_dvo.h"
#include "intel_dvo_dev.h"
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index ce5b1e3f1c20..4665bce3487a 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -45,7 +45,9 @@
#include <drm/drm_fourcc.h>
#include "gem/i915_gem_stolen.h"
+
#include "gt/intel_gt_types.h"
+
#include "i915_drv.h"
#include "i915_reg.h"
#include "i915_utils.h"
@@ -55,6 +57,7 @@
#include "intel_cdclk.h"
#include "intel_de.h"
#include "intel_display_device.h"
+#include "intel_display_regs.h"
#include "intel_display_rpm.h"
#include "intel_display_trace.h"
#include "intel_display_types.h"
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index 40deee0769ae..7fdd2254eba6 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -13,8 +13,9 @@
#include "intel_crtc.h"
#include "intel_ddi.h"
#include "intel_de.h"
-#include "intel_dp.h"
+#include "intel_display_regs.h"
#include "intel_display_types.h"
+#include "intel_dp.h"
#include "intel_fdi.h"
#include "intel_fdi_regs.h"
#include "intel_link_bw.h"
diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
index 451cd26024f7..7356b1d48a4b 100644
--- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
@@ -29,6 +29,7 @@
#include "i915_reg.h"
#include "intel_de.h"
#include "intel_display_irq.h"
+#include "intel_display_regs.h"
#include "intel_display_trace.h"
#include "intel_display_types.h"
#include "intel_fbc.h"
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index abf457e68ee9..c06eec0c654f 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -37,6 +37,7 @@
#include "i915_irq.h"
#include "i915_reg.h"
#include "intel_de.h"
+#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_gmbus.h"
#include "intel_gmbus_regs.h"
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 411f17655f89..e344fd1a4717 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -22,6 +22,7 @@
#include "intel_de.h"
#include "intel_display_power.h"
#include "intel_display_power_well.h"
+#include "intel_display_regs.h"
#include "intel_display_rpm.h"
#include "intel_display_types.h"
#include "intel_dp_mst.h"
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index f9fa17e1f584..fb8ead20e180 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -40,7 +40,6 @@
#include <drm/drm_edid.h>
#include <drm/drm_probe_helper.h>
#include <drm/intel/intel_lpe_audio.h>
-
#include <media/cec-notifier.h>
#include "g4x_hdmi.h"
@@ -53,6 +52,7 @@
#include "intel_ddi.h"
#include "intel_de.h"
#include "intel_display_driver.h"
+#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_dp.h"
#include "intel_gmbus.h"
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
index 2463e61e7802..8486a378a0e6 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
@@ -7,6 +7,7 @@
#include "i915_reg.h"
#include "intel_de.h"
#include "intel_display_irq.h"
+#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_dp_aux.h"
#include "intel_gmbus.h"
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
index f94b7eeae20f..a874a28e4cf9 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -32,6 +32,7 @@
#include "i915_reg.h"
#include "i915_utils.h"
#include "intel_de.h"
+#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_dp.h"
#include "intel_hdmi.h"
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index 9e963bce340f..85b53a08daf8 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -6,8 +6,8 @@
* state.
*/
-#include <drm/drm_atomic_uapi.h>
#include <drm/drm_atomic_state_helper.h>
+#include <drm/drm_atomic_uapi.h>
#include <drm/drm_vblank.h>
#include "i915_drv.h"
@@ -23,6 +23,7 @@
#include "intel_de.h"
#include "intel_display.h"
#include "intel_display_power.h"
+#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_dmc.h"
#include "intel_fifo_underrun.h"
diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c
index aff9a3455c1b..ff5dc2515f55 100644
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -31,6 +31,7 @@
#include "gem/i915_gem_internal.h"
#include "gem/i915_gem_object_frontbuffer.h"
#include "gem/i915_gem_pm.h"
+
#include "gt/intel_gpu_commands.h"
#include "gt/intel_ring.h"
@@ -38,6 +39,7 @@
#include "i915_reg.h"
#include "intel_color_regs.h"
#include "intel_de.h"
+#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_frontbuffer.h"
#include "intel_overlay.h"
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index b909ed18a5b2..567887a0cccf 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -9,6 +9,7 @@
#include "intel_crt.h"
#include "intel_crt_regs.h"
#include "intel_de.h"
+#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_dpll.h"
#include "intel_fdi.h"
diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
index 1307a478861a..221bf8d49afb 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
@@ -6,6 +6,7 @@
#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_de.h"
+#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_panel.h"
#include "intel_pch_refclk.h"
diff --git a/drivers/gpu/drm/i915/display/intel_pfit.c b/drivers/gpu/drm/i915/display/intel_pfit.c
index 3c3ecf288570..b615be868fd9 100644
--- a/drivers/gpu/drm/i915/display/intel_pfit.c
+++ b/drivers/gpu/drm/i915/display/intel_pfit.c
@@ -10,6 +10,7 @@
#include "intel_de.h"
#include "intel_display_core.h"
#include "intel_display_driver.h"
+#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_lvds_regs.h"
#include "intel_pfit.h"
diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc.c b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
index 6182f484b5bd..6e4c65a08949 100644
--- a/drivers/gpu/drm/i915/display/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
@@ -34,6 +34,7 @@
#include "intel_atomic.h"
#include "intel_de.h"
#include "intel_display_irq.h"
+#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_pipe_crc.h"
#include "intel_pipe_crc_regs.h"
diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
index d22b5469672d..86f924c2fe70 100644
--- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
@@ -13,6 +13,7 @@
#include "intel_bw.h"
#include "intel_cdclk.h"
#include "intel_de.h"
+#include "intel_display_regs.h"
#include "intel_display_trace.h"
#include "intel_pmdemand.h"
#include "intel_step.h"
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 4d4e2b9f5f2d..f2c87deca30e 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -10,6 +10,7 @@
#include "i915_reg.h"
#include "intel_de.h"
#include "intel_display_power_well.h"
+#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_dp.h"
#include "intel_dpio_phy.h"
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index eef48c014112..aa1915a30bea 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -36,6 +36,7 @@
#include "intel_ddi.h"
#include "intel_de.h"
#include "intel_display_irq.h"
+#include "intel_display_regs.h"
#include "intel_display_rpm.h"
#include "intel_display_types.h"
#include "intel_dp.h"
diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c
index 757b9ce7e3b1..89b66473fd17 100644
--- a/drivers/gpu/drm/i915/display/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
@@ -46,6 +46,7 @@
#include "intel_crtc.h"
#include "intel_de.h"
#include "intel_display_driver.h"
+#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_fdi.h"
#include "intel_fifo_underrun.h"
diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
index 2b53ac9f4935..8edc9252276b 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
@@ -12,6 +12,7 @@
#include "intel_ddi.h"
#include "intel_ddi_buf_trans.h"
#include "intel_de.h"
+#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_snps_hdmi_pll.h"
#include "intel_snps_phy.h"
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index c1014e74791f..3bc57579fe53 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -14,6 +14,7 @@
#include "intel_display.h"
#include "intel_display_driver.h"
#include "intel_display_power_map.h"
+#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_dkl_phy_regs.h"
#include "intel_dp.h"
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index 139fa5deba80..c1c6ce390bbc 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -10,6 +10,7 @@
#include "intel_color.h"
#include "intel_crtc.h"
#include "intel_de.h"
+#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_vblank.h"
#include "intel_vrr.h"
diff --git a/drivers/gpu/drm/i915/display/intel_vga.c b/drivers/gpu/drm/i915/display/intel_vga.c
index 684b5d1bc87c..85ec1969d4dd 100644
--- a/drivers/gpu/drm/i915/display/intel_vga.c
+++ b/drivers/gpu/drm/i915/display/intel_vga.c
@@ -7,11 +7,13 @@
#include <linux/vgaarb.h>
#include <video/vga.h>
+
#include "soc/intel_gmch.h"
#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_de.h"
+#include "intel_display_regs.h"
#include "intel_vga.h"
static i915_reg_t intel_vga_cntrl_reg(struct intel_display *display)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index c6565baf815a..619a6b78a991 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -8,6 +8,7 @@
#include "i915_reg.h"
#include "intel_de.h"
+#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_dp.h"
#include "intel_vrr.h"
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
index ee81220a7c88..b3e41b342127 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -6,6 +6,7 @@
#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_de.h"
+#include "intel_display_regs.h"
#include "intel_display_trace.h"
#include "intel_display_types.h"
#include "intel_fb.h"
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 8739195aba69..881a690c36e8 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -8,12 +8,15 @@
#include <drm/drm_damage_helper.h>
#include <drm/drm_fourcc.h>
+#include "pxp/intel_pxp.h"
+
#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_atomic_plane.h"
#include "intel_bo.h"
#include "intel_de.h"
#include "intel_display_irq.h"
+#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_dpt.h"
#include "intel_fb.h"
@@ -25,7 +28,6 @@
#include "skl_universal_plane.h"
#include "skl_universal_plane_regs.h"
#include "skl_watermark.h"
-#include "pxp/intel_pxp.h"
static const u32 skl_plane_formats[] = {
DRM_FORMAT_C8,
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 8080f777910a..689595693781 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -19,6 +19,7 @@
#include "intel_de.h"
#include "intel_display.h"
#include "intel_display_power.h"
+#include "intel_display_regs.h"
#include "intel_display_rpm.h"
#include "intel_display_types.h"
#include "intel_fb.h"
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index 346737f15fa9..cc16957da106 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -39,6 +39,7 @@
#include "intel_connector.h"
#include "intel_crtc.h"
#include "intel_de.h"
+#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_dsi.h"
#include "intel_dsi_vbt.h"
diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index f25ee2953baf..fa6625fdf4cb 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -38,6 +38,7 @@
#include "i915_drv.h"
#include "i915_reg.h"
+#include "display/intel_display_regs.h"
#include "gt/intel_engine_regs.h"
#include "gt/intel_gpu_commands.h"
#include "gt/intel_gt_regs.h"
diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
index 1e1af5e545a4..35e8103953a0 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -36,6 +36,7 @@
#include "i915_drv.h"
#include "i915_reg.h"
+#include "display/intel_display_regs.h"
#include "gvt.h"
#include "display/bxt_dpio_phy_regs.h"
diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c
index f9f7ef131371..1b009543d9a2 100644
--- a/drivers/gpu/drm/i915/gvt/fb_decoder.c
+++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
@@ -39,6 +39,7 @@
#include "i915_drv.h"
#include "i915_pvinfo.h"
#include "i915_reg.h"
+#include "display/intel_display_regs.h"
#include "display/i9xx_plane_regs.h"
#include "display/intel_cursor_regs.h"
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index e6e9010462e3..6ef1100b5917 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -40,6 +40,7 @@
#include "i915_drv.h"
#include "i915_reg.h"
+#include "display/intel_display_regs.h"
#include "gvt.h"
#include "i915_pvinfo.h"
#include "intel_mchbar_regs.h"
diff --git a/drivers/gpu/drm/i915/gvt/interrupt.c b/drivers/gpu/drm/i915/gvt/interrupt.c
index 336d079c4207..a956da68e6bd 100644
--- a/drivers/gpu/drm/i915/gvt/interrupt.c
+++ b/drivers/gpu/drm/i915/gvt/interrupt.c
@@ -33,6 +33,7 @@
#include "i915_drv.h"
#include "i915_reg.h"
+#include "display/intel_display_regs.h"
#include "gvt.h"
#include "trace.h"
diff --git a/drivers/gpu/drm/i915/gvt/mmio.c b/drivers/gpu/drm/i915/gvt/mmio.c
index e16e0d4c9534..da1135fa7cda 100644
--- a/drivers/gpu/drm/i915/gvt/mmio.c
+++ b/drivers/gpu/drm/i915/gvt/mmio.c
@@ -36,6 +36,7 @@
#include <linux/vmalloc.h>
#include "i915_drv.h"
#include "i915_reg.h"
+#include "display/intel_display_regs.h"
#include "gvt.h"
#include "display/bxt_dpio_phy_regs.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 88c46a7c948f..7ae9dc2970cd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -144,10 +144,6 @@
#define GEN6_STOLEN_RESERVED_ENABLE (1 << 0)
#define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20)
-#define _GEN7_PIPEA_DE_LOAD_SL 0x70068
-#define _GEN7_PIPEB_DE_LOAD_SL 0x71068
-#define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
-
/*
* Reset registers
*/
@@ -187,46 +183,6 @@
/* DPIO registers */
#define DPIO_DEVFN 0
-#define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110)
-#define DPIO_MODSEL1 (1 << 3) /* if ref clk b == 27 */
-#define DPIO_MODSEL0 (1 << 2) /* if ref clk a == 27 */
-#define DPIO_SFR_BYPASS (1 << 1)
-#define DPIO_CMNRST (1 << 0)
-
-#define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090)
-#define MIPIO_RST_CTRL (1 << 2)
-
-#define _BXT_PHY_CTL_DDI_A 0x64C00
-#define _BXT_PHY_CTL_DDI_B 0x64C10
-#define _BXT_PHY_CTL_DDI_C 0x64C20
-#define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10)
-#define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9)
-#define BXT_PHY_LANE_ENABLED (1 << 8)
-#define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \
- _BXT_PHY_CTL_DDI_B)
-
-#define _PHY_CTL_FAMILY_DDI 0x64C90
-#define _PHY_CTL_FAMILY_EDP 0x64C80
-#define _PHY_CTL_FAMILY_DDI_C 0x64CA0
-#define COMMON_RESET_DIS (1 << 31)
-#define BXT_PHY_CTL_FAMILY(phy) \
- _MMIO(_PICK_EVEN_2RANGES(phy, 1, \
- _PHY_CTL_FAMILY_DDI, _PHY_CTL_FAMILY_DDI, \
- _PHY_CTL_FAMILY_EDP, _PHY_CTL_FAMILY_DDI_C))
-
-/* UAIMI scratch pad register 1 */
-#define UAIMI_SPR1 _MMIO(0x4F074)
-/* SKL VccIO mask */
-#define SKL_VCCIO_MASK 0x1
-/* SKL balance leg register */
-#define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C)
-/* I_boost values */
-#define BALANCE_LEG_SHIFT(port) (8 + 3 * (port))
-#define BALANCE_LEG_MASK(port) (7 << (8 + 3 * (port)))
-/* Balance leg disable bits */
-#define BALANCE_LEG_DISABLE_SHIFT 23
-#define BALANCE_LEG_DISABLE(port) (1 << (23 + (port)))
-
/*
* Fence registers
* [0-7] @ 0x2000 gen2,gen3
@@ -372,16 +328,6 @@
#define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070)
#define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074)
-#define ILK_GTT_FAULT _MMIO(0x44040) /* ilk/snb */
-#define GTT_FAULT_INVALID_GTT_PTE (1 << 7)
-#define GTT_FAULT_INVALID_PTE_DATA (1 << 6)
-#define GTT_FAULT_CURSOR_B_FAULT (1 << 5)
-#define GTT_FAULT_CURSOR_A_FAULT (1 << 4)
-#define GTT_FAULT_SPRITE_B_FAULT (1 << 3)
-#define GTT_FAULT_SPRITE_A_FAULT (1 << 2)
-#define GTT_FAULT_PRIMARY_B_FAULT (1 << 1)
-#define GTT_FAULT_PRIMARY_A_FAULT (1 << 0)
-
#define GEN7_ERR_INT _MMIO(0x44040)
#define ERR_INT_POISON (1 << 31)
#define ERR_INT_INVALID_GTT_PTE (1 << 29)
@@ -458,10 +404,6 @@
#define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)
#define VLV_PCBR_ADDR_SHIFT 12
-#define VLV_IRQ_REGS I915_IRQ_REGS(VLV_IMR, \
- VLV_IER, \
- VLV_IIR)
-
#define DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */
#define EIR _MMIO(0x20b0)
#define EMR _MMIO(0x20b4)
@@ -475,16 +417,6 @@
#define GEN2_ERROR_REGS I915_ERROR_REGS(EMR, EIR)
-#define VLV_EIR _MMIO(VLV_DISPLAY_BASE + 0x20b0)
-#define VLV_EMR _MMIO(VLV_DISPLAY_BASE + 0x20b4)
-#define VLV_ESR _MMIO(VLV_DISPLAY_BASE + 0x20b8)
-#define VLV_ERROR_GUNIT_TLB_DATA (1 << 6)
-#define VLV_ERROR_GUNIT_TLB_PTE (1 << 5)
-#define VLV_ERROR_PAGE_TABLE (1 << 4)
-#define VLV_ERROR_CLAIM (1 << 0)
-
-#define VLV_ERROR_REGS I915_ERROR_REGS(VLV_EMR, VLV_EIR)
-
#define INSTPM _MMIO(0x20c0)
#define INSTPM_SELF_EN (1 << 12) /* 915GM only */
#define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
@@ -509,23 +441,6 @@
#define LM_FIFO_WATERMARK 0x0000001F
#define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */
-#define _MBUS_ABOX0_CTL 0x45038
-#define _MBUS_ABOX1_CTL 0x45048
-#define _MBUS_ABOX2_CTL 0x4504C
-#define MBUS_ABOX_CTL(x) \
- _MMIO(_PICK_EVEN_2RANGES(x, 2, \
- _MBUS_ABOX0_CTL, _MBUS_ABOX1_CTL, \
- _MBUS_ABOX2_CTL, _MBUS_ABOX2_CTL))
-
-#define MBUS_ABOX_BW_CREDIT_MASK (3 << 20)
-#define MBUS_ABOX_BW_CREDIT(x) ((x) << 20)
-#define MBUS_ABOX_B_CREDIT_MASK (0xF << 16)
-#define MBUS_ABOX_B_CREDIT(x) ((x) << 16)
-#define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8)
-#define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8)
-#define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0)
-#define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0)
-
/*
* Make render/texture TLB fetches lower priority than associated data
* fetches. This is not turned on by default.
@@ -700,173 +615,6 @@
#define IVB_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2)
#define IVB_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3)
-#define IPS_CTL _MMIO(0x43408)
-#define IPS_ENABLE REG_BIT(31)
-#define IPS_FALSE_COLOR REG_BIT(4)
-
-/*
- * Clock control & power management
- */
-#define _DPLL_A 0x6014
-#define _DPLL_B 0x6018
-#define _CHV_DPLL_C 0x6030
-#define DPLL(dev_priv, pipe) _MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \
- (pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
-
-#define VGA0 _MMIO(0x6000)
-#define VGA1 _MMIO(0x6004)
-#define VGA_PD _MMIO(0x6010)
-#define VGA0_PD_P2_DIV_4 (1 << 7)
-#define VGA0_PD_P1_DIV_2 (1 << 5)
-#define VGA0_PD_P1_SHIFT 0
-#define VGA0_PD_P1_MASK (0x1f << 0)
-#define VGA1_PD_P2_DIV_4 (1 << 15)
-#define VGA1_PD_P1_DIV_2 (1 << 13)
-#define VGA1_PD_P1_SHIFT 8
-#define VGA1_PD_P1_MASK (0x1f << 8)
-#define DPLL_VCO_ENABLE (1 << 31)
-#define DPLL_SDVO_HIGH_SPEED (1 << 30)
-#define DPLL_DVO_2X_MODE (1 << 30)
-#define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
-#define DPLL_SYNCLOCK_ENABLE (1 << 29)
-#define DPLL_REF_CLK_ENABLE_VLV (1 << 29)
-#define DPLL_VGA_MODE_DIS (1 << 28)
-#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
-#define DPLLB_MODE_LVDS (2 << 26) /* i915 */
-#define DPLL_MODE_MASK (3 << 26)
-#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
-#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
-#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
-#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
-#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
-#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
-#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
-#define DPLL_LOCK_VLV (1 << 15)
-#define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14)
-#define DPLL_INTEGRATED_REF_CLK_VLV (1 << 13)
-#define DPLL_SSC_REF_CLK_CHV (1 << 13)
-#define DPLL_PORTC_READY_MASK (0xf << 4)
-#define DPLL_PORTB_READY_MASK (0xf)
-
-#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
-
-/* Additional CHV pll/phy registers */
-#define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240)
-#define DPLL_PORTD_READY_MASK (0xf)
-#define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
-#define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2 * (phy) + (ch) + 27))
-#define PHY_LDO_DELAY_0NS 0x0
-#define PHY_LDO_DELAY_200NS 0x1
-#define PHY_LDO_DELAY_600NS 0x2
-#define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2 * (phy) + 23))
-#define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 * (phy) + 4 * (ch) + 11))
-#define PHY_CH_SU_PSR 0x1
-#define PHY_CH_DEEP_PSR 0x7
-#define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6 * (phy) + 3 * (ch) + 2))
-#define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))
-#define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
-#define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30))
-#define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch))))
-#define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline))))
-
-/*
- * The i830 generation, in LVDS mode, defines P1 as the bit number set within
- * this field (only one bit may be set).
- */
-#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
-#define DPLL_FPA01_P1_POST_DIV_SHIFT 16
-#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
-/* i830, required in DVO non-gang */
-#define PLL_P2_DIVIDE_BY_4 (1 << 23)
-#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
-#define PLL_REF_INPUT_DREFCLK (0 << 13)
-#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
-#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
-#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
-#define PLL_REF_INPUT_MASK (3 << 13)
-#define PLL_LOAD_PULSE_PHASE_SHIFT 9
-/* Ironlake */
-# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
-# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
-# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9)
-# define DPLL_FPA1_P1_POST_DIV_SHIFT 0
-# define DPLL_FPA1_P1_POST_DIV_MASK 0xff
-
-/*
- * Parallel to Serial Load Pulse phase selection.
- * Selects the phase for the 10X DPLL clock for the PCIe
- * digital display port. The range is 4 to 13; 10 or more
- * is just a flip delay. The default is 6
- */
-#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
-#define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
-/*
- * SDVO multiplier for 945G/GM. Not used on 965.
- */
-#define SDVO_MULTIPLIER_MASK 0x000000ff
-#define SDVO_MULTIPLIER_SHIFT_HIRES 4
-#define SDVO_MULTIPLIER_SHIFT_VGA 0
-
-#define _DPLL_A_MD 0x601c
-#define _DPLL_B_MD 0x6020
-#define _CHV_DPLL_C_MD 0x603c
-#define DPLL_MD(dev_priv, pipe) _MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \
- (pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
-
-/*
- * UDI pixel divider, controlling how many pixels are stuffed into a packet.
- *
- * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
- */
-#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
-#define DPLL_MD_UDI_DIVIDER_SHIFT 24
-/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
-#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
-#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
-/*
- * SDVO/UDI pixel multiplier.
- *
- * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
- * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
- * modes, the bus rate would be below the limits, so SDVO allows for stuffing
- * dummy bytes in the datastream at an increased clock rate, with both sides of
- * the link knowing how many bytes are fill.
- *
- * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
- * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
- * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
- * through an SDVO command.
- *
- * This register field has values of multiplication factor minus 1, with
- * a maximum multiplier of 5 for SDVO.
- */
-#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
-#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
-/*
- * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
- * This best be set to the default value (3) or the CRT won't work. No,
- * I don't entirely understand what this does...
- */
-#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
-#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
-
-#define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024)
-
-#define _FPA0 0x6040
-#define _FPA1 0x6044
-#define _FPB0 0x6048
-#define _FPB1 0x604c
-#define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0)
-#define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1)
-#define FP_N_DIV_MASK 0x003f0000
-#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
-#define FP_N_DIV_SHIFT 16
-#define FP_M1_DIV_MASK 0x00003f00
-#define FP_M1_DIV_SHIFT 8
-#define FP_M2_DIV_MASK 0x0000003f
-#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
-#define FP_M2_DIV_SHIFT 0
-
#define DPLL_TEST _MMIO(0x606c)
#define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
#define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
@@ -1000,27 +748,6 @@
#define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */
#define DEUC _MMIO(0x6214) /* CRL only */
-#define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500)
-#define FW_CSPWRDWNEN (1 << 15)
-
-#define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)
-
-#define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508)
-#define CDCLK_FREQ_SHIFT 4
-#define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT)
-#define CZCLK_FREQ_MASK 0xf
-
-#define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C)
-#define PFI_CREDIT_63 (9 << 28) /* chv only */
-#define PFI_CREDIT_31 (8 << 28) /* chv only */
-#define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */
-#define PFI_CREDIT_RESEND (1 << 27)
-#define VGA_FAST_MODE_DISABLE (1 << 14)
-
-#define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510)
-
-#define PEG_BAND_GAP_DATA _MMIO(0x14d68)
-
#define BXT_RP_STATE_CAP _MMIO(0x138170)
#define GEN9_RP_STATE_LIMITS _MMIO(0x138148)
@@ -1050,19 +777,6 @@
#define VLV_CLK_CTL2 _MMIO(0x101104)
#define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
-/*
- * Overlay regs
- */
-#define OVADD _MMIO(0x30000)
-#define DOVSTA _MMIO(0x30008)
-#define OC_BUF (0x3 << 20)
-#define OGAMC5 _MMIO(0x30010)
-#define OGAMC4 _MMIO(0x30014)
-#define OGAMC3 _MMIO(0x30018)
-#define OGAMC2 _MMIO(0x3001c)
-#define OGAMC1 _MMIO(0x30020)
-#define OGAMC0 _MMIO(0x30024)
-
/*
* GEN9 clock gating regs
*/
@@ -1077,482 +791,6 @@
#define TGL_VRH_GATING_DIS REG_BIT(31)
#define DPT_GATING_DIS REG_BIT(22)
-#define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
-#define BXT_GMBUS_GATING_DIS (1 << 14)
-#define DG2_DPFC_GATING_DIS REG_BIT(31)
-
-#define GEN9_CLKGATE_DIS_5 _MMIO(0x46540)
-#define DPCE_GATING_DIS REG_BIT(17)
-
-#define _CLKGATE_DIS_PSL_A 0x46520
-#define _CLKGATE_DIS_PSL_B 0x46524
-#define _CLKGATE_DIS_PSL_C 0x46528
-#define DUPS1_GATING_DIS (1 << 15)
-#define DUPS2_GATING_DIS (1 << 19)
-#define DUPS3_GATING_DIS (1 << 23)
-#define CURSOR_GATING_DIS REG_BIT(28)
-#define DPF_GATING_DIS (1 << 10)
-#define DPF_RAM_GATING_DIS (1 << 9)
-#define DPFR_GATING_DIS (1 << 8)
-
-#define CLKGATE_DIS_PSL(pipe) \
- _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B)
-
-#define _CLKGATE_DIS_PSL_EXT_A 0x4654C
-#define _CLKGATE_DIS_PSL_EXT_B 0x46550
-#define PIPEDMC_GATING_DIS REG_BIT(12)
-
-#define CLKGATE_DIS_PSL_EXT(pipe) \
- _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_EXT_A, _CLKGATE_DIS_PSL_EXT_B)
-
-/*
- * Display engine regs
- */
-/* Pipe/transcoder A timing regs */
-#define _TRANS_HTOTAL_A 0x60000
-#define _TRANS_HTOTAL_B 0x61000
-#define TRANS_HTOTAL(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HTOTAL_A)
-#define HTOTAL_MASK REG_GENMASK(31, 16)
-#define HTOTAL(htotal) REG_FIELD_PREP(HTOTAL_MASK, (htotal))
-#define HACTIVE_MASK REG_GENMASK(15, 0)
-#define HACTIVE(hdisplay) REG_FIELD_PREP(HACTIVE_MASK, (hdisplay))
-
-#define _TRANS_HBLANK_A 0x60004
-#define _TRANS_HBLANK_B 0x61004
-#define TRANS_HBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HBLANK_A)
-#define HBLANK_END_MASK REG_GENMASK(31, 16)
-#define HBLANK_END(hblank_end) REG_FIELD_PREP(HBLANK_END_MASK, (hblank_end))
-#define HBLANK_START_MASK REG_GENMASK(15, 0)
-#define HBLANK_START(hblank_start) REG_FIELD_PREP(HBLANK_START_MASK, (hblank_start))
-
-#define _TRANS_HSYNC_A 0x60008
-#define _TRANS_HSYNC_B 0x61008
-#define TRANS_HSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A)
-#define HSYNC_END_MASK REG_GENMASK(31, 16)
-#define HSYNC_END(hsync_end) REG_FIELD_PREP(HSYNC_END_MASK, (hsync_end))
-#define HSYNC_START_MASK REG_GENMASK(15, 0)
-#define HSYNC_START(hsync_start) REG_FIELD_PREP(HSYNC_START_MASK, (hsync_start))
-
-#define _TRANS_VTOTAL_A 0x6000c
-#define _TRANS_VTOTAL_B 0x6100c
-#define TRANS_VTOTAL(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A)
-#define VTOTAL_MASK REG_GENMASK(31, 16)
-#define VTOTAL(vtotal) REG_FIELD_PREP(VTOTAL_MASK, (vtotal))
-#define VACTIVE_MASK REG_GENMASK(15, 0)
-#define VACTIVE(vdisplay) REG_FIELD_PREP(VACTIVE_MASK, (vdisplay))
-
-#define _TRANS_VBLANK_A 0x60010
-#define _TRANS_VBLANK_B 0x61010
-#define TRANS_VBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A)
-#define VBLANK_END_MASK REG_GENMASK(31, 16)
-#define VBLANK_END(vblank_end) REG_FIELD_PREP(VBLANK_END_MASK, (vblank_end))
-#define VBLANK_START_MASK REG_GENMASK(15, 0)
-#define VBLANK_START(vblank_start) REG_FIELD_PREP(VBLANK_START_MASK, (vblank_start))
-
-#define _TRANS_VSYNC_A 0x60014
-#define _TRANS_VSYNC_B 0x61014
-#define TRANS_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A)
-#define VSYNC_END_MASK REG_GENMASK(31, 16)
-#define VSYNC_END(vsync_end) REG_FIELD_PREP(VSYNC_END_MASK, (vsync_end))
-#define VSYNC_START_MASK REG_GENMASK(15, 0)
-#define VSYNC_START(vsync_start) REG_FIELD_PREP(VSYNC_START_MASK, (vsync_start))
-
-#define _PIPEASRC 0x6001c
-#define _PIPEBSRC 0x6101c
-#define PIPESRC(dev_priv, pipe) _MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC)
-#define PIPESRC_WIDTH_MASK REG_GENMASK(31, 16)
-#define PIPESRC_WIDTH(w) REG_FIELD_PREP(PIPESRC_WIDTH_MASK, (w))
-#define PIPESRC_HEIGHT_MASK REG_GENMASK(15, 0)
-#define PIPESRC_HEIGHT(h) REG_FIELD_PREP(PIPESRC_HEIGHT_MASK, (h))
-
-#define _BCLRPAT_A 0x60020
-#define _BCLRPAT_B 0x61020
-#define BCLRPAT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A)
-
-#define _TRANS_VSYNCSHIFT_A 0x60028
-#define _TRANS_VSYNCSHIFT_B 0x61028
-#define TRANS_VSYNCSHIFT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A)
-
-#define _TRANS_MULT_A 0x6002c
-#define _TRANS_MULT_B 0x6102c
-#define TRANS_MULT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A)
-
-/* Hotplug control (945+ only) */
-#define PORT_HOTPLUG_EN(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
-#define PORTB_HOTPLUG_INT_EN (1 << 29)
-#define PORTC_HOTPLUG_INT_EN (1 << 28)
-#define PORTD_HOTPLUG_INT_EN (1 << 27)
-#define SDVOB_HOTPLUG_INT_EN (1 << 26)
-#define SDVOC_HOTPLUG_INT_EN (1 << 25)
-#define TV_HOTPLUG_INT_EN (1 << 18)
-#define CRT_HOTPLUG_INT_EN (1 << 9)
-#define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \
- PORTC_HOTPLUG_INT_EN | \
- PORTD_HOTPLUG_INT_EN | \
- SDVOC_HOTPLUG_INT_EN | \
- SDVOB_HOTPLUG_INT_EN | \
- CRT_HOTPLUG_INT_EN)
-#define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
-#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
-/* must use period 64 on GM45 according to docs */
-#define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
-#define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
-#define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
-#define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
-#define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
-#define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
-#define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
-#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
-#define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
-#define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
-#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
-#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
-
-#define PORT_HOTPLUG_STAT(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114)
-/* HDMI/DP bits are g4x+ */
-#define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27)
-#define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28)
-#define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29)
-#define PORTD_HOTPLUG_INT_STATUS (3 << 21)
-#define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21)
-#define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21)
-#define PORTC_HOTPLUG_INT_STATUS (3 << 19)
-#define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19)
-#define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19)
-#define PORTB_HOTPLUG_INT_STATUS (3 << 17)
-#define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17)
-#define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17)
-/* CRT/TV common between gen3+ */
-#define CRT_HOTPLUG_INT_STATUS (1 << 11)
-#define TV_HOTPLUG_INT_STATUS (1 << 10)
-#define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
-#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
-#define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
-#define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
-#define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6)
-#define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5)
-#define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4)
-#define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4)
-
-/* SDVO is different across gen3/4 */
-#define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
-#define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
-/*
- * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
- * since reality corrobates that they're the same as on gen3. But keep these
- * bits here (and the comment!) to help any other lost wanderers back onto the
- * right tracks.
- */
-#define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
-#define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
-#define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
-#define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
-#define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \
- SDVOB_HOTPLUG_INT_STATUS_G4X | \
- SDVOC_HOTPLUG_INT_STATUS_G4X | \
- PORTB_HOTPLUG_INT_STATUS | \
- PORTC_HOTPLUG_INT_STATUS | \
- PORTD_HOTPLUG_INT_STATUS)
-
-#define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \
- SDVOB_HOTPLUG_INT_STATUS_I915 | \
- SDVOC_HOTPLUG_INT_STATUS_I915 | \
- PORTB_HOTPLUG_INT_STATUS | \
- PORTC_HOTPLUG_INT_STATUS | \
- PORTD_HOTPLUG_INT_STATUS)
-
-/* SDVO and HDMI port control.
- * The same register may be used for SDVO or HDMI */
-#define _GEN3_SDVOB 0x61140
-#define _GEN3_SDVOC 0x61160
-#define GEN3_SDVOB _MMIO(_GEN3_SDVOB)
-#define GEN3_SDVOC _MMIO(_GEN3_SDVOC)
-#define GEN4_HDMIB GEN3_SDVOB
-#define GEN4_HDMIC GEN3_SDVOC
-#define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140)
-#define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160)
-#define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C)
-#define PCH_SDVOB _MMIO(0xe1140)
-#define PCH_HDMIB PCH_SDVOB
-#define PCH_HDMIC _MMIO(0xe1150)
-#define PCH_HDMID _MMIO(0xe1160)
-
-#define PORT_DFT_I9XX _MMIO(0x61150)
-#define DC_BALANCE_RESET (1 << 25)
-#define PORT_DFT2_G4X(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154)
-#define DC_BALANCE_RESET_VLV (1 << 31)
-#define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0))
-#define PIPE_C_SCRAMBLE_RESET REG_BIT(14) /* chv */
-#define PIPE_B_SCRAMBLE_RESET REG_BIT(1)
-#define PIPE_A_SCRAMBLE_RESET REG_BIT(0)
-
-/* Gen 3 SDVO bits: */
-#define SDVO_ENABLE (1 << 31)
-#define SDVO_PIPE_SEL_SHIFT 30
-#define SDVO_PIPE_SEL_MASK (1 << 30)
-#define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
-#define SDVO_STALL_SELECT (1 << 29)
-#define SDVO_INTERRUPT_ENABLE (1 << 26)
-/*
- * 915G/GM SDVO pixel multiplier.
- * Programmed value is multiplier - 1, up to 5x.
- * \sa DPLL_MD_UDI_MULTIPLIER_MASK
- */
-#define SDVO_PORT_MULTIPLY_MASK (7 << 23)
-#define SDVO_PORT_MULTIPLY_SHIFT 23
-#define SDVO_PHASE_SELECT_MASK (15 << 19)
-#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
-#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
-#define SDVOC_GANG_MODE (1 << 16) /* Port C only */
-#define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */
-#define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */
-#define SDVO_DETECTED (1 << 2)
-/* Bits to be preserved when writing */
-#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
- SDVO_INTERRUPT_ENABLE)
-#define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
-
-/* Gen 4 SDVO/HDMI bits: */
-#define SDVO_COLOR_FORMAT_8bpc (0 << 26)
-#define SDVO_COLOR_FORMAT_MASK (7 << 26)
-#define SDVO_ENCODING_SDVO (0 << 10)
-#define SDVO_ENCODING_HDMI (2 << 10)
-#define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */
-#define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */
-#define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */
-#define HDMI_AUDIO_ENABLE (1 << 6) /* HDMI only */
-/* VSYNC/HSYNC bits new with 965, default is to be set */
-#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
-#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
-
-/* Gen 5 (IBX) SDVO/HDMI bits: */
-#define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */
-#define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */
-
-/* Gen 6 (CPT) SDVO/HDMI bits: */
-#define SDVO_PIPE_SEL_SHIFT_CPT 29
-#define SDVO_PIPE_SEL_MASK_CPT (3 << 29)
-#define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
-
-/* CHV SDVO/HDMI bits: */
-#define SDVO_PIPE_SEL_SHIFT_CHV 24
-#define SDVO_PIPE_SEL_MASK_CHV (3 << 24)
-#define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24)
-
-/* Video Data Island Packet control */
-#define VIDEO_DIP_DATA _MMIO(0x61178)
-/* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC
- * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
- * of the infoframe structure specified by CEA-861. */
-#define VIDEO_DIP_DATA_SIZE 32
-#define VIDEO_DIP_ASYNC_DATA_SIZE 36
-#define VIDEO_DIP_GMP_DATA_SIZE 36
-#define VIDEO_DIP_VSC_DATA_SIZE 36
-#define VIDEO_DIP_PPS_DATA_SIZE 132
-#define VIDEO_DIP_CTL _MMIO(0x61170)
-/* Pre HSW: */
-#define VIDEO_DIP_ENABLE (1 << 31)
-#define VIDEO_DIP_PORT(port) ((port) << 29)
-#define VIDEO_DIP_PORT_MASK (3 << 29)
-#define VIDEO_DIP_ENABLE_GCP (1 << 25) /* ilk+ */
-#define VIDEO_DIP_ENABLE_AVI (1 << 21)
-#define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
-#define VIDEO_DIP_ENABLE_GAMUT (4 << 21) /* ilk+ */
-#define VIDEO_DIP_ENABLE_SPD (8 << 21)
-#define VIDEO_DIP_SELECT_AVI (0 << 19)
-#define VIDEO_DIP_SELECT_VENDOR (1 << 19)
-#define VIDEO_DIP_SELECT_GAMUT (2 << 19)
-#define VIDEO_DIP_SELECT_SPD (3 << 19)
-#define VIDEO_DIP_SELECT_MASK (3 << 19)
-#define VIDEO_DIP_FREQ_ONCE (0 << 16)
-#define VIDEO_DIP_FREQ_VSYNC (1 << 16)
-#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
-#define VIDEO_DIP_FREQ_MASK (3 << 16)
-/* HSW and later: */
-#define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28)
-#define PSR_VSC_BIT_7_SET (1 << 27)
-#define VSC_SELECT_MASK (0x3 << 25)
-#define VSC_SELECT_SHIFT 25
-#define VSC_DIP_HW_HEA_DATA (0 << 25)
-#define VSC_DIP_HW_HEA_SW_DATA (1 << 25)
-#define VSC_DIP_HW_DATA_SW_HEA (2 << 25)
-#define VSC_DIP_SW_HEA_DATA (3 << 25)
-#define VDIP_ENABLE_PPS (1 << 24)
-#define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
-#define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
-#define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
-#define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
-#define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
-#define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
-/* ADL and later: */
-#define VIDEO_DIP_ENABLE_AS_ADL REG_BIT(23)
-
-#define PCH_GTC_CTL _MMIO(0xe7000)
-#define PCH_GTC_ENABLE (1 << 31)
-
-/* Display Port */
-#define DP_A _MMIO(0x64000) /* eDP */
-#define DP_B _MMIO(0x64100)
-#define DP_C _MMIO(0x64200)
-#define DP_D _MMIO(0x64300)
-#define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100)
-#define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200)
-#define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300)
-#define DP_PORT_EN REG_BIT(31)
-#define DP_PIPE_SEL_MASK REG_GENMASK(30, 30)
-#define DP_PIPE_SEL(pipe) REG_FIELD_PREP(DP_PIPE_SEL_MASK, (pipe))
-#define DP_PIPE_SEL_MASK_IVB REG_GENMASK(30, 29)
-#define DP_PIPE_SEL_IVB(pipe) REG_FIELD_PREP(DP_PIPE_SEL_MASK_IVB, (pipe))
-#define DP_PIPE_SEL_SHIFT_CHV 16
-#define DP_PIPE_SEL_MASK_CHV REG_GENMASK(17, 16)
-#define DP_PIPE_SEL_CHV(pipe) REG_FIELD_PREP(DP_PIPE_SEL_MASK_CHV, (pipe))
-#define DP_LINK_TRAIN_MASK REG_GENMASK(29, 28)
-#define DP_LINK_TRAIN_PAT_1 REG_FIELD_PREP(DP_LINK_TRAIN_MASK, 0)
-#define DP_LINK_TRAIN_PAT_2 REG_FIELD_PREP(DP_LINK_TRAIN_MASK, 1)
-#define DP_LINK_TRAIN_PAT_IDLE REG_FIELD_PREP(DP_LINK_TRAIN_MASK, 2)
-#define DP_LINK_TRAIN_OFF REG_FIELD_PREP(DP_LINK_TRAIN_MASK, 3)
-#define DP_LINK_TRAIN_MASK_CPT REG_GENMASK(10, 8)
-#define DP_LINK_TRAIN_PAT_1_CPT REG_FIELD_PREP(DP_LINK_TRAIN_MASK_CPT, 0)
-#define DP_LINK_TRAIN_PAT_2_CPT REG_FIELD_PREP(DP_LINK_TRAIN_MASK_CPT, 1)
-#define DP_LINK_TRAIN_PAT_IDLE_CPT REG_FIELD_PREP(DP_LINK_TRAIN_MASK_CPT, 2)
-#define DP_LINK_TRAIN_OFF_CPT REG_FIELD_PREP(DP_LINK_TRAIN_MASK_CPT, 3)
-#define DP_VOLTAGE_MASK REG_GENMASK(27, 25)
-#define DP_VOLTAGE_0_4 REG_FIELD_PREP(DP_VOLTAGE_MASK, 0)
-#define DP_VOLTAGE_0_6 REG_FIELD_PREP(DP_VOLTAGE_MASK, 1)
-#define DP_VOLTAGE_0_8 REG_FIELD_PREP(DP_VOLTAGE_MASK, 2)
-#define DP_VOLTAGE_1_2 REG_FIELD_PREP(DP_VOLTAGE_MASK, 3)
-#define DP_PRE_EMPHASIS_MASK REG_GENMASK(24, 22)
-#define DP_PRE_EMPHASIS_0 REG_FIELD_PREP(DP_PRE_EMPHASIS_MASK, 0)
-#define DP_PRE_EMPHASIS_3_5 REG_FIELD_PREP(DP_PRE_EMPHASIS_MASK, 1)
-#define DP_PRE_EMPHASIS_6 REG_FIELD_PREP(DP_PRE_EMPHASIS_MASK, 2)
-#define DP_PRE_EMPHASIS_9_5 REG_FIELD_PREP(DP_PRE_EMPHASIS_MASK, 3)
-#define DP_PORT_WIDTH_MASK REG_GENMASK(21, 19)
-#define DP_PORT_WIDTH(width) REG_FIELD_PREP(DP_PORT_WIDTH_MASK, (width) - 1)
-#define DP_ENHANCED_FRAMING REG_BIT(18)
-#define EDP_PLL_FREQ_MASK REG_GENMASK(17, 16)
-#define EDP_PLL_FREQ_270MHZ REG_FIELD_PREP(EDP_PLL_FREQ_MASK, 0)
-#define EDP_PLL_FREQ_162MHZ REG_FIELD_PREP(EDP_PLL_FREQ_MASK, 1)
-#define DP_PORT_REVERSAL REG_BIT(15)
-#define EDP_PLL_ENABLE REG_BIT(14)
-#define DP_CLOCK_OUTPUT_ENABLE REG_BIT(13)
-#define DP_SCRAMBLING_DISABLE REG_BIT(12)
-#define DP_SCRAMBLING_DISABLE_ILK REG_BIT(7)
-#define DP_COLOR_RANGE_16_235 REG_BIT(8)
-#define DP_AUDIO_OUTPUT_ENABLE REG_BIT(6)
-#define DP_SYNC_VS_HIGH REG_BIT(4)
-#define DP_SYNC_HS_HIGH REG_BIT(3)
-#define DP_DETECTED REG_BIT(2)
-
-/*
- * Computing GMCH M and N values for the Display Port link
- *
- * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
- *
- * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
- *
- * The GMCH value is used internally
- *
- * bytes_per_pixel is the number of bytes coming out of the plane,
- * which is after the LUTs, so we want the bytes for our color format.
- * For our current usage, this is always 3, one byte for R, G and B.
- */
-#define _PIPEA_DATA_M_G4X 0x70050
-#define _PIPEB_DATA_M_G4X 0x71050
-#define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
-/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
-#define TU_SIZE_MASK REG_GENMASK(30, 25)
-#define TU_SIZE(x) REG_FIELD_PREP(TU_SIZE_MASK, (x) - 1) /* default size 64 */
-#define DATA_LINK_M_N_MASK REG_GENMASK(23, 0)
-#define DATA_LINK_N_MAX (0x800000)
-
-#define _PIPEA_DATA_N_G4X 0x70054
-#define _PIPEB_DATA_N_G4X 0x71054
-#define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
-
-/*
- * Computing Link M and N values for the Display Port link
- *
- * Link M / N = pixel_clock / ls_clk
- *
- * (the DP spec calls pixel_clock the 'strm_clk')
- *
- * The Link value is transmitted in the Main Stream
- * Attributes and VB-ID.
- */
-#define _PIPEA_LINK_M_G4X 0x70060
-#define _PIPEB_LINK_M_G4X 0x71060
-#define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
-
-#define _PIPEA_LINK_N_G4X 0x70064
-#define _PIPEB_LINK_N_G4X 0x71064
-#define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
-
-/* Pipe A */
-#define _PIPEADSL 0x70000
-#define PIPEDSL(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEADSL)
-#define PIPEDSL_CURR_FIELD REG_BIT(31) /* ctg+ */
-#define PIPEDSL_LINE_MASK REG_GENMASK(19, 0)
-
-#define _TRANSACONF 0x70008
-#define TRANSCONF(dev_priv, trans) _MMIO_PIPE2(dev_priv, (trans), _TRANSACONF)
-#define TRANSCONF_ENABLE REG_BIT(31)
-#define TRANSCONF_DOUBLE_WIDE REG_BIT(30) /* pre-i965 */
-#define TRANSCONF_STATE_ENABLE REG_BIT(30) /* i965+ */
-#define TRANSCONF_DSI_PLL_LOCKED REG_BIT(29) /* vlv & pipe A only */
-#define TRANSCONF_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* pre-hsw */
-#define TRANSCONF_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANSCONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */
-#define TRANSCONF_PIPE_LOCKED REG_BIT(25)
-#define TRANSCONF_FORCE_BORDER REG_BIT(25)
-#define TRANSCONF_GAMMA_MODE_MASK_I9XX REG_BIT(24) /* gmch */
-#define TRANSCONF_GAMMA_MODE_MASK_ILK REG_GENMASK(25, 24) /* ilk-ivb */
-#define TRANSCONF_GAMMA_MODE_8BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 0)
-#define TRANSCONF_GAMMA_MODE_10BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 1)
-#define TRANSCONF_GAMMA_MODE_12BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */
-#define TRANSCONF_GAMMA_MODE_SPLIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 3) /* ivb */
-#define TRANSCONF_GAMMA_MODE(x) REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, (x)) /* pass in GAMMA_MODE_MODE_* */
-#define TRANSCONF_INTERLACE_MASK REG_GENMASK(23, 21) /* gen3+ */
-#define TRANSCONF_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 0)
-#define TRANSCONF_INTERLACE_W_SYNC_SHIFT_PANEL REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 4) /* gen4 only */
-#define TRANSCONF_INTERLACE_W_SYNC_SHIFT REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 5) /* gen4 only */
-#define TRANSCONF_INTERLACE_W_FIELD_INDICATION REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 6)
-#define TRANSCONF_INTERLACE_FIELD_0_ONLY REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 7) /* gen3 only */
-/*
- * ilk+: PF/D=progressive fetch/display, IF/D=interlaced fetch/display,
- * DBL=power saving pixel doubling, PF-ID* requires panel fitter
- */
-#define TRANSCONF_INTERLACE_MASK_ILK REG_GENMASK(23, 21) /* ilk+ */
-#define TRANSCONF_INTERLACE_MASK_HSW REG_GENMASK(22, 21) /* hsw+ */
-#define TRANSCONF_INTERLACE_PF_PD_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 0)
-#define TRANSCONF_INTERLACE_PF_ID_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 1)
-#define TRANSCONF_INTERLACE_IF_ID_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 3)
-#define TRANSCONF_INTERLACE_IF_ID_DBL_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 4) /* ilk/snb only */
-#define TRANSCONF_INTERLACE_PF_ID_DBL_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 5) /* ilk/snb only */
-#define TRANSCONF_REFRESH_RATE_ALT_ILK REG_BIT(20)
-#define TRANSCONF_MSA_TIMING_DELAY_MASK REG_GENMASK(19, 18) /* ilk/snb/ivb */
-#define TRANSCONF_MSA_TIMING_DELAY(x) REG_FIELD_PREP(TRANSCONF_MSA_TIMING_DELAY_MASK, (x))
-#define TRANSCONF_CXSR_DOWNCLOCK REG_BIT(16)
-#define TRANSCONF_WGC_ENABLE REG_BIT(15) /* vlv/chv only */
-#define TRANSCONF_REFRESH_RATE_ALT_VLV REG_BIT(14)
-#define TRANSCONF_COLOR_RANGE_SELECT REG_BIT(13)
-#define TRANSCONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12, 11) /* ilk-ivb */
-#define TRANSCONF_OUTPUT_COLORSPACE_RGB REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */
-#define TRANSCONF_OUTPUT_COLORSPACE_YUV601 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */
-#define TRANSCONF_OUTPUT_COLORSPACE_YUV709 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */
-#define TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW REG_BIT(11) /* hsw only */
-#define TRANSCONF_BPC_MASK REG_GENMASK(7, 5) /* ctg-ivb */
-#define TRANSCONF_BPC_8 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 0)
-#define TRANSCONF_BPC_10 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 1)
-#define TRANSCONF_BPC_6 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 2)
-#define TRANSCONF_BPC_12 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 3)
-#define TRANSCONF_DITHER_EN REG_BIT(4)
-#define TRANSCONF_DITHER_TYPE_MASK REG_GENMASK(3, 2)
-#define TRANSCONF_DITHER_TYPE_SP REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 0)
-#define TRANSCONF_DITHER_TYPE_ST1 REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 1)
-#define TRANSCONF_DITHER_TYPE_ST2 REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 2)
-#define TRANSCONF_DITHER_TYPE_TEMP REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 3)
-#define TRANSCONF_PIXEL_COUNT_SCALING_MASK REG_GENMASK(1, 0)
-#define TRANSCONF_PIXEL_COUNT_SCALING_X4 1
-
#define _PIPEASTAT 0x70024
#define PIPESTAT(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT)
#define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31)
@@ -1604,50 +842,6 @@
#define PIPESTAT_INT_ENABLE_MASK 0x7fff0000
#define PIPESTAT_INT_STATUS_MASK 0x0000ffff
-#define _PIPE_ARB_CTL_A 0x70028 /* icl+ */
-#define PIPE_ARB_CTL(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPE_ARB_CTL_A)
-#define PIPE_ARB_USE_PROG_SLOTS REG_BIT(13)
-
-#define _PIPE_MISC_A 0x70030
-#define _PIPE_MISC_B 0x71030
-#define PIPE_MISC(pipe) _MMIO_PIPE(pipe, _PIPE_MISC_A, _PIPE_MISC_B)
-#define PIPE_MISC_YUV420_ENABLE REG_BIT(27) /* glk+ */
-#define PIPE_MISC_YUV420_MODE_FULL_BLEND REG_BIT(26) /* glk+ */
-#define PIPE_MISC_HDR_MODE_PRECISION REG_BIT(23) /* icl+ */
-#define PIPE_MISC_PSR_MASK_PRIMARY_FLIP REG_BIT(23) /* bdw */
-#define PIPE_MISC_PSR_MASK_SPRITE_ENABLE REG_BIT(22) /* bdw */
-#define PIPE_MISC_PSR_MASK_PIPE_REG_WRITE REG_BIT(21) /* skl+ */
-#define PIPE_MISC_PSR_MASK_CURSOR_MOVE REG_BIT(21) /* bdw */
-#define PIPE_MISC_PSR_MASK_VBLANK_VSYNC_INT REG_BIT(20)
-#define PIPE_MISC_OUTPUT_COLORSPACE_YUV REG_BIT(11)
-#define PIPE_MISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */
-/*
- * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with
- * valid values of: 6, 8, 10 BPC.
- * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of:
- * 6, 8, 10, 12 BPC.
- */
-#define PIPE_MISC_BPC_MASK REG_GENMASK(7, 5)
-#define PIPE_MISC_BPC_8 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 0)
-#define PIPE_MISC_BPC_10 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 1)
-#define PIPE_MISC_BPC_6 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 2)
-#define PIPE_MISC_BPC_12_ADLP REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 4) /* adlp+ */
-#define PIPE_MISC_DITHER_ENABLE REG_BIT(4)
-#define PIPE_MISC_DITHER_TYPE_MASK REG_GENMASK(3, 2)
-#define PIPE_MISC_DITHER_TYPE_SP REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 0)
-#define PIPE_MISC_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 1)
-#define PIPE_MISC_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 2)
-#define PIPE_MISC_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 3)
-
-#define _PIPE_MISC2_A 0x7002C
-#define _PIPE_MISC2_B 0x7102C
-#define PIPE_MISC2(pipe) _MMIO_PIPE(pipe, _PIPE_MISC2_A, _PIPE_MISC2_B)
-#define PIPE_MISC2_BUBBLE_COUNTER_MASK REG_GENMASK(31, 24)
-#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 80)
-#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 20)
-#define PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK REG_GENMASK(2, 0) /* tgl+ */
-#define PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id) REG_FIELD_PREP(PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK, (plane_id))
-
#define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028)
#define PIPEB_LINE_COMPARE_INT_EN REG_BIT(29)
#define PIPEB_HLINE_INT_EN REG_BIT(28)
@@ -1669,141 +863,8 @@
#define SPRITEE_FLIPDONE_INT_EN REG_BIT(9)
#define PLANEC_FLIPDONE_INT_EN REG_BIT(8)
-#define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
-#define DPINVGTT_EN_MASK_CHV REG_GENMASK(27, 16)
-#define DPINVGTT_EN_MASK_VLV REG_GENMASK(23, 16)
-#define SPRITEF_INVALID_GTT_INT_EN REG_BIT(27)
-#define SPRITEE_INVALID_GTT_INT_EN REG_BIT(26)
-#define PLANEC_INVALID_GTT_INT_EN REG_BIT(25)
-#define CURSORC_INVALID_GTT_INT_EN REG_BIT(24)
-#define CURSORB_INVALID_GTT_INT_EN REG_BIT(23)
-#define CURSORA_INVALID_GTT_INT_EN REG_BIT(22)
-#define SPRITED_INVALID_GTT_INT_EN REG_BIT(21)
-#define SPRITEC_INVALID_GTT_INT_EN REG_BIT(20)
-#define PLANEB_INVALID_GTT_INT_EN REG_BIT(19)
-#define SPRITEB_INVALID_GTT_INT_EN REG_BIT(18)
-#define SPRITEA_INVALID_GTT_INT_EN REG_BIT(17)
-#define PLANEA_INVALID_GTT_INT_EN REG_BIT(16)
-#define DPINVGTT_STATUS_MASK_CHV REG_GENMASK(11, 0)
-#define DPINVGTT_STATUS_MASK_VLV REG_GENMASK(7, 0)
-#define SPRITEF_INVALID_GTT_STATUS REG_BIT(11)
-#define SPRITEE_INVALID_GTT_STATUS REG_BIT(10)
-#define PLANEC_INVALID_GTT_STATUS REG_BIT(9)
-#define CURSORC_INVALID_GTT_STATUS REG_BIT(8)
-#define CURSORB_INVALID_GTT_STATUS REG_BIT(7)
-#define CURSORA_INVALID_GTT_STATUS REG_BIT(6)
-#define SPRITED_INVALID_GTT_STATUS REG_BIT(5)
-#define SPRITEC_INVALID_GTT_STATUS REG_BIT(4)
-#define PLANEB_INVALID_GTT_STATUS REG_BIT(3)
-#define SPRITEB_INVALID_GTT_STATUS REG_BIT(2)
-#define SPRITEA_INVALID_GTT_STATUS REG_BIT(1)
-#define PLANEA_INVALID_GTT_STATUS REG_BIT(0)
-
-#define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400)
-#define CBR_PND_DEADLINE_DISABLE (1 << 31)
-#define CBR_PWM_CLOCK_MUX_SELECT (1 << 30)
-
-#define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450)
-#define CBR_DPLLBMD_PIPE(pipe) (1 << (7 + (pipe) * 11)) /* pipes B and C */
-
-/*
- * The two pipe frame counter registers are not synchronized, so
- * reading a stable value is somewhat tricky. The following code
- * should work:
- *
- * do {
- * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
- * PIPE_FRAME_HIGH_SHIFT;
- * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
- * PIPE_FRAME_LOW_SHIFT);
- * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
- * PIPE_FRAME_HIGH_SHIFT);
- * } while (high1 != high2);
- * frame = (high1 << 8) | low1;
- */
-#define _PIPEAFRAMEHIGH 0x70040
-#define PIPEFRAME(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEHIGH)
-#define PIPE_FRAME_HIGH_MASK 0x0000ffff
-#define PIPE_FRAME_HIGH_SHIFT 0
-
-#define _PIPEAFRAMEPIXEL 0x70044
-#define PIPEFRAMEPIXEL(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEPIXEL)
-#define PIPE_FRAME_LOW_MASK 0xff000000
-#define PIPE_FRAME_LOW_SHIFT 24
-#define PIPE_PIXEL_MASK 0x00ffffff
-#define PIPE_PIXEL_SHIFT 0
-
-/* GM45+ just has to be different */
-#define _PIPEA_FRMCOUNT_G4X 0x70040
-#define PIPE_FRMCOUNT_G4X(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FRMCOUNT_G4X)
-
-#define _PIPEA_FLIPCOUNT_G4X 0x70044
-#define PIPE_FLIPCOUNT_G4X(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FLIPCOUNT_G4X)
-
-/* CHV pipe B blender */
-#define _CHV_BLEND_A 0x60a00
-#define CHV_BLEND(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _CHV_BLEND_A)
-#define CHV_BLEND_MASK REG_GENMASK(31, 30)
-#define CHV_BLEND_LEGACY REG_FIELD_PREP(CHV_BLEND_MASK, 0)
-#define CHV_BLEND_ANDROID REG_FIELD_PREP(CHV_BLEND_MASK, 1)
-#define CHV_BLEND_MPO REG_FIELD_PREP(CHV_BLEND_MASK, 2)
-
-#define _CHV_CANVAS_A 0x60a04
-#define CHV_CANVAS(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _CHV_CANVAS_A)
-#define CHV_CANVAS_RED_MASK REG_GENMASK(29, 20)
-#define CHV_CANVAS_GREEN_MASK REG_GENMASK(19, 10)
-#define CHV_CANVAS_BLUE_MASK REG_GENMASK(9, 0)
-
-/* Display/Sprite base address macros */
-#define DISP_BASEADDR_MASK (0xfffff000)
-#define I915_LO_DISPBASE(val) ((val) & ~DISP_BASEADDR_MASK)
-#define I915_HI_DISPBASE(val) ((val) & DISP_BASEADDR_MASK)
-
-/*
- * VBIOS flags
- * gen2:
- * [00:06] alm,mgm
- * [10:16] all
- * [30:32] alm,mgm
- * gen3+:
- * [00:0f] all
- * [10:1f] all
- * [30:32] all
- */
-#define SWF0(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4)
-#define SWF1(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4)
-#define SWF3(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
-#define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)
-
-/* VBIOS regs */
-#define VGACNTRL _MMIO(0x71400)
-# define VGA_DISP_DISABLE (1 << 31)
-# define VGA_2X_MODE (1 << 30)
-# define VGA_PIPE_B_SELECT (1 << 29)
-
-#define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400)
-
/* Ironlake */
-#define CPU_VGACNTRL _MMIO(0x41000)
-
-#define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030)
-#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
-#define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */
-#define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */
-#define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */
-#define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */
-#define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */
-#define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0)
-#define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0)
-#define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0)
-#define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0)
-
-/* refresh rate hardware control */
-#define RR_HW_CTL _MMIO(0x45300)
-#define RR_HW_LOW_POWER_FRAMES_MASK 0xff
-#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
-
#define PCH_3DCGDIS0 _MMIO(0x46020)
# define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
# define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
@@ -1811,211 +872,6 @@
#define PCH_3DCGDIS1 _MMIO(0x46024)
# define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
-#define _PIPEA_DATA_M1 0x60030
-#define _PIPEB_DATA_M1 0x61030
-#define PIPE_DATA_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M1)
-
-#define _PIPEA_DATA_N1 0x60034
-#define _PIPEB_DATA_N1 0x61034
-#define PIPE_DATA_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N1)
-
-#define _PIPEA_DATA_M2 0x60038
-#define _PIPEB_DATA_M2 0x61038
-#define PIPE_DATA_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M2)
-
-#define _PIPEA_DATA_N2 0x6003c
-#define _PIPEB_DATA_N2 0x6103c
-#define PIPE_DATA_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2)
-
-#define _PIPEA_LINK_M1 0x60040
-#define _PIPEB_LINK_M1 0x61040
-#define PIPE_LINK_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1)
-
-#define _PIPEA_LINK_N1 0x60044
-#define _PIPEB_LINK_N1 0x61044
-#define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1)
-
-#define _PIPEA_LINK_M2 0x60048
-#define _PIPEB_LINK_M2 0x61048
-#define PIPE_LINK_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M2)
-
-#define _PIPEA_LINK_N2 0x6004c
-#define _PIPEB_LINK_N2 0x6104c
-#define PIPE_LINK_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N2)
-
-/*
- * Skylake scalers
- */
-#define _ID(id, a, b) _PICK_EVEN(id, a, b)
-#define _PS_1A_CTRL 0x68180
-#define _PS_2A_CTRL 0x68280
-#define _PS_1B_CTRL 0x68980
-#define _PS_2B_CTRL 0x68A80
-#define _PS_1C_CTRL 0x69180
-#define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \
- _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \
- _ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
-#define PS_SCALER_EN REG_BIT(31)
-#define PS_SCALER_TYPE_MASK REG_BIT(30) /* icl+ */
-#define PS_SCALER_TYPE_NON_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 0)
-#define PS_SCALER_TYPE_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 1)
-#define SKL_PS_SCALER_MODE_MASK REG_GENMASK(29, 28) /* skl/bxt */
-#define SKL_PS_SCALER_MODE_DYN REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 0)
-#define SKL_PS_SCALER_MODE_HQ REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 1)
-#define SKL_PS_SCALER_MODE_NV12 REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 2)
-#define PS_SCALER_MODE_MASK REG_BIT(29) /* glk-tgl */
-#define PS_SCALER_MODE_NORMAL REG_FIELD_PREP(PS_SCALER_MODE_MASK, 0)
-#define PS_SCALER_MODE_PLANAR REG_FIELD_PREP(PS_SCALER_MODE_MASK, 1)
-#define PS_ADAPTIVE_FILTERING_EN REG_BIT(28) /* icl+ */
-#define PS_BINDING_MASK REG_GENMASK(27, 25)
-#define PS_BINDING_PIPE REG_FIELD_PREP(PS_BINDING_MASK, 0)
-#define PS_BINDING_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_MASK, (plane_id) + 1)
-#define PS_FILTER_MASK REG_GENMASK(24, 23)
-#define PS_FILTER_MEDIUM REG_FIELD_PREP(PS_FILTER_MASK, 0)
-#define PS_FILTER_PROGRAMMED REG_FIELD_PREP(PS_FILTER_MASK, 1)
-#define PS_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_FILTER_MASK, 2)
-#define PS_FILTER_BILINEAR REG_FIELD_PREP(PS_FILTER_MASK, 3)
-#define PS_ADAPTIVE_FILTER_MASK REG_BIT(22) /* icl+ */
-#define PS_ADAPTIVE_FILTER_MEDIUM REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 0)
-#define PS_ADAPTIVE_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 1)
-#define PS_PIPE_SCALER_LOC_MASK REG_BIT(21) /* icl+ */
-#define PS_PIPE_SCALER_LOC_AFTER_OUTPUT_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 0) /* non-linear */
-#define PS_PIPE_SCALER_LOC_AFTER_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 1) /* linear */
-#define PS_VERT3TAP REG_BIT(21) /* skl/bxt */
-#define PS_VERT_INT_INVERT_FIELD REG_BIT(20)
-#define PS_PROG_SCALE_FACTOR REG_BIT(19) /* tgl+ */
-#define PS_PWRUP_PROGRESS REG_BIT(17)
-#define PS_V_FILTER_BYPASS REG_BIT(8)
-#define PS_VADAPT_EN REG_BIT(7) /* skl/bxt */
-#define PS_VADAPT_MODE_MASK REG_GENMASK(6, 5) /* skl/bxt */
-#define PS_VADAPT_MODE_LEAST_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 0)
-#define PS_VADAPT_MODE_MOD_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 1)
-#define PS_VADAPT_MODE_MOST_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 3)
-#define PS_BINDING_Y_MASK REG_GENMASK(7, 5) /* icl-tgl */
-#define PS_BINDING_Y_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_Y_MASK, (plane_id) + 1)
-#define PS_Y_VERT_FILTER_SELECT_MASK REG_BIT(4) /* glk+ */
-#define PS_Y_VERT_FILTER_SELECT(set) REG_FIELD_PREP(PS_Y_VERT_FILTER_SELECT_MASK, (set))
-#define PS_Y_HORZ_FILTER_SELECT_MASK REG_BIT(3) /* glk+ */
-#define PS_Y_HORZ_FILTER_SELECT(set) REG_FIELD_PREP(PS_Y_HORZ_FILTER_SELECT_MASK, (set))
-#define PS_UV_VERT_FILTER_SELECT_MASK REG_BIT(2) /* glk+ */
-#define PS_UV_VERT_FILTER_SELECT(set) REG_FIELD_PREP(PS_UV_VERT_FILTER_SELECT_MASK, (set))
-#define PS_UV_HORZ_FILTER_SELECT_MASK REG_BIT(1) /* glk+ */
-#define PS_UV_HORZ_FILTER_SELECT(set) REG_FIELD_PREP(PS_UV_HORZ_FILTER_SELECT_MASK, (set))
-
-#define _PS_PWR_GATE_1A 0x68160
-#define _PS_PWR_GATE_2A 0x68260
-#define _PS_PWR_GATE_1B 0x68960
-#define _PS_PWR_GATE_2B 0x68A60
-#define _PS_PWR_GATE_1C 0x69160
-#define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \
- _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \
- _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))
-#define PS_PWR_GATE_DIS_OVERRIDE REG_BIT(31)
-#define PS_PWR_GATE_SETTLING_TIME_MASK REG_GENMASK(4, 3)
-#define PS_PWR_GATE_SETTLING_TIME_32 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 0)
-#define PS_PWR_GATE_SETTLING_TIME_64 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 1)
-#define PS_PWR_GATE_SETTLING_TIME_96 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 2)
-#define PS_PWR_GATE_SETTLING_TIME_128 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 3)
-#define PS_PWR_GATE_SLPEN_MASK REG_GENMASK(1, 0)
-#define PS_PWR_GATE_SLPEN_8 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 0)
-#define PS_PWR_GATE_SLPEN_16 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 1)
-#define PS_PWR_GATE_SLPEN_24 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 2)
-#define PS_PWR_GATE_SLPEN_32 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 3)
-
-#define _PS_WIN_POS_1A 0x68170
-#define _PS_WIN_POS_2A 0x68270
-#define _PS_WIN_POS_1B 0x68970
-#define _PS_WIN_POS_2B 0x68A70
-#define _PS_WIN_POS_1C 0x69170
-#define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \
- _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \
- _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))
-#define PS_WIN_XPOS_MASK REG_GENMASK(31, 16)
-#define PS_WIN_XPOS(x) REG_FIELD_PREP(PS_WIN_XPOS_MASK, (x))
-#define PS_WIN_YPOS_MASK REG_GENMASK(15, 0)
-#define PS_WIN_YPOS(y) REG_FIELD_PREP(PS_WIN_YPOS_MASK, (y))
-
-#define _PS_WIN_SZ_1A 0x68174
-#define _PS_WIN_SZ_2A 0x68274
-#define _PS_WIN_SZ_1B 0x68974
-#define _PS_WIN_SZ_2B 0x68A74
-#define _PS_WIN_SZ_1C 0x69174
-#define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \
- _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \
- _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))
-#define PS_WIN_XSIZE_MASK REG_GENMASK(31, 16)
-#define PS_WIN_XSIZE(w) REG_FIELD_PREP(PS_WIN_XSIZE_MASK, (w))
-#define PS_WIN_YSIZE_MASK REG_GENMASK(15, 0)
-#define PS_WIN_YSIZE(h) REG_FIELD_PREP(PS_WIN_YSIZE_MASK, (h))
-
-#define _PS_VSCALE_1A 0x68184
-#define _PS_VSCALE_2A 0x68284
-#define _PS_VSCALE_1B 0x68984
-#define _PS_VSCALE_2B 0x68A84
-#define _PS_VSCALE_1C 0x69184
-#define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \
- _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \
- _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))
-
-#define _PS_HSCALE_1A 0x68190
-#define _PS_HSCALE_2A 0x68290
-#define _PS_HSCALE_1B 0x68990
-#define _PS_HSCALE_2B 0x68A90
-#define _PS_HSCALE_1C 0x69190
-#define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \
- _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \
- _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))
-
-#define _PS_VPHASE_1A 0x68188
-#define _PS_VPHASE_2A 0x68288
-#define _PS_VPHASE_1B 0x68988
-#define _PS_VPHASE_2B 0x68A88
-#define _PS_VPHASE_1C 0x69188
-#define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \
- _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \
- _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))
-#define PS_Y_PHASE_MASK REG_GENMASK(31, 16)
-#define PS_Y_PHASE(x) REG_FIELD_PREP(PS_Y_PHASE_MASK, (x))
-#define PS_UV_RGB_PHASE_MASK REG_GENMASK(15, 0)
-#define PS_UV_RGB_PHASE(x) REG_FIELD_PREP(PS_UV_RGB_PHASE_MASK, (x))
-#define PS_PHASE_MASK (0x7fff << 1) /* u2.13 */
-#define PS_PHASE_TRIP (1 << 0)
-
-#define _PS_HPHASE_1A 0x68194
-#define _PS_HPHASE_2A 0x68294
-#define _PS_HPHASE_1B 0x68994
-#define _PS_HPHASE_2B 0x68A94
-#define _PS_HPHASE_1C 0x69194
-#define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \
- _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \
- _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))
-
-#define _PS_ECC_STAT_1A 0x681D0
-#define _PS_ECC_STAT_2A 0x682D0
-#define _PS_ECC_STAT_1B 0x689D0
-#define _PS_ECC_STAT_2B 0x68AD0
-#define _PS_ECC_STAT_1C 0x691D0
-#define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \
- _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
- _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
-
-#define _PS_COEF_SET0_INDEX_1A 0x68198
-#define _PS_COEF_SET0_INDEX_2A 0x68298
-#define _PS_COEF_SET0_INDEX_1B 0x68998
-#define _PS_COEF_SET0_INDEX_2B 0x68A98
-#define GLK_PS_COEF_INDEX_SET(pipe, id, set) _MMIO_PIPE(pipe, \
- _ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A) + (set) * 8, \
- _ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B) + (set) * 8)
-#define PS_COEF_INDEX_AUTO_INC REG_BIT(10)
-
-#define _PS_COEF_SET0_DATA_1A 0x6819C
-#define _PS_COEF_SET0_DATA_2A 0x6829C
-#define _PS_COEF_SET0_DATA_1B 0x6899C
-#define _PS_COEF_SET0_DATA_2B 0x68A9C
-#define GLK_PS_COEF_DATA_SET(pipe, id, set) _MMIO_PIPE(pipe, \
- _ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + (set) * 8, \
- _ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + (set) * 8)
-
/* Display Internal Timeout Register */
#define RM_TIMEOUT _MMIO(0x42060)
#define RM_TIMEOUT_REG_CAPTURE _MMIO(0x420E0)
@@ -2054,25 +910,6 @@
#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
#define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe)))
-/* More Ivybridge lolz */
-#define DE_ERR_INT_IVB (1 << 30)
-#define DE_GSE_IVB (1 << 29)
-#define DE_PCH_EVENT_IVB (1 << 28)
-#define DE_DP_A_HOTPLUG_IVB (1 << 27)
-#define DE_AUX_CHANNEL_A_IVB (1 << 26)
-#define DE_EDP_PSR_INT_HSW (1 << 19)
-#define DE_SPRITEC_FLIP_DONE_IVB (1 << 14)
-#define DE_PLANEC_FLIP_DONE_IVB (1 << 13)
-#define DE_PIPEC_VBLANK_IVB (1 << 10)
-#define DE_SPRITEB_FLIP_DONE_IVB (1 << 9)
-#define DE_PLANEB_FLIP_DONE_IVB (1 << 8)
-#define DE_PIPEB_VBLANK_IVB (1 << 5)
-#define DE_SPRITEA_FLIP_DONE_IVB (1 << 4)
-#define DE_PLANEA_FLIP_DONE_IVB (1 << 3)
-#define DE_PLANE_FLIP_DONE_IVB(plane) (1 << (3 + 5 * (plane)))
-#define DE_PIPEA_VBLANK_IVB (1 << 0)
-#define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5))
-
#define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */
#define MASTER_INTERRUPT_ENABLE (1 << 31)
@@ -2112,8 +949,6 @@
#define GEN8_GT_BCS_IRQ (1 << 1)
#define GEN8_GT_RCS_IRQ (1 << 0)
-#define XELPD_DISPLAY_ERR_FATAL_MASK _MMIO(0x4421c)
-
#define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
#define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
#define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
@@ -2130,91 +965,6 @@
#define GEN8_VECS_IRQ_SHIFT 0
#define GEN8_WD_IRQ_SHIFT 16
-#define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))
-#define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))
-#define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))
-#define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))
-#define GEN8_PIPE_FIFO_UNDERRUN REG_BIT(31)
-#define GEN8_PIPE_CDCLK_CRC_ERROR REG_BIT(29)
-#define GEN8_PIPE_CDCLK_CRC_DONE REG_BIT(28)
-#define GEN12_PIPEDMC_INTERRUPT REG_BIT(26) /* tgl+ */
-#define GEN12_PIPEDMC_FAULT REG_BIT(25) /* tgl+ */
-#define MTL_PIPEDMC_ATS_FAULT REG_BIT(24) /* mtl+ */
-#define GEN11_PIPE_PLANE7_FAULT REG_BIT(22) /* icl/tgl */
-#define GEN11_PIPE_PLANE6_FAULT REG_BIT(21) /* icl/tgl */
-#define GEN11_PIPE_PLANE5_FAULT REG_BIT(20) /* icl+ */
-#define GEN12_PIPE_VBLANK_UNMOD REG_BIT(19) /* tgl+ */
-#define MTL_PLANE_ATS_FAULT REG_BIT(18) /* mtl+ */
-#define GEN11_PIPE_PLANE7_FLIP_DONE REG_BIT(18) /* icl/tgl */
-#define GEN11_PIPE_PLANE6_FLIP_DONE REG_BIT(17) /* icl/tgl */
-#define GEN11_PIPE_PLANE5_FLIP_DONE REG_BIT(16) /* icl+ */
-#define GEN12_DSB_2_INT REG_BIT(15) /* tgl+ */
-#define GEN12_DSB_1_INT REG_BIT(14) /* tgl+ */
-#define GEN12_DSB_0_INT REG_BIT(13) /* tgl+ */
-#define GEN12_DSB_INT(dsb_id) REG_BIT(13 + (dsb_id))
-#define GEN9_PIPE_CURSOR_FAULT REG_BIT(11) /* skl+ */
-#define GEN9_PIPE_PLANE4_FAULT REG_BIT(10) /* skl+ */
-#define GEN8_PIPE_CURSOR_FAULT REG_BIT(10) /* bdw */
-#define GEN9_PIPE_PLANE3_FAULT REG_BIT(9) /* skl+ */
-#define GEN8_PIPE_SPRITE_FAULT REG_BIT(9) /* bdw */
-#define GEN9_PIPE_PLANE2_FAULT REG_BIT(8) /* skl+ */
-#define GEN8_PIPE_PRIMARY_FAULT REG_BIT(8) /* bdw */
-#define GEN9_PIPE_PLANE1_FAULT REG_BIT(7) /* skl+ */
-#define GEN9_PIPE_PLANE4_FLIP_DONE REG_BIT(6) /* skl+ */
-#define GEN9_PIPE_PLANE3_FLIP_DONE REG_BIT(5) /* skl+ */
-#define GEN8_PIPE_SPRITE_FLIP_DONE REG_BIT(5) /* bdw */
-#define GEN9_PIPE_PLANE2_FLIP_DONE REG_BIT(4) /* skl+ */
-#define GEN8_PIPE_PRIMARY_FLIP_DONE REG_BIT(4) /* bdw */
-#define GEN9_PIPE_PLANE1_FLIP_DONE REG_BIT(3) /* skl+ */
-#define GEN9_PIPE_PLANE_FLIP_DONE(plane_id) \
- REG_BIT(((plane_id) >= PLANE_5 ? 16 - PLANE_5 : 3 - PLANE_1) + (plane_id)) /* skl+ */
-#define GEN8_PIPE_SCAN_LINE_EVENT REG_BIT(2)
-#define GEN8_PIPE_VSYNC REG_BIT(1)
-#define GEN8_PIPE_VBLANK REG_BIT(0)
-
-#define GEN8_DE_PIPE_IRQ_REGS(pipe) I915_IRQ_REGS(GEN8_DE_PIPE_IMR(pipe), \
- GEN8_DE_PIPE_IER(pipe), \
- GEN8_DE_PIPE_IIR(pipe))
-
-#define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A)
-#define _HPD_PIN_TC(hpd_pin) ((hpd_pin) - HPD_PORT_TC1)
-
-#define GEN8_DE_PORT_ISR _MMIO(0x44440)
-#define GEN8_DE_PORT_IMR _MMIO(0x44444)
-#define GEN8_DE_PORT_IIR _MMIO(0x44448)
-#define GEN8_DE_PORT_IER _MMIO(0x4444c)
-#define DSI1_NON_TE (1 << 31)
-#define DSI0_NON_TE (1 << 30)
-#define ICL_AUX_CHANNEL_E (1 << 29)
-#define ICL_AUX_CHANNEL_F (1 << 28)
-#define GEN9_AUX_CHANNEL_D (1 << 27)
-#define GEN9_AUX_CHANNEL_C (1 << 26)
-#define GEN9_AUX_CHANNEL_B (1 << 25)
-#define DSI1_TE (1 << 24)
-#define DSI0_TE (1 << 23)
-#define GEN8_DE_PORT_HOTPLUG(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))
-#define BXT_DE_PORT_HOTPLUG_MASK (GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \
- GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \
- GEN8_DE_PORT_HOTPLUG(HPD_PORT_C))
-#define BDW_DE_PORT_HOTPLUG_MASK GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)
-#define BXT_DE_PORT_GMBUS (1 << 1)
-#define GEN8_AUX_CHANNEL_A (1 << 0)
-#define TGL_DE_PORT_AUX_USBC6 REG_BIT(13)
-#define XELPD_DE_PORT_AUX_DDIE REG_BIT(13)
-#define TGL_DE_PORT_AUX_USBC5 REG_BIT(12)
-#define XELPD_DE_PORT_AUX_DDID REG_BIT(12)
-#define TGL_DE_PORT_AUX_USBC4 REG_BIT(11)
-#define TGL_DE_PORT_AUX_USBC3 REG_BIT(10)
-#define TGL_DE_PORT_AUX_USBC2 REG_BIT(9)
-#define TGL_DE_PORT_AUX_USBC1 REG_BIT(8)
-#define TGL_DE_PORT_AUX_DDIC REG_BIT(2)
-#define TGL_DE_PORT_AUX_DDIB REG_BIT(1)
-#define TGL_DE_PORT_AUX_DDIA REG_BIT(0)
-
-#define GEN8_DE_PORT_IRQ_REGS I915_IRQ_REGS(GEN8_DE_PORT_IMR, \
- GEN8_DE_PORT_IER, \
- GEN8_DE_PORT_IIR)
-
#define GEN8_DE_MISC_ISR _MMIO(0x44460)
#define GEN8_DE_MISC_IMR _MMIO(0x44464)
#define GEN8_DE_MISC_IIR _MMIO(0x44468)
@@ -2226,10 +976,6 @@
#define XELPDP_PMDEMAND_RSP REG_BIT(3)
#define XE2LPD_DBUF_OVERLAP_DETECTED REG_BIT(1)
-#define GEN8_DE_MISC_IRQ_REGS I915_IRQ_REGS(GEN8_DE_MISC_IMR, \
- GEN8_DE_MISC_IER, \
- GEN8_DE_MISC_IIR)
-
#define GEN8_PCU_ISR _MMIO(0x444e0)
#define GEN8_PCU_IMR _MMIO(0x444e4)
#define GEN8_PCU_IIR _MMIO(0x444e8)
@@ -2262,110 +1008,12 @@
#define DG1_MSTR_IRQ REG_BIT(31)
#define DG1_MSTR_TILE(t) REG_BIT(t)
-#define GEN11_DISPLAY_INT_CTL _MMIO(0x44200)
-#define GEN11_DISPLAY_IRQ_ENABLE (1 << 31)
-#define GEN11_AUDIO_CODEC_IRQ (1 << 24)
-#define GEN11_DE_PCH_IRQ (1 << 23)
-#define GEN11_DE_MISC_IRQ (1 << 22)
-#define GEN11_DE_HPD_IRQ (1 << 21)
-#define GEN11_DE_PORT_IRQ (1 << 20)
-#define GEN11_DE_PIPE_C (1 << 18)
-#define GEN11_DE_PIPE_B (1 << 17)
-#define GEN11_DE_PIPE_A (1 << 16)
-
-#define GEN11_DE_HPD_ISR _MMIO(0x44470)
-#define GEN11_DE_HPD_IMR _MMIO(0x44474)
-#define GEN11_DE_HPD_IIR _MMIO(0x44478)
-#define GEN11_DE_HPD_IER _MMIO(0x4447c)
-#define GEN11_TC_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin))
-#define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(HPD_PORT_TC6) | \
- GEN11_TC_HOTPLUG(HPD_PORT_TC5) | \
- GEN11_TC_HOTPLUG(HPD_PORT_TC4) | \
- GEN11_TC_HOTPLUG(HPD_PORT_TC3) | \
- GEN11_TC_HOTPLUG(HPD_PORT_TC2) | \
- GEN11_TC_HOTPLUG(HPD_PORT_TC1))
-#define GEN11_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin))
-#define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(HPD_PORT_TC6) | \
- GEN11_TBT_HOTPLUG(HPD_PORT_TC5) | \
- GEN11_TBT_HOTPLUG(HPD_PORT_TC4) | \
- GEN11_TBT_HOTPLUG(HPD_PORT_TC3) | \
- GEN11_TBT_HOTPLUG(HPD_PORT_TC2) | \
- GEN11_TBT_HOTPLUG(HPD_PORT_TC1))
-
-#define GEN11_DE_HPD_IRQ_REGS I915_IRQ_REGS(GEN11_DE_HPD_IMR, \
- GEN11_DE_HPD_IER, \
- GEN11_DE_HPD_IIR)
-
-#define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030)
-#define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038)
-#define GEN11_HOTPLUG_CTL_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4))
-#define GEN11_HOTPLUG_CTL_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4))
-#define GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4))
-#define GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin) (0 << (_HPD_PIN_TC(hpd_pin) * 4))
-
-#define PICAINTERRUPT_ISR _MMIO(0x16FE50)
-#define PICAINTERRUPT_IMR _MMIO(0x16FE54)
-#define PICAINTERRUPT_IIR _MMIO(0x16FE58)
-#define PICAINTERRUPT_IER _MMIO(0x16FE5C)
-#define XELPDP_DP_ALT_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin))
-#define XELPDP_DP_ALT_HOTPLUG_MASK REG_GENMASK(19, 16)
-#define XELPDP_AUX_TC(hpd_pin) REG_BIT(8 + _HPD_PIN_TC(hpd_pin))
-#define XELPDP_AUX_TC_MASK REG_GENMASK(11, 8)
-#define XE2LPD_AUX_DDI(hpd_pin) REG_BIT(6 + _HPD_PIN_DDI(hpd_pin))
-#define XE2LPD_AUX_DDI_MASK REG_GENMASK(7, 6)
-#define XELPDP_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin))
-#define XELPDP_TBT_HOTPLUG_MASK REG_GENMASK(3, 0)
-
-#define PICAINTERRUPT_IRQ_REGS I915_IRQ_REGS(PICAINTERRUPT_IMR, \
- PICAINTERRUPT_IER, \
- PICAINTERRUPT_IIR)
-
-#define XELPDP_PORT_HOTPLUG_CTL(hpd_pin) _MMIO(0x16F270 + (_HPD_PIN_TC(hpd_pin) * 0x200))
-#define XELPDP_TBT_HOTPLUG_ENABLE REG_BIT(6)
-#define XELPDP_TBT_HPD_LONG_DETECT REG_BIT(5)
-#define XELPDP_TBT_HPD_SHORT_DETECT REG_BIT(4)
-#define XELPDP_DP_ALT_HOTPLUG_ENABLE REG_BIT(2)
-#define XELPDP_DP_ALT_HPD_LONG_DETECT REG_BIT(1)
-#define XELPDP_DP_ALT_HPD_SHORT_DETECT REG_BIT(0)
-
-#define XELPDP_INITIATE_PMDEMAND_REQUEST(dword) _MMIO(0x45230 + 4 * (dword))
-#define XELPDP_PMDEMAND_QCLK_GV_BW_MASK REG_GENMASK(31, 16)
-#define XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK REG_GENMASK(14, 12)
-#define XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK REG_GENMASK(11, 8)
-#define XE3_PMDEMAND_PIPES_MASK REG_GENMASK(7, 4)
-#define XELPDP_PMDEMAND_PIPES_MASK REG_GENMASK(7, 6)
-#define XELPDP_PMDEMAND_DBUFS_MASK REG_GENMASK(5, 4)
-#define XELPDP_PMDEMAND_PHYS_MASK REG_GENMASK(2, 0)
-
-#define XELPDP_PMDEMAND_REQ_ENABLE REG_BIT(31)
-#define XELPDP_PMDEMAND_CDCLK_FREQ_MASK REG_GENMASK(30, 20)
-#define XELPDP_PMDEMAND_DDICLK_FREQ_MASK REG_GENMASK(18, 8)
-#define XELPDP_PMDEMAND_SCALERS_MASK REG_GENMASK(6, 4)
-#define XELPDP_PMDEMAND_PLLS_MASK REG_GENMASK(2, 0)
-
-#define GEN12_DCPR_STATUS_1 _MMIO(0x46440)
-#define XELPDP_PMDEMAND_INFLIGHT_STATUS REG_BIT(26)
-
#define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004)
/* Required on all Ironlake and Sandybridge according to the B-Spec. */
#define ILK_ELPIN_409_SELECT REG_BIT(25)
#define ILK_DPARB_GATE REG_BIT(22)
#define ILK_VSDPFD_FULL REG_BIT(21)
-#define FUSE_STRAP _MMIO(0x42014)
-#define ILK_INTERNAL_GRAPHICS_DISABLE REG_BIT(31)
-#define ILK_INTERNAL_DISPLAY_DISABLE REG_BIT(30)
-#define ILK_DISPLAY_DEBUG_DISABLE REG_BIT(29)
-#define IVB_PIPE_C_DISABLE REG_BIT(28)
-#define ILK_HDCP_DISABLE REG_BIT(25)
-#define ILK_eDP_A_DISABLE REG_BIT(24)
-#define HSW_CDCLK_LIMIT REG_BIT(24)
-#define ILK_DESKTOP REG_BIT(23)
-#define HSW_CPU_SSC_ENABLE REG_BIT(21)
-
-#define FUSE_STRAP3 _MMIO(0x42020)
-#define HSW_REF_CLK_SELECT REG_BIT(1)
-
#define ILK_DSPCLK_GATE_D _MMIO(0x42020)
#define ILK_VRHUNIT_CLOCK_GATE_DISABLE REG_BIT(28)
#define ILK_DPFCUNIT_CLOCK_GATE_DISABLE REG_BIT(9)
@@ -2390,25 +1038,6 @@
#define CHICKEN_PAR2_1 _MMIO(0x42090)
#define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT REG_BIT(14)
-#define CHICKEN_MISC_2 _MMIO(0x42084)
-#define CHICKEN_MISC_DISABLE_DPT REG_BIT(30) /* adl,dg2 */
-#define BMG_DARB_HALF_BLK_END_BURST REG_BIT(27)
-#define KBL_ARB_FILL_SPARE_14 REG_BIT(14)
-#define KBL_ARB_FILL_SPARE_13 REG_BIT(13)
-#define GLK_CL2_PWR_DOWN REG_BIT(12)
-#define GLK_CL1_PWR_DOWN REG_BIT(11)
-#define GLK_CL0_PWR_DOWN REG_BIT(10)
-
-#define CHICKEN_MISC_3 _MMIO(0x42088)
-#define DP_MST_DPT_DPTP_ALIGN_WA(trans) REG_BIT(9 + (trans) - TRANSCODER_A)
-#define DP_MST_SHORT_HBLANK_WA(trans) REG_BIT(5 + (trans) - TRANSCODER_A)
-#define DP_MST_FEC_BS_JITTER_WA(trans) REG_BIT(0 + (trans) - TRANSCODER_A)
-
-#define CHICKEN_MISC_4 _MMIO(0x4208c)
-#define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13)
-#define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0)
-#define CHICKEN_FBC_STRIDE(x) REG_FIELD_PREP(CHICKEN_FBC_STRIDE_MASK, (x))
-
#define _CHICKEN_PIPESL_1_A 0x420b0
#define _CHICKEN_PIPESL_1_B 0x420b4
#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
@@ -2432,72 +1061,11 @@
#define SKL_PLANE1_STRETCH_MAX_X1 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3)
#define BDW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(0) /* bdw */
-#define _CHICKEN_TRANS_A 0x420c0
-#define _CHICKEN_TRANS_B 0x420c4
-#define _CHICKEN_TRANS_C 0x420c8
-#define _CHICKEN_TRANS_EDP 0x420cc
-#define _CHICKEN_TRANS_D 0x420d8
-#define _CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \
- [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \
- [TRANSCODER_A] = _CHICKEN_TRANS_A, \
- [TRANSCODER_B] = _CHICKEN_TRANS_B, \
- [TRANSCODER_C] = _CHICKEN_TRANS_C, \
- [TRANSCODER_D] = _CHICKEN_TRANS_D))
-#define _MTL_CHICKEN_TRANS_A 0x604e0
-#define _MTL_CHICKEN_TRANS_B 0x614e0
-#define _MTL_CHICKEN_TRANS(trans) _MMIO_TRANS((trans), \
- _MTL_CHICKEN_TRANS_A, \
- _MTL_CHICKEN_TRANS_B)
-#define CHICKEN_TRANS(display, trans) (DISPLAY_VER(display) >= 14 ? _MTL_CHICKEN_TRANS(trans) : _CHICKEN_TRANS(trans))
-#define PIPE_VBLANK_WITH_DELAY REG_BIT(31) /* tgl+ */
-#define SKL_UNMASK_VBL_TO_PIPE_IN_SRD REG_BIT(30) /* skl+ */
-#define HSW_FRAME_START_DELAY_MASK REG_GENMASK(28, 27)
-#define HSW_FRAME_START_DELAY(x) REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x)
-#define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */
-#define FECSTALL_DIS_DPTSTREAM_DPTTG REG_BIT(23)
-#define DDI_TRAINING_OVERRIDE_ENABLE REG_BIT(19)
-#define ADLP_1_BASED_X_GRANULARITY REG_BIT(18)
-#define DDI_TRAINING_OVERRIDE_VALUE REG_BIT(18)
-#define DDIE_TRAINING_OVERRIDE_ENABLE REG_BIT(17) /* CHICKEN_TRANS_A only */
-#define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /* CHICKEN_TRANS_A only */
-#define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15)
-#define DP_FEC_BS_JITTER_WA REG_BIT(15)
-#define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12)
-#define DP_DSC_INSERT_SF_AT_EOL_WA REG_BIT(4)
-#define HDCP_LINE_REKEY_DISABLE REG_BIT(0)
-
#define DISP_ARB_CTL _MMIO(0x45000)
#define DISP_FBC_MEMORY_WAKE REG_BIT(31)
#define DISP_TILE_SURFACE_SWIZZLING REG_BIT(13)
#define DISP_FBC_WM_DIS REG_BIT(15)
-#define DISP_ARB_CTL2 _MMIO(0x45004)
-#define DISP_DATA_PARTITION_5_6 REG_BIT(6)
-#define DISP_IPC_ENABLE REG_BIT(3)
-
-#define GEN7_MSG_CTL _MMIO(0x45010)
-#define WAIT_FOR_PCH_RESET_ACK (1 << 1)
-#define WAIT_FOR_PCH_FLR_ACK (1 << 0)
-
-#define _BW_BUDDY0_CTL 0x45130
-#define _BW_BUDDY1_CTL 0x45140
-#define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \
- _BW_BUDDY0_CTL, \
- _BW_BUDDY1_CTL))
-#define BW_BUDDY_DISABLE REG_BIT(31)
-#define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16)
-#define BW_BUDDY_TLB_REQ_TIMER(x) REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, x)
-
-#define _BW_BUDDY0_PAGE_MASK 0x45134
-#define _BW_BUDDY1_PAGE_MASK 0x45144
-#define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \
- _BW_BUDDY0_PAGE_MASK, \
- _BW_BUDDY1_PAGE_MASK))
-
-#define HSW_NDE_RSTWRN_OPT _MMIO(0x46408)
-#define MTL_RESET_PICA_HANDSHAKE_EN REG_BIT(6)
-#define RESET_PCH_HANDSHAKE_ENABLE REG_BIT(4)
-
#define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
#define _LATENCY_REPORTING_REMOVED_PIPE_D REG_BIT(31)
#define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30)
@@ -2514,171 +1082,13 @@
#define MASK_WAKEMEM REG_BIT(13)
#define DDI_CLOCK_REG_ACCESS REG_BIT(7)
-#define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434)
-#define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27)
-#define DCPR_MASK_LPMODE REG_BIT(26)
-#define DCPR_SEND_RESP_IMM REG_BIT(25)
-#define DCPR_CLEAR_MEMSTAT_DIS REG_BIT(24)
-
-#define XELPD_CHICKEN_DCPR_3 _MMIO(0x46438)
-#define DMD_RSP_TIMEOUT_DISABLE REG_BIT(19)
-
-#define SKL_DFSM _MMIO(0x51000)
-#define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27)
-#define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25)
-#define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
-#define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
-#define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
-#define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
-#define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
-#define ICL_DFSM_DMC_DISABLE (1 << 23)
-#define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
-#define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
-#define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
-#define TGL_DFSM_PIPE_D_DISABLE (1 << 22)
-#define GLK_DFSM_DISPLAY_DSC_DISABLE (1 << 7)
-#define XE2LPD_DFSM_DBUF_OVERLAP_DISABLE (1 << 3)
-
-#define XE2LPD_DE_CAP _MMIO(0x41100)
-#define XE2LPD_DE_CAP_3DLUT_MASK REG_GENMASK(31, 30)
-#define XE2LPD_DE_CAP_DSC_MASK REG_GENMASK(29, 28)
-#define XE2LPD_DE_CAP_DSC_REMOVED 1
-#define XE2LPD_DE_CAP_SCALER_MASK REG_GENMASK(27, 26)
-#define XE2LPD_DE_CAP_SCALER_SINGLE 1
-
-#define SKL_DSSM _MMIO(0x51004)
-#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29)
-#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29)
-#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29)
-#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29)
-
#define GMD_ID_DISPLAY _MMIO(0x510a0)
#define GMD_ID_ARCH_MASK REG_GENMASK(31, 22)
#define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14)
#define GMD_ID_STEP REG_GENMASK(5, 0)
-/*GEN11 chicken */
-#define _PIPEA_CHICKEN 0x70038
-#define _PIPEB_CHICKEN 0x71038
-#define _PIPEC_CHICKEN 0x72038
-#define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\
- _PIPEB_CHICKEN)
-#define UNDERRUN_RECOVERY_DISABLE_ADLP REG_BIT(30)
-#define UNDERRUN_RECOVERY_ENABLE_DG2 REG_BIT(30)
-#define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU REG_BIT(15)
-#define DG2_RENDER_CCSTAG_4_3_EN REG_BIT(12)
-#define PER_PIXEL_ALPHA_BYPASS_EN REG_BIT(7)
-
/* PCH */
-#define PCH_DISPLAY_BASE 0xc0000u
-
-/* south display engine interrupt: IBX */
-#define SDE_AUDIO_POWER_D (1 << 27)
-#define SDE_AUDIO_POWER_C (1 << 26)
-#define SDE_AUDIO_POWER_B (1 << 25)
-#define SDE_AUDIO_POWER_SHIFT (25)
-#define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
-#define SDE_GMBUS (1 << 24)
-#define SDE_AUDIO_HDCP_TRANSB (1 << 23)
-#define SDE_AUDIO_HDCP_TRANSA (1 << 22)
-#define SDE_AUDIO_HDCP_MASK (3 << 22)
-#define SDE_AUDIO_TRANSB (1 << 21)
-#define SDE_AUDIO_TRANSA (1 << 20)
-#define SDE_AUDIO_TRANS_MASK (3 << 20)
-#define SDE_POISON (1 << 19)
-/* 18 reserved */
-#define SDE_FDI_RXB (1 << 17)
-#define SDE_FDI_RXA (1 << 16)
-#define SDE_FDI_MASK (3 << 16)
-#define SDE_AUXD (1 << 15)
-#define SDE_AUXC (1 << 14)
-#define SDE_AUXB (1 << 13)
-#define SDE_AUX_MASK (7 << 13)
-/* 12 reserved */
-#define SDE_CRT_HOTPLUG (1 << 11)
-#define SDE_PORTD_HOTPLUG (1 << 10)
-#define SDE_PORTC_HOTPLUG (1 << 9)
-#define SDE_PORTB_HOTPLUG (1 << 8)
-#define SDE_SDVOB_HOTPLUG (1 << 6)
-#define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \
- SDE_SDVOB_HOTPLUG | \
- SDE_PORTB_HOTPLUG | \
- SDE_PORTC_HOTPLUG | \
- SDE_PORTD_HOTPLUG)
-#define SDE_TRANSB_CRC_DONE (1 << 5)
-#define SDE_TRANSB_CRC_ERR (1 << 4)
-#define SDE_TRANSB_FIFO_UNDER (1 << 3)
-#define SDE_TRANSA_CRC_DONE (1 << 2)
-#define SDE_TRANSA_CRC_ERR (1 << 1)
-#define SDE_TRANSA_FIFO_UNDER (1 << 0)
-#define SDE_TRANS_MASK (0x3f)
-
-/* south display engine interrupt: CPT - CNP */
-#define SDE_AUDIO_POWER_D_CPT (1 << 31)
-#define SDE_AUDIO_POWER_C_CPT (1 << 30)
-#define SDE_AUDIO_POWER_B_CPT (1 << 29)
-#define SDE_AUDIO_POWER_SHIFT_CPT 29
-#define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
-#define SDE_AUXD_CPT (1 << 27)
-#define SDE_AUXC_CPT (1 << 26)
-#define SDE_AUXB_CPT (1 << 25)
-#define SDE_AUX_MASK_CPT (7 << 25)
-#define SDE_PORTE_HOTPLUG_SPT (1 << 25)
-#define SDE_PORTA_HOTPLUG_SPT (1 << 24)
-#define SDE_PORTD_HOTPLUG_CPT (1 << 23)
-#define SDE_PORTC_HOTPLUG_CPT (1 << 22)
-#define SDE_PORTB_HOTPLUG_CPT (1 << 21)
-#define SDE_CRT_HOTPLUG_CPT (1 << 19)
-#define SDE_SDVOB_HOTPLUG_CPT (1 << 18)
-#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
- SDE_SDVOB_HOTPLUG_CPT | \
- SDE_PORTD_HOTPLUG_CPT | \
- SDE_PORTC_HOTPLUG_CPT | \
- SDE_PORTB_HOTPLUG_CPT)
-#define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \
- SDE_PORTD_HOTPLUG_CPT | \
- SDE_PORTC_HOTPLUG_CPT | \
- SDE_PORTB_HOTPLUG_CPT | \
- SDE_PORTA_HOTPLUG_SPT)
-#define SDE_GMBUS_CPT (1 << 17)
-#define SDE_ERROR_CPT (1 << 16)
-#define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
-#define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
-#define SDE_FDI_RXC_CPT (1 << 8)
-#define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
-#define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
-#define SDE_FDI_RXB_CPT (1 << 4)
-#define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
-#define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
-#define SDE_FDI_RXA_CPT (1 << 0)
-#define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
- SDE_AUDIO_CP_REQ_B_CPT | \
- SDE_AUDIO_CP_REQ_A_CPT)
-#define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
- SDE_AUDIO_CP_CHG_B_CPT | \
- SDE_AUDIO_CP_CHG_A_CPT)
-#define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
- SDE_FDI_RXB_CPT | \
- SDE_FDI_RXA_CPT)
-
-/* south display engine interrupt: ICP/TGP/MTP */
-#define SDE_PICAINTERRUPT REG_BIT(31)
-#define SDE_GMBUS_ICP (1 << 23)
-#define SDE_TC_HOTPLUG_ICP(hpd_pin) REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
-#define SDE_TC_HOTPLUG_DG2(hpd_pin) REG_BIT(25 + _HPD_PIN_TC(hpd_pin)) /* sigh */
-#define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
-#define SDE_DDI_HOTPLUG_MASK_ICP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \
- SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
- SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
- SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
-#define SDE_TC_HOTPLUG_MASK_ICP (SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \
- SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \
- SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \
- SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \
- SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \
- SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))
-
#define SDEISR _MMIO(0xc4000)
#define SDEIMR _MMIO(0xc4004)
#define SDEIIR _MMIO(0xc4008)
@@ -2692,340 +1102,12 @@
#define SERR_INT_POISON (1 << 31)
#define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
-/* digital port hotplug */
-#define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */
-#define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */
-#define BXT_DDIA_HPD_INVERT (1 << 27)
-#define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */
-#define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */
-#define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */
-#define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */
-#define PORTD_HOTPLUG_ENABLE (1 << 20)
-#define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */
-#define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */
-#define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */
-#define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */
-#define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */
-#define PORTD_HOTPLUG_STATUS_MASK (3 << 16)
-#define PORTD_HOTPLUG_NO_DETECT (0 << 16)
-#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
-#define PORTD_HOTPLUG_LONG_DETECT (2 << 16)
-#define PORTC_HOTPLUG_ENABLE (1 << 12)
-#define BXT_DDIC_HPD_INVERT (1 << 11)
-#define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */
-#define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */
-#define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */
-#define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */
-#define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */
-#define PORTC_HOTPLUG_STATUS_MASK (3 << 8)
-#define PORTC_HOTPLUG_NO_DETECT (0 << 8)
-#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
-#define PORTC_HOTPLUG_LONG_DETECT (2 << 8)
-#define PORTB_HOTPLUG_ENABLE (1 << 4)
-#define BXT_DDIB_HPD_INVERT (1 << 3)
-#define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */
-#define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */
-#define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */
-#define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */
-#define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */
-#define PORTB_HOTPLUG_STATUS_MASK (3 << 0)
-#define PORTB_HOTPLUG_NO_DETECT (0 << 0)
-#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
-#define PORTB_HOTPLUG_LONG_DETECT (2 << 0)
-#define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \
- BXT_DDIB_HPD_INVERT | \
- BXT_DDIC_HPD_INVERT)
-
-#define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */
-#define PORTE_HOTPLUG_ENABLE (1 << 4)
-#define PORTE_HOTPLUG_STATUS_MASK (3 << 0)
-#define PORTE_HOTPLUG_NO_DETECT (0 << 0)
-#define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)
-#define PORTE_HOTPLUG_LONG_DETECT (2 << 0)
-
-/* This register is a reuse of PCH_PORT_HOTPLUG register. The
- * functionality covered in PCH_PORT_HOTPLUG is split into
- * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
- */
-#define SHOTPLUG_CTL_DDI _MMIO(0xc4030)
-#define SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin) (0x8 << (_HPD_PIN_DDI(hpd_pin) * 4))
-#define SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(hpd_pin) (0x4 << (_HPD_PIN_DDI(hpd_pin) * 4))
-#define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
-#define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin) (0x0 << (_HPD_PIN_DDI(hpd_pin) * 4))
-#define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin) (0x1 << (_HPD_PIN_DDI(hpd_pin) * 4))
-#define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(hpd_pin) (0x2 << (_HPD_PIN_DDI(hpd_pin) * 4))
-#define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
-
-#define SHOTPLUG_CTL_TC _MMIO(0xc4034)
-#define ICP_TC_HPD_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4))
-#define ICP_TC_HPD_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4))
-#define ICP_TC_HPD_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4))
-
-#define SHPD_FILTER_CNT _MMIO(0xc4038)
-#define SHPD_FILTER_CNT_500_ADJ 0x001D9
-#define SHPD_FILTER_CNT_250 0x000F8
-
-#define _PCH_DPLL_A 0xc6014
-#define _PCH_DPLL_B 0xc6018
-#define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
-
-#define _PCH_FPA0 0xc6040
-#define _PCH_FPB0 0xc6048
-#define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0)
-#define FP_CB_TUNE (0x3 << 22)
-
-#define _PCH_FPA1 0xc6044
-#define _PCH_FPB1 0xc604c
-#define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1)
-
-#define PCH_DPLL_TEST _MMIO(0xc606c)
-
-#define PCH_DREF_CONTROL _MMIO(0xC6200)
-#define DREF_CONTROL_MASK 0x7fc3
-#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13)
-#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13)
-#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13)
-#define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13)
-#define DREF_SSC_SOURCE_DISABLE (0 << 11)
-#define DREF_SSC_SOURCE_ENABLE (2 << 11)
-#define DREF_SSC_SOURCE_MASK (3 << 11)
-#define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9)
-#define DREF_NONSPREAD_CK505_ENABLE (1 << 9)
-#define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9)
-#define DREF_NONSPREAD_SOURCE_MASK (3 << 9)
-#define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7)
-#define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7)
-#define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7)
-#define DREF_SSC4_DOWNSPREAD (0 << 6)
-#define DREF_SSC4_CENTERSPREAD (1 << 6)
-#define DREF_SSC1_DISABLE (0 << 1)
-#define DREF_SSC1_ENABLE (1 << 1)
-#define DREF_SSC4_DISABLE (0)
-#define DREF_SSC4_ENABLE (1)
-
-#define PCH_RAWCLK_FREQ _MMIO(0xc6204)
-#define FDL_TP1_TIMER_SHIFT 12
-#define FDL_TP1_TIMER_MASK (3 << 12)
-#define FDL_TP2_TIMER_SHIFT 10
-#define FDL_TP2_TIMER_MASK (3 << 10)
-#define RAWCLK_FREQ_MASK 0x3ff
-#define CNP_RAWCLK_DIV_MASK (0x3ff << 16)
-#define CNP_RAWCLK_DIV(div) ((div) << 16)
-#define CNP_RAWCLK_FRAC_MASK (0xf << 26)
-#define CNP_RAWCLK_DEN(den) ((den) << 26)
-#define ICP_RAWCLK_NUM(num) ((num) << 11)
-
-#define PCH_DPLL_TMR_CFG _MMIO(0xc6208)
-
-#define PCH_SSC4_PARMS _MMIO(0xc6210)
-#define PCH_SSC4_AUX_PARMS _MMIO(0xc6214)
-
-#define PCH_DPLL_SEL _MMIO(0xc7000)
-#define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4))
-#define TRANS_DPLLA_SEL(pipe) 0
-#define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3))
-
-/* transcoder */
-#define _PCH_TRANS_HTOTAL_A 0xe0000
-#define _PCH_TRANS_HTOTAL_B 0xe1000
-#define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
-#define TRANS_HTOTAL_SHIFT 16
-#define TRANS_HACTIVE_SHIFT 0
-
-#define _PCH_TRANS_HBLANK_A 0xe0004
-#define _PCH_TRANS_HBLANK_B 0xe1004
-#define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
-#define TRANS_HBLANK_END_SHIFT 16
-#define TRANS_HBLANK_START_SHIFT 0
-
-#define _PCH_TRANS_HSYNC_A 0xe0008
-#define _PCH_TRANS_HSYNC_B 0xe1008
-#define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
-#define TRANS_HSYNC_END_SHIFT 16
-#define TRANS_HSYNC_START_SHIFT 0
-
-#define _PCH_TRANS_VTOTAL_A 0xe000c
-#define _PCH_TRANS_VTOTAL_B 0xe100c
-#define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
-#define TRANS_VTOTAL_SHIFT 16
-#define TRANS_VACTIVE_SHIFT 0
-
-#define _PCH_TRANS_VBLANK_A 0xe0010
-#define _PCH_TRANS_VBLANK_B 0xe1010
-#define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
-#define TRANS_VBLANK_END_SHIFT 16
-#define TRANS_VBLANK_START_SHIFT 0
-
-#define _PCH_TRANS_VSYNC_A 0xe0014
-#define _PCH_TRANS_VSYNC_B 0xe1014
-#define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
-#define TRANS_VSYNC_END_SHIFT 16
-#define TRANS_VSYNC_START_SHIFT 0
-
-#define _PCH_TRANS_VSYNCSHIFT_A 0xe0028
-#define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
-#define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)
-
-#define _PCH_TRANSA_DATA_M1 0xe0030
-#define _PCH_TRANSB_DATA_M1 0xe1030
-#define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
-
-#define _PCH_TRANSA_DATA_N1 0xe0034
-#define _PCH_TRANSB_DATA_N1 0xe1034
-#define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
-
-#define _PCH_TRANSA_DATA_M2 0xe0038
-#define _PCH_TRANSB_DATA_M2 0xe1038
-#define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
-
-#define _PCH_TRANSA_DATA_N2 0xe003c
-#define _PCH_TRANSB_DATA_N2 0xe103c
-#define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
-
-#define _PCH_TRANSA_LINK_M1 0xe0040
-#define _PCH_TRANSB_LINK_M1 0xe1040
-#define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
-
-#define _PCH_TRANSA_LINK_N1 0xe0044
-#define _PCH_TRANSB_LINK_N1 0xe1044
-#define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
-
-#define _PCH_TRANSA_LINK_M2 0xe0048
-#define _PCH_TRANSB_LINK_M2 0xe1048
-#define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
-
-#define _PCH_TRANSA_LINK_N2 0xe004c
-#define _PCH_TRANSB_LINK_N2 0xe104c
-#define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
-
-/* Per-transcoder DIP controls (PCH) */
-#define _VIDEO_DIP_CTL_A 0xe0200
-#define _VIDEO_DIP_CTL_B 0xe1200
-#define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
-
-#define _VIDEO_DIP_DATA_A 0xe0208
-#define _VIDEO_DIP_DATA_B 0xe1208
-#define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
-
-#define _VIDEO_DIP_GCP_A 0xe0210
-#define _VIDEO_DIP_GCP_B 0xe1210
-#define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
-#define GCP_COLOR_INDICATION (1 << 2)
-#define GCP_DEFAULT_PHASE_ENABLE (1 << 1)
-#define GCP_AV_MUTE (1 << 0)
-
-/* Per-transcoder DIP controls (VLV) */
-#define _VLV_VIDEO_DIP_CTL_A 0x60200
-#define _VLV_VIDEO_DIP_CTL_B 0x61170
-#define _CHV_VIDEO_DIP_CTL_C 0x611f0
-#define VLV_TVIDEO_DIP_CTL(pipe) _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \
- _VLV_VIDEO_DIP_CTL_A, \
- _VLV_VIDEO_DIP_CTL_B, \
- _CHV_VIDEO_DIP_CTL_C)
-
-#define _VLV_VIDEO_DIP_DATA_A 0x60208
-#define _VLV_VIDEO_DIP_DATA_B 0x61174
-#define _CHV_VIDEO_DIP_DATA_C 0x611f4
-#define VLV_TVIDEO_DIP_DATA(pipe) _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \
- _VLV_VIDEO_DIP_DATA_A, \
- _VLV_VIDEO_DIP_DATA_B, \
- _CHV_VIDEO_DIP_DATA_C)
-
-#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A 0x60210
-#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B 0x61178
-#define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C 0x611f8
-#define VLV_TVIDEO_DIP_GCP(pipe) _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \
- _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
- _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, \
- _CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
-
-/* Haswell DIP controls */
-#define _HSW_VIDEO_DIP_CTL_A 0x60200
-#define _HSW_VIDEO_DIP_CTL_B 0x61200
-#define HSW_TVIDEO_DIP_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_CTL_A)
-
-#define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220
-#define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220
-#define HSW_TVIDEO_DIP_AVI_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
-
-#define _HSW_VIDEO_DIP_VS_DATA_A 0x60260
-#define _HSW_VIDEO_DIP_VS_DATA_B 0x61260
-#define HSW_TVIDEO_DIP_VS_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
-
-#define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
-#define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
-#define HSW_TVIDEO_DIP_SPD_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
-
-#define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
-#define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
-#define HSW_TVIDEO_DIP_GMP_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4)
-
-#define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320
-#define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320
-#define HSW_TVIDEO_DIP_VSC_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
-
-/*ADLP and later: */
-#define _ADL_VIDEO_DIP_AS_DATA_A 0x60484
-#define _ADL_VIDEO_DIP_AS_DATA_B 0x61484
-#define ADL_TVIDEO_DIP_AS_SDP_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans,\
- _ADL_VIDEO_DIP_AS_DATA_A + (i) * 4)
-
-#define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440
-#define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440
-#define GLK_TVIDEO_DIP_DRM_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4)
-
-#define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240
-#define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240
-#define _HSW_VIDEO_DIP_VS_ECC_A 0x60280
-#define _HSW_VIDEO_DIP_VS_ECC_B 0x61280
-#define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
-#define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
-#define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300
-#define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300
-#define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344
-#define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344
-
-#define _HSW_VIDEO_DIP_GCP_A 0x60210
-#define _HSW_VIDEO_DIP_GCP_B 0x61210
-#define HSW_TVIDEO_DIP_GCP(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GCP_A)
-
/* Icelake PPS_DATA and _ECC DIP Registers.
* These are available for transcoders B,C and eDP.
* Adding the _A so as to reuse the _MMIO_TRANS2
* definition, with which it offsets to the right location.
*/
-#define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350
-#define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350
-#define ICL_VIDEO_DIP_PPS_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
-
-#define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4
-#define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4
-#define ICL_VIDEO_DIP_PPS_ECC(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
-
-#define _HSW_STEREO_3D_CTL_A 0x70020
-#define _HSW_STEREO_3D_CTL_B 0x71020
-#define HSW_STEREO_3D_CTL(dev_priv, trans) _MMIO_PIPE2(dev_priv, trans, _HSW_STEREO_3D_CTL_A)
-#define S3D_ENABLE (1 << 31)
-
-#define _PCH_TRANSACONF 0xf0008
-#define _PCH_TRANSBCONF 0xf1008
-#define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
-#define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */
-#define TRANS_ENABLE REG_BIT(31)
-#define TRANS_STATE_ENABLE REG_BIT(30)
-#define TRANS_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* ibx */
-#define TRANS_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */
-#define TRANS_INTERLACE_MASK REG_GENMASK(23, 21)
-#define TRANS_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANS_INTERLACE_MASK, 0)
-#define TRANS_INTERLACE_LEGACY_VSYNC_IBX REG_FIELD_PREP(TRANS_INTERLACE_MASK, 2) /* ibx */
-#define TRANS_INTERLACE_INTERLACED REG_FIELD_PREP(TRANS_INTERLACE_MASK, 3)
-#define TRANS_BPC_MASK REG_GENMASK(7, 5) /* ibx */
-#define TRANS_BPC_8 REG_FIELD_PREP(TRANS_BPC_MASK, 0)
-#define TRANS_BPC_10 REG_FIELD_PREP(TRANS_BPC_MASK, 1)
-#define TRANS_BPC_6 REG_FIELD_PREP(TRANS_BPC_MASK, 2)
-#define TRANS_BPC_12 REG_FIELD_PREP(TRANS_BPC_MASK, 3)
-
#define _TRANSA_CHICKEN1 0xf0060
#define _TRANSB_CHICKEN1 0xf1060
#define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
@@ -3078,88 +1160,6 @@
#define CNP_PWM_CGE_GATING_DISABLE (1 << 13)
#define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12)
-#define PCH_DP_B _MMIO(0xe4100)
-#define PCH_DP_C _MMIO(0xe4200)
-#define PCH_DP_D _MMIO(0xe4300)
-
-/* CPT */
-#define _TRANS_DP_CTL_A 0xe0300
-#define _TRANS_DP_CTL_B 0xe1300
-#define _TRANS_DP_CTL_C 0xe2300
-#define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
-#define TRANS_DP_OUTPUT_ENABLE REG_BIT(31)
-#define TRANS_DP_PORT_SEL_MASK REG_GENMASK(30, 29)
-#define TRANS_DP_PORT_SEL_NONE REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, 3)
-#define TRANS_DP_PORT_SEL(port) REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, (port) - PORT_B)
-#define TRANS_DP_AUDIO_ONLY REG_BIT(26)
-#define TRANS_DP_ENH_FRAMING REG_BIT(18)
-#define TRANS_DP_BPC_MASK REG_GENMASK(10, 9)
-#define TRANS_DP_BPC_8 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 0)
-#define TRANS_DP_BPC_10 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 1)
-#define TRANS_DP_BPC_6 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 2)
-#define TRANS_DP_BPC_12 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 3)
-#define TRANS_DP_VSYNC_ACTIVE_HIGH REG_BIT(4)
-#define TRANS_DP_HSYNC_ACTIVE_HIGH REG_BIT(3)
-
-#define _TRANS_DP2_CTL_A 0x600a0
-#define _TRANS_DP2_CTL_B 0x610a0
-#define _TRANS_DP2_CTL_C 0x620a0
-#define _TRANS_DP2_CTL_D 0x630a0
-#define TRANS_DP2_CTL(trans) _MMIO_TRANS(trans, _TRANS_DP2_CTL_A, _TRANS_DP2_CTL_B)
-#define TRANS_DP2_128B132B_CHANNEL_CODING REG_BIT(31)
-#define TRANS_DP2_PANEL_REPLAY_ENABLE REG_BIT(30)
-#define TRANS_DP2_DEBUG_ENABLE REG_BIT(23)
-
-#define _TRANS_DP2_VFREQHIGH_A 0x600a4
-#define _TRANS_DP2_VFREQHIGH_B 0x610a4
-#define _TRANS_DP2_VFREQHIGH_C 0x620a4
-#define _TRANS_DP2_VFREQHIGH_D 0x630a4
-#define TRANS_DP2_VFREQHIGH(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQHIGH_A, _TRANS_DP2_VFREQHIGH_B)
-#define TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK REG_GENMASK(31, 8)
-#define TRANS_DP2_VFREQ_PIXEL_CLOCK(clk_hz) REG_FIELD_PREP(TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK, (clk_hz))
-
-#define _TRANS_DP2_VFREQLOW_A 0x600a8
-#define _TRANS_DP2_VFREQLOW_B 0x610a8
-#define _TRANS_DP2_VFREQLOW_C 0x620a8
-#define _TRANS_DP2_VFREQLOW_D 0x630a8
-#define TRANS_DP2_VFREQLOW(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQLOW_A, _TRANS_DP2_VFREQLOW_B)
-
-#define _DP_MIN_HBLANK_CTL_A 0x600ac
-#define _DP_MIN_HBLANK_CTL_B 0x610ac
-#define DP_MIN_HBLANK_CTL(trans) _MMIO_TRANS(trans, _DP_MIN_HBLANK_CTL_A, _DP_MIN_HBLANK_CTL_B)
-
-/* SNB eDP training params */
-/* SNB A-stepping */
-#define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22)
-#define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22)
-#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22)
-#define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22)
-/* SNB B-stepping */
-#define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0 << 22)
-#define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1 << 22)
-#define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a << 22)
-#define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39 << 22)
-#define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38 << 22)
-#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f << 22)
-
-/* IVB */
-#define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 << 22)
-#define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a << 22)
-#define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f << 22)
-#define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 << 22)
-#define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 << 22)
-#define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 << 22)
-#define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e << 22)
-
-/* legacy values */
-#define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 << 22)
-#define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 << 22)
-#define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 << 22)
-#define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 << 22)
-#define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 << 22)
-
-#define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f << 22)
-
#define VLV_PMWGICZ _MMIO(0x1300a4)
#define HSW_EDRAM_CAP _MMIO(0x120010)
@@ -3168,10 +1168,6 @@
#define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7)
#define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3)
-#define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C)
-#define PIXEL_OVERLAP_CNT_MASK (3 << 30)
-#define PIXEL_OVERLAP_CNT_SHIFT 30
-
#define GEN6_PCODE_MAILBOX _MMIO(0x138124)
#define GEN6_PCODE_READY (1 << 31)
#define GEN6_PCODE_MB_PARAM2 REG_GENMASK(23, 16)
@@ -3300,110 +1296,6 @@
*/
#define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4)
-/*
- * HSW - ICL power wells
- *
- * Platforms have up to 3 power well control register sets, each set
- * controlling up to 16 power wells via a request/status HW flag tuple:
- * - main (HSW_PWR_WELL_CTL[1-4])
- * - AUX (ICL_PWR_WELL_CTL_AUX[1-4])
- * - DDI (ICL_PWR_WELL_CTL_DDI[1-4])
- * Each control register set consists of up to 4 registers used by different
- * sources that can request a power well to be enabled:
- * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1)
- * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2)
- * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set)
- * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4)
- */
-#define HSW_PWR_WELL_CTL1 _MMIO(0x45400)
-#define HSW_PWR_WELL_CTL2 _MMIO(0x45404)
-#define HSW_PWR_WELL_CTL3 _MMIO(0x45408)
-#define HSW_PWR_WELL_CTL4 _MMIO(0x4540C)
-#define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2))
-#define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2))
-
-/* HSW/BDW power well */
-#define HSW_PW_CTL_IDX_GLOBAL 15
-
-/* SKL/BXT/GLK power wells */
-#define SKL_PW_CTL_IDX_PW_2 15
-#define SKL_PW_CTL_IDX_PW_1 14
-#define GLK_PW_CTL_IDX_AUX_C 10
-#define GLK_PW_CTL_IDX_AUX_B 9
-#define GLK_PW_CTL_IDX_AUX_A 8
-#define SKL_PW_CTL_IDX_DDI_D 4
-#define SKL_PW_CTL_IDX_DDI_C 3
-#define SKL_PW_CTL_IDX_DDI_B 2
-#define SKL_PW_CTL_IDX_DDI_A_E 1
-#define GLK_PW_CTL_IDX_DDI_A 1
-#define SKL_PW_CTL_IDX_MISC_IO 0
-
-/* ICL/TGL - power wells */
-#define TGL_PW_CTL_IDX_PW_5 4
-#define ICL_PW_CTL_IDX_PW_4 3
-#define ICL_PW_CTL_IDX_PW_3 2
-#define ICL_PW_CTL_IDX_PW_2 1
-#define ICL_PW_CTL_IDX_PW_1 0
-
-/* XE_LPD - power wells */
-#define XELPD_PW_CTL_IDX_PW_D 8
-#define XELPD_PW_CTL_IDX_PW_C 7
-#define XELPD_PW_CTL_IDX_PW_B 6
-#define XELPD_PW_CTL_IDX_PW_A 5
-
-#define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440)
-#define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444)
-#define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C)
-#define TGL_PW_CTL_IDX_AUX_TBT6 14
-#define TGL_PW_CTL_IDX_AUX_TBT5 13
-#define TGL_PW_CTL_IDX_AUX_TBT4 12
-#define ICL_PW_CTL_IDX_AUX_TBT4 11
-#define TGL_PW_CTL_IDX_AUX_TBT3 11
-#define ICL_PW_CTL_IDX_AUX_TBT3 10
-#define TGL_PW_CTL_IDX_AUX_TBT2 10
-#define ICL_PW_CTL_IDX_AUX_TBT2 9
-#define TGL_PW_CTL_IDX_AUX_TBT1 9
-#define ICL_PW_CTL_IDX_AUX_TBT1 8
-#define TGL_PW_CTL_IDX_AUX_TC6 8
-#define XELPD_PW_CTL_IDX_AUX_E 8
-#define TGL_PW_CTL_IDX_AUX_TC5 7
-#define XELPD_PW_CTL_IDX_AUX_D 7
-#define TGL_PW_CTL_IDX_AUX_TC4 6
-#define ICL_PW_CTL_IDX_AUX_F 5
-#define TGL_PW_CTL_IDX_AUX_TC3 5
-#define ICL_PW_CTL_IDX_AUX_E 4
-#define TGL_PW_CTL_IDX_AUX_TC2 4
-#define ICL_PW_CTL_IDX_AUX_D 3
-#define TGL_PW_CTL_IDX_AUX_TC1 3
-#define ICL_PW_CTL_IDX_AUX_C 2
-#define ICL_PW_CTL_IDX_AUX_B 1
-#define ICL_PW_CTL_IDX_AUX_A 0
-
-#define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450)
-#define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454)
-#define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C)
-#define XELPD_PW_CTL_IDX_DDI_E 8
-#define TGL_PW_CTL_IDX_DDI_TC6 8
-#define XELPD_PW_CTL_IDX_DDI_D 7
-#define TGL_PW_CTL_IDX_DDI_TC5 7
-#define TGL_PW_CTL_IDX_DDI_TC4 6
-#define ICL_PW_CTL_IDX_DDI_F 5
-#define TGL_PW_CTL_IDX_DDI_TC3 5
-#define ICL_PW_CTL_IDX_DDI_E 4
-#define TGL_PW_CTL_IDX_DDI_TC2 4
-#define ICL_PW_CTL_IDX_DDI_D 3
-#define TGL_PW_CTL_IDX_DDI_TC1 3
-#define ICL_PW_CTL_IDX_DDI_C 2
-#define ICL_PW_CTL_IDX_DDI_B 1
-#define ICL_PW_CTL_IDX_DDI_A 0
-
-/* HSW - power well misc debug registers */
-#define HSW_PWR_WELL_CTL5 _MMIO(0x45410)
-#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31)
-#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20)
-#define HSW_PWR_WELL_FORCE_ON (1 << 19)
-#define HSW_PWR_WELL_CTL6 _MMIO(0x45414)
-
/* SKL Fuse Status */
enum skl_power_gate {
SKL_PG0,
@@ -3413,193 +1305,6 @@ enum skl_power_gate {
ICL_PG4,
};
-#define SKL_FUSE_STATUS _MMIO(0x42000)
-#define SKL_FUSE_DOWNLOAD_STATUS (1 << 31)
-/*
- * PG0 is HW controlled, so doesn't have a corresponding power well control knob
- * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2
- */
-#define SKL_PW_CTL_IDX_TO_PG(pw_idx) \
- ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1)
-/*
- * PG0 is HW controlled, so doesn't have a corresponding power well control knob
- * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4
- */
-#define ICL_PW_CTL_IDX_TO_PG(pw_idx) \
- ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1)
-#define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
-
-/* Per-pipe DDI Function Control */
-#define _TRANS_DDI_FUNC_CTL_A 0x60400
-#define _TRANS_DDI_FUNC_CTL_B 0x61400
-#define _TRANS_DDI_FUNC_CTL_C 0x62400
-#define _TRANS_DDI_FUNC_CTL_D 0x63400
-#define _TRANS_DDI_FUNC_CTL_EDP 0x6F400
-#define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400
-#define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00
-#define TRANS_DDI_FUNC_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_DDI_FUNC_CTL_A)
-
-#define TRANS_DDI_FUNC_ENABLE (1 << 31)
-/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
-#define TRANS_DDI_PORT_SHIFT 28
-#define TGL_TRANS_DDI_PORT_SHIFT 27
-#define TRANS_DDI_PORT_MASK (7 << TRANS_DDI_PORT_SHIFT)
-#define TGL_TRANS_DDI_PORT_MASK (0xf << TGL_TRANS_DDI_PORT_SHIFT)
-#define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT)
-#define TGL_TRANS_DDI_SELECT_PORT(x) (((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT)
-#define TRANS_DDI_MODE_SELECT_MASK (7 << 24)
-#define TRANS_DDI_MODE_SELECT_HDMI (0 << 24)
-#define TRANS_DDI_MODE_SELECT_DVI (1 << 24)
-#define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24)
-#define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24)
-#define TRANS_DDI_MODE_SELECT_FDI_OR_128B132B (4 << 24)
-#define TRANS_DDI_BPC_MASK (7 << 20)
-#define TRANS_DDI_BPC_8 (0 << 20)
-#define TRANS_DDI_BPC_10 (1 << 20)
-#define TRANS_DDI_BPC_6 (2 << 20)
-#define TRANS_DDI_BPC_12 (3 << 20)
-#define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK REG_GENMASK(19, 18)
-#define TRANS_DDI_PORT_SYNC_MASTER_SELECT(x) REG_FIELD_PREP(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, (x))
-#define TRANS_DDI_PVSYNC (1 << 17)
-#define TRANS_DDI_PHSYNC (1 << 16)
-#define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15)
-#define XE3_TRANS_DDI_HDCP_LINE_REKEY_DISABLE REG_BIT(15)
-#define TRANS_DDI_EDP_INPUT_MASK (7 << 12)
-#define TRANS_DDI_EDP_INPUT_A_ON (0 << 12)
-#define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12)
-#define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12)
-#define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12)
-#define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12)
-#define TRANS_DDI_HDCP_LINE_REKEY_DISABLE REG_BIT(12)
-#define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10)
-#define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \
- REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans)
-#define TRANS_DDI_HDCP_SIGNALLING (1 << 9)
-#define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8)
-#define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7)
-#define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6)
-#define TRANS_DDI_HDCP_SELECT REG_BIT(5)
-#define TRANS_DDI_BFI_ENABLE (1 << 4)
-#define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4)
-#define TRANS_DDI_PORT_WIDTH_MASK REG_GENMASK(3, 1)
-#define TRANS_DDI_PORT_WIDTH(width) REG_FIELD_PREP(TRANS_DDI_PORT_WIDTH_MASK, (width) - 1)
-#define TRANS_DDI_HDMI_SCRAMBLING (1 << 0)
-#define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \
- | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \
- | TRANS_DDI_HDMI_SCRAMBLING)
-
-#define _TRANS_DDI_FUNC_CTL2_A 0x60404
-#define _TRANS_DDI_FUNC_CTL2_B 0x61404
-#define _TRANS_DDI_FUNC_CTL2_C 0x62404
-#define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404
-#define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404
-#define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04
-#define TRANS_DDI_FUNC_CTL2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_DDI_FUNC_CTL2_A)
-#define PORT_SYNC_MODE_ENABLE REG_BIT(4)
-#define CMTG_SECONDARY_MODE REG_BIT(3)
-#define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0)
-#define PORT_SYNC_MODE_MASTER_SELECT(x) REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x))
-
-#define TRANS_CMTG_CHICKEN _MMIO(0x6fa90)
-#define DISABLE_DPT_CLK_GATING REG_BIT(1)
-
-/* DisplayPort Transport Control */
-#define _DP_TP_CTL_A 0x64040
-#define _DP_TP_CTL_B 0x64140
-#define _TGL_DP_TP_CTL_A 0x60540
-#define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
-#define TGL_DP_TP_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_CTL_A)
-#define DP_TP_CTL_ENABLE REG_BIT(31)
-#define DP_TP_CTL_FEC_ENABLE REG_BIT(30)
-#define DP_TP_CTL_MODE_MASK REG_BIT(27)
-#define DP_TP_CTL_MODE_SST REG_FIELD_PREP(DP_TP_CTL_MODE_MASK, 0)
-#define DP_TP_CTL_MODE_MST REG_FIELD_PREP(DP_TP_CTL_MODE_MASK, 1)
-#define DP_TP_CTL_FORCE_ACT REG_BIT(25)
-#define DP_TP_CTL_TRAIN_PAT4_SEL_MASK REG_GENMASK(20, 19)
-#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4A REG_FIELD_PREP(DP_TP_CTL_TRAIN_PAT4_SEL_MASK, 0)
-#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4B REG_FIELD_PREP(DP_TP_CTL_TRAIN_PAT4_SEL_MASK, 1)
-#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4C REG_FIELD_PREP(DP_TP_CTL_TRAIN_PAT4_SEL_MASK, 2)
-#define DP_TP_CTL_ENHANCED_FRAME_ENABLE REG_BIT(18)
-#define DP_TP_CTL_FDI_AUTOTRAIN REG_BIT(15)
-#define DP_TP_CTL_LINK_TRAIN_MASK REG_GENMASK(10, 8)
-#define DP_TP_CTL_LINK_TRAIN_PAT1 REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 0)
-#define DP_TP_CTL_LINK_TRAIN_PAT2 REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 1)
-#define DP_TP_CTL_LINK_TRAIN_PAT3 REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 4)
-#define DP_TP_CTL_LINK_TRAIN_PAT4 REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 5)
-#define DP_TP_CTL_LINK_TRAIN_IDLE REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 2)
-#define DP_TP_CTL_LINK_TRAIN_NORMAL REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 3)
-#define DP_TP_CTL_SCRAMBLE_DISABLE REG_BIT(7)
-
-/* DisplayPort Transport Status */
-#define _DP_TP_STATUS_A 0x64044
-#define _DP_TP_STATUS_B 0x64144
-#define _TGL_DP_TP_STATUS_A 0x60544
-#define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
-#define TGL_DP_TP_STATUS(dev_priv, tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_STATUS_A)
-#define DP_TP_STATUS_FEC_ENABLE_LIVE REG_BIT(28)
-#define DP_TP_STATUS_IDLE_DONE REG_BIT(25)
-#define DP_TP_STATUS_ACT_SENT REG_BIT(24)
-#define DP_TP_STATUS_MODE_STATUS_MST REG_BIT(23)
-#define DP_TP_STATUS_STREAMS_ENABLED_MASK REG_GENMASK(18, 16) /* 17:16 on hsw but bit 18 mbz */
-#define DP_TP_STATUS_AUTOTRAIN_DONE REG_BIT(12)
-#define DP_TP_STATUS_PAYLOAD_MAPPING_VC2_MASK REG_GENMASK(9, 8)
-#define DP_TP_STATUS_PAYLOAD_MAPPING_VC1_MASK REG_GENMASK(5, 4)
-#define DP_TP_STATUS_PAYLOAD_MAPPING_VC0_MASK REG_GENMASK(1, 0)
-
-/* DDI Buffer Control */
-#define _DDI_BUF_CTL_A 0x64000
-#define _DDI_BUF_CTL_B 0x64100
-/* Known as DDI_CTL_DE in MTL+ */
-#define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
-#define DDI_BUF_CTL_ENABLE REG_BIT(31)
-#define XE2LPD_DDI_BUF_D2D_LINK_ENABLE REG_BIT(29)
-#define XE2LPD_DDI_BUF_D2D_LINK_STATE REG_BIT(28)
-#define DDI_BUF_EMP_MASK REG_GENMASK(27, 24)
-#define DDI_BUF_TRANS_SELECT(n) REG_FIELD_PREP(DDI_BUF_EMP_MASK, (n))
-#define DDI_BUF_PHY_LINK_RATE_MASK REG_GENMASK(23, 20)
-#define DDI_BUF_PHY_LINK_RATE(r) REG_FIELD_PREP(DDI_BUF_PHY_LINK_RATE_MASK, (r))
-#define DDI_BUF_PORT_DATA_MASK REG_GENMASK(19, 18)
-#define DDI_BUF_PORT_DATA_10BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 0)
-#define DDI_BUF_PORT_DATA_20BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 1)
-#define DDI_BUF_PORT_DATA_40BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 2)
-#define DDI_BUF_PORT_REVERSAL REG_BIT(16)
-#define DDI_BUF_LANE_STAGGER_DELAY_MASK REG_GENMASK(15, 8)
-#define DDI_BUF_LANE_STAGGER_DELAY(symbols) REG_FIELD_PREP(DDI_BUF_LANE_STAGGER_DELAY_MASK, \
- (symbols))
-#define DDI_BUF_IS_IDLE REG_BIT(7)
-#define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6)
-#define DDI_A_4_LANES REG_BIT(4)
-#define DDI_PORT_WIDTH_MASK REG_GENMASK(3, 1)
-#define DDI_PORT_WIDTH(width) REG_FIELD_PREP(DDI_PORT_WIDTH_MASK, \
- ((width) == 3 ? 4 : (width) - 1))
-#define DDI_PORT_WIDTH_SHIFT 1
-#define DDI_INIT_DISPLAY_DETECTED REG_BIT(0)
-
-/* DDI Buffer Translations */
-#define _DDI_BUF_TRANS_A 0x64E00
-#define _DDI_BUF_TRANS_B 0x64E60
-#define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)
-#define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
-#define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
-
-/* DDI DP Compliance Control */
-#define _DDI_DP_COMP_CTL_A 0x605F0
-#define _DDI_DP_COMP_CTL_B 0x615F0
-#define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B)
-#define DDI_DP_COMP_CTL_ENABLE (1 << 31)
-#define DDI_DP_COMP_CTL_D10_2 (0 << 28)
-#define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28)
-#define DDI_DP_COMP_CTL_PRBS7 (2 << 28)
-#define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28)
-#define DDI_DP_COMP_CTL_HBR2 (4 << 28)
-#define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28)
-#define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0)
-
-/* DDI DP Compliance Pattern */
-#define _DDI_DP_COMP_PAT_A 0x605F4
-#define _DDI_DP_COMP_PAT_B 0x615F4
-#define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4)
-
/* Sideband Interface (SBI) is programmed indirectly, via
* SBI_ADDR, which contains the register offset; and SBI_DATA,
* which contains the payload */
@@ -3617,489 +1322,6 @@ enum skl_power_gate {
#define SBI_BUSY (0x1 << 0)
#define SBI_READY (0x0 << 0)
-/* SBI offsets */
-#define SBI_SSCDIVINTPHASE 0x0200
-#define SBI_SSCDIVINTPHASE6 0x0600
-#define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1
-#define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1)
-#define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1)
-#define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8
-#define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8)
-#define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8)
-#define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15)
-#define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0)
-#define SBI_SSCDITHPHASE 0x0204
-#define SBI_SSCCTL 0x020c
-#define SBI_SSCCTL6 0x060C
-#define SBI_SSCCTL_PATHALT (1 << 3)
-#define SBI_SSCCTL_DISABLE (1 << 0)
-#define SBI_SSCAUXDIV6 0x0610
-#define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4
-#define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4)
-#define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4)
-#define SBI_DBUFF0 0x2a00
-#define SBI_GEN0 0x1f00
-#define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0)
-
-/* LPT PIXCLK_GATE */
-#define PIXCLK_GATE _MMIO(0xC6020)
-#define PIXCLK_GATE_UNGATE (1 << 0)
-#define PIXCLK_GATE_GATE (0 << 0)
-
-/* SPLL */
-#define SPLL_CTL _MMIO(0x46020)
-#define SPLL_PLL_ENABLE (1 << 31)
-#define SPLL_REF_BCLK (0 << 28)
-#define SPLL_REF_MUXED_SSC (1 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
-#define SPLL_REF_NON_SSC_HSW (2 << 28)
-#define SPLL_REF_PCH_SSC_BDW (2 << 28)
-#define SPLL_REF_LCPLL (3 << 28)
-#define SPLL_REF_MASK (3 << 28)
-#define SPLL_FREQ_810MHz (0 << 26)
-#define SPLL_FREQ_1350MHz (1 << 26)
-#define SPLL_FREQ_2700MHz (2 << 26)
-#define SPLL_FREQ_MASK (3 << 26)
-
-/* WRPLL */
-#define _WRPLL_CTL1 0x46040
-#define _WRPLL_CTL2 0x46060
-#define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2)
-#define WRPLL_PLL_ENABLE (1 << 31)
-#define WRPLL_REF_BCLK (0 << 28)
-#define WRPLL_REF_PCH_SSC (1 << 28)
-#define WRPLL_REF_MUXED_SSC_BDW (2 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
-#define WRPLL_REF_SPECIAL_HSW (2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */
-#define WRPLL_REF_LCPLL (3 << 28)
-#define WRPLL_REF_MASK (3 << 28)
-/* WRPLL divider programming */
-#define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0)
-#define WRPLL_DIVIDER_REF_MASK (0xff)
-#define WRPLL_DIVIDER_POST(x) ((x) << 8)
-#define WRPLL_DIVIDER_POST_MASK (0x3f << 8)
-#define WRPLL_DIVIDER_POST_SHIFT 8
-#define WRPLL_DIVIDER_FEEDBACK(x) ((x) << 16)
-#define WRPLL_DIVIDER_FB_SHIFT 16
-#define WRPLL_DIVIDER_FB_MASK (0xff << 16)
-
-/* Port clock selection */
-#define _PORT_CLK_SEL_A 0x46100
-#define _PORT_CLK_SEL_B 0x46104
-#define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B)
-#define PORT_CLK_SEL_MASK REG_GENMASK(31, 29)
-#define PORT_CLK_SEL_LCPLL_2700 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 0)
-#define PORT_CLK_SEL_LCPLL_1350 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 1)
-#define PORT_CLK_SEL_LCPLL_810 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 2)
-#define PORT_CLK_SEL_SPLL REG_FIELD_PREP(PORT_CLK_SEL_MASK, 3)
-#define PORT_CLK_SEL_WRPLL(pll) REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4 + (pll))
-#define PORT_CLK_SEL_WRPLL1 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4)
-#define PORT_CLK_SEL_WRPLL2 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 5)
-#define PORT_CLK_SEL_NONE REG_FIELD_PREP(PORT_CLK_SEL_MASK, 7)
-
-/* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */
-#define DDI_CLK_SEL(port) PORT_CLK_SEL(port)
-#define DDI_CLK_SEL_MASK REG_GENMASK(31, 28)
-#define DDI_CLK_SEL_NONE REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x0)
-#define DDI_CLK_SEL_MG REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x8)
-#define DDI_CLK_SEL_TBT_162 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xC)
-#define DDI_CLK_SEL_TBT_270 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xD)
-#define DDI_CLK_SEL_TBT_540 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xE)
-#define DDI_CLK_SEL_TBT_810 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xF)
-
-/* Transcoder clock selection */
-#define _TRANS_CLK_SEL_A 0x46140
-#define _TRANS_CLK_SEL_B 0x46144
-#define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B)
-/* For each transcoder, we need to select the corresponding port clock */
-#define TRANS_CLK_SEL_DISABLED (0x0 << 29)
-#define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29)
-#define TGL_TRANS_CLK_SEL_DISABLED (0x0 << 28)
-#define TGL_TRANS_CLK_SEL_PORT(x) (((x) + 1) << 28)
-
-
-#define CDCLK_FREQ _MMIO(0x46200)
-
-#define _TRANSA_MSA_MISC 0x60410
-#define _TRANSB_MSA_MISC 0x61410
-#define _TRANSC_MSA_MISC 0x62410
-#define _TRANS_EDP_MSA_MISC 0x6f410
-#define TRANS_MSA_MISC(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANSA_MSA_MISC)
-/* See DP_MSA_MISC_* for the bit definitions */
-
-#define _TRANS_A_SET_CONTEXT_LATENCY 0x6007C
-#define _TRANS_B_SET_CONTEXT_LATENCY 0x6107C
-#define _TRANS_C_SET_CONTEXT_LATENCY 0x6207C
-#define _TRANS_D_SET_CONTEXT_LATENCY 0x6307C
-#define TRANS_SET_CONTEXT_LATENCY(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_A_SET_CONTEXT_LATENCY)
-#define TRANS_SET_CONTEXT_LATENCY_MASK REG_GENMASK(15, 0)
-#define TRANS_SET_CONTEXT_LATENCY_VALUE(x) REG_FIELD_PREP(TRANS_SET_CONTEXT_LATENCY_MASK, (x))
-
-/* LCPLL Control */
-#define LCPLL_CTL _MMIO(0x130040)
-#define LCPLL_PLL_DISABLE (1 << 31)
-#define LCPLL_PLL_LOCK (1 << 30)
-#define LCPLL_REF_NON_SSC (0 << 28)
-#define LCPLL_REF_BCLK (2 << 28)
-#define LCPLL_REF_PCH_SSC (3 << 28)
-#define LCPLL_REF_MASK (3 << 28)
-#define LCPLL_CLK_FREQ_MASK (3 << 26)
-#define LCPLL_CLK_FREQ_450 (0 << 26)
-#define LCPLL_CLK_FREQ_54O_BDW (1 << 26)
-#define LCPLL_CLK_FREQ_337_5_BDW (2 << 26)
-#define LCPLL_CLK_FREQ_675_BDW (3 << 26)
-#define LCPLL_CD_CLOCK_DISABLE (1 << 25)
-#define LCPLL_ROOT_CD_CLOCK_DISABLE (1 << 24)
-#define LCPLL_CD2X_CLOCK_DISABLE (1 << 23)
-#define LCPLL_POWER_DOWN_ALLOW (1 << 22)
-#define LCPLL_CD_SOURCE_FCLK (1 << 21)
-#define LCPLL_CD_SOURCE_FCLK_DONE (1 << 19)
-
-/*
- * SKL Clocks
- */
-/* CDCLK_CTL */
-#define CDCLK_CTL _MMIO(0x46000)
-#define CDCLK_FREQ_SEL_MASK REG_GENMASK(27, 26)
-#define CDCLK_FREQ_450_432 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 0)
-#define CDCLK_FREQ_540 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1)
-#define CDCLK_FREQ_337_308 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2)
-#define CDCLK_FREQ_675_617 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3)
-#define MDCLK_SOURCE_SEL_MASK REG_GENMASK(25, 25)
-#define MDCLK_SOURCE_SEL_CD2XCLK REG_FIELD_PREP(MDCLK_SOURCE_SEL_MASK, 0)
-#define MDCLK_SOURCE_SEL_CDCLK_PLL REG_FIELD_PREP(MDCLK_SOURCE_SEL_MASK, 1)
-#define BXT_CDCLK_CD2X_DIV_SEL_MASK REG_GENMASK(23, 22)
-#define BXT_CDCLK_CD2X_DIV_SEL_1 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0)
-#define BXT_CDCLK_CD2X_DIV_SEL_1_5 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1)
-#define BXT_CDCLK_CD2X_DIV_SEL_2 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 2)
-#define BXT_CDCLK_CD2X_DIV_SEL_4 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 3)
-#define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20)
-#define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19)
-#define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
-#define ICL_CDCLK_CD2X_PIPE(pipe) (_PICK(pipe, 0, 2, 6) << 19)
-#define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19)
-#define TGL_CDCLK_CD2X_PIPE(pipe) BXT_CDCLK_CD2X_PIPE(pipe)
-#define TGL_CDCLK_CD2X_PIPE_NONE ICL_CDCLK_CD2X_PIPE_NONE
-#define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16)
-#define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
-
-/* CDCLK_SQUASH_CTL */
-#define CDCLK_SQUASH_CTL _MMIO(0x46008)
-#define CDCLK_SQUASH_ENABLE REG_BIT(31)
-#define CDCLK_SQUASH_WINDOW_SIZE_MASK REG_GENMASK(27, 24)
-#define CDCLK_SQUASH_WINDOW_SIZE(x) REG_FIELD_PREP(CDCLK_SQUASH_WINDOW_SIZE_MASK, (x))
-#define CDCLK_SQUASH_WAVEFORM_MASK REG_GENMASK(15, 0)
-#define CDCLK_SQUASH_WAVEFORM(x) REG_FIELD_PREP(CDCLK_SQUASH_WAVEFORM_MASK, (x))
-
-/* LCPLL_CTL */
-#define LCPLL1_CTL _MMIO(0x46010)
-#define LCPLL2_CTL _MMIO(0x46014)
-#define LCPLL_PLL_ENABLE (1 << 31)
-
-/* DPLL control1 */
-#define DPLL_CTRL1 _MMIO(0x6C058)
-#define DPLL_CTRL1_HDMI_MODE(id) (1 << ((id) * 6 + 5))
-#define DPLL_CTRL1_SSC(id) (1 << ((id) * 6 + 4))
-#define DPLL_CTRL1_LINK_RATE_MASK(id) (7 << ((id) * 6 + 1))
-#define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id) * 6 + 1)
-#define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate) << ((id) * 6 + 1))
-#define DPLL_CTRL1_OVERRIDE(id) (1 << ((id) * 6))
-#define DPLL_CTRL1_LINK_RATE_2700 0
-#define DPLL_CTRL1_LINK_RATE_1350 1
-#define DPLL_CTRL1_LINK_RATE_810 2
-#define DPLL_CTRL1_LINK_RATE_1620 3
-#define DPLL_CTRL1_LINK_RATE_1080 4
-#define DPLL_CTRL1_LINK_RATE_2160 5
-
-/* DPLL control2 */
-#define DPLL_CTRL2 _MMIO(0x6C05C)
-#define DPLL_CTRL2_DDI_CLK_OFF(port) (1 << ((port) + 15))
-#define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3 << ((port) * 3 + 1))
-#define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port) * 3 + 1)
-#define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk) << ((port) * 3 + 1))
-#define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1 << ((port) * 3))
-
-/* DPLL Status */
-#define DPLL_STATUS _MMIO(0x6C060)
-#define DPLL_LOCK(id) (1 << ((id) * 8))
-
-/* DPLL cfg */
-#define _DPLL1_CFGCR1 0x6C040
-#define _DPLL2_CFGCR1 0x6C048
-#define _DPLL3_CFGCR1 0x6C050
-#define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
-#define DPLL_CFGCR1_FREQ_ENABLE (1 << 31)
-#define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff << 9)
-#define DPLL_CFGCR1_DCO_FRACTION(x) ((x) << 9)
-#define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff)
-
-#define _DPLL1_CFGCR2 0x6C044
-#define _DPLL2_CFGCR2 0x6C04C
-#define _DPLL3_CFGCR2 0x6C054
-#define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
-#define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff << 8)
-#define DPLL_CFGCR2_QDIV_RATIO(x) ((x) << 8)
-#define DPLL_CFGCR2_QDIV_MODE(x) ((x) << 7)
-#define DPLL_CFGCR2_KDIV_MASK (3 << 5)
-#define DPLL_CFGCR2_KDIV(x) ((x) << 5)
-#define DPLL_CFGCR2_KDIV_5 (0 << 5)
-#define DPLL_CFGCR2_KDIV_2 (1 << 5)
-#define DPLL_CFGCR2_KDIV_3 (2 << 5)
-#define DPLL_CFGCR2_KDIV_1 (3 << 5)
-#define DPLL_CFGCR2_PDIV_MASK (7 << 2)
-#define DPLL_CFGCR2_PDIV(x) ((x) << 2)
-#define DPLL_CFGCR2_PDIV_1 (0 << 2)
-#define DPLL_CFGCR2_PDIV_2 (1 << 2)
-#define DPLL_CFGCR2_PDIV_3 (2 << 2)
-#define DPLL_CFGCR2_PDIV_7 (4 << 2)
-#define DPLL_CFGCR2_PDIV_7_INVALID (5 << 2)
-#define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
-
-/* ICL Clocks */
-#define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
-#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24, 4, 5))
-#define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10)
-#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_4 ? \
- (tc_port) + 12 : \
- (tc_port) - TC_PORT_4 + 21))
-#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2)
-#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
-#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
-#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27)
-#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \
- (3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
-#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \
- ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
-
-/*
- * DG1 Clocks
- * First registers controls the first A and B, while the second register
- * controls the phy C and D. The bits on these registers are the
- * same, but refer to different phys
- */
-#define _DG1_DPCLKA_CFGCR0 0x164280
-#define _DG1_DPCLKA1_CFGCR0 0x16C280
-#define _DG1_DPCLKA_PHY_IDX(phy) ((phy) % 2)
-#define _DG1_DPCLKA_PLL_IDX(pll) ((pll) % 2)
-#define DG1_DPCLKA_CFGCR0(phy) _MMIO_PHY((phy) / 2, \
- _DG1_DPCLKA_CFGCR0, \
- _DG1_DPCLKA1_CFGCR0)
-#define DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT(_DG1_DPCLKA_PHY_IDX(phy) + 10)
-#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) (_DG1_DPCLKA_PHY_IDX(phy) * 2)
-#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) (_DG1_DPCLKA_PLL_IDX(pll) << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
-#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (0x3 << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
-
-/* ADLS Clocks */
-#define _ADLS_DPCLKA_CFGCR0 0x164280
-#define _ADLS_DPCLKA_CFGCR1 0x1642BC
-#define ADLS_DPCLKA_CFGCR(phy) _MMIO_PHY((phy) / 3, \
- _ADLS_DPCLKA_CFGCR0, \
- _ADLS_DPCLKA_CFGCR1)
-#define ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy) (((phy) % 3) * 2)
-/* ADLS DPCLKA_CFGCR0 DDI mask */
-#define ADLS_DPCLKA_DDII_SEL_MASK REG_GENMASK(5, 4)
-#define ADLS_DPCLKA_DDIB_SEL_MASK REG_GENMASK(3, 2)
-#define ADLS_DPCLKA_DDIA_SEL_MASK REG_GENMASK(1, 0)
-/* ADLS DPCLKA_CFGCR1 DDI mask */
-#define ADLS_DPCLKA_DDIK_SEL_MASK REG_GENMASK(3, 2)
-#define ADLS_DPCLKA_DDIJ_SEL_MASK REG_GENMASK(1, 0)
-#define ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy) _PICK((phy), \
- ADLS_DPCLKA_DDIA_SEL_MASK, \
- ADLS_DPCLKA_DDIB_SEL_MASK, \
- ADLS_DPCLKA_DDII_SEL_MASK, \
- ADLS_DPCLKA_DDIJ_SEL_MASK, \
- ADLS_DPCLKA_DDIK_SEL_MASK)
-
-/* ICL PLL */
-#define _DPLL0_ENABLE 0x46010
-#define _DPLL1_ENABLE 0x46014
-#define _ADLS_DPLL2_ENABLE 0x46018
-#define _ADLS_DPLL3_ENABLE 0x46030
-#define PLL_ENABLE REG_BIT(31)
-#define PLL_LOCK REG_BIT(30)
-#define PLL_POWER_ENABLE REG_BIT(27)
-#define PLL_POWER_STATE REG_BIT(26)
-#define ICL_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \
- _DPLL0_ENABLE, _DPLL1_ENABLE, \
- _ADLS_DPLL3_ENABLE, _ADLS_DPLL3_ENABLE))
-
-#define _DG2_PLL3_ENABLE 0x4601C
-
-#define DG2_PLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \
- _DPLL0_ENABLE, _DPLL1_ENABLE, \
- _DG2_PLL3_ENABLE, _DG2_PLL3_ENABLE))
-
-#define TBT_PLL_ENABLE _MMIO(0x46020)
-
-#define _MG_PLL1_ENABLE 0x46030
-#define _MG_PLL2_ENABLE 0x46034
-#define _MG_PLL3_ENABLE 0x46038
-#define _MG_PLL4_ENABLE 0x4603C
-/* Bits are the same as _DPLL0_ENABLE */
-#define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \
- _MG_PLL2_ENABLE)
-
-/* DG1 PLL */
-#define DG1_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
- _DPLL0_ENABLE, _DPLL1_ENABLE, \
- _MG_PLL1_ENABLE, _MG_PLL2_ENABLE))
-
-/* ADL-P Type C PLL */
-#define PORTTC1_PLL_ENABLE 0x46038
-#define PORTTC2_PLL_ENABLE 0x46040
-#define ADLP_PORTTC_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), \
- PORTTC1_PLL_ENABLE, \
- PORTTC2_PLL_ENABLE)
-
-#define _ICL_DPLL0_CFGCR0 0x164000
-#define _ICL_DPLL1_CFGCR0 0x164080
-#define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \
- _ICL_DPLL1_CFGCR0)
-#define DPLL_CFGCR0_HDMI_MODE (1 << 30)
-#define DPLL_CFGCR0_SSC_ENABLE (1 << 29)
-#define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25)
-#define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25)
-#define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25)
-#define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25)
-#define DPLL_CFGCR0_LINK_RATE_810 (2 << 25)
-#define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25)
-#define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25)
-#define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25)
-#define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25)
-#define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25)
-#define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10)
-#define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10)
-#define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10)
-#define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff)
-
-#define _ICL_DPLL0_CFGCR1 0x164004
-#define _ICL_DPLL1_CFGCR1 0x164084
-#define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \
- _ICL_DPLL1_CFGCR1)
-#define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10)
-#define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10)
-#define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10)
-#define DPLL_CFGCR1_QDIV_MODE_SHIFT (9)
-#define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9)
-#define DPLL_CFGCR1_KDIV_MASK (7 << 6)
-#define DPLL_CFGCR1_KDIV_SHIFT (6)
-#define DPLL_CFGCR1_KDIV(x) ((x) << 6)
-#define DPLL_CFGCR1_KDIV_1 (1 << 6)
-#define DPLL_CFGCR1_KDIV_2 (2 << 6)
-#define DPLL_CFGCR1_KDIV_3 (4 << 6)
-#define DPLL_CFGCR1_PDIV_MASK (0xf << 2)
-#define DPLL_CFGCR1_PDIV_SHIFT (2)
-#define DPLL_CFGCR1_PDIV(x) ((x) << 2)
-#define DPLL_CFGCR1_PDIV_2 (1 << 2)
-#define DPLL_CFGCR1_PDIV_3 (2 << 2)
-#define DPLL_CFGCR1_PDIV_5 (4 << 2)
-#define DPLL_CFGCR1_PDIV_7 (8 << 2)
-#define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0)
-#define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0)
-#define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0)
-
-#define _TGL_DPLL0_CFGCR0 0x164284
-#define _TGL_DPLL1_CFGCR0 0x16428C
-#define _TGL_TBTPLL_CFGCR0 0x16429C
-#define TGL_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
- _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \
- _TGL_TBTPLL_CFGCR0, _TGL_TBTPLL_CFGCR0))
-#define RKL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \
- _TGL_DPLL1_CFGCR0)
-
-#define _TGL_DPLL0_DIV0 0x164B00
-#define _TGL_DPLL1_DIV0 0x164C00
-#define TGL_DPLL0_DIV0(pll) _MMIO_PLL(pll, _TGL_DPLL0_DIV0, _TGL_DPLL1_DIV0)
-#define TGL_DPLL0_DIV0_AFC_STARTUP_MASK REG_GENMASK(27, 25)
-#define TGL_DPLL0_DIV0_AFC_STARTUP(val) REG_FIELD_PREP(TGL_DPLL0_DIV0_AFC_STARTUP_MASK, (val))
-
-#define _TGL_DPLL0_CFGCR1 0x164288
-#define _TGL_DPLL1_CFGCR1 0x164290
-#define _TGL_TBTPLL_CFGCR1 0x1642A0
-#define TGL_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
- _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \
- _TGL_TBTPLL_CFGCR1, _TGL_TBTPLL_CFGCR1))
-#define RKL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \
- _TGL_DPLL1_CFGCR1)
-
-#define _DG1_DPLL2_CFGCR0 0x16C284
-#define _DG1_DPLL3_CFGCR0 0x16C28C
-#define DG1_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
- _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \
- _DG1_DPLL2_CFGCR0, _DG1_DPLL3_CFGCR0))
-
-#define _DG1_DPLL2_CFGCR1 0x16C288
-#define _DG1_DPLL3_CFGCR1 0x16C290
-#define DG1_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
- _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \
- _DG1_DPLL2_CFGCR1, _DG1_DPLL3_CFGCR1))
-
-/* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */
-#define _ADLS_DPLL4_CFGCR0 0x164294
-#define _ADLS_DPLL3_CFGCR0 0x1642C0
-#define ADLS_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
- _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \
- _ADLS_DPLL4_CFGCR0, _ADLS_DPLL3_CFGCR0))
-
-#define _ADLS_DPLL4_CFGCR1 0x164298
-#define _ADLS_DPLL3_CFGCR1 0x1642C4
-#define ADLS_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
- _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \
- _ADLS_DPLL4_CFGCR1, _ADLS_DPLL3_CFGCR1))
-
-/* BXT display engine PLL */
-#define BXT_DE_PLL_CTL _MMIO(0x6d000)
-#define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */
-#define BXT_DE_PLL_RATIO_MASK 0xff
-
-#define BXT_DE_PLL_ENABLE _MMIO(0x46070)
-#define BXT_DE_PLL_PLL_ENABLE (1 << 31)
-#define BXT_DE_PLL_LOCK (1 << 30)
-#define BXT_DE_PLL_FREQ_REQ (1 << 23)
-#define BXT_DE_PLL_FREQ_REQ_ACK (1 << 22)
-#define ICL_CDCLK_PLL_RATIO(x) (x)
-#define ICL_CDCLK_PLL_RATIO_MASK 0xff
-
-/* GEN9 DC */
-#define DC_STATE_EN _MMIO(0x45504)
-#define DC_STATE_DISABLE 0
-#define DC_STATE_EN_DC3CO REG_BIT(30)
-#define DC_STATE_DC3CO_STATUS REG_BIT(29)
-#define HOLD_PHY_CLKREQ_PG1_LATCH REG_BIT(21)
-#define HOLD_PHY_PG1_LATCH REG_BIT(20)
-#define DC_STATE_EN_UPTO_DC5 (1 << 0)
-#define DC_STATE_EN_DC9 (1 << 3)
-#define DC_STATE_EN_UPTO_DC6 (2 << 0)
-#define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3
-
-#define DC_STATE_DEBUG _MMIO(0x45520)
-#define DC_STATE_DEBUG_MASK_CORES (1 << 0)
-#define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1)
-
-#define D_COMP_BDW _MMIO(0x138144)
-
-/* Pipe WM_LINETIME - watermark line time */
-#define _WM_LINETIME_A 0x45270
-#define _WM_LINETIME_B 0x45274
-#define WM_LINETIME(pipe) _MMIO_PIPE(pipe, _WM_LINETIME_A, _WM_LINETIME_B)
-#define HSW_LINETIME_MASK REG_GENMASK(8, 0)
-#define HSW_LINETIME(x) REG_FIELD_PREP(HSW_LINETIME_MASK, (x))
-#define HSW_IPS_LINETIME_MASK REG_GENMASK(24, 16)
-#define HSW_IPS_LINETIME(x) REG_FIELD_PREP(HSW_IPS_LINETIME_MASK, (x))
-
-/* SFUSE_STRAP */
-#define SFUSE_STRAP _MMIO(0xc2014)
-#define SFUSE_STRAP_FUSE_LOCK (1 << 13)
-#define SFUSE_STRAP_RAW_FREQUENCY (1 << 8)
-#define SFUSE_STRAP_DISPLAY_DISABLED (1 << 7)
-#define SFUSE_STRAP_CRT_DISABLED (1 << 6)
-#define SFUSE_STRAP_DDIF_DETECTED (1 << 3)
-#define SFUSE_STRAP_DDIB_DETECTED (1 << 2)
-#define SFUSE_STRAP_DDIC_DETECTED (1 << 1)
-#define SFUSE_STRAP_DDID_DETECTED (1 << 0)
-
-/* Gen4+ Timestamp and Pipe Frame time stamp registers */
-#define GEN4_TIMESTAMP _MMIO(0x2358)
-#define ILK_TIMESTAMP_HI _MMIO(0x70070)
-#define IVB_TIMESTAMP_CTR _MMIO(0x44070)
#define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074)
#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0
@@ -4107,30 +1329,6 @@ enum skl_power_gate {
#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12
#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12)
-/* g4x+, except vlv/chv! */
-#define _PIPE_FRMTMSTMP_A 0x70048
-#define _PIPE_FRMTMSTMP_B 0x71048
-#define PIPE_FRMTMSTMP(pipe) \
- _MMIO_PIPE(pipe, _PIPE_FRMTMSTMP_A, _PIPE_FRMTMSTMP_B)
-
-/* g4x+, except vlv/chv! */
-#define _PIPE_FLIPTMSTMP_A 0x7004C
-#define _PIPE_FLIPTMSTMP_B 0x7104C
-#define PIPE_FLIPTMSTMP(pipe) \
- _MMIO_PIPE(pipe, _PIPE_FLIPTMSTMP_A, _PIPE_FLIPTMSTMP_B)
-
-/* tgl+ */
-#define _PIPE_FLIPDONETMSTMP_A 0x70054
-#define _PIPE_FLIPDONETMSTMP_B 0x71054
-#define PIPE_FLIPDONETIMSTMP(pipe) \
- _MMIO_PIPE(pipe, _PIPE_FLIPDONETMSTMP_A, _PIPE_FLIPDONETMSTMP_B)
-
-#define _VLV_PIPE_MSA_MISC_A 0x70048
-#define VLV_PIPE_MSA_MISC(__display, pipe) \
- _MMIO_PIPE2(__display, pipe, _VLV_PIPE_MSA_MISC_A)
-#define VLV_MSA_MISC1_HW_ENABLE REG_BIT(31)
-#define VLV_MSA_MISC1_SW_S3D_MASK REG_GENMASK(2, 0) /* MSA MISC1 3:1 */
-
#define GGC _MMIO(0x108040)
#define GMS_MASK REG_GENMASK(15, 8)
#define GGMS_MASK REG_GENMASK(7, 6)
@@ -4145,45 +1343,6 @@ enum skl_power_gate {
#define SGGI_DIS REG_BIT(15)
#define SGR_DIS REG_BIT(13)
-#define _ICL_PHY_MISC_A 0x64C00
-#define _ICL_PHY_MISC_B 0x64C04
-#define _DG2_PHY_MISC_TC1 0x64C14 /* TC1="PHY E" but offset as if "PHY F" */
-#define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, _ICL_PHY_MISC_B)
-#define DG2_PHY_MISC(port) ((port) == PHY_E ? _MMIO(_DG2_PHY_MISC_TC1) : \
- ICL_PHY_MISC(port))
-#define ICL_PHY_MISC_MUX_DDID (1 << 28)
-#define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
-#define DG2_PHY_DP_TX_ACK_MASK REG_GENMASK(23, 20)
-
-#define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0)
-#define MODULAR_FIA_MASK (1 << 4)
-#define TC_LIVE_STATE_TBT(idx) (1 << ((idx) * 8 + 6))
-#define TC_LIVE_STATE_TC(idx) (1 << ((idx) * 8 + 5))
-#define DP_LANE_ASSIGNMENT_SHIFT(idx) ((idx) * 8)
-#define DP_LANE_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 8))
-#define DP_LANE_ASSIGNMENT(idx, x) ((x) << ((idx) * 8))
-
-#define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia), 0x00890)
-#define DP_PHY_MODE_STATUS_COMPLETED(idx) (1 << (idx))
-
-#define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894)
-#define DP_PHY_MODE_STATUS_NOT_SAFE(idx) (1 << (idx))
-
-#define PORT_TX_DFLEXPA1(fia) _MMIO_FIA((fia), 0x00880)
-#define DP_PIN_ASSIGNMENT_SHIFT(idx) ((idx) * 4)
-#define DP_PIN_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 4))
-#define DP_PIN_ASSIGNMENT(idx, x) ((x) << ((idx) * 4))
-
-#define _TCSS_DDI_STATUS_1 0x161500
-#define _TCSS_DDI_STATUS_2 0x161504
-#define TCSS_DDI_STATUS(tc) _MMIO(_PICK_EVEN(tc, \
- _TCSS_DDI_STATUS_1, \
- _TCSS_DDI_STATUS_2))
-#define TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK REG_GENMASK(28, 25)
-#define TCSS_DDI_STATUS_READY REG_BIT(2)
-#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1)
-#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0)
-
#define PRIMARY_SPI_TRIGGER _MMIO(0x102040)
#define PRIMARY_SPI_ADDRESS _MMIO(0x102080)
#define PRIMARY_SPI_REGIONID _MMIO(0x102084)
@@ -4192,37 +1351,11 @@ enum skl_power_gate {
#define OROM_OFFSET _MMIO(0x1020c0)
#define OROM_OFFSET_MASK REG_GENMASK(20, 16)
-#define CLKREQ_POLICY _MMIO(0x101038)
-#define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1)
-
-#define CLKGATE_DIS_MISC _MMIO(0x46534)
-#define CLKGATE_DIS_MISC_DMASC_GATING_DIS REG_BIT(21)
-
-#define _MTL_CLKGATE_DIS_TRANS_A 0x604E8
-#define _MTL_CLKGATE_DIS_TRANS_B 0x614E8
-#define MTL_CLKGATE_DIS_TRANS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _MTL_CLKGATE_DIS_TRANS_A)
-#define MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS REG_BIT(7)
-
-#define _MTL_PIPE_CLKGATE_DIS2_A 0x60114
-#define _MTL_PIPE_CLKGATE_DIS2_B 0x61114
-#define MTL_PIPE_CLKGATE_DIS2(pipe) _MMIO_PIPE(pipe, _MTL_PIPE_CLKGATE_DIS2_A, _MTL_PIPE_CLKGATE_DIS2_B)
-#define MTL_DPFC_GATING_DIS REG_BIT(6)
-
#define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700)
#define MTL_N_OF_ENABLED_QGV_POINTS_MASK REG_GENMASK(11, 8)
#define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4)
#define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0)
-#define MTL_MEM_SS_INFO_QGV_POINT_OFFSET 0x45710
-#define MTL_MEM_SS_INFO_QGV_POINT_LOW(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8)
-#define MTL_TRCD_MASK REG_GENMASK(31, 24)
-#define MTL_TRP_MASK REG_GENMASK(23, 16)
-#define MTL_DCLK_MASK REG_GENMASK(15, 0)
-
-#define MTL_MEM_SS_INFO_QGV_POINT_HIGH(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8 + 4)
-#define MTL_TRAS_MASK REG_GENMASK(16, 8)
-#define MTL_TRDPRE_MASK REG_GENMASK(7, 0)
-
#define MTL_MEDIA_GSI_BASE 0x380000
#endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 76d84cbb8361..de48dbc11740 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -31,6 +31,7 @@
#include "i915_drv.h"
#include "i915_pvinfo.h"
#include "i915_reg.h"
+#include "display/intel_display_regs.h"
#include "intel_gvt.h"
#include "intel_mchbar_regs.h"
diff --git a/drivers/gpu/drm/xe/display/xe_plane_initial.c b/drivers/gpu/drm/xe/display/xe_plane_initial.c
index 6502b8274173..d7a7ccab9e2e 100644
--- a/drivers/gpu/drm/xe/display/xe_plane_initial.c
+++ b/drivers/gpu/drm/xe/display/xe_plane_initial.c
@@ -14,6 +14,7 @@
#include "intel_atomic_plane.h"
#include "intel_crtc.h"
#include "intel_display.h"
+#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_fb.h"
#include "intel_fb_pin.h"
--
2.39.5
^ permalink raw reply related [flat|nested] 13+ messages in thread
* ✓ CI.Patch_applied: success for drm/i915: i915_reg.h display split (rev2)
2025-04-15 10:51 [PATCH v2 0/3] drm/i915: i915_reg.h display split Jani Nikula
` (2 preceding siblings ...)
2025-04-15 10:51 ` [PATCH v2 3/3] drm/i915: split out display register macros to a separate file Jani Nikula
@ 2025-04-15 11:42 ` Patchwork
2025-04-15 11:43 ` ✗ CI.checkpatch: warning " Patchwork
` (6 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2025-04-15 11:42 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-xe
== Series Details ==
Series: drm/i915: i915_reg.h display split (rev2)
URL : https://patchwork.freedesktop.org/series/144506/
State : success
== Summary ==
=== Applying kernel patches on branch 'drm-tip' with base: ===
Base commit: 22c34bd976f4 drm-tip: 2025y-04m-15d-11h-13m-08s UTC integration manifest
=== git am output follows ===
Applying: drm/i915/reg: use REG_BIT and friends to define DP registers
Applying: drm/i915/reg: Add/remove some extra blank lines
Applying: drm/i915: split out display register macros to a separate file
^ permalink raw reply [flat|nested] 13+ messages in thread
* ✗ CI.checkpatch: warning for drm/i915: i915_reg.h display split (rev2)
2025-04-15 10:51 [PATCH v2 0/3] drm/i915: i915_reg.h display split Jani Nikula
` (3 preceding siblings ...)
2025-04-15 11:42 ` ✓ CI.Patch_applied: success for drm/i915: i915_reg.h display split (rev2) Patchwork
@ 2025-04-15 11:43 ` Patchwork
2025-04-15 11:44 ` ✓ CI.KUnit: success " Patchwork
` (5 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2025-04-15 11:43 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-xe
== Series Details ==
Series: drm/i915: i915_reg.h display split (rev2)
URL : https://patchwork.freedesktop.org/series/144506/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
13a92ce9fd458ebd6064f23cec8c39c53d02ed26
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 0d09370b87a1e582e636b5db9d3e4bb1f824bc30
Author: Jani Nikula <jani.nikula@intel.com>
Date: Tue Apr 15 13:51:22 2025 +0300
drm/i915: split out display register macros to a separate file
This is a scripted split of the display related register macros from
i915_reg.h to display/intel_display_regs.h. As a starting point, move
all the macros that are only used in display code (or GVT). If there are
users in core i915 code or soc/, or no users anywhere, keep the macros
in i915_reg.h. This is done in groups of macros separated by blank
lines, moving the comments along with the groups.
Some manually picked macro groups are kept/moved regardless of the
heuristics above.
This is obviously a very crude approach. It's not perfect. But there are
4.2k lines in i915_reg.h, and its refactoring has ground to a halt. This
is the big hammer that splits the file to two, and enables further
cleanup.
Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+ /mt/dim checkpatch 22c34bd976f4b047263dafa7b88f60f953ccddd3 drm-intel
f98d90912855 drm/i915/reg: use REG_BIT and friends to define DP registers
10a96345870c drm/i915/reg: Add/remove some extra blank lines
0d09370b87a1 drm/i915: split out display register macros to a separate file
-:340: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#340:
new file mode 100644
-:505: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#505: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:161:
+#define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline))))
-:824: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#824: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:480:
+ * The same register may be used for SDVO or HDMI */
-:905: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#905: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:561:
+ * of the infoframe structure specified by CEA-861. */
-:1062: WARNING:LONG_LINE: line length of 128 exceeds 100 columns
#1062: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:718:
+#define TRANSCONF_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANSCONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */
-:1069: WARNING:LONG_LINE_COMMENT: line length of 110 exceeds 100 columns
#1069: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:725:
+#define TRANSCONF_GAMMA_MODE_12BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */
-:1070: WARNING:LONG_LINE_COMMENT: line length of 106 exceeds 100 columns
#1070: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:726:
+#define TRANSCONF_GAMMA_MODE_SPLIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 3) /* ivb */
-:1071: WARNING:LONG_LINE_COMMENT: line length of 130 exceeds 100 columns
#1071: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:727:
+#define TRANSCONF_GAMMA_MODE(x) REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, (x)) /* pass in GAMMA_MODE_MODE_* */
-:1074: WARNING:LONG_LINE_COMMENT: line length of 115 exceeds 100 columns
#1074: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:730:
+#define TRANSCONF_INTERLACE_W_SYNC_SHIFT_PANEL REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 4) /* gen4 only */
-:1075: WARNING:LONG_LINE_COMMENT: line length of 107 exceeds 100 columns
#1075: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:731:
+#define TRANSCONF_INTERLACE_W_SYNC_SHIFT REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 5) /* gen4 only */
-:1077: WARNING:LONG_LINE_COMMENT: line length of 107 exceeds 100 columns
#1077: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:733:
+#define TRANSCONF_INTERLACE_FIELD_0_ONLY REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 7) /* gen3 only */
-:1087: WARNING:LONG_LINE_COMMENT: line length of 114 exceeds 100 columns
#1087: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:743:
+#define TRANSCONF_INTERLACE_IF_ID_DBL_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 4) /* ilk/snb only */
-:1088: WARNING:LONG_LINE_COMMENT: line length of 114 exceeds 100 columns
#1088: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:744:
+#define TRANSCONF_INTERLACE_PF_ID_DBL_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 5) /* ilk/snb only */
-:1097: WARNING:LONG_LINE_COMMENT: line length of 113 exceeds 100 columns
#1097: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:753:
+#define TRANSCONF_OUTPUT_COLORSPACE_RGB REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */
-:1098: WARNING:LONG_LINE_COMMENT: line length of 113 exceeds 100 columns
#1098: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:754:
+#define TRANSCONF_OUTPUT_COLORSPACE_YUV601 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */
-:1099: WARNING:LONG_LINE_COMMENT: line length of 113 exceeds 100 columns
#1099: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:755:
+#define TRANSCONF_OUTPUT_COLORSPACE_YUV709 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */
-:1157: WARNING:LONG_LINE: line length of 119 exceeds 100 columns
#1157: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:813:
+#define PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id) REG_FIELD_PREP(PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK, (plane_id))
-:1333: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'id' - possible side-effects?
#1333: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:989:
+#define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \
+ _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \
+ _ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
-:1360: WARNING:LONG_LINE_COMMENT: line length of 107 exceeds 100 columns
#1360: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:1016:
+#define PS_PIPE_SCALER_LOC_AFTER_OUTPUT_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 0) /* non-linear */
-:1361: WARNING:LONG_LINE_COMMENT: line length of 103 exceeds 100 columns
#1361: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:1017:
+#define PS_PIPE_SCALER_LOC_AFTER_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 1) /* linear */
-:1388: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'id' - possible side-effects?
#1388: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:1044:
+#define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \
+ _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \
+ _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))
-:1408: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'id' - possible side-effects?
#1408: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:1064:
+#define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \
+ _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \
+ _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))
-:1421: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'id' - possible side-effects?
#1421: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:1077:
+#define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \
+ _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \
+ _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))
-:1434: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'id' - possible side-effects?
#1434: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:1090:
+#define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \
+ _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \
+ _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))
-:1443: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'id' - possible side-effects?
#1443: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:1099:
+#define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \
+ _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \
+ _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))
-:1452: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'id' - possible side-effects?
#1452: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:1108:
+#define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \
+ _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \
+ _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))
-:1467: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'id' - possible side-effects?
#1467: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:1123:
+#define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \
+ _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \
+ _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))
-:1476: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'id' - possible side-effects?
#1476: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:1132:
+#define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \
+ _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
+ _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
-:1484: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'id' - possible side-effects?
#1484: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:1140:
+#define GLK_PS_COEF_INDEX_SET(pipe, id, set) _MMIO_PIPE(pipe, \
+ _ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A) + (set) * 8, \
+ _ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B) + (set) * 8)
-:1484: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'set' - possible side-effects?
#1484: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:1140:
+#define GLK_PS_COEF_INDEX_SET(pipe, id, set) _MMIO_PIPE(pipe, \
+ _ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A) + (set) * 8, \
+ _ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B) + (set) * 8)
-:1493: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'id' - possible side-effects?
#1493: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:1149:
+#define GLK_PS_COEF_DATA_SET(pipe, id, set) _MMIO_PIPE(pipe, \
+ _ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + (set) * 8, \
+ _ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + (set) * 8)
-:1493: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'set' - possible side-effects?
#1493: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:1149:
+#define GLK_PS_COEF_DATA_SET(pipe, id, set) _MMIO_PIPE(pipe, \
+ _ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + (set) * 8, \
+ _ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + (set) * 8)
-:1554: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'plane_id' - possible side-effects?
#1554: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:1210:
+#define GEN9_PIPE_PLANE_FLIP_DONE(plane_id) \
+ REG_BIT(((plane_id) >= PLANE_5 ? 16 - PLANE_5 : 3 - PLANE_1) + (plane_id)) /* skl+ */
-:1560: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#1560: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:1216:
+#define GEN8_DE_PIPE_IRQ_REGS(pipe) I915_IRQ_REGS(GEN8_DE_PIPE_IMR(pipe), \
+ GEN8_DE_PIPE_IER(pipe), \
+ GEN8_DE_PIPE_IIR(pipe))
-:1740: WARNING:LONG_LINE: line length of 120 exceeds 100 columns
#1740: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:1396:
+#define CHICKEN_TRANS(display, trans) (DISPLAY_VER(display) >= 14 ? _MTL_CHICKEN_TRANS(trans) : _CHICKEN_TRANS(trans))
-:1740: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'trans' - possible side-effects?
#1740: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:1396:
+#define CHICKEN_TRANS(display, trans) (DISPLAY_VER(display) >= 14 ? _MTL_CHICKEN_TRANS(trans) : _CHICKEN_TRANS(trans))
-:2073: WARNING:MACRO_ARG_UNUSED: Argument 'pipe' is not used in function-like macro
#2073: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:1729:
+#define TRANS_DPLLA_SEL(pipe) 0
-:2115: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#2115: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:1771:
+#define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)
-:2193: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#2193: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:1849:
+#define HSW_TVIDEO_DIP_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_CTL_A)
-:2197: WARNING:LONG_LINE: line length of 122 exceeds 100 columns
#2197: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:1853:
+#define HSW_TVIDEO_DIP_AVI_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
-:2201: WARNING:LONG_LINE: line length of 121 exceeds 100 columns
#2201: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:1857:
+#define HSW_TVIDEO_DIP_VS_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
-:2205: WARNING:LONG_LINE: line length of 122 exceeds 100 columns
#2205: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:1861:
+#define HSW_TVIDEO_DIP_SPD_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
-:2209: WARNING:LONG_LINE: line length of 122 exceeds 100 columns
#2209: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:1865:
+#define HSW_TVIDEO_DIP_GMP_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4)
-:2213: WARNING:LONG_LINE: line length of 122 exceeds 100 columns
#2213: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:1869:
+#define HSW_TVIDEO_DIP_VSC_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
-:2223: WARNING:LONG_LINE: line length of 122 exceeds 100 columns
#2223: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:1879:
+#define GLK_TVIDEO_DIP_DRM_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4)
-:2238: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#2238: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:1894:
+#define HSW_TVIDEO_DIP_GCP(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GCP_A)
-:2242: WARNING:LONG_LINE: line length of 122 exceeds 100 columns
#2242: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:1898:
+#define ICL_VIDEO_DIP_PPS_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
-:2246: WARNING:LONG_LINE: line length of 129 exceeds 100 columns
#2246: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:1902:
+#define ICL_VIDEO_DIP_PPS_ECC(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
-:2260: WARNING:LONG_LINE_COMMENT: line length of 104 exceeds 100 columns
#2260: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:1916:
+#define TRANS_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */
-:2298: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#2298: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:1954:
+#define TRANS_DP2_CTL(trans) _MMIO_TRANS(trans, _TRANS_DP2_CTL_A, _TRANS_DP2_CTL_B)
-:2307: WARNING:LONG_LINE: line length of 114 exceeds 100 columns
#2307: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:1963:
+#define TRANS_DP2_VFREQHIGH(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQHIGH_A, _TRANS_DP2_VFREQHIGH_B)
-:2309: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#2309: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:1965:
+#define TRANS_DP2_VFREQ_PIXEL_CLOCK(clk_hz) REG_FIELD_PREP(TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK, (clk_hz))
-:2315: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#2315: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:1971:
+#define TRANS_DP2_VFREQLOW(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQLOW_A, _TRANS_DP2_VFREQLOW_B)
-:2319: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#2319: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:1975:
+#define DP_MIN_HBLANK_CTL(trans) _MMIO_TRANS(trans, _DP_MIN_HBLANK_CTL_A, _DP_MIN_HBLANK_CTL_B)
-:2507: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#2507: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:2163:
+#define TRANS_DDI_PORT_SYNC_MASTER_SELECT(x) REG_FIELD_PREP(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, (x))
-:2546: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#2546: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:2202:
+#define PORT_SYNC_MODE_MASTER_SELECT(x) REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x))
-:2588: WARNING:LONG_LINE_COMMENT: line length of 101 exceeds 100 columns
#2588: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:2244:
+#define DP_TP_STATUS_STREAMS_ENABLED_MASK REG_GENMASK(18, 16) /* 17:16 on hsw but bit 18 mbz */
-:2618: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'width' - possible side-effects?
#2618: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:2274:
+#define DDI_PORT_WIDTH(width) REG_FIELD_PREP(DDI_PORT_WIDTH_MASK, \
+ ((width) == 3 ? 4 : (width) - 1))
-:2626: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#2626: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:2282:
+#define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)
-:2628: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#2628: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:2284:
+#define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
-:2633: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#2633: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:2289:
+#define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B)
-:2646: WARNING:LONG_LINE: line length of 116 exceeds 100 columns
#2646: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:2302:
+#define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4)
-:2759: WARNING:LONG_LINE: line length of 122 exceeds 100 columns
#2759: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:2415:
+#define TRANS_SET_CONTEXT_LATENCY(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_A_SET_CONTEXT_LATENCY)
-:2887: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'tc_port' - possible side-effects?
#2887: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:2543:
+#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_4 ? \
+ (tc_port) + 12 : \
+ (tc_port) - TC_PORT_4 + 21))
-:2891: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#2891: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:2547:
+#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
-:2892: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#2892: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:2548:
+#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
-:2914: WARNING:LONG_LINE: line length of 126 exceeds 100 columns
#2914: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:2570:
+#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) (_DG1_DPCLKA_PLL_IDX(pll) << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
-:2915: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#2915: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:2571:
+#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (0x3 << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
-:3037: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#3037: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:2693:
+#define TGL_DPLL0_DIV0(pll) _MMIO_PLL(pll, _TGL_DPLL0_DIV0, _TGL_DPLL1_DIV0)
-:3039: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#3039: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:2695:
+#define TGL_DPLL0_DIV0_AFC_STARTUP(val) REG_FIELD_PREP(TGL_DPLL0_DIV0_AFC_STARTUP_MASK, (val))
-:3159: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'port' - possible side-effects?
#3159: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:2815:
+#define DG2_PHY_MISC(port) ((port) == PHY_E ? _MMIO(_DG2_PHY_MISC_TC1) : \
+ ICL_PHY_MISC(port))
-:3202: WARNING:LONG_LINE: line length of 119 exceeds 100 columns
#3202: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:2858:
+#define MTL_CLKGATE_DIS_TRANS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _MTL_CLKGATE_DIS_TRANS_A)
-:3207: WARNING:LONG_LINE: line length of 116 exceeds 100 columns
#3207: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:2863:
+#define MTL_PIPE_CLKGATE_DIS2(pipe) _MMIO_PIPE(pipe, _MTL_PIPE_CLKGATE_DIS2_A, _MTL_PIPE_CLKGATE_DIS2_B)
-:3211: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#3211: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:2867:
+#define MTL_MEM_SS_INFO_QGV_POINT_LOW(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8)
-:3216: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#3216: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:2872:
+#define MTL_MEM_SS_INFO_QGV_POINT_HIGH(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8 + 4)
-:3220: CHECK:LINE_SPACING: Please don't use multiple blank lines
#3220: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:2876:
+
+
total: 0 errors, 56 warnings, 20 checks, 6596 lines checked
^ permalink raw reply [flat|nested] 13+ messages in thread
* ✓ CI.KUnit: success for drm/i915: i915_reg.h display split (rev2)
2025-04-15 10:51 [PATCH v2 0/3] drm/i915: i915_reg.h display split Jani Nikula
` (4 preceding siblings ...)
2025-04-15 11:43 ` ✗ CI.checkpatch: warning " Patchwork
@ 2025-04-15 11:44 ` Patchwork
2025-04-15 11:52 ` ✓ CI.Build: " Patchwork
` (4 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2025-04-15 11:44 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-xe
== Series Details ==
Series: drm/i915: i915_reg.h display split (rev2)
URL : https://patchwork.freedesktop.org/series/144506/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[11:43:23] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:43:27] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[11:43:53] Starting KUnit Kernel (1/1)...
[11:43:53] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:43:54] ================== guc_buf (11 subtests) ===================
[11:43:54] [PASSED] test_smallest
[11:43:54] [PASSED] test_largest
[11:43:54] [PASSED] test_granular
[11:43:54] [PASSED] test_unique
[11:43:54] [PASSED] test_overlap
[11:43:54] [PASSED] test_reusable
[11:43:54] [PASSED] test_too_big
[11:43:54] [PASSED] test_flush
[11:43:54] [PASSED] test_lookup
[11:43:54] [PASSED] test_data
[11:43:54] [PASSED] test_class
[11:43:54] ===================== [PASSED] guc_buf =====================
[11:43:54] =================== guc_dbm (7 subtests) ===================
[11:43:54] [PASSED] test_empty
[11:43:54] [PASSED] test_default
[11:43:54] ======================== test_size ========================
[11:43:54] [PASSED] 4
[11:43:54] [PASSED] 8
[11:43:54] [PASSED] 32
[11:43:54] [PASSED] 256
[11:43:54] ==================== [PASSED] test_size ====================
[11:43:54] ======================= test_reuse ========================
[11:43:54] [PASSED] 4
[11:43:54] [PASSED] 8
[11:43:54] [PASSED] 32
[11:43:54] [PASSED] 256
[11:43:54] =================== [PASSED] test_reuse ====================
[11:43:54] =================== test_range_overlap ====================
[11:43:54] [PASSED] 4
[11:43:54] [PASSED] 8
[11:43:54] [PASSED] 32
[11:43:54] [PASSED] 256
[11:43:54] =============== [PASSED] test_range_overlap ================
[11:43:54] =================== test_range_compact ====================
[11:43:54] [PASSED] 4
[11:43:54] [PASSED] 8
[11:43:54] [PASSED] 32
[11:43:54] [PASSED] 256
[11:43:54] =============== [PASSED] test_range_compact ================
[11:43:54] ==================== test_range_spare =====================
[11:43:54] [PASSED] 4
[11:43:54] [PASSED] 8
[11:43:54] [PASSED] 32
[11:43:54] [PASSED] 256
[11:43:54] ================ [PASSED] test_range_spare =================
[11:43:54] ===================== [PASSED] guc_dbm =====================
[11:43:54] =================== guc_idm (6 subtests) ===================
[11:43:54] [PASSED] bad_init
[11:43:54] [PASSED] no_init
[11:43:54] [PASSED] init_fini
[11:43:54] [PASSED] check_used
[11:43:54] [PASSED] check_quota
[11:43:54] [PASSED] check_all
[11:43:54] ===================== [PASSED] guc_idm =====================
[11:43:54] ================== no_relay (3 subtests) ===================
[11:43:54] [PASSED] xe_drops_guc2pf_if_not_ready
[11:43:54] [PASSED] xe_drops_guc2vf_if_not_ready
[11:43:54] [PASSED] xe_rejects_send_if_not_ready
[11:43:54] ==================== [PASSED] no_relay =====================
[11:43:54] ================== pf_relay (14 subtests) ==================
[11:43:54] [PASSED] pf_rejects_guc2pf_too_short
[11:43:54] [PASSED] pf_rejects_guc2pf_too_long
[11:43:54] [PASSED] pf_rejects_guc2pf_no_payload
[11:43:54] [PASSED] pf_fails_no_payload
[11:43:54] [PASSED] pf_fails_bad_origin
[11:43:54] [PASSED] pf_fails_bad_type
[11:43:54] [PASSED] pf_txn_reports_error
[11:43:54] [PASSED] pf_txn_sends_pf2guc
[11:43:54] [PASSED] pf_sends_pf2guc
[11:43:54] [SKIPPED] pf_loopback_nop
[11:43:54] [SKIPPED] pf_loopback_echo
[11:43:54] [SKIPPED] pf_loopback_fail
[11:43:54] [SKIPPED] pf_loopback_busy
[11:43:54] [SKIPPED] pf_loopback_retry
[11:43:54] ==================== [PASSED] pf_relay =====================
[11:43:54] ================== vf_relay (3 subtests) ===================
[11:43:54] [PASSED] vf_rejects_guc2vf_too_short
[11:43:54] [PASSED] vf_rejects_guc2vf_too_long
[11:43:54] [PASSED] vf_rejects_guc2vf_no_payload
[11:43:54] ==================== [PASSED] vf_relay =====================
[11:43:54] ================= pf_service (11 subtests) =================
[11:43:54] [PASSED] pf_negotiate_any
[11:43:54] [PASSED] pf_negotiate_base_match
[11:43:54] [PASSED] pf_negotiate_base_newer
[11:43:54] [PASSED] pf_negotiate_base_next
[11:43:54] [SKIPPED] pf_negotiate_base_older
[11:43:54] [PASSED] pf_negotiate_base_prev
[11:43:54] [PASSED] pf_negotiate_latest_match
[11:43:54] [PASSED] pf_negotiate_latest_newer
[11:43:54] [PASSED] pf_negotiate_latest_next
[11:43:54] [SKIPPED] pf_negotiate_latest_older
[11:43:54] [SKIPPED] pf_negotiate_latest_prev
[11:43:54] =================== [PASSED] pf_service ====================
[11:43:54] ===================== lmtt (1 subtest) =====================
[11:43:54] ======================== test_ops =========================
[11:43:54] [PASSED] 2-level
[11:43:54] [PASSED] multi-level
[11:43:54] ==================== [PASSED] test_ops =====================
[11:43:54] ====================== [PASSED] lmtt =======================
[11:43:54] =================== xe_mocs (2 subtests) ===================
[11:43:54] ================ xe_live_mocs_kernel_kunit ================
[11:43:54] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[11:43:54] ================ xe_live_mocs_reset_kunit =================
[11:43:54] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[11:43:54] ==================== [SKIPPED] xe_mocs =====================
[11:43:54] ================= xe_migrate (2 subtests) ==================
[11:43:54] ================= xe_migrate_sanity_kunit =================
[11:43:54] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[11:43:54] ================== xe_validate_ccs_kunit ==================
[11:43:54] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[11:43:54] =================== [SKIPPED] xe_migrate ===================
[11:43:54] ================== xe_dma_buf (1 subtest) ==================
[11:43:54] ==================== xe_dma_buf_kunit =====================
[11:43:54] ================ [SKIPPED] xe_dma_buf_kunit ================
[11:43:54] =================== [SKIPPED] xe_dma_buf ===================
[11:43:54] ================= xe_bo_shrink (1 subtest) =================
[11:43:54] =================== xe_bo_shrink_kunit ====================
[11:43:54] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[11:43:54] ================== [SKIPPED] xe_bo_shrink ==================
[11:43:54] ==================== xe_bo (2 subtests) ====================
[11:43:54] ================== xe_ccs_migrate_kunit ===================
[11:43:54] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[11:43:54] ==================== xe_bo_evict_kunit ====================
[11:43:54] =============== [SKIPPED] xe_bo_evict_kunit ================
[11:43:54] ===================== [SKIPPED] xe_bo ======================
[11:43:54] ==================== args (11 subtests) ====================
[11:43:54] [PASSED] count_args_test
[11:43:54] [PASSED] call_args_example
[11:43:54] [PASSED] call_args_test
[11:43:54] [PASSED] drop_first_arg_example
[11:43:54] [PASSED] drop_first_arg_test
[11:43:54] [PASSED] first_arg_example
[11:43:54] [PASSED] first_arg_test
[11:43:54] [PASSED] last_arg_example
[11:43:54] [PASSED] last_arg_test
[11:43:54] [PASSED] pick_arg_example
[11:43:54] [PASSED] sep_comma_example
[11:43:54] ====================== [PASSED] args =======================
[11:43:54] =================== xe_pci (2 subtests) ====================
[11:43:54] [PASSED] xe_gmdid_graphics_ip
[11:43:54] [PASSED] xe_gmdid_media_ip
[11:43:54] ===================== [PASSED] xe_pci ======================
[11:43:54] =================== xe_rtp (2 subtests) ====================
[11:43:54] =============== xe_rtp_process_to_sr_tests ================
[11:43:54] [PASSED] coalesce-same-reg
[11:43:54] [PASSED] no-match-no-add
[11:43:54] [PASSED] match-or
[11:43:54] [PASSED] match-or-xfail
[11:43:54] [PASSED] no-match-no-add-multiple-rules
[11:43:54] [PASSED] two-regs-two-entries
[11:43:54] [PASSED] clr-one-set-other
[11:43:54] [PASSED] set-field
[11:43:54] [PASSED] conflict-duplicate
[11:43:54] [PASSED] conflict-not-disjoint
stty: 'standard input': Inappropriate ioctl for device
[11:43:54] [PASSED] conflict-reg-type
[11:43:54] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[11:43:54] ================== xe_rtp_process_tests ===================
[11:43:54] [PASSED] active1
[11:43:54] [PASSED] active2
[11:43:54] [PASSED] active-inactive
[11:43:54] [PASSED] inactive-active
[11:43:54] [PASSED] inactive-1st_or_active-inactive
[11:43:54] [PASSED] inactive-2nd_or_active-inactive
[11:43:54] [PASSED] inactive-last_or_active-inactive
[11:43:54] [PASSED] inactive-no_or_active-inactive
[11:43:54] ============== [PASSED] xe_rtp_process_tests ===============
[11:43:54] ===================== [PASSED] xe_rtp ======================
[11:43:54] ==================== xe_wa (1 subtest) =====================
[11:43:54] ======================== xe_wa_gt =========================
[11:43:54] [PASSED] TIGERLAKE (B0)
[11:43:54] [PASSED] DG1 (A0)
[11:43:54] [PASSED] DG1 (B0)
[11:43:54] [PASSED] ALDERLAKE_S (A0)
[11:43:54] [PASSED] ALDERLAKE_S (B0)
[11:43:54] [PASSED] ALDERLAKE_S (C0)
[11:43:54] [PASSED] ALDERLAKE_S (D0)
[11:43:54] [PASSED] ALDERLAKE_P (A0)
[11:43:54] [PASSED] ALDERLAKE_P (B0)
[11:43:54] [PASSED] ALDERLAKE_P (C0)
[11:43:54] [PASSED] ALDERLAKE_S_RPLS (D0)
[11:43:54] [PASSED] ALDERLAKE_P_RPLU (E0)
[11:43:54] [PASSED] DG2_G10 (C0)
[11:43:54] [PASSED] DG2_G11 (B1)
[11:43:54] [PASSED] DG2_G12 (A1)
[11:43:54] [PASSED] METEORLAKE (g:A0, m:A0)
[11:43:54] [PASSED] METEORLAKE (g:A0, m:A0)
[11:43:54] [PASSED] METEORLAKE (g:A0, m:A0)
[11:43:54] [PASSED] LUNARLAKE (g:A0, m:A0)
[11:43:54] [PASSED] LUNARLAKE (g:B0, m:A0)
[11:43:54] [PASSED] BATTLEMAGE (g:A0, m:A1)
[11:43:54] ==================== [PASSED] xe_wa_gt =====================
[11:43:54] ====================== [PASSED] xe_wa ======================
[11:43:54] ============================================================
[11:43:54] Testing complete. Ran 133 tests: passed: 117, skipped: 16
[11:43:54] Elapsed time: 30.964s total, 4.261s configuring, 26.387s building, 0.294s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[11:43:54] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:43:56] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[11:44:17] Starting KUnit Kernel (1/1)...
[11:44:17] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:44:17] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[11:44:17] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[11:44:17] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[11:44:17] =========== drm_validate_clone_mode (2 subtests) ===========
[11:44:17] ============== drm_test_check_in_clone_mode ===============
[11:44:17] [PASSED] in_clone_mode
[11:44:17] [PASSED] not_in_clone_mode
[11:44:17] ========== [PASSED] drm_test_check_in_clone_mode ===========
[11:44:17] =============== drm_test_check_valid_clones ===============
[11:44:17] [PASSED] not_in_clone_mode
[11:44:17] [PASSED] valid_clone
[11:44:17] [PASSED] invalid_clone
[11:44:17] =========== [PASSED] drm_test_check_valid_clones ===========
[11:44:17] ============= [PASSED] drm_validate_clone_mode =============
[11:44:17] ============= drm_validate_modeset (1 subtest) =============
[11:44:17] [PASSED] drm_test_check_connector_changed_modeset
[11:44:17] ============== [PASSED] drm_validate_modeset ===============
[11:44:17] ====== drm_test_bridge_get_current_state (2 subtests) ======
[11:44:17] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[11:44:17] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[11:44:17] ======== [PASSED] drm_test_bridge_get_current_state ========
[11:44:17] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[11:44:17] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[11:44:17] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[11:44:17] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[11:44:17] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[11:44:17] ================== drm_buddy (7 subtests) ==================
[11:44:17] [PASSED] drm_test_buddy_alloc_limit
[11:44:17] [PASSED] drm_test_buddy_alloc_optimistic
[11:44:17] [PASSED] drm_test_buddy_alloc_pessimistic
[11:44:17] [PASSED] drm_test_buddy_alloc_pathological
[11:44:17] [PASSED] drm_test_buddy_alloc_contiguous
[11:44:17] [PASSED] drm_test_buddy_alloc_clear
[11:44:17] [PASSED] drm_test_buddy_alloc_range_bias
[11:44:17] ==================== [PASSED] drm_buddy ====================
[11:44:17] ============= drm_cmdline_parser (40 subtests) =============
[11:44:17] [PASSED] drm_test_cmdline_force_d_only
[11:44:17] [PASSED] drm_test_cmdline_force_D_only_dvi
[11:44:17] [PASSED] drm_test_cmdline_force_D_only_hdmi
[11:44:17] [PASSED] drm_test_cmdline_force_D_only_not_digital
[11:44:17] [PASSED] drm_test_cmdline_force_e_only
[11:44:17] [PASSED] drm_test_cmdline_res
[11:44:17] [PASSED] drm_test_cmdline_res_vesa
[11:44:17] [PASSED] drm_test_cmdline_res_vesa_rblank
[11:44:17] [PASSED] drm_test_cmdline_res_rblank
[11:44:17] [PASSED] drm_test_cmdline_res_bpp
[11:44:17] [PASSED] drm_test_cmdline_res_refresh
[11:44:17] [PASSED] drm_test_cmdline_res_bpp_refresh
[11:44:17] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[11:44:17] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[11:44:17] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[11:44:17] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[11:44:17] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[11:44:17] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[11:44:17] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[11:44:17] [PASSED] drm_test_cmdline_res_margins_force_on
[11:44:17] [PASSED] drm_test_cmdline_res_vesa_margins
[11:44:17] [PASSED] drm_test_cmdline_name
[11:44:17] [PASSED] drm_test_cmdline_name_bpp
[11:44:17] [PASSED] drm_test_cmdline_name_option
[11:44:17] [PASSED] drm_test_cmdline_name_bpp_option
[11:44:17] [PASSED] drm_test_cmdline_rotate_0
[11:44:17] [PASSED] drm_test_cmdline_rotate_90
[11:44:17] [PASSED] drm_test_cmdline_rotate_180
[11:44:17] [PASSED] drm_test_cmdline_rotate_270
[11:44:17] [PASSED] drm_test_cmdline_hmirror
[11:44:17] [PASSED] drm_test_cmdline_vmirror
[11:44:17] [PASSED] drm_test_cmdline_margin_options
[11:44:17] [PASSED] drm_test_cmdline_multiple_options
[11:44:17] [PASSED] drm_test_cmdline_bpp_extra_and_option
[11:44:17] [PASSED] drm_test_cmdline_extra_and_option
[11:44:17] [PASSED] drm_test_cmdline_freestanding_options
[11:44:17] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[11:44:17] [PASSED] drm_test_cmdline_panel_orientation
[11:44:17] ================ drm_test_cmdline_invalid =================
[11:44:17] [PASSED] margin_only
[11:44:17] [PASSED] interlace_only
[11:44:17] [PASSED] res_missing_x
[11:44:17] [PASSED] res_missing_y
[11:44:17] [PASSED] res_bad_y
[11:44:17] [PASSED] res_missing_y_bpp
[11:44:17] [PASSED] res_bad_bpp
[11:44:17] [PASSED] res_bad_refresh
[11:44:17] [PASSED] res_bpp_refresh_force_on_off
[11:44:17] [PASSED] res_invalid_mode
[11:44:17] [PASSED] res_bpp_wrong_place_mode
[11:44:17] [PASSED] name_bpp_refresh
[11:44:17] [PASSED] name_refresh
[11:44:17] [PASSED] name_refresh_wrong_mode
[11:44:17] [PASSED] name_refresh_invalid_mode
[11:44:17] [PASSED] rotate_multiple
[11:44:17] [PASSED] rotate_invalid_val
[11:44:17] [PASSED] rotate_truncated
[11:44:17] [PASSED] invalid_option
[11:44:17] [PASSED] invalid_tv_option
[11:44:17] [PASSED] truncated_tv_option
[11:44:17] ============ [PASSED] drm_test_cmdline_invalid =============
[11:44:17] =============== drm_test_cmdline_tv_options ===============
[11:44:17] [PASSED] NTSC
[11:44:17] [PASSED] NTSC_443
[11:44:17] [PASSED] NTSC_J
[11:44:17] [PASSED] PAL
[11:44:17] [PASSED] PAL_M
[11:44:17] [PASSED] PAL_N
[11:44:17] [PASSED] SECAM
[11:44:17] [PASSED] MONO_525
[11:44:17] [PASSED] MONO_625
[11:44:17] =========== [PASSED] drm_test_cmdline_tv_options ===========
[11:44:17] =============== [PASSED] drm_cmdline_parser ================
[11:44:17] ========== drmm_connector_hdmi_init (20 subtests) ==========
[11:44:17] [PASSED] drm_test_connector_hdmi_init_valid
[11:44:17] [PASSED] drm_test_connector_hdmi_init_bpc_8
[11:44:17] [PASSED] drm_test_connector_hdmi_init_bpc_10
[11:44:17] [PASSED] drm_test_connector_hdmi_init_bpc_12
[11:44:17] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[11:44:17] [PASSED] drm_test_connector_hdmi_init_bpc_null
[11:44:17] [PASSED] drm_test_connector_hdmi_init_formats_empty
[11:44:17] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[11:44:17] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[11:44:17] [PASSED] supported_formats=0x9 yuv420_allowed=1
[11:44:17] [PASSED] supported_formats=0x9 yuv420_allowed=0
[11:44:17] [PASSED] supported_formats=0x3 yuv420_allowed=1
[11:44:17] [PASSED] supported_formats=0x3 yuv420_allowed=0
[11:44:17] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[11:44:17] [PASSED] drm_test_connector_hdmi_init_null_ddc
[11:44:17] [PASSED] drm_test_connector_hdmi_init_null_product
[11:44:17] [PASSED] drm_test_connector_hdmi_init_null_vendor
[11:44:17] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[11:44:17] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[11:44:17] [PASSED] drm_test_connector_hdmi_init_product_valid
[11:44:17] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[11:44:17] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[11:44:17] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[11:44:17] ========= drm_test_connector_hdmi_init_type_valid =========
[11:44:17] [PASSED] HDMI-A
[11:44:17] [PASSED] HDMI-B
[11:44:17] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[11:44:17] ======== drm_test_connector_hdmi_init_type_invalid ========
[11:44:17] [PASSED] Unknown
[11:44:17] [PASSED] VGA
[11:44:17] [PASSED] DVI-I
[11:44:17] [PASSED] DVI-D
[11:44:17] [PASSED] DVI-A
[11:44:17] [PASSED] Composite
[11:44:17] [PASSED] SVIDEO
[11:44:17] [PASSED] LVDS
[11:44:17] [PASSED] Component
[11:44:17] [PASSED] DIN
[11:44:17] [PASSED] DP
[11:44:17] [PASSED] TV
[11:44:17] [PASSED] eDP
[11:44:17] [PASSED] Virtual
[11:44:17] [PASSED] DSI
[11:44:17] [PASSED] DPI
[11:44:17] [PASSED] Writeback
[11:44:17] [PASSED] SPI
[11:44:17] [PASSED] USB
[11:44:17] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[11:44:17] ============ [PASSED] drmm_connector_hdmi_init =============
[11:44:17] ============= drmm_connector_init (3 subtests) =============
[11:44:17] [PASSED] drm_test_drmm_connector_init
[11:44:17] [PASSED] drm_test_drmm_connector_init_null_ddc
[11:44:17] ========= drm_test_drmm_connector_init_type_valid =========
[11:44:17] [PASSED] Unknown
[11:44:17] [PASSED] VGA
[11:44:17] [PASSED] DVI-I
[11:44:17] [PASSED] DVI-D
[11:44:17] [PASSED] DVI-A
[11:44:17] [PASSED] Composite
[11:44:17] [PASSED] SVIDEO
[11:44:17] [PASSED] LVDS
[11:44:17] [PASSED] Component
[11:44:17] [PASSED] DIN
[11:44:17] [PASSED] DP
[11:44:17] [PASSED] HDMI-A
[11:44:17] [PASSED] HDMI-B
[11:44:17] [PASSED] TV
[11:44:17] [PASSED] eDP
[11:44:17] [PASSED] Virtual
[11:44:17] [PASSED] DSI
[11:44:17] [PASSED] DPI
[11:44:17] [PASSED] Writeback
[11:44:17] [PASSED] SPI
[11:44:17] [PASSED] USB
[11:44:17] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[11:44:17] =============== [PASSED] drmm_connector_init ===============
[11:44:17] ========= drm_connector_dynamic_init (6 subtests) ==========
[11:44:17] [PASSED] drm_test_drm_connector_dynamic_init
[11:44:17] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[11:44:17] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[11:44:17] [PASSED] drm_test_drm_connector_dynamic_init_properties
[11:44:17] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[11:44:17] [PASSED] Unknown
[11:44:17] [PASSED] VGA
[11:44:17] [PASSED] DVI-I
[11:44:17] [PASSED] DVI-D
[11:44:17] [PASSED] DVI-A
[11:44:17] [PASSED] Composite
[11:44:17] [PASSED] SVIDEO
[11:44:17] [PASSED] LVDS
[11:44:17] [PASSED] Component
[11:44:17] [PASSED] DIN
[11:44:17] [PASSED] DP
[11:44:17] [PASSED] HDMI-A
[11:44:17] [PASSED] HDMI-B
[11:44:17] [PASSED] TV
[11:44:17] [PASSED] eDP
[11:44:17] [PASSED] Virtual
[11:44:17] [PASSED] DSI
[11:44:17] [PASSED] DPI
[11:44:17] [PASSED] Writeback
[11:44:17] [PASSED] SPI
[11:44:17] [PASSED] USB
[11:44:17] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[11:44:17] ======== drm_test_drm_connector_dynamic_init_name =========
[11:44:17] [PASSED] Unknown
[11:44:17] [PASSED] VGA
[11:44:17] [PASSED] DVI-I
[11:44:17] [PASSED] DVI-D
[11:44:17] [PASSED] DVI-A
[11:44:17] [PASSED] Composite
[11:44:17] [PASSED] SVIDEO
[11:44:17] [PASSED] LVDS
[11:44:17] [PASSED] Component
[11:44:17] [PASSED] DIN
[11:44:17] [PASSED] DP
[11:44:17] [PASSED] HDMI-A
[11:44:17] [PASSED] HDMI-B
[11:44:17] [PASSED] TV
[11:44:17] [PASSED] eDP
[11:44:17] [PASSED] Virtual
[11:44:17] [PASSED] DSI
[11:44:17] [PASSED] DPI
[11:44:17] [PASSED] Writeback
[11:44:17] [PASSED] SPI
[11:44:17] [PASSED] USB
[11:44:17] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[11:44:17] =========== [PASSED] drm_connector_dynamic_init ============
[11:44:17] ==== drm_connector_dynamic_register_early (4 subtests) =====
[11:44:17] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[11:44:17] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[11:44:17] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[11:44:17] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[11:44:17] ====== [PASSED] drm_connector_dynamic_register_early =======
[11:44:17] ======= drm_connector_dynamic_register (7 subtests) ========
[11:44:17] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[11:44:17] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[11:44:17] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[11:44:17] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[11:44:17] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[11:44:17] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[11:44:17] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[11:44:17] ========= [PASSED] drm_connector_dynamic_register ==========
[11:44:17] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[11:44:17] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[11:44:17] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[11:44:17] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[11:44:17] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[11:44:17] ========== drm_test_get_tv_mode_from_name_valid ===========
[11:44:17] [PASSED] NTSC
[11:44:17] [PASSED] NTSC-443
[11:44:17] [PASSED] NTSC-J
[11:44:17] [PASSED] PAL
[11:44:17] [PASSED] PAL-M
[11:44:17] [PASSED] PAL-N
[11:44:17] [PASSED] SECAM
[11:44:17] [PASSED] Mono
[11:44:17] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[11:44:17] [PASSED] drm_test_get_tv_mode_from_name_truncated
[11:44:17] ============ [PASSED] drm_get_tv_mode_from_name ============
[11:44:17] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[11:44:17] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[11:44:17] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[11:44:17] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[11:44:17] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[11:44:17] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[11:44:17] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[11:44:17] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[11:44:17] [PASSED] VIC 96
[11:44:17] [PASSED] VIC 97
[11:44:17] [PASSED] VIC 101
[11:44:17] [PASSED] VIC 102
[11:44:17] [PASSED] VIC 106
[11:44:17] [PASSED] VIC 107
[11:44:17] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[11:44:17] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[11:44:17] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[11:44:17] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[11:44:17] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[11:44:17] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[11:44:17] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[11:44:17] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[11:44:17] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[11:44:17] [PASSED] Automatic
[11:44:17] [PASSED] Full
[11:44:17] [PASSED] Limited 16:235
[11:44:17] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[11:44:17] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[11:44:17] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[11:44:17] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[11:44:17] === drm_test_drm_hdmi_connector_get_output_format_name ====
[11:44:17] [PASSED] RGB
[11:44:17] [PASSED] YUV 4:2:0
[11:44:17] [PASSED] YUV 4:2:2
[11:44:17] [PASSED] YUV 4:4:4
[11:44:17] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[11:44:17] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[11:44:17] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[11:44:17] ============= drm_damage_helper (21 subtests) ==============
[11:44:17] [PASSED] drm_test_damage_iter_no_damage
[11:44:17] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[11:44:17] [PASSED] drm_test_damage_iter_no_damage_src_moved
[11:44:17] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[11:44:17] [PASSED] drm_test_damage_iter_no_damage_not_visible
[11:44:17] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[11:44:17] [PASSED] drm_test_damage_iter_no_damage_no_fb
[11:44:17] [PASSED] drm_test_damage_iter_simple_damage
[11:44:17] [PASSED] drm_test_damage_iter_single_damage
[11:44:17] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[11:44:17] [PASSED] drm_test_damage_iter_single_damage_outside_src
[11:44:17] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[11:44:17] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[11:44:17] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[11:44:17] [PASSED] drm_test_damage_iter_single_damage_src_moved
[11:44:17] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[11:44:17] [PASSED] drm_test_damage_iter_damage
[11:44:17] [PASSED] drm_test_damage_iter_damage_one_intersect
[11:44:17] [PASSED] drm_test_damage_iter_damage_one_outside
[11:44:17] [PASSED] drm_test_damage_iter_damage_src_moved
[11:44:17] [PASSED] drm_test_damage_iter_damage_not_visible
[11:44:17] ================ [PASSED] drm_damage_helper ================
[11:44:17] ============== drm_dp_mst_helper (3 subtests) ==============
[11:44:17] ============== drm_test_dp_mst_calc_pbn_mode ==============
[11:44:17] [PASSED] Clock 154000 BPP 30 DSC disabled
[11:44:17] [PASSED] Clock 234000 BPP 30 DSC disabled
[11:44:17] [PASSED] Clock 297000 BPP 24 DSC disabled
[11:44:17] [PASSED] Clock 332880 BPP 24 DSC enabled
[11:44:17] [PASSED] Clock 324540 BPP 24 DSC enabled
[11:44:17] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[11:44:17] ============== drm_test_dp_mst_calc_pbn_div ===============
[11:44:17] [PASSED] Link rate 2000000 lane count 4
[11:44:17] [PASSED] Link rate 2000000 lane count 2
[11:44:17] [PASSED] Link rate 2000000 lane count 1
[11:44:17] [PASSED] Link rate 1350000 lane count 4
[11:44:17] [PASSED] Link rate 1350000 lane count 2
[11:44:17] [PASSED] Link rate 1350000 lane count 1
[11:44:17] [PASSED] Link rate 1000000 lane count 4
[11:44:17] [PASSED] Link rate 1000000 lane count 2
[11:44:17] [PASSED] Link rate 1000000 lane count 1
[11:44:17] [PASSED] Link rate 810000 lane count 4
[11:44:17] [PASSED] Link rate 810000 lane count 2
[11:44:17] [PASSED] Link rate 810000 lane count 1
[11:44:17] [PASSED] Link rate 540000 lane count 4
[11:44:17] [PASSED] Link rate 540000 lane count 2
[11:44:17] [PASSED] Link rate 540000 lane count 1
[11:44:17] [PASSED] Link rate 270000 lane count 4
[11:44:17] [PASSED] Link rate 270000 lane count 2
[11:44:17] [PASSED] Link rate 270000 lane count 1
[11:44:17] [PASSED] Link rate 162000 lane count 4
[11:44:17] [PASSED] Link rate 162000 lane count 2
[11:44:17] [PASSED] Link rate 162000 lane count 1
[11:44:17] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[11:44:17] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[11:44:17] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[11:44:17] [PASSED] DP_POWER_UP_PHY with port number
[11:44:17] [PASSED] DP_POWER_DOWN_PHY with port number
[11:44:17] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[11:44:17] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[11:44:17] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[11:44:17] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[11:44:17] [PASSED] DP_QUERY_PAYLOAD with port number
[11:44:17] [PASSED] DP_QUERY_PAYLOAD with VCPI
[11:44:17] [PASSED] DP_REMOTE_DPCD_READ with port number
[11:44:17] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[11:44:17] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[11:44:17] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[11:44:17] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[11:44:17] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[11:44:17] [PASSED] DP_REMOTE_I2C_READ with port number
[11:44:17] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[11:44:17] [PASSED] DP_REMOTE_I2C_READ with transactions array
[11:44:17] [PASSED] DP_REMOTE_I2C_WRITE with port number
[11:44:17] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[11:44:17] [PASSED] DP_REMOTE_I2C_WRITE with data array
[11:44:17] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[11:44:17] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[11:44:17] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[11:44:17] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[11:44:17] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[11:44:17] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[11:44:17] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[11:44:17] ================ [PASSED] drm_dp_mst_helper ================
[11:44:17] ================== drm_exec (7 subtests) ===================
[11:44:17] [PASSED] sanitycheck
[11:44:17] [PASSED] test_lock
[11:44:17] [PASSED] test_lock_unlock
[11:44:17] [PASSED] test_duplicates
[11:44:17] [PASSED] test_prepare
[11:44:17] [PASSED] test_prepare_array
[11:44:17] [PASSED] test_multiple_loops
[11:44:17] ==================== [PASSED] drm_exec =====================
[11:44:17] =========== drm_format_helper_test (18 subtests) ===========
[11:44:17] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[11:44:17] [PASSED] single_pixel_source_buffer
[11:44:17] [PASSED] single_pixel_clip_rectangle
[11:44:17] [PASSED] well_known_colors
[11:44:17] [PASSED] destination_pitch
[11:44:17] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[11:44:17] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[11:44:17] [PASSED] single_pixel_source_buffer
[11:44:17] [PASSED] single_pixel_clip_rectangle
[11:44:17] [PASSED] well_known_colors
[11:44:17] [PASSED] destination_pitch
[11:44:17] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[11:44:17] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[11:44:17] [PASSED] single_pixel_source_buffer
[11:44:17] [PASSED] single_pixel_clip_rectangle
[11:44:17] [PASSED] well_known_colors
[11:44:17] [PASSED] destination_pitch
[11:44:17] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[11:44:17] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[11:44:17] [PASSED] single_pixel_source_buffer
[11:44:17] [PASSED] single_pixel_clip_rectangle
[11:44:17] [PASSED] well_known_colors
[11:44:17] [PASSED] destination_pitch
[11:44:17] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[11:44:17] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[11:44:17] [PASSED] single_pixel_source_buffer
[11:44:17] [PASSED] single_pixel_clip_rectangle
[11:44:17] [PASSED] well_known_colors
[11:44:17] [PASSED] destination_pitch
[11:44:17] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[11:44:17] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[11:44:17] [PASSED] single_pixel_source_buffer
[11:44:17] [PASSED] single_pixel_clip_rectangle
[11:44:17] [PASSED] well_known_colors
[11:44:17] [PASSED] destination_pitch
[11:44:17] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[11:44:17] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[11:44:17] [PASSED] single_pixel_source_buffer
[11:44:17] [PASSED] single_pixel_clip_rectangle
[11:44:17] [PASSED] well_known_colors
[11:44:17] [PASSED] destination_pitch
[11:44:17] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[11:44:17] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[11:44:17] [PASSED] single_pixel_source_buffer
[11:44:17] [PASSED] single_pixel_clip_rectangle
[11:44:17] [PASSED] well_known_colors
[11:44:17] [PASSED] destination_pitch
[11:44:17] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[11:44:17] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[11:44:17] [PASSED] single_pixel_source_buffer
[11:44:17] [PASSED] single_pixel_clip_rectangle
[11:44:17] [PASSED] well_known_colors
[11:44:17] [PASSED] destination_pitch
[11:44:17] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[11:44:17] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[11:44:17] [PASSED] single_pixel_source_buffer
[11:44:17] [PASSED] single_pixel_clip_rectangle
[11:44:17] [PASSED] well_known_colors
[11:44:17] [PASSED] destination_pitch
[11:44:17] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[11:44:17] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[11:44:17] [PASSED] single_pixel_source_buffer
[11:44:17] [PASSED] single_pixel_clip_rectangle
[11:44:17] [PASSED] well_known_colors
[11:44:17] [PASSED] destination_pitch
[11:44:17] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[11:44:17] ============== drm_test_fb_xrgb8888_to_mono ===============
[11:44:17] [PASSED] single_pixel_source_buffer
[11:44:17] [PASSED] single_pixel_clip_rectangle
[11:44:17] [PASSED] well_known_colors
[11:44:17] [PASSED] destination_pitch
[11:44:17] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[11:44:17] ==================== drm_test_fb_swab =====================
[11:44:17] [PASSED] single_pixel_source_buffer
[11:44:17] [PASSED] single_pixel_clip_rectangle
[11:44:17] [PASSED] well_known_colors
[11:44:17] [PASSED] destination_pitch
[11:44:17] ================ [PASSED] drm_test_fb_swab =================
[11:44:17] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[11:44:17] [PASSED] single_pixel_source_buffer
[11:44:17] [PASSED] single_pixel_clip_rectangle
[11:44:17] [PASSED] well_known_colors
[11:44:17] [PASSED] destination_pitch
[11:44:17] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[11:44:17] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[11:44:17] [PASSED] single_pixel_source_buffer
[11:44:17] [PASSED] single_pixel_clip_rectangle
[11:44:17] [PASSED] well_known_colors
[11:44:17] [PASSED] destination_pitch
[11:44:17] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[11:44:17] ================= drm_test_fb_clip_offset =================
[11:44:17] [PASSED] pass through
[11:44:17] [PASSED] horizontal offset
[11:44:17] [PASSED] vertical offset
[11:44:17] [PASSED] horizontal and vertical offset
[11:44:17] [PASSED] horizontal offset (custom pitch)
[11:44:17] [PASSED] vertical offset (custom pitch)
[11:44:17] [PASSED] horizontal and vertical offset (custom pitch)
[11:44:17] ============= [PASSED] drm_test_fb_clip_offset =============
[11:44:17] ============== drm_test_fb_build_fourcc_list ==============
[11:44:17] [PASSED] no native formats
[11:44:17] [PASSED] XRGB8888 as native format
[11:44:17] [PASSED] remove duplicates
[11:44:17] [PASSED] convert alpha formats
[11:44:17] [PASSED] random formats
[11:44:17] ========== [PASSED] drm_test_fb_build_fourcc_list ==========
[11:44:17] =================== drm_test_fb_memcpy ====================
[11:44:17] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[11:44:17] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[11:44:17] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[11:44:17] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[11:44:17] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[11:44:17] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[11:44:17] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[11:44:17] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[11:44:17] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[11:44:17] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[11:44:17] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[11:44:17] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[11:44:17] =============== [PASSED] drm_test_fb_memcpy ================
[11:44:17] ============= [PASSED] drm_format_helper_test ==============
[11:44:17] ================= drm_format (18 subtests) =================
[11:44:17] [PASSED] drm_test_format_block_width_invalid
[11:44:17] [PASSED] drm_test_format_block_width_one_plane
[11:44:17] [PASSED] drm_test_format_block_width_two_plane
[11:44:17] [PASSED] drm_test_format_block_width_three_plane
[11:44:17] [PASSED] drm_test_format_block_width_tiled
[11:44:17] [PASSED] drm_test_format_block_height_invalid
[11:44:17] [PASSED] drm_test_format_block_height_one_plane
[11:44:17] [PASSED] drm_test_format_block_height_two_plane
[11:44:17] [PASSED] drm_test_format_block_height_three_plane
[11:44:17] [PASSED] drm_test_format_block_height_tiled
[11:44:17] [PASSED] drm_test_format_min_pitch_invalid
[11:44:17] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[11:44:17] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[11:44:17] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[11:44:17] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[11:44:17] [PASSED] drm_test_format_min_pitch_two_plane
[11:44:17] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[11:44:17] [PASSED] drm_test_format_min_pitch_tiled
[11:44:17] =================== [PASSED] drm_format ====================
[11:44:17] ============== drm_framebuffer (10 subtests) ===============
[11:44:17] ========== drm_test_framebuffer_check_src_coords ==========
[11:44:17] [PASSED] Success: source fits into fb
[11:44:17] [PASSED] Fail: overflowing fb with x-axis coordinate
[11:44:17] [PASSED] Fail: overflowing fb with y-axis coordinate
[11:44:17] [PASSED] Fail: overflowing fb with source width
[11:44:17] [PASSED] Fail: overflowing fb with source height
[11:44:17] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[11:44:17] [PASSED] drm_test_framebuffer_cleanup
[11:44:17] =============== drm_test_framebuffer_create ===============
[11:44:17] [PASSED] ABGR8888 normal sizes
[11:44:17] [PASSED] ABGR8888 max sizes
[11:44:17] [PASSED] ABGR8888 pitch greater than min required
[11:44:17] [PASSED] ABGR8888 pitch less than min required
[11:44:17] [PASSED] ABGR8888 Invalid width
[11:44:17] [PASSED] ABGR8888 Invalid buffer handle
[11:44:17] [PASSED] No pixel format
[11:44:17] [PASSED] ABGR8888 Width 0
[11:44:17] [PASSED] ABGR8888 Height 0
[11:44:17] [PASSED] ABGR8888 Out of bound height * pitch combination
[11:44:17] [PASSED] ABGR8888 Large buffer offset
[11:44:17] [PASSED] ABGR8888 Buffer offset for inexistent plane
[11:44:17] [PASSED] ABGR8888 Invalid flag
[11:44:17] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[11:44:17] [PASSED] ABGR8888 Valid buffer modifier
[11:44:17] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[11:44:17] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[11:44:17] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[11:44:17] [PASSED] NV12 Normal sizes
[11:44:17] [PASSED] NV12 Max sizes
[11:44:17] [PASSED] NV12 Invalid pitch
[11:44:17] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[11:44:17] [PASSED] NV12 different modifier per-plane
[11:44:17] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[11:44:17] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[11:44:17] [PASSED] NV12 Modifier for inexistent plane
[11:44:17] [PASSED] NV12 Handle for inexistent plane
[11:44:17] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[11:44:17] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[11:44:17] [PASSED] YVU420 Normal sizes
[11:44:17] [PASSED] YVU420 Max sizes
[11:44:17] [PASSED] YVU420 Invalid pitch
[11:44:17] [PASSED] YVU420 Different pitches
[11:44:17] [PASSED] YVU420 Different buffer offsets/pitches
[11:44:17] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[11:44:17] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[11:44:17] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[11:44:17] [PASSED] YVU420 Valid modifier
[11:44:17] [PASSED] YVU420 Different modifiers per plane
[11:44:17] [PASSED] YVU420 Modifier for inexistent plane
[11:44:17] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[11:44:17] [PASSED] X0L2 Normal sizes
[11:44:17] [PASSED] X0L2 Max sizes
[11:44:17] [PASSED] X0L2 Invalid pitch
[11:44:17] [PASSED] X0L2 Pitch greater than minimum required
[11:44:17] [PASSED] X0L2 Handle for inexistent plane
[11:44:17] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[11:44:17] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[11:44:17] [PASSED] X0L2 Valid modifier
[11:44:17] [PASSED] X0L2 Modifier for inexistent plane
[11:44:17] =========== [PASSED] drm_test_framebuffer_create ===========
[11:44:17] [PASSED] drm_test_framebuffer_free
[11:44:17] [PASSED] drm_test_framebuffer_init
[11:44:17] [PASSED] drm_test_framebuffer_init_bad_format
[11:44:17] [PASSED] drm_test_framebuffer_init_dev_mismatch
[11:44:17] [PASSED] drm_test_framebuffer_lookup
[11:44:17] [PASSED] drm_test_framebuffer_lookup_inexistent
[11:44:17] [PASSED] drm_test_framebuffer_modifiers_not_supported
[11:44:17] ================= [PASSED] drm_framebuffer =================
[11:44:17] ================ drm_gem_shmem (8 subtests) ================
[11:44:17] [PASSED] drm_gem_shmem_test_obj_create
[11:44:17] [PASSED] drm_gem_shmem_test_obj_create_private
[11:44:17] [PASSED] drm_gem_shmem_test_pin_pages
[11:44:17] [PASSED] drm_gem_shmem_test_vmap
[11:44:17] [PASSED] drm_gem_shmem_test_get_pages_sgt
[11:44:17] [PASSED] drm_gem_shmem_test_get_sg_table
[11:44:17] [PASSED] drm_gem_shmem_test_madvise
[11:44:17] [PASSED] drm_gem_shmem_test_purge
[11:44:17] ================== [PASSED] drm_gem_shmem ==================
[11:44:17] === drm_atomic_helper_connector_hdmi_check (23 subtests) ===
[11:44:17] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[11:44:17] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[11:44:17] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[11:44:17] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[11:44:17] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[11:44:17] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[11:44:17] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[11:44:17] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[11:44:17] [PASSED] drm_test_check_disable_connector
[11:44:17] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[11:44:17] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback
[11:44:17] [PASSED] drm_test_check_max_tmds_rate_format_fallback
[11:44:17] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[11:44:17] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[11:44:17] [PASSED] drm_test_check_output_bpc_dvi
[11:44:17] [PASSED] drm_test_check_output_bpc_format_vic_1
[11:44:17] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[11:44:17] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[11:44:17] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[11:44:17] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[11:44:17] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[11:44:17] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[11:44:17] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[11:44:17] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[11:44:17] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[11:44:17] [PASSED] drm_test_check_broadcast_rgb_value
[11:44:17] [PASSED] drm_test_check_bpc_8_value
[11:44:17] [PASSED] drm_test_check_bpc_10_value
[11:44:17] [PASSED] drm_test_check_bpc_12_value
[11:44:17] [PASSED] drm_test_check_format_value
[11:44:17] [PASSED] drm_test_check_tmds_char_value
[11:44:17] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[11:44:17] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[11:44:17] [PASSED] drm_test_check_mode_valid
[11:44:17] [PASSED] drm_test_check_mode_valid_reject
[11:44:17] [PASSED] drm_test_check_mode_valid_reject_rate
[11:44:17] [PASSED] drm_test_check_mode_valid_reject_max_clock
[11:44:17] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[11:44:17] ================= drm_managed (2 subtests) =================
[11:44:17] [PASSED] drm_test_managed_release_action
[11:44:17] [PASSED] drm_test_managed_run_action
[11:44:17] =================== [PASSED] drm_managed ===================
[11:44:17] =================== drm_mm (6 subtests) ====================
[11:44:17] [PASSED] drm_test_mm_init
[11:44:17] [PASSED] drm_test_mm_debug
[11:44:17] [PASSED] drm_test_mm_align32
[11:44:17] [PASSED] drm_test_mm_align64
[11:44:17] [PASSED] drm_test_mm_lowest
[11:44:17] [PASSED] drm_test_mm_highest
[11:44:17] ===================== [PASSED] drm_mm ======================
[11:44:17] ============= drm_modes_analog_tv (5 subtests) =============
[11:44:17] [PASSED] drm_test_modes_analog_tv_mono_576i
[11:44:17] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[11:44:17] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[11:44:17] [PASSED] drm_test_modes_analog_tv_pal_576i
[11:44:17] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[11:44:17] =============== [PASSED] drm_modes_analog_tv ===============
[11:44:17] ============== drm_plane_helper (2 subtests) ===============
[11:44:17] =============== drm_test_check_plane_state ================
[11:44:17] [PASSED] clipping_simple
[11:44:17] [PASSED] clipping_rotate_reflect
[11:44:17] [PASSED] positioning_simple
[11:44:17] [PASSED] upscaling
[11:44:17] [PASSED] downscaling
[11:44:17] [PASSED] rounding1
[11:44:17] [PASSED] rounding2
[11:44:17] [PASSED] rounding3
[11:44:17] [PASSED] rounding4
[11:44:17] =========== [PASSED] drm_test_check_plane_state ============
[11:44:17] =========== drm_test_check_invalid_plane_state ============
[11:44:17] [PASSED] positioning_invalid
[11:44:17] [PASSED] upscaling_invalid
[11:44:17] [PASSED] downscaling_invalid
[11:44:17] ======= [PASSED] drm_test_check_invalid_plane_state ========
[11:44:17] ================ [PASSED] drm_plane_helper =================
[11:44:17] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[11:44:17] ====== drm_test_connector_helper_tv_get_modes_check =======
[11:44:17] [PASSED] None
[11:44:17] [PASSED] PAL
[11:44:17] [PASSED] NTSC
[11:44:17] [PASSED] Both, NTSC Default
[11:44:17] [PASSED] Both, PAL Default
[11:44:17] [PASSED] Both, NTSC Default, with PAL on command-line
[11:44:17] [PASSED] Both, PAL Default, with NTSC on command-line
[11:44:17] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[11:44:17] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[11:44:17] ================== drm_rect (9 subtests) ===================
[11:44:17] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[11:44:17] [PASSED] drm_test_rect_clip_scaled_not_clipped
[11:44:17] [PASSED] drm_test_rect_clip_scaled_clipped
[11:44:17] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[11:44:17] ================= drm_test_rect_intersect =================
[11:44:17] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[11:44:17] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[11:44:17] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[11:44:17] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[11:44:17] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[11:44:17] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[11:44:17] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[11:44:17] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[11:44:17] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[11:44:17] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[11:44:17] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[11:44:17] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[11:44:17] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[11:44:17] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[11:44:17] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[11:44:17] ============= [PASSED] drm_test_rect_intersect =============
[11:44:17] ================ drm_test_rect_calc_hscale ================
[11:44:17] [PASSED] normal use
[11:44:17] [PASSED] out of max range
[11:44:17] [PASSED] out of min range
[11:44:17] [PASSED] zero dst
[11:44:17] [PASSED] negative src
[11:44:17] [PASSED] negative dst
[11:44:17] ============ [PASSED] drm_test_rect_calc_hscale ============
[11:44:17] ================ drm_test_rect_calc_vscale ================
[11:44:17] [PASSED] normal use
[11:44:17] [PASSED] out of max range
[11:44:17] [PASSED] out of min range
[11:44:17] [PASSED] zero dst
[11:44:17] [PASSED] negative src
[11:44:17] [PASSED] negative dst
[11:44:17] ============ [PASSED] drm_test_rect_calc_vscale ============
[11:44:17] ================== drm_test_rect_rotate ===================
[11:44:17] [PASSED] reflect-x
[11:44:17] [PASSED] reflect-y
[11:44:17] [PASSED] rotate-0
[11:44:17] [PASSED] rotate-90
[11:44:17] [PASSED] rotate-180
[11:44:17] [PASSED] rotate-270
[11:44:17] ============== [PASSED] drm_test_rect_rotate ===============
[11:44:17] ================ drm_test_rect_rotate_inv =================
[11:44:17] [PASSED] reflect-x
[11:44:17] [PASSED] reflect-y
[11:44:17] [PASSED] rotate-0
[11:44:17] [PASSED] rotate-90
[11:44:17] [PASSED] rotate-180
[11:44:17] [PASSED] rotate-270
[11:44:17] ============ [PASSED] drm_test_rect_rotate_inv =============
stty: 'standard input': Inappropriate ioctl for device
[11:44:17] ==================== [PASSED] drm_rect =====================
[11:44:17] ============================================================
[11:44:17] Testing complete. Ran 608 tests: passed: 608
[11:44:17] Elapsed time: 23.332s total, 1.776s configuring, 21.389s building, 0.148s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[11:44:17] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:44:19] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[11:44:27] Starting KUnit Kernel (1/1)...
[11:44:27] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:44:27] ================= ttm_device (5 subtests) ==================
[11:44:27] [PASSED] ttm_device_init_basic
[11:44:27] [PASSED] ttm_device_init_multiple
[11:44:27] [PASSED] ttm_device_fini_basic
[11:44:27] [PASSED] ttm_device_init_no_vma_man
[11:44:27] ================== ttm_device_init_pools ==================
[11:44:27] [PASSED] No DMA allocations, no DMA32 required
[11:44:27] [PASSED] DMA allocations, DMA32 required
[11:44:27] [PASSED] No DMA allocations, DMA32 required
[11:44:27] [PASSED] DMA allocations, no DMA32 required
[11:44:27] ============== [PASSED] ttm_device_init_pools ==============
[11:44:27] =================== [PASSED] ttm_device ====================
[11:44:27] ================== ttm_pool (8 subtests) ===================
[11:44:27] ================== ttm_pool_alloc_basic ===================
[11:44:27] [PASSED] One page
[11:44:27] [PASSED] More than one page
[11:44:27] [PASSED] Above the allocation limit
[11:44:27] [PASSED] One page, with coherent DMA mappings enabled
[11:44:27] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[11:44:27] ============== [PASSED] ttm_pool_alloc_basic ===============
[11:44:27] ============== ttm_pool_alloc_basic_dma_addr ==============
[11:44:27] [PASSED] One page
[11:44:27] [PASSED] More than one page
[11:44:27] [PASSED] Above the allocation limit
[11:44:27] [PASSED] One page, with coherent DMA mappings enabled
[11:44:27] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[11:44:27] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[11:44:27] [PASSED] ttm_pool_alloc_order_caching_match
[11:44:27] [PASSED] ttm_pool_alloc_caching_mismatch
[11:44:27] [PASSED] ttm_pool_alloc_order_mismatch
[11:44:27] [PASSED] ttm_pool_free_dma_alloc
[11:44:27] [PASSED] ttm_pool_free_no_dma_alloc
[11:44:27] [PASSED] ttm_pool_fini_basic
[11:44:27] ==================== [PASSED] ttm_pool =====================
[11:44:27] ================ ttm_resource (8 subtests) =================
[11:44:27] ================= ttm_resource_init_basic =================
[11:44:27] [PASSED] Init resource in TTM_PL_SYSTEM
[11:44:27] [PASSED] Init resource in TTM_PL_VRAM
[11:44:27] [PASSED] Init resource in a private placement
[11:44:27] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[11:44:27] ============= [PASSED] ttm_resource_init_basic =============
[11:44:27] [PASSED] ttm_resource_init_pinned
[11:44:27] [PASSED] ttm_resource_fini_basic
[11:44:27] [PASSED] ttm_resource_manager_init_basic
[11:44:27] [PASSED] ttm_resource_manager_usage_basic
[11:44:27] [PASSED] ttm_resource_manager_set_used_basic
[11:44:27] [PASSED] ttm_sys_man_alloc_basic
[11:44:27] [PASSED] ttm_sys_man_free_basic
[11:44:27] ================== [PASSED] ttm_resource ===================
[11:44:27] =================== ttm_tt (15 subtests) ===================
[11:44:27] ==================== ttm_tt_init_basic ====================
[11:44:27] [PASSED] Page-aligned size
[11:44:27] [PASSED] Extra pages requested
[11:44:27] ================ [PASSED] ttm_tt_init_basic ================
[11:44:27] [PASSED] ttm_tt_init_misaligned
[11:44:27] [PASSED] ttm_tt_fini_basic
[11:44:27] [PASSED] ttm_tt_fini_sg
[11:44:27] [PASSED] ttm_tt_fini_shmem
[11:44:27] [PASSED] ttm_tt_create_basic
[11:44:27] [PASSED] ttm_tt_create_invalid_bo_type
[11:44:27] [PASSED] ttm_tt_create_ttm_exists
[11:44:27] [PASSED] ttm_tt_create_failed
[11:44:27] [PASSED] ttm_tt_destroy_basic
[11:44:27] [PASSED] ttm_tt_populate_null_ttm
[11:44:27] [PASSED] ttm_tt_populate_populated_ttm
[11:44:27] [PASSED] ttm_tt_unpopulate_basic
[11:44:27] [PASSED] ttm_tt_unpopulate_empty_ttm
[11:44:27] [PASSED] ttm_tt_swapin_basic
[11:44:27] ===================== [PASSED] ttm_tt ======================
[11:44:27] =================== ttm_bo (14 subtests) ===================
[11:44:27] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[11:44:27] [PASSED] Cannot be interrupted and sleeps
[11:44:27] [PASSED] Cannot be interrupted, locks straight away
[11:44:27] [PASSED] Can be interrupted, sleeps
[11:44:27] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[11:44:27] [PASSED] ttm_bo_reserve_locked_no_sleep
[11:44:27] [PASSED] ttm_bo_reserve_no_wait_ticket
[11:44:27] [PASSED] ttm_bo_reserve_double_resv
[11:44:27] [PASSED] ttm_bo_reserve_interrupted
[11:44:27] [PASSED] ttm_bo_reserve_deadlock
[11:44:27] [PASSED] ttm_bo_unreserve_basic
[11:44:27] [PASSED] ttm_bo_unreserve_pinned
[11:44:27] [PASSED] ttm_bo_unreserve_bulk
[11:44:27] [PASSED] ttm_bo_put_basic
[11:44:27] [PASSED] ttm_bo_put_shared_resv
[11:44:27] [PASSED] ttm_bo_pin_basic
[11:44:27] [PASSED] ttm_bo_pin_unpin_resource
[11:44:27] [PASSED] ttm_bo_multiple_pin_one_unpin
[11:44:27] ===================== [PASSED] ttm_bo ======================
[11:44:27] ============== ttm_bo_validate (22 subtests) ===============
[11:44:27] ============== ttm_bo_init_reserved_sys_man ===============
[11:44:27] [PASSED] Buffer object for userspace
[11:44:27] [PASSED] Kernel buffer object
[11:44:27] [PASSED] Shared buffer object
[11:44:27] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[11:44:27] ============== ttm_bo_init_reserved_mock_man ==============
[11:44:27] [PASSED] Buffer object for userspace
[11:44:27] [PASSED] Kernel buffer object
[11:44:27] [PASSED] Shared buffer object
[11:44:27] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[11:44:27] [PASSED] ttm_bo_init_reserved_resv
[11:44:27] ================== ttm_bo_validate_basic ==================
[11:44:27] [PASSED] Buffer object for userspace
[11:44:27] [PASSED] Kernel buffer object
[11:44:27] [PASSED] Shared buffer object
[11:44:27] ============== [PASSED] ttm_bo_validate_basic ==============
[11:44:27] [PASSED] ttm_bo_validate_invalid_placement
[11:44:27] ============= ttm_bo_validate_same_placement ==============
[11:44:27] [PASSED] System manager
[11:44:27] [PASSED] VRAM manager
[11:44:27] ========= [PASSED] ttm_bo_validate_same_placement ==========
[11:44:27] [PASSED] ttm_bo_validate_failed_alloc
[11:44:27] [PASSED] ttm_bo_validate_pinned
[11:44:27] [PASSED] ttm_bo_validate_busy_placement
[11:44:27] ================ ttm_bo_validate_multihop =================
[11:44:27] [PASSED] Buffer object for userspace
[11:44:27] [PASSED] Kernel buffer object
[11:44:27] [PASSED] Shared buffer object
[11:44:27] ============ [PASSED] ttm_bo_validate_multihop =============
[11:44:27] ========== ttm_bo_validate_no_placement_signaled ==========
[11:44:27] [PASSED] Buffer object in system domain, no page vector
[11:44:27] [PASSED] Buffer object in system domain with an existing page vector
[11:44:27] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[11:44:27] ======== ttm_bo_validate_no_placement_not_signaled ========
[11:44:27] [PASSED] Buffer object for userspace
[11:44:27] [PASSED] Kernel buffer object
[11:44:27] [PASSED] Shared buffer object
[11:44:27] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[11:44:27] [PASSED] ttm_bo_validate_move_fence_signaled
[11:44:27] ========= ttm_bo_validate_move_fence_not_signaled =========
[11:44:27] [PASSED] Waits for GPU
[11:44:27] [PASSED] Tries to lock straight away
[11:44:27] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[11:44:27] [PASSED] ttm_bo_validate_swapout
[11:44:27] [PASSED] ttm_bo_validate_happy_evict
[11:44:27] [PASSED] ttm_bo_validate_all_pinned_evict
[11:44:27] [PASSED] ttm_bo_validate_allowed_only_evict
[11:44:27] [PASSED] ttm_bo_validate_deleted_evict
[11:44:27] [PASSED] ttm_bo_validate_busy_domain_evict
[11:44:27] [PASSED] ttm_bo_validate_evict_gutting
[11:44:27] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[11:44:27] ================= [PASSED] ttm_bo_validate =================
[11:44:27] ============================================================
[11:44:27] Testing complete. Ran 102 tests: passed: 102
[11:44:27] Elapsed time: 10.121s total, 1.743s configuring, 7.762s building, 0.529s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 13+ messages in thread
* ✓ CI.Build: success for drm/i915: i915_reg.h display split (rev2)
2025-04-15 10:51 [PATCH v2 0/3] drm/i915: i915_reg.h display split Jani Nikula
` (5 preceding siblings ...)
2025-04-15 11:44 ` ✓ CI.KUnit: success " Patchwork
@ 2025-04-15 11:52 ` Patchwork
2025-04-15 11:55 ` ✓ CI.Hooks: " Patchwork
` (3 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2025-04-15 11:52 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-xe
== Series Details ==
Series: drm/i915: i915_reg.h display split (rev2)
URL : https://patchwork.freedesktop.org/series/144506/
State : success
== Summary ==
lib/modules/6.15.0-rc2-xe+/kernel/arch/x86/events/rapl.ko
lib/modules/6.15.0-rc2-xe+/kernel/arch/x86/kvm/
lib/modules/6.15.0-rc2-xe+/kernel/arch/x86/kvm/kvm.ko
lib/modules/6.15.0-rc2-xe+/kernel/arch/x86/kvm/kvm-intel.ko
lib/modules/6.15.0-rc2-xe+/kernel/arch/x86/kvm/kvm-amd.ko
lib/modules/6.15.0-rc2-xe+/kernel/virt/
lib/modules/6.15.0-rc2-xe+/kernel/virt/lib/
lib/modules/6.15.0-rc2-xe+/kernel/virt/lib/irqbypass.ko
lib/modules/6.15.0-rc2-xe+/kernel/kernel/
lib/modules/6.15.0-rc2-xe+/kernel/kernel/kheaders.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/
lib/modules/6.15.0-rc2-xe+/kernel/crypto/ecrdsa_generic.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/xcbc.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/serpent_generic.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/aria_generic.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/crypto_simd.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/adiantum.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/tcrypt.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/crypto_engine.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/zstd.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/asymmetric_keys/
lib/modules/6.15.0-rc2-xe+/kernel/crypto/asymmetric_keys/pkcs7_test_key.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/asymmetric_keys/pkcs8_key_parser.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/des_generic.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/xctr.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/authenc.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/sm4_generic.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/camellia_generic.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/sm3.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/pcrypt.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/aegis128.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/af_alg.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/algif_aead.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/cmac.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/sm3_generic.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/aes_ti.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/chacha_generic.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/poly1305_generic.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/nhpoly1305.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/crc32_generic.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/essiv.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/ccm.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/wp512.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/streebog_generic.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/authencesn.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/echainiv.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/lrw.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/cryptd.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/crypto_user.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/algif_hash.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/polyval-generic.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/hctr2.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/842.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/pcbc.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/ansi_cprng.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/cast6_generic.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/twofish_common.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/twofish_generic.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/lz4hc.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/blowfish_generic.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/md4.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/chacha20poly1305.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/curve25519-generic.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/lz4.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/rmd160.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/algif_skcipher.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/cast5_generic.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/fcrypt.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/ecdsa_generic.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/sm4.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/cast_common.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/blowfish_common.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/michael_mic.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/async_tx/
lib/modules/6.15.0-rc2-xe+/kernel/crypto/async_tx/async_xor.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/async_tx/async_tx.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/async_tx/async_memcpy.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/async_tx/async_pq.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/async_tx/async_raid6_recov.ko
lib/modules/6.15.0-rc2-xe+/kernel/crypto/algif_rng.ko
lib/modules/6.15.0-rc2-xe+/kernel/block/
lib/modules/6.15.0-rc2-xe+/kernel/block/bfq.ko
lib/modules/6.15.0-rc2-xe+/kernel/block/kyber-iosched.ko
lib/modules/6.15.0-rc2-xe+/build
lib/modules/6.15.0-rc2-xe+/modules.alias.bin
lib/modules/6.15.0-rc2-xe+/modules.builtin
lib/modules/6.15.0-rc2-xe+/modules.softdep
lib/modules/6.15.0-rc2-xe+/modules.alias
lib/modules/6.15.0-rc2-xe+/modules.order
lib/modules/6.15.0-rc2-xe+/modules.symbols
lib/modules/6.15.0-rc2-xe+/modules.dep.bin
+ mv kernel-debug.tar.gz ..
+ cd ..
+ rm -rf archive-debug
+ sync
+ echo '[+] Finished building and packaging '\''debug'\''!'
+ cleanup
[+] Finished building and packaging 'debug'!
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 13+ messages in thread
* ✓ CI.Hooks: success for drm/i915: i915_reg.h display split (rev2)
2025-04-15 10:51 [PATCH v2 0/3] drm/i915: i915_reg.h display split Jani Nikula
` (6 preceding siblings ...)
2025-04-15 11:52 ` ✓ CI.Build: " Patchwork
@ 2025-04-15 11:55 ` Patchwork
2025-04-15 11:56 ` ✓ CI.checksparse: " Patchwork
` (2 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2025-04-15 11:55 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-xe
== Series Details ==
Series: drm/i915: i915_reg.h display split (rev2)
URL : https://patchwork.freedesktop.org/series/144506/
State : success
== Summary ==
run-parts: executing /workspace/ci/hooks/00-showenv
+ export
+ grep -Ei '(^|\W)CI_'
declare -x CI_KERNEL_BUILD_DIR="/workspace/kernel/build64-debug"
declare -x CI_KERNEL_SRC_DIR="/workspace/kernel"
declare -x CI_TOOLS_SRC_DIR="/workspace/ci"
declare -x CI_WORKSPACE_DIR="/workspace"
run-parts: executing /workspace/ci/hooks/10-build-W1
+ SRC_DIR=/workspace/kernel
+ RESTORE_DISPLAY_CONFIG=0
+ '[' -n /workspace/kernel/build64-debug ']'
+ BUILD_DIR=/workspace/kernel/build64-debug
+ cd /workspace/kernel
++ nproc
+ make -j48 O=/workspace/kernel/build64-debug modules_prepare
make[1]: Entering directory '/workspace/kernel/build64-debug'
GEN Makefile
DESCEND objtool
CALL ../scripts/checksyscalls.sh
INSTALL libsubcmd_headers
CC /workspace/kernel/build64-debug/tools/objtool/libsubcmd/exec-cmd.o
CC /workspace/kernel/build64-debug/tools/objtool/libsubcmd/help.o
CC /workspace/kernel/build64-debug/tools/objtool/libsubcmd/pager.o
CC /workspace/kernel/build64-debug/tools/objtool/libsubcmd/parse-options.o
CC /workspace/kernel/build64-debug/tools/objtool/libsubcmd/run-command.o
CC /workspace/kernel/build64-debug/tools/objtool/libsubcmd/sigchain.o
CC /workspace/kernel/build64-debug/tools/objtool/libsubcmd/subcmd-config.o
LD /workspace/kernel/build64-debug/tools/objtool/libsubcmd/libsubcmd-in.o
AR /workspace/kernel/build64-debug/tools/objtool/libsubcmd/libsubcmd.a
CC /workspace/kernel/build64-debug/tools/objtool/weak.o
CC /workspace/kernel/build64-debug/tools/objtool/check.o
CC /workspace/kernel/build64-debug/tools/objtool/special.o
CC /workspace/kernel/build64-debug/tools/objtool/builtin-check.o
CC /workspace/kernel/build64-debug/tools/objtool/arch/x86/special.o
CC /workspace/kernel/build64-debug/tools/objtool/elf.o
CC /workspace/kernel/build64-debug/tools/objtool/arch/x86/decode.o
CC /workspace/kernel/build64-debug/tools/objtool/objtool.o
CC /workspace/kernel/build64-debug/tools/objtool/arch/x86/orc.o
CC /workspace/kernel/build64-debug/tools/objtool/orc_gen.o
CC /workspace/kernel/build64-debug/tools/objtool/libstring.o
CC /workspace/kernel/build64-debug/tools/objtool/orc_dump.o
CC /workspace/kernel/build64-debug/tools/objtool/libctype.o
CC /workspace/kernel/build64-debug/tools/objtool/str_error_r.o
CC /workspace/kernel/build64-debug/tools/objtool/librbtree.o
LD /workspace/kernel/build64-debug/tools/objtool/arch/x86/objtool-in.o
LD /workspace/kernel/build64-debug/tools/objtool/objtool-in.o
LINK /workspace/kernel/build64-debug/tools/objtool/objtool
make[1]: Leaving directory '/workspace/kernel/build64-debug'
++ nproc
+ make -j48 O=/workspace/kernel/build64-debug W=1 drivers/gpu/drm/xe
make[1]: Entering directory '/workspace/kernel/build64-debug'
make[2]: Nothing to be done for 'drivers/gpu/drm/xe'.
make[1]: Leaving directory '/workspace/kernel/build64-debug'
run-parts: executing /workspace/ci/hooks/11-build-32b
+++ realpath /workspace/ci/hooks/11-build-32b
++ dirname /workspace/ci/hooks/11-build-32b
+ THIS_SCRIPT_DIR=/workspace/ci/hooks
+ SRC_DIR=/workspace/kernel
+ TOOLS_SRC_DIR=/workspace/ci
+ '[' -n /workspace/kernel/build64-debug ']'
+ BUILD_DIR=/workspace/kernel/build64-debug
+ BUILD_DIR=/workspace/kernel/build64-debug/build32
+ cd /workspace/kernel
+ mkdir -p /workspace/kernel/build64-debug/build32
++ nproc
+ make -j48 ARCH=i386 O=/workspace/kernel/build64-debug/build32 defconfig
make[1]: Entering directory '/workspace/kernel/build64-debug/build32'
GEN Makefile
HOSTCC scripts/basic/fixdep
HOSTCC scripts/kconfig/confdata.o
HOSTCC scripts/kconfig/conf.o
LEX scripts/kconfig/lexer.lex.c
HOSTCC scripts/kconfig/expr.o
YACC scripts/kconfig/parser.tab.[ch]
HOSTCC scripts/kconfig/menu.o
HOSTCC scripts/kconfig/preprocess.o
HOSTCC scripts/kconfig/symbol.o
HOSTCC scripts/kconfig/util.o
HOSTCC scripts/kconfig/lexer.lex.o
HOSTCC scripts/kconfig/parser.tab.o
HOSTLD scripts/kconfig/conf
*** Default configuration is based on 'i386_defconfig'
#
# configuration written to .config
#
make[1]: Leaving directory '/workspace/kernel/build64-debug/build32'
+ cd /workspace/kernel/build64-debug/build32
+ /workspace/kernel/scripts/kconfig/merge_config.sh .config /workspace/ci/kernel/fragments/10-xe.fragment
Using .config as base
Merging /workspace/ci/kernel/fragments/10-xe.fragment
Value of CONFIG_DRM_XE is redefined by fragment /workspace/ci/kernel/fragments/10-xe.fragment:
Previous value: # CONFIG_DRM_XE is not set
New value: CONFIG_DRM_XE=m
GEN Makefile
#
# configuration written to .config
#
Value requested for CONFIG_HAVE_UID16 not in final .config
Requested value: CONFIG_HAVE_UID16=y
Actual value:
Value requested for CONFIG_UID16 not in final .config
Requested value: CONFIG_UID16=y
Actual value:
Value requested for CONFIG_X86_32 not in final .config
Requested value: CONFIG_X86_32=y
Actual value:
Value requested for CONFIG_OUTPUT_FORMAT not in final .config
Requested value: CONFIG_OUTPUT_FORMAT="elf32-i386"
Actual value: CONFIG_OUTPUT_FORMAT="elf64-x86-64"
Value requested for CONFIG_ARCH_MMAP_RND_BITS_MIN not in final .config
Requested value: CONFIG_ARCH_MMAP_RND_BITS_MIN=8
Actual value: CONFIG_ARCH_MMAP_RND_BITS_MIN=28
Value requested for CONFIG_ARCH_MMAP_RND_BITS_MAX not in final .config
Requested value: CONFIG_ARCH_MMAP_RND_BITS_MAX=16
Actual value: CONFIG_ARCH_MMAP_RND_BITS_MAX=32
Value requested for CONFIG_PGTABLE_LEVELS not in final .config
Requested value: CONFIG_PGTABLE_LEVELS=2
Actual value: CONFIG_PGTABLE_LEVELS=5
Value requested for CONFIG_X86_INTEL_QUARK not in final .config
Requested value: # CONFIG_X86_INTEL_QUARK is not set
Actual value:
Value requested for CONFIG_X86_RDC321X not in final .config
Requested value: # CONFIG_X86_RDC321X is not set
Actual value:
Value requested for CONFIG_X86_32_IRIS not in final .config
Requested value: # CONFIG_X86_32_IRIS is not set
Actual value:
Value requested for CONFIG_M486SX not in final .config
Requested value: # CONFIG_M486SX is not set
Actual value:
Value requested for CONFIG_M486 not in final .config
Requested value: # CONFIG_M486 is not set
Actual value:
Value requested for CONFIG_M586 not in final .config
Requested value: # CONFIG_M586 is not set
Actual value:
Value requested for CONFIG_M586TSC not in final .config
Requested value: # CONFIG_M586TSC is not set
Actual value:
Value requested for CONFIG_M586MMX not in final .config
Requested value: # CONFIG_M586MMX is not set
Actual value:
Value requested for CONFIG_M686 not in final .config
Requested value: CONFIG_M686=y
Actual value:
Value requested for CONFIG_MPENTIUMII not in final .config
Requested value: # CONFIG_MPENTIUMII is not set
Actual value:
Value requested for CONFIG_MPENTIUMIII not in final .config
Requested value: # CONFIG_MPENTIUMIII is not set
Actual value:
Value requested for CONFIG_MPENTIUMM not in final .config
Requested value: # CONFIG_MPENTIUMM is not set
Actual value:
Value requested for CONFIG_MPENTIUM4 not in final .config
Requested value: # CONFIG_MPENTIUM4 is not set
Actual value:
Value requested for CONFIG_MK6 not in final .config
Requested value: # CONFIG_MK6 is not set
Actual value:
Value requested for CONFIG_MK7 not in final .config
Requested value: # CONFIG_MK7 is not set
Actual value:
Value requested for CONFIG_MCRUSOE not in final .config
Requested value: # CONFIG_MCRUSOE is not set
Actual value:
Value requested for CONFIG_MEFFICEON not in final .config
Requested value: # CONFIG_MEFFICEON is not set
Actual value:
Value requested for CONFIG_MWINCHIPC6 not in final .config
Requested value: # CONFIG_MWINCHIPC6 is not set
Actual value:
Value requested for CONFIG_MWINCHIP3D not in final .config
Requested value: # CONFIG_MWINCHIP3D is not set
Actual value:
Value requested for CONFIG_MELAN not in final .config
Requested value: # CONFIG_MELAN is not set
Actual value:
Value requested for CONFIG_MGEODEGX1 not in final .config
Requested value: # CONFIG_MGEODEGX1 is not set
Actual value:
Value requested for CONFIG_MGEODE_LX not in final .config
Requested value: # CONFIG_MGEODE_LX is not set
Actual value:
Value requested for CONFIG_MCYRIXIII not in final .config
Requested value: # CONFIG_MCYRIXIII is not set
Actual value:
Value requested for CONFIG_MVIAC3_2 not in final .config
Requested value: # CONFIG_MVIAC3_2 is not set
Actual value:
Value requested for CONFIG_MVIAC7 not in final .config
Requested value: # CONFIG_MVIAC7 is not set
Actual value:
Value requested for CONFIG_MATOM not in final .config
Requested value: # CONFIG_MATOM is not set
Actual value:
Value requested for CONFIG_X86_GENERIC not in final .config
Requested value: # CONFIG_X86_GENERIC is not set
Actual value:
Value requested for CONFIG_X86_INTERNODE_CACHE_SHIFT not in final .config
Requested value: CONFIG_X86_INTERNODE_CACHE_SHIFT=5
Actual value: CONFIG_X86_INTERNODE_CACHE_SHIFT=6
Value requested for CONFIG_X86_L1_CACHE_SHIFT not in final .config
Requested value: CONFIG_X86_L1_CACHE_SHIFT=5
Actual value: CONFIG_X86_L1_CACHE_SHIFT=6
Value requested for CONFIG_X86_USE_PPRO_CHECKSUM not in final .config
Requested value: CONFIG_X86_USE_PPRO_CHECKSUM=y
Actual value:
Value requested for CONFIG_X86_MINIMUM_CPU_FAMILY not in final .config
Requested value: CONFIG_X86_MINIMUM_CPU_FAMILY=6
Actual value: CONFIG_X86_MINIMUM_CPU_FAMILY=64
Value requested for CONFIG_CPU_SUP_TRANSMETA_32 not in final .config
Requested value: CONFIG_CPU_SUP_TRANSMETA_32=y
Actual value:
Value requested for CONFIG_CPU_SUP_VORTEX_32 not in final .config
Requested value: CONFIG_CPU_SUP_VORTEX_32=y
Actual value:
Value requested for CONFIG_HPET_TIMER not in final .config
Requested value: # CONFIG_HPET_TIMER is not set
Actual value: CONFIG_HPET_TIMER=y
Value requested for CONFIG_NR_CPUS_RANGE_END not in final .config
Requested value: CONFIG_NR_CPUS_RANGE_END=8
Actual value: CONFIG_NR_CPUS_RANGE_END=512
Value requested for CONFIG_NR_CPUS_DEFAULT not in final .config
Requested value: CONFIG_NR_CPUS_DEFAULT=8
Actual value: CONFIG_NR_CPUS_DEFAULT=64
Value requested for CONFIG_X86_ANCIENT_MCE not in final .config
Requested value: # CONFIG_X86_ANCIENT_MCE is not set
Actual value:
Value requested for CONFIG_X86_LEGACY_VM86 not in final .config
Requested value: # CONFIG_X86_LEGACY_VM86 is not set
Actual value:
Value requested for CONFIG_X86_ESPFIX32 not in final .config
Requested value: CONFIG_X86_ESPFIX32=y
Actual value:
Value requested for CONFIG_TOSHIBA not in final .config
Requested value: # CONFIG_TOSHIBA is not set
Actual value:
Value requested for CONFIG_X86_REBOOTFIXUPS not in final .config
Requested value: # CONFIG_X86_REBOOTFIXUPS is not set
Actual value:
Value requested for CONFIG_MICROCODE_INITRD32 not in final .config
Requested value: CONFIG_MICROCODE_INITRD32=y
Actual value:
Value requested for CONFIG_HIGHMEM4G not in final .config
Requested value: # CONFIG_HIGHMEM4G is not set
Actual value:
Value requested for CONFIG_VMSPLIT_3G not in final .config
Requested value: CONFIG_VMSPLIT_3G=y
Actual value:
Value requested for CONFIG_VMSPLIT_3G_OPT not in final .config
Requested value: # CONFIG_VMSPLIT_3G_OPT is not set
Actual value:
Value requested for CONFIG_VMSPLIT_2G not in final .config
Requested value: # CONFIG_VMSPLIT_2G is not set
Actual value:
Value requested for CONFIG_VMSPLIT_2G_OPT not in final .config
Requested value: # CONFIG_VMSPLIT_2G_OPT is not set
Actual value:
Value requested for CONFIG_VMSPLIT_1G not in final .config
Requested value: # CONFIG_VMSPLIT_1G is not set
Actual value:
Value requested for CONFIG_PAGE_OFFSET not in final .config
Requested value: CONFIG_PAGE_OFFSET=0xC0000000
Actual value:
Value requested for CONFIG_X86_PAE not in final .config
Requested value: # CONFIG_X86_PAE is not set
Actual value:
Value requested for CONFIG_ARCH_FLATMEM_ENABLE not in final .config
Requested value: CONFIG_ARCH_FLATMEM_ENABLE=y
Actual value:
Value requested for CONFIG_ARCH_SELECT_MEMORY_MODEL not in final .config
Requested value: CONFIG_ARCH_SELECT_MEMORY_MODEL=y
Actual value:
Value requested for CONFIG_ILLEGAL_POINTER_VALUE not in final .config
Requested value: CONFIG_ILLEGAL_POINTER_VALUE=0
Actual value: CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
Value requested for CONFIG_COMPAT_VDSO not in final .config
Requested value: # CONFIG_COMPAT_VDSO is not set
Actual value:
Value requested for CONFIG_FUNCTION_PADDING_CFI not in final .config
Requested value: CONFIG_FUNCTION_PADDING_CFI=0
Actual value: CONFIG_FUNCTION_PADDING_CFI=11
Value requested for CONFIG_FUNCTION_PADDING_BYTES not in final .config
Requested value: CONFIG_FUNCTION_PADDING_BYTES=4
Actual value: CONFIG_FUNCTION_PADDING_BYTES=16
Value requested for CONFIG_APM not in final .config
Requested value: # CONFIG_APM is not set
Actual value:
Value requested for CONFIG_X86_POWERNOW_K6 not in final .config
Requested value: # CONFIG_X86_POWERNOW_K6 is not set
Actual value:
Value requested for CONFIG_X86_POWERNOW_K7 not in final .config
Requested value: # CONFIG_X86_POWERNOW_K7 is not set
Actual value:
Value requested for CONFIG_X86_GX_SUSPMOD not in final .config
Requested value: # CONFIG_X86_GX_SUSPMOD is not set
Actual value:
Value requested for CONFIG_X86_SPEEDSTEP_ICH not in final .config
Requested value: # CONFIG_X86_SPEEDSTEP_ICH is not set
Actual value:
Value requested for CONFIG_X86_SPEEDSTEP_SMI not in final .config
Requested value: # CONFIG_X86_SPEEDSTEP_SMI is not set
Actual value:
Value requested for CONFIG_X86_CPUFREQ_NFORCE2 not in final .config
Requested value: # CONFIG_X86_CPUFREQ_NFORCE2 is not set
Actual value:
Value requested for CONFIG_X86_LONGRUN not in final .config
Requested value: # CONFIG_X86_LONGRUN is not set
Actual value:
Value requested for CONFIG_X86_LONGHAUL not in final .config
Requested value: # CONFIG_X86_LONGHAUL is not set
Actual value:
Value requested for CONFIG_X86_E_POWERSAVER not in final .config
Requested value: # CONFIG_X86_E_POWERSAVER is not set
Actual value:
Value requested for CONFIG_PCI_GOBIOS not in final .config
Requested value: # CONFIG_PCI_GOBIOS is not set
Actual value:
Value requested for CONFIG_PCI_GOMMCONFIG not in final .config
Requested value: # CONFIG_PCI_GOMMCONFIG is not set
Actual value:
Value requested for CONFIG_PCI_GODIRECT not in final .config
Requested value: # CONFIG_PCI_GODIRECT is not set
Actual value:
Value requested for CONFIG_PCI_GOANY not in final .config
Requested value: CONFIG_PCI_GOANY=y
Actual value:
Value requested for CONFIG_PCI_BIOS not in final .config
Requested value: CONFIG_PCI_BIOS=y
Actual value:
Value requested for CONFIG_ISA not in final .config
Requested value: # CONFIG_ISA is not set
Actual value:
Value requested for CONFIG_SCx200 not in final .config
Requested value: # CONFIG_SCx200 is not set
Actual value:
Value requested for CONFIG_OLPC not in final .config
Requested value: # CONFIG_OLPC is not set
Actual value:
Value requested for CONFIG_ALIX not in final .config
Requested value: # CONFIG_ALIX is not set
Actual value:
Value requested for CONFIG_NET5501 not in final .config
Requested value: # CONFIG_NET5501 is not set
Actual value:
Value requested for CONFIG_GEOS not in final .config
Requested value: # CONFIG_GEOS is not set
Actual value:
Value requested for CONFIG_COMPAT_32 not in final .config
Requested value: CONFIG_COMPAT_32=y
Actual value:
Value requested for CONFIG_HAVE_ATOMIC_IOMAP not in final .config
Requested value: CONFIG_HAVE_ATOMIC_IOMAP=y
Actual value:
Value requested for CONFIG_X86_DISABLED_FEATURE_PCID not in final .config
Requested value: CONFIG_X86_DISABLED_FEATURE_PCID=y
Actual value:
Value requested for CONFIG_X86_DISABLED_FEATURE_PKU not in final .config
Requested value: CONFIG_X86_DISABLED_FEATURE_PKU=y
Actual value:
Value requested for CONFIG_X86_DISABLED_FEATURE_OSPKE not in final .config
Requested value: CONFIG_X86_DISABLED_FEATURE_OSPKE=y
Actual value:
Value requested for CONFIG_X86_DISABLED_FEATURE_LA57 not in final .config
Requested value: CONFIG_X86_DISABLED_FEATURE_LA57=y
Actual value:
Value requested for CONFIG_X86_DISABLED_FEATURE_PTI not in final .config
Requested value: CONFIG_X86_DISABLED_FEATURE_PTI=y
Actual value:
Value requested for CONFIG_X86_DISABLED_FEATURE_IBT not in final .config
Requested value: CONFIG_X86_DISABLED_FEATURE_IBT=y
Actual value:
Value requested for CONFIG_X86_DISABLED_FEATURE_INVLPGB not in final .config
Requested value: CONFIG_X86_DISABLED_FEATURE_INVLPGB=y
Actual value:
Value requested for CONFIG_ARCH_32BIT_OFF_T not in final .config
Requested value: CONFIG_ARCH_32BIT_OFF_T=y
Actual value:
Value requested for CONFIG_ARCH_WANT_IPC_PARSE_VERSION not in final .config
Requested value: CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
Actual value:
Value requested for CONFIG_MODULES_USE_ELF_REL not in final .config
Requested value: CONFIG_MODULES_USE_ELF_REL=y
Actual value:
Value requested for CONFIG_ARCH_MMAP_RND_BITS not in final .config
Requested value: CONFIG_ARCH_MMAP_RND_BITS=8
Actual value: CONFIG_ARCH_MMAP_RND_BITS=28
Value requested for CONFIG_CLONE_BACKWARDS not in final .config
Requested value: CONFIG_CLONE_BACKWARDS=y
Actual value:
Value requested for CONFIG_OLD_SIGSUSPEND3 not in final .config
Requested value: CONFIG_OLD_SIGSUSPEND3=y
Actual value:
Value requested for CONFIG_OLD_SIGACTION not in final .config
Requested value: CONFIG_OLD_SIGACTION=y
Actual value:
Value requested for CONFIG_ARCH_SPLIT_ARG64 not in final .config
Requested value: CONFIG_ARCH_SPLIT_ARG64=y
Actual value:
Value requested for CONFIG_FUNCTION_ALIGNMENT not in final .config
Requested value: CONFIG_FUNCTION_ALIGNMENT=4
Actual value: CONFIG_FUNCTION_ALIGNMENT=16
Value requested for CONFIG_SELECT_MEMORY_MODEL not in final .config
Requested value: CONFIG_SELECT_MEMORY_MODEL=y
Actual value:
Value requested for CONFIG_FLATMEM_MANUAL not in final .config
Requested value: CONFIG_FLATMEM_MANUAL=y
Actual value:
Value requested for CONFIG_SPARSEMEM_MANUAL not in final .config
Requested value: # CONFIG_SPARSEMEM_MANUAL is not set
Actual value:
Value requested for CONFIG_FLATMEM not in final .config
Requested value: CONFIG_FLATMEM=y
Actual value:
Value requested for CONFIG_SPARSEMEM_STATIC not in final .config
Requested value: CONFIG_SPARSEMEM_STATIC=y
Actual value:
Value requested for CONFIG_KMAP_LOCAL not in final .config
Requested value: CONFIG_KMAP_LOCAL=y
Actual value:
Value requested for CONFIG_HAVE_EISA not in final .config
Requested value: CONFIG_HAVE_EISA=y
Actual value:
Value requested for CONFIG_EISA not in final .config
Requested value: # CONFIG_EISA is not set
Actual value:
Value requested for CONFIG_HOTPLUG_PCI_COMPAQ not in final .config
Requested value: # CONFIG_HOTPLUG_PCI_COMPAQ is not set
Actual value:
Value requested for CONFIG_HOTPLUG_PCI_IBM not in final .config
Requested value: # CONFIG_HOTPLUG_PCI_IBM is not set
Actual value:
Value requested for CONFIG_EFI_CAPSULE_QUIRK_QUARK_CSH not in final .config
Requested value: CONFIG_EFI_CAPSULE_QUIRK_QUARK_CSH=y
Actual value:
Value requested for CONFIG_PCH_PHUB not in final .config
Requested value: # CONFIG_PCH_PHUB is not set
Actual value:
Value requested for CONFIG_SCSI_NSP32 not in final .config
Requested value: # CONFIG_SCSI_NSP32 is not set
Actual value:
Value requested for CONFIG_PATA_CS5520 not in final .config
Requested value: # CONFIG_PATA_CS5520 is not set
Actual value:
Value requested for CONFIG_PATA_CS5530 not in final .config
Requested value: # CONFIG_PATA_CS5530 is not set
Actual value:
Value requested for CONFIG_PATA_CS5535 not in final .config
Requested value: # CONFIG_PATA_CS5535 is not set
Actual value:
Value requested for CONFIG_PATA_CS5536 not in final .config
Requested value: # CONFIG_PATA_CS5536 is not set
Actual value:
Value requested for CONFIG_PATA_SC1200 not in final .config
Requested value: # CONFIG_PATA_SC1200 is not set
Actual value:
Value requested for CONFIG_PCH_GBE not in final .config
Requested value: # CONFIG_PCH_GBE is not set
Actual value:
Value requested for CONFIG_INPUT_WISTRON_BTNS not in final .config
Requested value: # CONFIG_INPUT_WISTRON_BTNS is not set
Actual value:
Value requested for CONFIG_SERIAL_TIMBERDALE not in final .config
Requested value: # CONFIG_SERIAL_TIMBERDALE is not set
Actual value:
Value requested for CONFIG_SERIAL_PCH_UART not in final .config
Requested value: # CONFIG_SERIAL_PCH_UART is not set
Actual value:
Value requested for CONFIG_HW_RANDOM_GEODE not in final .config
Requested value: CONFIG_HW_RANDOM_GEODE=y
Actual value:
Value requested for CONFIG_SONYPI not in final .config
Requested value: # CONFIG_SONYPI is not set
Actual value:
Value requested for CONFIG_PC8736x_GPIO not in final .config
Requested value: # CONFIG_PC8736x_GPIO is not set
Actual value:
Value requested for CONFIG_NSC_GPIO not in final .config
Requested value: # CONFIG_NSC_GPIO is not set
Actual value:
Value requested for CONFIG_I2C_EG20T not in final .config
Requested value: # CONFIG_I2C_EG20T is not set
Actual value:
Value requested for CONFIG_SCx200_ACB not in final .config
Requested value: # CONFIG_SCx200_ACB is not set
Actual value:
Value requested for CONFIG_PTP_1588_CLOCK_PCH not in final .config
Requested value: # CONFIG_PTP_1588_CLOCK_PCH is not set
Actual value:
Value requested for CONFIG_SBC8360_WDT not in final .config
Requested value: # CONFIG_SBC8360_WDT is not set
Actual value:
Value requested for CONFIG_SBC7240_WDT not in final .config
Requested value: # CONFIG_SBC7240_WDT is not set
Actual value:
Value requested for CONFIG_MFD_CS5535 not in final .config
Requested value: # CONFIG_MFD_CS5535 is not set
Actual value:
Value requested for CONFIG_AGP_ALI not in final .config
Requested value: # CONFIG_AGP_ALI is not set
Actual value:
Value requested for CONFIG_AGP_ATI not in final .config
Requested value: # CONFIG_AGP_ATI is not set
Actual value:
Value requested for CONFIG_AGP_AMD not in final .config
Requested value: # CONFIG_AGP_AMD is not set
Actual value:
Value requested for CONFIG_AGP_NVIDIA not in final .config
Requested value: # CONFIG_AGP_NVIDIA is not set
Actual value:
Value requested for CONFIG_AGP_SWORKS not in final .config
Requested value: # CONFIG_AGP_SWORKS is not set
Actual value:
Value requested for CONFIG_AGP_EFFICEON not in final .config
Requested value: # CONFIG_AGP_EFFICEON is not set
Actual value:
Value requested for CONFIG_SND_CS5530 not in final .config
Requested value: # CONFIG_SND_CS5530 is not set
Actual value:
Value requested for CONFIG_SND_CS5535AUDIO not in final .config
Requested value: # CONFIG_SND_CS5535AUDIO is not set
Actual value:
Value requested for CONFIG_SND_SIS7019 not in final .config
Requested value: # CONFIG_SND_SIS7019 is not set
Actual value:
Value requested for CONFIG_LEDS_OT200 not in final .config
Requested value: # CONFIG_LEDS_OT200 is not set
Actual value:
Value requested for CONFIG_PCH_DMA not in final .config
Requested value: # CONFIG_PCH_DMA is not set
Actual value:
Value requested for CONFIG_CLKSRC_I8253 not in final .config
Requested value: CONFIG_CLKSRC_I8253=y
Actual value:
Value requested for CONFIG_MAILBOX not in final .config
Requested value: # CONFIG_MAILBOX is not set
Actual value: CONFIG_MAILBOX=y
Value requested for CONFIG_CRYPTO_SERPENT_SSE2_586 not in final .config
Requested value: # CONFIG_CRYPTO_SERPENT_SSE2_586 is not set
Actual value:
Value requested for CONFIG_CRYPTO_TWOFISH_586 not in final .config
Requested value: # CONFIG_CRYPTO_TWOFISH_586 is not set
Actual value:
Value requested for CONFIG_CRYPTO_DEV_GEODE not in final .config
Requested value: # CONFIG_CRYPTO_DEV_GEODE is not set
Actual value:
Value requested for CONFIG_CRYPTO_DEV_HIFN_795X not in final .config
Requested value: # CONFIG_CRYPTO_DEV_HIFN_795X is not set
Actual value:
Value requested for CONFIG_CRYPTO_LIB_POLY1305_RSIZE not in final .config
Requested value: CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1
Actual value: CONFIG_CRYPTO_LIB_POLY1305_RSIZE=11
Value requested for CONFIG_AUDIT_GENERIC not in final .config
Requested value: CONFIG_AUDIT_GENERIC=y
Actual value:
Value requested for CONFIG_GENERIC_VDSO_32 not in final .config
Requested value: CONFIG_GENERIC_VDSO_32=y
Actual value:
Value requested for CONFIG_DEBUG_KMAP_LOCAL not in final .config
Requested value: # CONFIG_DEBUG_KMAP_LOCAL is not set
Actual value:
Value requested for CONFIG_HAVE_DEBUG_STACKOVERFLOW not in final .config
Requested value: CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
Actual value:
Value requested for CONFIG_DEBUG_STACKOVERFLOW not in final .config
Requested value: # CONFIG_DEBUG_STACKOVERFLOW is not set
Actual value:
Value requested for CONFIG_HAVE_FUNCTION_GRAPH_TRACER not in final .config
Requested value: CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
Actual value:
Value requested for CONFIG_HAVE_FUNCTION_GRAPH_FREGS not in final .config
Requested value: CONFIG_HAVE_FUNCTION_GRAPH_FREGS=y
Actual value:
Value requested for CONFIG_HAVE_FTRACE_GRAPH_FUNC not in final .config
Requested value: CONFIG_HAVE_FTRACE_GRAPH_FUNC=y
Actual value:
Value requested for CONFIG_DRM_KUNIT_TEST not in final .config
Requested value: CONFIG_DRM_KUNIT_TEST=m
Actual value:
Value requested for CONFIG_DRM_XE_WERROR not in final .config
Requested value: CONFIG_DRM_XE_WERROR=y
Actual value:
Value requested for CONFIG_DRM_XE_DEBUG not in final .config
Requested value: CONFIG_DRM_XE_DEBUG=y
Actual value:
Value requested for CONFIG_DRM_XE_DEBUG_MEM not in final .config
Requested value: CONFIG_DRM_XE_DEBUG_MEM=y
Actual value:
Value requested for CONFIG_DRM_XE_KUNIT_TEST not in final .config
Requested value: CONFIG_DRM_XE_KUNIT_TEST=m
Actual value:
++ nproc
+ make -j48 ARCH=i386 olddefconfig
GEN Makefile
#
# configuration written to .config
#
++ nproc
+ make -j48 ARCH=i386
SYNC include/config/auto.conf.cmd
GEN Makefile
GEN Makefile
WRAP arch/x86/include/generated/uapi/asm/bpf_perf_event.h
WRAP arch/x86/include/generated/uapi/asm/errno.h
WRAP arch/x86/include/generated/uapi/asm/fcntl.h
WRAP arch/x86/include/generated/uapi/asm/ioctl.h
WRAP arch/x86/include/generated/uapi/asm/ioctls.h
WRAP arch/x86/include/generated/uapi/asm/param.h
WRAP arch/x86/include/generated/uapi/asm/ipcbuf.h
SYSHDR arch/x86/include/generated/uapi/asm/unistd_32.h
WRAP arch/x86/include/generated/uapi/asm/poll.h
SYSHDR arch/x86/include/generated/uapi/asm/unistd_64.h
UPD include/generated/uapi/linux/version.h
WRAP arch/x86/include/generated/uapi/asm/resource.h
SYSHDR arch/x86/include/generated/uapi/asm/unistd_x32.h
WRAP arch/x86/include/generated/uapi/asm/socket.h
UPD arch/x86/include/generated/asm/cpufeaturemasks.h
SYSTBL arch/x86/include/generated/asm/syscalls_32.h
WRAP arch/x86/include/generated/uapi/asm/sockios.h
WRAP arch/x86/include/generated/uapi/asm/termbits.h
WRAP arch/x86/include/generated/uapi/asm/termios.h
WRAP arch/x86/include/generated/uapi/asm/types.h
UPD include/generated/compile.h
HOSTCC arch/x86/tools/relocs_32.o
WRAP arch/x86/include/generated/asm/early_ioremap.h
HOSTCC arch/x86/tools/relocs_64.o
WRAP arch/x86/include/generated/asm/fprobe.h
HOSTCC arch/x86/tools/relocs_common.o
WRAP arch/x86/include/generated/asm/mcs_spinlock.h
WRAP arch/x86/include/generated/asm/mmzone.h
WRAP arch/x86/include/generated/asm/irq_regs.h
WRAP arch/x86/include/generated/asm/kmap_size.h
WRAP arch/x86/include/generated/asm/local64.h
WRAP arch/x86/include/generated/asm/mmiowb.h
WRAP arch/x86/include/generated/asm/module.lds.h
WRAP arch/x86/include/generated/asm/rwonce.h
HOSTCC scripts/kallsyms
HOSTCC scripts/sorttable
HOSTCC scripts/asn1_compiler
HOSTCC scripts/selinux/mdp/mdp
HOSTLD arch/x86/tools/relocs
UPD include/config/kernel.release
UPD include/generated/utsrelease.h
CC scripts/mod/empty.o
HOSTCC scripts/mod/mk_elfconfig
CC scripts/mod/devicetable-offsets.s
UPD scripts/mod/devicetable-offsets.h
MKELF scripts/mod/elfconfig.h
HOSTCC scripts/mod/modpost.o
HOSTCC scripts/mod/file2alias.o
HOSTCC scripts/mod/sumversion.o
HOSTCC scripts/mod/symsearch.o
HOSTLD scripts/mod/modpost
CC kernel/bounds.s
CHKSHA1 /workspace/kernel/include/linux/atomic/atomic-arch-fallback.h
CHKSHA1 /workspace/kernel/include/linux/atomic/atomic-instrumented.h
CHKSHA1 /workspace/kernel/include/linux/atomic/atomic-long.h
UPD include/generated/timeconst.h
UPD include/generated/bounds.h
CC arch/x86/kernel/asm-offsets.s
UPD include/generated/asm-offsets.h
CALL /workspace/kernel/scripts/checksyscalls.sh
LDS scripts/module.lds
CC init/main.o
HOSTCC usr/gen_init_cpio
CC init/do_mounts.o
CC certs/system_keyring.o
CC init/do_mounts_initrd.o
UPD init/utsversion-tmp.h
CC init/initramfs.o
CC ipc/util.o
CC init/calibrate.o
CC ipc/msgutil.o
CC mm/filemap.o
CC security/commoncap.o
CC init/init_task.o
CC ipc/msg.o
CC io_uring/io_uring.o
CC mm/mempool.o
CC security/lsm_syscalls.o
CC block/bdev.o
CC arch/x86/realmode/init.o
CC io_uring/opdef.o
CC ipc/sem.o
AS arch/x86/lib/atomic64_cx8_32.o
AR arch/x86/crypto/built-in.a
CC security/keys/gc.o
CC arch/x86/power/cpu.o
CC arch/x86/pci/i386.o
CC arch/x86/video/video-common.o
CC security/integrity/iint.o
AR arch/x86/net/built-in.a
AR virt/lib/built-in.a
HOSTCC security/selinux/genheaders
CC block/partitions/core.o
AR arch/x86/entry/vsyscall/built-in.a
CC fs/nfs_common/nfsacl.o
CC fs/iomap/trace.o
AR arch/x86/platform/atom/built-in.a
CC arch/x86/events/amd/core.o
CC arch/x86/events/intel/core.o
AR virt/built-in.a
AR drivers/cache/built-in.a
CC security/min_addr.o
CC arch/x86/mm/pat/set_memory.o
CC fs/notify/dnotify/dnotify.o
CC net/core/sock.o
CC arch/x86/kernel/fpu/init.o
CC arch/x86/virt/svm/cmdline.o
CC sound/core/seq/seq.o
AR lib/math/tests/built-in.a
AR arch/x86/virt/vmx/built-in.a
AR arch/x86/platform/ce4100/built-in.a
CC lib/math/div64.o
AS arch/x86/lib/checksum_32.o
AR drivers/irqchip/built-in.a
CC lib/crypto/mpi/generic_mpih-lshift.o
CC arch/x86/entry/vdso/vma.o
CC ipc/shm.o
CC lib/crypto/mpi/generic_mpih-mul1.o
CC arch/x86/platform/efi/memmap.o
CC kernel/sched/core.o
AR drivers/bus/mhi/built-in.a
CC arch/x86/lib/cmdline.o
AR drivers/bus/built-in.a
CC crypto/asymmetric_keys/asymmetric_type.o
AR drivers/pwm/built-in.a
AR drivers/leds/trigger/built-in.a
AR drivers/leds/blink/built-in.a
AR arch/x86/virt/svm/built-in.a
AR arch/x86/virt/built-in.a
AR drivers/leds/simatic/built-in.a
CC drivers/leds/led-core.o
CC arch/x86/mm/pat/memtype.o
AS arch/x86/lib/cmpxchg8b_emu.o
CC lib/math/gcd.o
GEN security/selinux/flask.h security/selinux/av_permissions.h
CC arch/x86/lib/cpu.o
CC security/selinux/avc.o
CC lib/math/lcm.o
CC security/integrity/integrity_audit.o
CC lib/math/int_log.o
GEN usr/initramfs_data.cpio
COPY usr/initramfs_inc_data
AS usr/initramfs_data.o
CC arch/x86/kernel/fpu/bugs.o
AR usr/built-in.a
HOSTCC certs/extract-cert
CC lib/math/int_pow.o
CC arch/x86/events/zhaoxin/core.o
CC lib/math/int_sqrt.o
CC arch/x86/kernel/fpu/core.o
CC lib/math/reciprocal_div.o
CC sound/core/seq/seq_lock.o
CC arch/x86/lib/delay.o
AS arch/x86/lib/getuser.o
AS arch/x86/realmode/rm/header.o
CC lib/crypto/mpi/generic_mpih-mul2.o
CC lib/math/rational.o
AR arch/x86/video/built-in.a
AS arch/x86/realmode/rm/trampoline_32.o
CC security/security.o
CC kernel/sched/fair.o
AS arch/x86/realmode/rm/stack.o
AS arch/x86/realmode/rm/reboot.o
CC crypto/api.o
CERT certs/x509_certificate_list
CERT certs/signing_key.x509
AS certs/system_certificates.o
CC fs/notify/inotify/inotify_fsnotify.o
AS arch/x86/realmode/rm/wakeup_asm.o
CC security/keys/key.o
CC fs/nfs_common/grace.o
AR certs/built-in.a
CC arch/x86/realmode/rm/wakemain.o
CC sound/core/sound.o
AR lib/tests/built-in.a
CC drivers/leds/led-class.o
CC drivers/leds/led-triggers.o
CC fs/iomap/iter.o
CC fs/iomap/buffered-io.o
CC arch/x86/entry/vdso/extable.o
AR arch/x86/platform/geode/built-in.a
CC arch/x86/pci/init.o
CC crypto/asymmetric_keys/restrict.o
CC arch/x86/pci/pcbios.o
CC fs/notify/inotify/inotify_user.o
CC arch/x86/realmode/rm/video-mode.o
AR fs/notify/dnotify/built-in.a
CC arch/x86/mm/init.o
CC arch/x86/platform/efi/quirks.o
CC arch/x86/events/amd/lbr.o
CC arch/x86/power/hibernate_32.o
AS arch/x86/realmode/rm/copy.o
GEN arch/x86/lib/inat-tables.c
CC block/partitions/msdos.o
CC arch/x86/lib/insn-eval.o
AS arch/x86/realmode/rm/bioscall.o
CC arch/x86/realmode/rm/regs.o
CC sound/core/seq/seq_clientmgr.o
CC arch/x86/realmode/rm/video-vga.o
AR lib/math/built-in.a
AR security/integrity/built-in.a
CC net/ethernet/eth.o
CC arch/x86/platform/efi/efi.o
LDS arch/x86/entry/vdso/vdso32/vdso32.lds
CC crypto/cipher.o
CC security/keys/keyring.o
CC arch/x86/realmode/rm/video-vesa.o
CC fs/nfs_common/common.o
CC arch/x86/mm/init_32.o
CC arch/x86/realmode/rm/video-bios.o
CC lib/crypto/mpi/generic_mpih-mul3.o
CC arch/x86/events/intel/bts.o
AS arch/x86/entry/entry.o
CC fs/quota/dquot.o
PASYMS arch/x86/realmode/rm/pasyms.h
AR net/802/built-in.a
CC security/keys/keyctl.o
CC crypto/asymmetric_keys/signature.o
CC arch/x86/kernel/fpu/regset.o
CC arch/x86/lib/insn.o
LDS arch/x86/realmode/rm/realmode.lds
CC block/partitions/efi.o
CC fs/quota/quota_v2.o
LD arch/x86/realmode/rm/realmode.elf
RELOCS arch/x86/realmode/rm/realmode.relocs
OBJCOPY arch/x86/realmode/rm/realmode.bin
AR arch/x86/events/zhaoxin/built-in.a
AS arch/x86/realmode/rmpiggy.o
CC security/selinux/hooks.o
CC lib/vdso/datastore.o
AR arch/x86/realmode/built-in.a
CC drivers/pci/msi/pcidev_msi.o
CC drivers/pci/pcie/portdrv.o
AR drivers/pci/pwrctrl/built-in.a
CC arch/x86/mm/pat/memtype_interval.o
AR sound/i2c/other/built-in.a
AR sound/i2c/built-in.a
CC drivers/video/console/dummycon.o
AR drivers/idle/built-in.a
CC drivers/video/console/vgacon.o
CC net/core/request_sock.o
CC arch/x86/pci/mmconfig_32.o
AR drivers/leds/built-in.a
CC drivers/pci/msi/api.o
CC lib/crypto/mpi/generic_mpih-rshift.o
AS arch/x86/power/hibernate_asm_32.o
CC init/version.o
AS arch/x86/entry/vdso/vdso32/note.o
CC arch/x86/power/hibernate.o
AS arch/x86/entry/entry_32.o
AS arch/x86/entry/vdso/vdso32/system_call.o
AS arch/x86/entry/vdso/vdso32/sigreturn.o
CC arch/x86/entry/vdso/vdso32/vclock_gettime.o
CC drivers/pci/hotplug/pci_hotplug_core.o
CC arch/x86/mm/fault.o
CC arch/x86/kernel/cpu/mce/core.o
CC sound/core/seq/seq_memory.o
CC crypto/asymmetric_keys/public_key.o
CC sound/core/seq/seq_queue.o
CC arch/x86/events/amd/ibs.o
ASN.1 crypto/asymmetric_keys/x509.asn1.[ch]
CC arch/x86/entry/vdso/vdso32/vgetcpu.o
AR init/built-in.a
CC arch/x86/lib/kaslr.o
CC ipc/syscall.o
CC arch/x86/events/intel/ds.o
AR fs/notify/inotify/built-in.a
CC arch/x86/entry/syscall_32.o
AS arch/x86/entry/thunk.o
AR fs/notify/fanotify/built-in.a
CC fs/notify/fsnotify.o
AR drivers/pci/controller/dwc/built-in.a
CC drivers/video/backlight/backlight.o
AR fs/nfs_common/built-in.a
AR drivers/video/fbdev/core/built-in.a
AR drivers/pci/controller/mobiveil/built-in.a
CC security/keys/permission.o
AR drivers/pci/controller/plda/built-in.a
AR drivers/video/fbdev/omap/built-in.a
AR drivers/pci/controller/built-in.a
CC arch/x86/mm/ioremap.o
AR drivers/video/fbdev/omap2/omapfb/dss/built-in.a
AR drivers/video/fbdev/omap2/omapfb/displays/built-in.a
AR drivers/video/fbdev/omap2/omapfb/built-in.a
AR drivers/video/fbdev/omap2/built-in.a
AR lib/vdso/built-in.a
AR drivers/video/fbdev/built-in.a
CC arch/x86/events/intel/knc.o
CC block/fops.o
CC mm/oom_kill.o
CC arch/x86/kernel/cpu/mce/severity.o
CC arch/x86/platform/efi/efi_32.o
CC arch/x86/lib/memcpy_32.o
CC security/selinux/selinuxfs.o
CC arch/x86/events/intel/lbr.o
CC arch/x86/kernel/fpu/signal.o
AS arch/x86/lib/memmove_32.o
AR arch/x86/mm/pat/built-in.a
CC arch/x86/lib/misc.o
CC arch/x86/kernel/acpi/boot.o
CC lib/crypto/mpi/generic_mpih-sub1.o
CC arch/x86/lib/pc-conf-reg.o
CC drivers/pci/hotplug/acpi_pcihp.o
CC arch/x86/pci/direct.o
CC drivers/pci/pcie/rcec.o
AR block/partitions/built-in.a
CC arch/x86/pci/mmconfig-shared.o
CC drivers/pci/msi/msi.o
AR arch/x86/power/built-in.a
CC security/keys/process_keys.o
CC fs/iomap/direct-io.o
AS arch/x86/lib/putuser.o
AR drivers/char/ipmi/built-in.a
HOSTCC arch/x86/entry/vdso/vdso2c
CC arch/x86/kernel/acpi/sleep.o
AS arch/x86/lib/retpoline.o
CC arch/x86/lib/string_32.o
AR net/ethernet/built-in.a
CC arch/x86/lib/strstr_32.o
ASN.1 crypto/asymmetric_keys/x509_akid.asn1.[ch]
CC crypto/asymmetric_keys/x509_loader.o
CC arch/x86/mm/extable.o
CC arch/x86/pci/fixup.o
CC arch/x86/lib/usercopy.o
CC sound/core/init.o
CC ipc/ipc_sysctl.o
AR drivers/video/console/built-in.a
CC lib/crypto/memneq.o
CC block/bio.o
CC lib/crypto/utils.o
CC block/elevator.o
CC sound/core/seq/seq_fifo.o
CC crypto/asymmetric_keys/x509_public_key.o
AR drivers/video/backlight/built-in.a
CC drivers/video/aperture.o
CC lib/crypto/mpi/generic_mpih-add1.o
CC block/blk-core.o
CC lib/crypto/chacha.o
AS arch/x86/platform/efi/efi_stub_32.o
CC fs/notify/notification.o
CC arch/x86/entry/vdso/vdso32-setup.o
CC security/lsm_audit.o
CC arch/x86/lib/usercopy_32.o
CC arch/x86/platform/efi/runtime-map.o
CC ipc/mqueue.o
CC drivers/pci/pcie/bwctrl.o
CC arch/x86/kernel/cpu/mtrr/mtrr.o
AR drivers/pci/hotplug/built-in.a
CC kernel/sched/build_policy.o
CC mm/fadvise.o
ASN.1 crypto/asymmetric_keys/pkcs7.asn1.[ch]
CC arch/x86/kernel/fpu/xstate.o
CC fs/proc/task_mmu.o
CC crypto/algapi.o
CC sound/core/memory.o
CC lib/zlib_inflate/inffast.o
CC security/selinux/netlink.o
CC mm/maccess.o
CC mm/page-writeback.o
VDSO arch/x86/entry/vdso/vdso32.so.dbg
CC arch/x86/lib/msr-smp.o
OBJCOPY arch/x86/entry/vdso/vdso32.so
VDSO2C arch/x86/entry/vdso/vdso-image-32.c
CC arch/x86/entry/vdso/vdso-image-32.o
CC arch/x86/events/amd/uncore.o
CC net/core/skbuff.o
CC sound/core/seq/seq_prioq.o
CC lib/zlib_inflate/inflate.o
AS arch/x86/kernel/acpi/wakeup_32.o
CC block/blk-sysfs.o
CC drivers/pci/msi/irqdomain.o
CC arch/x86/kernel/acpi/cstate.o
CC crypto/asymmetric_keys/pkcs7_trust.o
CC kernel/locking/mutex.o
CC lib/crypto/mpi/mpicoder.o
CC fs/quota/quota_tree.o
CC arch/x86/mm/mmap.o
CC security/keys/request_key.o
AR arch/x86/entry/vdso/built-in.a
CC arch/x86/pci/acpi.o
AR arch/x86/entry/built-in.a
CC fs/notify/group.o
CC kernel/power/qos.o
CC fs/iomap/ioend.o
CC arch/x86/lib/cache-smp.o
CC kernel/printk/printk.o
CC security/device_cgroup.o
CC kernel/irq/irqdesc.o
CC arch/x86/kernel/cpu/mtrr/if.o
CC drivers/video/cmdline.o
AR arch/x86/platform/efi/built-in.a
CC drivers/pci/pcie/aspm.o
AR arch/x86/platform/iris/built-in.a
CC arch/x86/lib/crc32-glue.o
CC arch/x86/platform/intel/iosf_mbi.o
CC arch/x86/kernel/cpu/mce/genpool.o
CC kernel/power/main.o
CC drivers/pci/pcie/pme.o
CC crypto/asymmetric_keys/pkcs7_verify.o
CC arch/x86/kernel/cpu/microcode/core.o
CC sound/core/seq/seq_timer.o
CC security/keys/request_key_auth.o
CC crypto/scatterwalk.o
AR arch/x86/kernel/acpi/built-in.a
CC fs/proc/inode.o
CC arch/x86/events/intel/p4.o
CC arch/x86/kernel/cpu/microcode/intel.o
CC io_uring/kbuf.o
CC lib/zlib_inflate/infutil.o
CC kernel/rcu/update.o
CC mm/folio-compat.o
CC kernel/irq/handle.o
AR drivers/pci/msi/built-in.a
CC arch/x86/mm/pgtable.o
CC fs/iomap/fiemap.o
AS arch/x86/lib/crc32-pclmul.o
CC lib/crypto/mpi/mpi-add.o
CC arch/x86/kernel/cpu/mtrr/generic.o
CC arch/x86/lib/msr.o
CC crypto/asymmetric_keys/x509.asn1.o
CC fs/notify/mark.o
CC kernel/printk/printk_safe.o
AR arch/x86/kernel/fpu/built-in.a
CC crypto/asymmetric_keys/x509_akid.asn1.o
AR sound/drivers/opl3/built-in.a
CC crypto/asymmetric_keys/x509_cert_parser.o
AR sound/drivers/opl4/built-in.a
AR sound/drivers/mpu401/built-in.a
AR sound/drivers/vx/built-in.a
CC arch/x86/pci/legacy.o
AR sound/drivers/pcsp/built-in.a
AR sound/drivers/built-in.a
CC kernel/power/console.o
AR sound/isa/ad1816a/built-in.a
CC lib/zlib_inflate/inftrees.o
CC fs/iomap/seek.o
CC net/core/datagram.o
AR sound/isa/ad1848/built-in.a
AR kernel/livepatch/built-in.a
AR sound/isa/cs423x/built-in.a
CC fs/quota/quota.o
AR sound/isa/es1688/built-in.a
CC arch/x86/kernel/cpu/mce/intel.o
AR sound/isa/galaxy/built-in.a
CC drivers/video/nomodeset.o
AR sound/isa/gus/built-in.a
CC drivers/video/hdmi.o
AR sound/isa/msnd/built-in.a
AR arch/x86/events/amd/built-in.a
AR sound/isa/opti9xx/built-in.a
CC arch/x86/kernel/cpu/cacheinfo.o
CC arch/x86/kernel/cpu/scattered.o
AR sound/isa/sb/built-in.a
AR sound/isa/wavefront/built-in.a
AR sound/isa/wss/built-in.a
AR sound/isa/built-in.a
CC fs/proc/root.o
AR arch/x86/platform/intel/built-in.a
CC lib/zlib_inflate/inflate_syms.o
AR arch/x86/platform/intel-mid/built-in.a
AR arch/x86/platform/intel-quark/built-in.a
CC lib/crypto/mpi/mpi-bit.o
CC security/keys/user_defined.o
CC arch/x86/kernel/cpu/mtrr/cleanup.o
AR arch/x86/platform/olpc/built-in.a
AR arch/x86/platform/scx200/built-in.a
AR arch/x86/platform/ts5500/built-in.a
CC ipc/namespace.o
CC kernel/power/process.o
CC sound/core/seq/seq_system.o
AR arch/x86/platform/uv/built-in.a
CC kernel/dma/mapping.o
AR arch/x86/platform/built-in.a
CC arch/x86/pci/irq.o
CC kernel/irq/manage.o
CC lib/crypto/mpi/mpi-cmp.o
CC arch/x86/kernel/cpu/microcode/amd.o
CC arch/x86/kernel/cpu/mtrr/amd.o
CC arch/x86/kernel/cpu/mtrr/cyrix.o
CC kernel/locking/semaphore.o
CC crypto/asymmetric_keys/pkcs7.asn1.o
CC kernel/locking/rwsem.o
CC arch/x86/kernel/apic/apic.o
CC arch/x86/kernel/cpu/mtrr/centaur.o
CC kernel/locking/percpu-rwsem.o
CC crypto/asymmetric_keys/pkcs7_parser.o
CC kernel/locking/spinlock.o
CC arch/x86/kernel/apic/apic_common.o
AR lib/zlib_inflate/built-in.a
CC arch/x86/kernel/apic/apic_noop.o
CC block/blk-flush.o
CC ipc/mq_sysctl.o
CC lib/zlib_deflate/deflate.o
CC arch/x86/mm/physaddr.o
AR drivers/pci/pcie/built-in.a
AR drivers/pci/switch/built-in.a
CC drivers/pci/access.o
CC arch/x86/kernel/cpu/mce/amd.o
CC fs/iomap/swapfile.o
CC mm/readahead.o
CC arch/x86/events/intel/p6.o
CC net/sched/sch_generic.o
CC io_uring/rsrc.o
AS arch/x86/lib/msr-reg.o
CC net/sched/sch_mq.o
CC arch/x86/lib/msr-reg-export.o
CC sound/core/seq/seq_ports.o
AS arch/x86/lib/hweight.o
CC lib/zlib_deflate/deftree.o
CC security/keys/proc.o
AR drivers/video/built-in.a
CC arch/x86/kernel/apic/ipi.o
CC crypto/proc.o
CC fs/notify/fdinfo.o
CC drivers/acpi/acpica/dsargs.o
CC drivers/pnp/pnpacpi/core.o
CC fs/proc/base.o
CC drivers/pnp/core.o
AR ipc/built-in.a
CC fs/quota/kqid.o
CC lib/crypto/mpi/mpi-sub-ui.o
CC arch/x86/events/core.o
CC kernel/entry/common.o
CC security/selinux/nlmsgtab.o
CC block/blk-settings.o
CC arch/x86/lib/iomem.o
CC lib/crypto/mpi/mpi-div.o
AR crypto/asymmetric_keys/built-in.a
CC arch/x86/kernel/cpu/mtrr/legacy.o
CC kernel/power/suspend.o
CC arch/x86/kernel/cpu/topology_common.o
CC arch/x86/kernel/cpu/mce/threshold.o
CC arch/x86/mm/tlb.o
CC arch/x86/kernel/kprobes/core.o
CC net/netlink/af_netlink.o
AR net/bpf/built-in.a
CC kernel/dma/direct.o
CC drivers/acpi/acpica/dscontrol.o
CC kernel/locking/osq_lock.o
CC arch/x86/kernel/kprobes/opt.o
CC kernel/printk/nbcon.o
AR fs/iomap/built-in.a
CC net/core/stream.o
CC arch/x86/lib/atomic64_32.o
AR arch/x86/kernel/cpu/microcode/built-in.a
AR arch/x86/kernel/cpu/mtrr/built-in.a
CC fs/proc/generic.o
CC fs/quota/netlink.o
CC kernel/dma/ops_helpers.o
CC lib/zlib_deflate/deflate_syms.o
CC net/ethtool/ioctl.o
CC io_uring/notif.o
CC crypto/aead.o
CC arch/x86/lib/inat.o
AR fs/notify/built-in.a
CC crypto/geniv.o
CC kernel/rcu/sync.o
CC drivers/pnp/pnpacpi/rsparser.o
CC arch/x86/events/intel/pt.o
CC drivers/pci/bus.o
CC arch/x86/pci/common.o
CC security/keys/sysctl.o
CC kernel/locking/qspinlock.o
CC net/netfilter/core.o
AR arch/x86/lib/built-in.a
CC arch/x86/events/probe.o
AR arch/x86/lib/lib.a
CC sound/core/seq/seq_info.o
AR drivers/amba/built-in.a
CC arch/x86/pci/early.o
CC arch/x86/kernel/apic/vector.o
CC kernel/rcu/srcutree.o
CC lib/crypto/mpi/mpi-mod.o
CC drivers/acpi/acpica/dsdebug.o
CC mm/swap.o
CC net/sched/sch_frag.o
AR lib/zlib_deflate/built-in.a
CC kernel/power/hibernate.o
CC kernel/irq/spurious.o
CC arch/x86/events/utils.o
CC block/blk-ioc.o
CC security/selinux/netif.o
CC kernel/locking/rtmutex_api.o
CC kernel/entry/syscall_user_dispatch.o
CC drivers/acpi/acpica/dsfield.o
CC kernel/sched/build_utility.o
AR drivers/acpi/pmic/built-in.a
CC drivers/pci/probe.o
CC security/keys/keyctl_pkey.o
CC net/ipv4/netfilter/nf_defrag_ipv4.o
CC net/netfilter/nf_log.o
AR arch/x86/kernel/cpu/mce/built-in.a
CC net/ipv4/route.o
CC arch/x86/kernel/cpu/topology_ext.o
CC fs/proc/array.o
CC net/ipv4/netfilter/nf_reject_ipv4.o
CC sound/core/seq/seq_dummy.o
CC crypto/lskcipher.o
AR arch/x86/kernel/kprobes/built-in.a
CC block/blk-map.o
CC kernel/printk/printk_ringbuffer.o
AR fs/quota/built-in.a
CC drivers/pnp/card.o
CC lib/crypto/mpi/mpi-mul.o
CC net/netlink/genetlink.o
CC drivers/acpi/dptf/int340x_thermal.o
CC lib/crypto/aes.o
CC arch/x86/events/intel/uncore.o
CC arch/x86/mm/cpu_entry_area.o
CC kernel/printk/sysctl.o
CC kernel/irq/resend.o
CC drivers/acpi/acpica/dsinit.o
CC arch/x86/pci/bus_numa.o
AR drivers/pnp/pnpacpi/built-in.a
CC io_uring/tctx.o
CC lib/lzo/lzo1x_compress.o
CC arch/x86/pci/amd_bus.o
CC kernel/dma/remap.o
CC lib/lzo/lzo1x_compress_safe.o
CC arch/x86/kernel/cpu/topology_amd.o
AR kernel/entry/built-in.a
CC kernel/irq/chip.o
CC net/ipv4/netfilter/ip_tables.o
CC net/ethtool/common.o
CC drivers/pnp/driver.o
AR security/keys/built-in.a
CC arch/x86/kernel/cpu/common.o
CC mm/truncate.o
AR drivers/acpi/dptf/built-in.a
CC mm/vmscan.o
CC drivers/acpi/acpica/dsmethod.o
AR sound/core/seq/built-in.a
CC sound/core/control.o
CC kernel/rcu/tree.o
CC crypto/skcipher.o
CC kernel/irq/dummychip.o
CC lib/crypto/mpi/mpih-cmp.o
CC net/netfilter/nf_queue.o
CC drivers/pci/host-bridge.o
CC net/sched/sch_api.o
CC arch/x86/mm/maccess.o
CC arch/x86/mm/pgprot.o
AR kernel/printk/built-in.a
CC net/core/scm.o
CC arch/x86/kernel/apic/init.o
CC kernel/locking/qrwlock.o
CC net/ipv4/inetpeer.o
AR drivers/clk/analogbits/built-in.a
CC kernel/power/snapshot.o
AR drivers/clk/actions/built-in.a
CC kernel/power/swap.o
AR drivers/clk/bcm/built-in.a
AR drivers/clk/imgtec/built-in.a
CC arch/x86/kernel/apic/hw_nmi.o
AR drivers/clk/imx/built-in.a
AR drivers/clk/ingenic/built-in.a
CC net/netlink/policy.o
CC lib/lzo/lzo1x_decompress_safe.o
CC block/blk-merge.o
CC kernel/irq/devres.o
AR drivers/clk/mediatek/built-in.a
CC security/selinux/netnode.o
AR drivers/clk/microchip/built-in.a
AR kernel/dma/built-in.a
CC security/selinux/netport.o
AR drivers/clk/mstar/built-in.a
CC kernel/irq/kexec.o
AR drivers/clk/mvebu/built-in.a
AR drivers/clk/ralink/built-in.a
AR drivers/clk/renesas/built-in.a
CC fs/proc/fd.o
CC drivers/acpi/acpica/dsmthdat.o
AR drivers/clk/socfpga/built-in.a
AR drivers/clk/sophgo/built-in.a
AR drivers/clk/sprd/built-in.a
AR drivers/clk/starfive/built-in.a
AR drivers/clk/sunxi-ng/built-in.a
CC kernel/power/user.o
CC kernel/power/poweroff.o
AR drivers/clk/ti/built-in.a
CC drivers/pnp/resource.o
LDS arch/x86/kernel/vmlinux.lds
AR drivers/clk/versatile/built-in.a
CC net/core/gen_stats.o
AR drivers/clk/xilinx/built-in.a
AR drivers/clk/built-in.a
AR arch/x86/pci/built-in.a
CC lib/lz4/lz4_decompress.o
CC mm/shrinker.o
CC net/netfilter/nf_sockopt.o
CC kernel/module/main.o
CC io_uring/filetable.o
CC lib/crypto/mpi/mpih-div.o
CC arch/x86/mm/pgtable_32.o
AR kernel/locking/built-in.a
CC net/ethtool/netlink.o
CC kernel/rcu/rcu_segcblist.o
CC net/xfrm/xfrm_policy.o
CC net/unix/af_unix.o
CC arch/x86/kernel/cpu/rdrand.o
CC arch/x86/events/intel/uncore_nhmex.o
CC arch/x86/events/rapl.o
CC kernel/irq/autoprobe.o
AR lib/lzo/built-in.a
CC drivers/acpi/acpica/dsobject.o
CC crypto/seqiv.o
CC crypto/echainiv.o
CC mm/shmem.o
CC arch/x86/kernel/apic/io_apic.o
CC drivers/pci/remove.o
CC net/core/gen_estimator.o
CC fs/kernfs/mount.o
CC arch/x86/events/msr.o
AS arch/x86/kernel/head_32.o
CC security/selinux/status.o
CC drivers/dma/dw/core.o
CC drivers/dma/hsu/hsu.o
AR drivers/dma/idxd/built-in.a
CC net/ipv4/protocol.o
CC fs/kernfs/inode.o
AR net/netlink/built-in.a
CC kernel/time/time.o
CC lib/zstd/zstd_decompress_module.o
CC fs/proc/proc_tty.o
CC drivers/acpi/acpica/dsopcode.o
CC kernel/irq/irqdomain.o
CC arch/x86/mm/iomap_32.o
CC net/xfrm/xfrm_state.o
CC lib/zstd/decompress/huf_decompress.o
CC net/sched/sch_blackhole.o
CC arch/x86/kernel/cpu/match.o
CC io_uring/rw.o
CC net/unix/garbage.o
CC net/ipv4/netfilter/iptable_filter.o
CC sound/core/misc.o
CC lib/crypto/mpi/mpih-mul.o
CC net/ipv4/ip_input.o
CC arch/x86/kernel/head32.o
CC crypto/ahash.o
CC kernel/module/strict_rwx.o
CC drivers/pnp/manager.o
CC net/netfilter/utils.o
CC arch/x86/kernel/apic/msi.o
AR sound/pci/ac97/built-in.a
CC drivers/pci/pci.o
AR sound/pci/ali5451/built-in.a
AR sound/pci/asihpi/built-in.a
AR sound/ppc/built-in.a
AR sound/pci/au88x0/built-in.a
AR sound/pci/aw2/built-in.a
CC drivers/pnp/support.o
AR sound/pci/ctxfi/built-in.a
AR sound/pci/ca0106/built-in.a
CC drivers/acpi/acpica/dspkginit.o
AR kernel/power/built-in.a
AR sound/pci/cs46xx/built-in.a
CC net/netfilter/nfnetlink.o
AR sound/pci/cs5535audio/built-in.a
CC block/blk-timeout.o
AR sound/pci/lola/built-in.a
AR sound/pci/lx6464es/built-in.a
CC drivers/pnp/interface.o
AR sound/pci/echoaudio/built-in.a
CC arch/x86/kernel/cpu/bugs.o
AR sound/pci/emu10k1/built-in.a
CC sound/pci/hda/hda_bind.o
AR lib/lz4/built-in.a
CC fs/kernfs/dir.o
CC arch/x86/mm/hugetlbpage.o
CC fs/proc/cmdline.o
CC block/blk-lib.o
CC drivers/acpi/acpica/dsutils.o
CC net/ethtool/bitset.o
CC arch/x86/events/intel/uncore_snb.o
CC io_uring/net.o
AR drivers/dma/hsu/built-in.a
CC arch/x86/kernel/cpu/aperfmperf.o
CC net/core/net_namespace.o
CC sound/core/device.o
CC lib/crypto/arc4.o
AR drivers/soc/apple/built-in.a
CC crypto/shash.o
AR drivers/soc/aspeed/built-in.a
AR drivers/soc/bcm/built-in.a
CC block/blk-mq.o
CC block/blk-mq-tag.o
CC block/blk-stat.o
AR drivers/soc/fsl/built-in.a
CC net/ipv4/ip_fragment.o
AR drivers/soc/fujitsu/built-in.a
AR drivers/soc/hisilicon/built-in.a
CC security/selinux/ss/ebitmap.o
AR drivers/soc/imx/built-in.a
CC kernel/time/timer.o
AR drivers/soc/ixp4xx/built-in.a
CC block/blk-mq-sysfs.o
AR drivers/soc/loongson/built-in.a
AR drivers/soc/mediatek/built-in.a
CC lib/crypto/mpi/mpi-pow.o
AR drivers/soc/microchip/built-in.a
CC net/sched/cls_api.o
AR drivers/soc/nuvoton/built-in.a
AR drivers/soc/pxa/built-in.a
CC drivers/dma/dw/dw.o
AR drivers/soc/amlogic/built-in.a
AR drivers/soc/qcom/built-in.a
AR drivers/soc/renesas/built-in.a
AR drivers/soc/rockchip/built-in.a
AR drivers/soc/sunxi/built-in.a
AR drivers/soc/ti/built-in.a
CC drivers/acpi/acpica/dswexec.o
CC kernel/irq/proc.o
AR drivers/soc/versatile/built-in.a
AR drivers/soc/xilinx/built-in.a
AR drivers/soc/built-in.a
CC fs/proc/consoles.o
CC net/ipv4/netfilter/iptable_mangle.o
CC drivers/pnp/quirks.o
CC kernel/time/hrtimer.o
CC mm/util.o
CC net/netfilter/nfnetlink_log.o
CC sound/pci/hda/hda_codec.o
CC lib/zstd/decompress/zstd_ddict.o
CC fs/kernfs/file.o
AR arch/x86/mm/built-in.a
AR sound/pci/ice1712/built-in.a
CC arch/x86/kernel/cpu/cpuid-deps.o
CC sound/core/info.o
CC arch/x86/kernel/apic/probe_32.o
CC sound/core/isadma.o
CC sound/core/vmaster.o
CC arch/x86/kernel/cpu/umwait.o
CC lib/crypto/mpi/mpiutil.o
MKCAP arch/x86/kernel/cpu/capflags.c
CC drivers/acpi/acpica/dswload.o
CC kernel/module/kmod.o
CC security/selinux/ss/hashtab.o
CC drivers/dma/dw/idma32.o
CC drivers/acpi/x86/apple.o
CC drivers/acpi/tables.o
CC kernel/irq/migration.o
CC drivers/pci/pci-driver.o
CC fs/proc/cpuinfo.o
CC arch/x86/kernel/ebda.o
CC arch/x86/events/intel/uncore_snbep.o
CC net/ethtool/strset.o
CC net/ethtool/linkinfo.o
AR arch/x86/kernel/apic/built-in.a
CC net/ethtool/linkmodes.o
CC crypto/akcipher.o
CC mm/mmzone.o
AR sound/pci/korg1212/built-in.a
CC kernel/irq/cpuhotplug.o
CC net/unix/sysctl_net_unix.o
CC fs/kernfs/symlink.o
CC lib/xz/xz_dec_syms.o
CC net/sched/act_api.o
CC drivers/acpi/acpica/dswload2.o
CC drivers/pnp/system.o
CC block/blk-mq-cpumap.o
AR lib/crypto/mpi/built-in.a
CC net/ipv4/ip_forward.o
CC lib/crypto/gf128mul.o
CC net/netfilter/nf_conntrack_core.o
CC sound/pci/hda/hda_jack.o
AR drivers/dma/amd/built-in.a
CC drivers/acpi/x86/cmos_rtc.o
CC security/selinux/ss/symtab.o
CC io_uring/poll.o
CC io_uring/eventfd.o
CC drivers/acpi/osi.o
CC sound/core/ctljack.o
CC lib/xz/xz_dec_stream.o
CC net/ipv4/netfilter/ipt_REJECT.o
CC net/core/secure_seq.o
AR sound/arm/built-in.a
CC [M] net/ipv4/netfilter/iptable_nat.o
CC fs/proc/devices.o
CC drivers/virtio/virtio.o
CC drivers/dma/dw/acpi.o
CC drivers/tty/vt/vt_ioctl.o
CC security/selinux/ss/sidtab.o
CC mm/vmstat.o
CC kernel/module/tree_lookup.o
CC drivers/acpi/acpica/dswscope.o
AR kernel/rcu/built-in.a
AR drivers/pnp/built-in.a
CC drivers/tty/hvc/hvc_console.o
CC drivers/tty/serial/8250/8250_core.o
CC lib/zstd/decompress/zstd_decompress.o
CC kernel/irq/pm.o
CC kernel/irq/msi.o
CC net/core/flow_dissector.o
CC net/core/sysctl_net_core.o
CC lib/crypto/blake2s.o
CC sound/core/jack.o
AR fs/kernfs/built-in.a
CC security/selinux/ss/avtab.o
CC sound/core/hwdep.o
CC lib/xz/xz_dec_lzma2.o
CC crypto/sig.o
CC drivers/tty/vt/vc_screen.o
CC drivers/acpi/x86/lpss.o
CC drivers/acpi/acpica/dswstate.o
AR net/unix/built-in.a
CC drivers/acpi/acpica/evevent.o
CC drivers/acpi/acpica/evgpe.o
CC block/blk-mq-sched.o
CC kernel/time/sleep_timeout.o
CC arch/x86/kernel/platform-quirks.o
CC net/core/dev.o
CC drivers/tty/serial/8250/8250_platform.o
CC fs/proc/interrupts.o
CC net/ethtool/rss.o
CC net/ethtool/linkstate.o
AR drivers/dma/dw/built-in.a
CC lib/crypto/blake2s-generic.o
AR drivers/dma/mediatek/built-in.a
AR drivers/dma/qcom/built-in.a
AR drivers/dma/stm32/built-in.a
CC kernel/module/kallsyms.o
AR drivers/dma/ti/built-in.a
AR drivers/dma/xilinx/built-in.a
CC drivers/dma/dmaengine.o
AR sound/sh/built-in.a
CC kernel/irq/affinity.o
CC drivers/virtio/virtio_ring.o
CC net/xfrm/xfrm_hash.o
CC net/xfrm/xfrm_input.o
CC drivers/pci/search.o
CC arch/x86/kernel/cpu/powerflags.o
CC drivers/acpi/acpica/evgpeblk.o
CC drivers/acpi/acpica/evgpeinit.o
CC lib/zstd/decompress/zstd_decompress_block.o
CC kernel/time/timekeeping.o
AR kernel/sched/built-in.a
CC block/ioctl.o
CC crypto/kpp.o
AR drivers/tty/hvc/built-in.a
CC lib/dim/dim.o
CC drivers/tty/serial/serial_core.o
CC lib/dim/net_dim.o
CC drivers/tty/serial/serial_base_bus.o
CC net/sched/sch_fifo.o
CC sound/core/timer.o
CC fs/proc/loadavg.o
AR net/ipv4/netfilter/built-in.a
CC lib/xz/xz_dec_bcj.o
CC net/ipv4/ip_options.o
CC drivers/acpi/x86/s2idle.o
CC drivers/char/hw_random/core.o
CC lib/crypto/sha1.o
AR drivers/iommu/amd/built-in.a
AR drivers/gpu/host1x/built-in.a
CC lib/crypto/sha256.o
AR drivers/iommu/intel/built-in.a
AR drivers/iommu/arm/arm-smmu/built-in.a
AR drivers/iommu/arm/arm-smmu-v3/built-in.a
AR drivers/iommu/arm/built-in.a
CC sound/pci/hda/hda_auto_parser.o
AR drivers/iommu/iommufd/built-in.a
CC drivers/tty/vt/selection.o
AR drivers/iommu/riscv/built-in.a
CC drivers/char/agp/backend.o
CC drivers/iommu/iommu.o
CC drivers/char/hw_random/intel-rng.o
CC net/core/dev_api.o
CC kernel/module/procfs.o
AR drivers/gpu/drm/tests/built-in.a
CC drivers/tty/serial/8250/8250_pnp.o
AR drivers/gpu/drm/arm/built-in.a
AR drivers/gpu/drm/clients/built-in.a
CC kernel/irq/matrix.o
CC drivers/acpi/acpica/evgpeutil.o
CC kernel/module/sysfs.o
CC drivers/gpu/drm/display/drm_display_helper_mod.o
CC sound/core/hrtimer.o
CC net/sched/cls_cgroup.o
CC io_uring/uring_cmd.o
CC drivers/acpi/acpica/evglock.o
CC mm/backing-dev.o
CC security/selinux/ss/policydb.o
CC arch/x86/events/intel/uncore_discovery.o
CC arch/x86/events/intel/cstate.o
AR drivers/gpu/vga/built-in.a
AR sound/pci/mixart/built-in.a
AR lib/xz/built-in.a
CC net/xfrm/xfrm_output.o
ASN.1 crypto/rsapubkey.asn1.[ch]
CC drivers/dma/virt-dma.o
CC block/genhd.o
CC net/sched/ematch.o
CC drivers/pci/rom.o
CC net/ethtool/debug.o
CC fs/proc/meminfo.o
CC drivers/gpu/drm/ttm/ttm_tt.o
CC drivers/gpu/drm/display/drm_dp_dual_mode_helper.o
AR lib/crypto/built-in.a
CC drivers/gpu/drm/display/drm_dp_helper.o
CC lib/dim/rdma_dim.o
ASN.1 crypto/rsaprivkey.asn1.[ch]
CC crypto/rsa.o
CC security/selinux/ss/services.o
CC drivers/acpi/acpica/evhandler.o
CC kernel/futex/core.o
CC drivers/connector/cn_queue.o
CC drivers/iommu/iommu-traces.o
CC drivers/acpi/x86/utils.o
CC drivers/char/hw_random/amd-rng.o
CC kernel/cgroup/cgroup.o
AR drivers/tty/ipwireless/built-in.a
CC net/netfilter/nf_conntrack_standalone.o
CC drivers/acpi/x86/blacklist.o
CC drivers/char/agp/generic.o
CC drivers/tty/vt/keyboard.o
CC drivers/base/power/sysfs.o
CC drivers/tty/serial/8250/8250_rsa.o
CC drivers/block/loop.o
AR kernel/module/built-in.a
CC drivers/virtio/virtio_anchor.o
AR lib/dim/built-in.a
CC drivers/block/virtio_blk.o
CC drivers/pci/setup-res.o
CC drivers/pci/irq.o
CC drivers/dma/acpi-dma.o
CC drivers/acpi/acpica/evmisc.o
CC net/core/dev_addr_lists.o
CC fs/proc/stat.o
CC sound/pci/hda/hda_sysfs.o
AR sound/synth/emux/built-in.a
AR sound/synth/built-in.a
CC drivers/base/power/generic_ops.o
CC net/ipv4/ip_output.o
CC drivers/tty/serial/8250/8250_port.o
CC arch/x86/kernel/process_32.o
CC crypto/rsa_helper.o
CC kernel/time/ntp.o
CC fs/proc/uptime.o
CC sound/core/pcm.o
CC lib/zstd/zstd_common_module.o
CC drivers/gpu/drm/ttm/ttm_bo.o
CC security/selinux/ss/conditional.o
AR kernel/irq/built-in.a
CC mm/mm_init.o
CC net/ethtool/wol.o
CC drivers/char/mem.o
CC drivers/acpi/osl.o
AR arch/x86/events/intel/built-in.a
AR arch/x86/events/built-in.a
CC drivers/char/hw_random/geode-rng.o
CC drivers/char/random.o
CC io_uring/openclose.o
CC drivers/acpi/acpica/evregion.o
CC drivers/virtio/virtio_pci_modern_dev.o
AR drivers/acpi/x86/built-in.a
CC net/netfilter/nf_conntrack_expect.o
AR net/sched/built-in.a
CC fs/sysfs/file.o
CC drivers/tty/serial/8250/8250_dma.o
CC kernel/futex/syscalls.o
CC crypto/rsa-pkcs1pad.o
CC drivers/base/power/common.o
CC block/ioprio.o
CC net/ipv4/ip_sockglue.o
CC drivers/base/power/qos.o
CC kernel/cgroup/rstat.o
CC drivers/connector/connector.o
AR drivers/dma/built-in.a
CC arch/x86/kernel/signal.o
CC drivers/pci/vpd.o
CC drivers/gpu/drm/i915/i915_config.o
CC drivers/char/agp/isoch.o
CC sound/pci/hda/hda_controller.o
CC net/xfrm/xfrm_sysctl.o
CC drivers/acpi/acpica/evrgnini.o
CC fs/proc/util.o
CC fs/sysfs/dir.o
CC drivers/iommu/iommu-sysfs.o
CC drivers/char/hw_random/via-rng.o
CC drivers/tty/vt/vt.o
CC drivers/gpu/drm/i915/i915_driver.o
AR sound/pci/nm256/built-in.a
CC kernel/time/clocksource.o
CC lib/fonts/fonts.o
CC kernel/futex/pi.o
CC lib/fonts/font_8x16.o
AR sound/usb/misc/built-in.a
AR sound/usb/usx2y/built-in.a
AR sound/usb/caiaq/built-in.a
CC sound/core/pcm_native.o
AR sound/usb/6fire/built-in.a
AR sound/usb/hiface/built-in.a
CC drivers/pci/setup-bus.o
AR sound/usb/bcd2000/built-in.a
AR sound/usb/built-in.a
CC drivers/gpu/drm/i915/i915_drm_client.o
CC drivers/virtio/virtio_pci_legacy_dev.o
CC drivers/acpi/acpica/evsci.o
CC drivers/base/power/runtime.o
CC net/ethtool/features.o
CC io_uring/sqpoll.o
CC crypto/rsassa-pkcs1.o
AR drivers/block/built-in.a
CC net/ethtool/privflags.o
CC kernel/cgroup/namespace.o
CC drivers/gpu/drm/ttm/ttm_bo_util.o
CC lib/zstd/common/debug.o
CC kernel/time/jiffies.o
CC fs/proc/version.o
AR drivers/char/hw_random/built-in.a
AR drivers/gpu/drm/renesas/rcar-du/built-in.a
AR drivers/gpu/drm/renesas/rz-du/built-in.a
AR drivers/gpu/drm/renesas/built-in.a
CC block/badblocks.o
CC fs/sysfs/symlink.o
CC drivers/gpu/drm/i915/i915_getparam.o
CC drivers/gpu/drm/display/drm_dp_mst_topology.o
CC drivers/misc/eeprom/eeprom_93cx6.o
AR lib/fonts/built-in.a
AR drivers/misc/cb710/built-in.a
CC block/blk-rq-qos.o
CC drivers/char/agp/amd64-agp.o
CC drivers/char/agp/intel-agp.o
CC net/ethtool/rings.o
CC drivers/char/agp/intel-gtt.o
CC drivers/iommu/dma-iommu.o
CC mm/percpu.o
CC net/ethtool/channels.o
CC drivers/gpu/drm/ttm/ttm_bo_vm.o
CC drivers/acpi/acpica/evxface.o
CC drivers/connector/cn_proc.o
CC drivers/tty/serial/8250/8250_dwlib.o
CC sound/core/pcm_lib.o
CC drivers/pci/vc.o
CC net/netfilter/nf_conntrack_helper.o
CC arch/x86/kernel/signal_32.o
CC drivers/char/misc.o
CC net/xfrm/xfrm_replay.o
CC arch/x86/kernel/cpu/topology.o
CC kernel/futex/requeue.o
CC drivers/virtio/virtio_pci_modern.o
AR drivers/misc/eeprom/built-in.a
CC fs/proc/softirqs.o
AR drivers/misc/lis3lv02d/built-in.a
CC crypto/acompress.o
AR drivers/misc/cardreader/built-in.a
AR drivers/misc/keba/built-in.a
CC kernel/time/timer_list.o
AR drivers/misc/built-in.a
CC drivers/base/firmware_loader/builtin/main.o
CC drivers/base/regmap/regmap.o
AR drivers/base/test/built-in.a
CC arch/x86/kernel/cpu/proc.o
CC security/selinux/ss/mls.o
CC drivers/acpi/acpica/evxfevnt.o
CC fs/sysfs/mount.o
CC sound/pci/hda/hda_proc.o
CC drivers/base/component.o
CC block/disk-events.o
CC net/netfilter/nf_conntrack_proto.o
CC net/netfilter/nf_conntrack_proto_generic.o
CC net/netfilter/nf_conntrack_proto_tcp.o
CC drivers/base/power/wakeirq.o
CC net/ethtool/coalesce.o
CC security/selinux/ss/context.o
CC drivers/base/power/main.o
CC drivers/base/power/wakeup.o
AR drivers/base/firmware_loader/builtin/built-in.a
CC drivers/base/firmware_loader/main.o
CC drivers/gpu/drm/ttm/ttm_module.o
CC kernel/cgroup/cgroup-v1.o
CC net/netfilter/nf_conntrack_proto_udp.o
CC lib/zstd/common/entropy_common.o
CC drivers/tty/serial/8250/8250_pcilib.o
CC net/ipv6/netfilter/ip6_tables.o
CC net/packet/af_packet.o
CC fs/proc/namespaces.o
CC drivers/acpi/acpica/evxfgpe.o
CC net/ipv4/inet_hashtables.o
CC net/ipv6/netfilter/ip6table_filter.o
AR drivers/char/agp/built-in.a
CC drivers/char/virtio_console.o
CC kernel/futex/waitwake.o
CC drivers/gpu/drm/i915/i915_ioctl.o
CC net/ipv4/inet_timewait_sock.o
CC net/netfilter/nf_conntrack_proto_icmp.o
CC kernel/time/timeconv.o
CC arch/x86/kernel/cpu/feat_ctl.o
CC lib/zstd/common/error_private.o
CC lib/zstd/common/fse_decompress.o
AR drivers/connector/built-in.a
CC arch/x86/kernel/cpu/intel.o
CC drivers/virtio/virtio_pci_common.o
CC io_uring/xattr.o
AR sound/pci/oxygen/built-in.a
CC net/netfilter/nf_conntrack_extend.o
CC drivers/pci/mmap.o
CC crypto/scompress.o
CC drivers/gpu/drm/ttm/ttm_execbuf_util.o
CC fs/sysfs/group.o
CC drivers/iommu/iova.o
CC drivers/acpi/acpica/evxfregn.o
AR sound/firewire/built-in.a
CC kernel/time/timecounter.o
CC drivers/base/regmap/regcache.o
COPY drivers/tty/vt/defkeymap.c
CC block/blk-ia-ranges.o
CC lib/zstd/common/zstd_common.o
CC net/xfrm/xfrm_device.o
CC drivers/tty/serial/8250/8250_early.o
CC kernel/time/alarmtimer.o
AR drivers/mfd/built-in.a
CC sound/core/pcm_misc.o
CC sound/core/pcm_memory.o
CC fs/proc/self.o
CC sound/pci/hda/hda_hwdep.o
CC net/ipv6/af_inet6.o
CC drivers/base/power/wakeup_stats.o
CC security/selinux/netlabel.o
AR kernel/futex/built-in.a
AR lib/zstd/built-in.a
CC drivers/acpi/acpica/exconcat.o
CC net/ethtool/pause.o
CC lib/argv_split.o
CC arch/x86/kernel/cpu/tsx.o
AR drivers/base/firmware_loader/built-in.a
CC arch/x86/kernel/cpu/intel_epb.o
CC net/core/dst.o
CC drivers/tty/vt/consolemap.o
CC drivers/pci/devres.o
CC drivers/base/power/trace.o
CC drivers/gpu/drm/i915/i915_irq.o
CC arch/x86/kernel/traps.o
CC drivers/gpu/drm/ttm/ttm_range_manager.o
CC net/xfrm/xfrm_nat_keepalive.o
AR fs/sysfs/built-in.a
CC io_uring/nop.o
AR sound/pci/pcxhr/built-in.a
CC sound/pci/hda/hda_intel.o
CC drivers/base/regmap/regcache-rbtree.o
CC drivers/tty/serial/8250/8250_exar.o
CC net/ipv6/anycast.o
CC drivers/gpu/drm/display/drm_dsc_helper.o
CC drivers/virtio/virtio_pci_legacy.o
CC lib/bug.o
CC drivers/tty/tty_io.o
CC drivers/acpi/acpica/exconfig.o
CC kernel/cgroup/freezer.o
CC crypto/algboss.o
CC block/early-lookup.o
CC io_uring/fs.o
HOSTCC drivers/tty/vt/conmakehash
CC mm/slab_common.o
CC fs/proc/thread_self.o
AR net/dsa/built-in.a
CC drivers/pci/proc.o
CC drivers/base/regmap/regcache-flat.o
AR drivers/iommu/built-in.a
CC drivers/base/core.o
CC arch/x86/kernel/cpu/amd.o
CC kernel/trace/trace_clock.o
CC sound/core/memalloc.o
CC net/ipv6/netfilter/ip6table_mangle.o
CC kernel/time/posix-timers.o
CC drivers/char/hpet.o
CC drivers/char/nvram.o
CC net/sunrpc/auth_gss/auth_gss.o
CC net/sunrpc/clnt.o
CC net/netfilter/nf_conntrack_acct.o
CC net/ethtool/eee.o
CC drivers/acpi/acpica/exconvrt.o
AR drivers/base/power/built-in.a
CC net/sunrpc/auth_gss/gss_mech_switch.o
AR net/wireless/tests/built-in.a
CC drivers/gpu/drm/ttm/ttm_resource.o
CC net/wireless/core.o
CC fs/devpts/inode.o
CC kernel/trace/ring_buffer.o
AR drivers/nfc/built-in.a
CC drivers/acpi/utils.o
CC drivers/tty/vt/defkeymap.o
CC lib/buildid.o
CC drivers/acpi/reboot.o
CC net/sunrpc/auth_gss/svcauth_gss.o
CC drivers/virtio/virtio_pci_admin_legacy_io.o
AR sound/pci/riptide/built-in.a
CC fs/proc/proc_sysctl.o
CC fs/proc/proc_net.o
CC arch/x86/kernel/cpu/hygon.o
CC net/ipv4/inet_connection_sock.o
CC block/bsg.o
CC drivers/tty/serial/serial_ctrl.o
CONMK drivers/tty/vt/consolemap_deftbl.c
CC drivers/tty/vt/consolemap_deftbl.o
AR drivers/tty/vt/built-in.a
CC net/xfrm/xfrm_algo.o
CC drivers/base/regmap/regcache-maple.o
CC drivers/gpu/drm/i915/i915_mitigations.o
CC io_uring/splice.o
CC drivers/acpi/acpica/excreate.o
CC drivers/gpu/drm/display/drm_hdcp_helper.o
AR security/selinux/built-in.a
AR security/built-in.a
CC drivers/tty/serial/8250/8250_lpss.o
CC net/ethtool/tsinfo.o
CC kernel/cgroup/legacy_freezer.o
CC drivers/pci/pci-sysfs.o
CC crypto/testmgr.o
AR sound/sparc/built-in.a
CC lib/clz_tab.o
CC net/netfilter/nf_conntrack_seqadj.o
CC net/ipv4/tcp.o
CC drivers/tty/serial/8250/8250_mid.o
CC net/netfilter/nf_conntrack_proto_icmpv6.o
CC sound/core/pcm_timer.o
AR net/mac80211/tests/built-in.a
CC net/mac80211/main.o
CC arch/x86/kernel/cpu/centaur.o
AR drivers/char/built-in.a
CC drivers/gpu/drm/display/drm_hdmi_helper.o
CC block/blk-cgroup.o
CC mm/compaction.o
CC drivers/acpi/acpica/exdebug.o
CC drivers/virtio/virtio_input.o
CC drivers/virtio/virtio_dma_buf.o
CC kernel/trace/trace.o
CC lib/cmdline.o
CC net/wireless/sysfs.o
AR fs/devpts/built-in.a
CC kernel/time/posix-cpu-timers.o
CC net/ipv6/netfilter/nf_defrag_ipv6_hooks.o
AR sound/spi/built-in.a
CC net/xfrm/xfrm_user.o
CC drivers/acpi/acpica/exdump.o
AR sound/pci/hda/built-in.a
AR sound/pci/rme9652/built-in.a
AR sound/pci/trident/built-in.a
CC kernel/cgroup/pids.o
CC lib/cpumask.o
AR sound/pci/ymfpci/built-in.a
CC drivers/gpu/drm/ttm/ttm_pool.o
AR sound/pci/vx222/built-in.a
AR sound/pci/built-in.a
CC drivers/gpu/drm/display/drm_scdc_helper.o
CC drivers/base/regmap/regmap-debugfs.o
CC net/core/netevent.o
CC drivers/tty/serial/serial_port.o
CC arch/x86/kernel/cpu/transmeta.o
CC crypto/cmac.o
CC net/sunrpc/auth_gss/gss_rpc_upcall.o
CC net/mac80211/status.o
CC net/ethtool/cabletest.o
CC drivers/gpu/drm/i915/i915_module.o
CC io_uring/sync.o
CC sound/core/seq_device.o
CC arch/x86/kernel/cpu/zhaoxin.o
CC drivers/acpi/acpica/exfield.o
CC drivers/tty/serial/8250/8250_pci.o
AR sound/parisc/built-in.a
CC lib/ctype.o
CC crypto/hmac.o
CC drivers/tty/serial/earlycon.o
CC kernel/time/posix-clock.o
AR drivers/dax/hmem/built-in.a
AR drivers/dax/built-in.a
CC net/sunrpc/xprt.o
CC fs/proc/kcore.o
AR net/packet/built-in.a
CC drivers/dma-buf/dma-buf.o
AR drivers/cxl/core/built-in.a
AR drivers/cxl/built-in.a
CC net/mac80211/driver-ops.o
CC lib/dec_and_lock.o
CC kernel/cgroup/rdma.o
AR drivers/virtio/built-in.a
CC fs/netfs/buffered_read.o
CC kernel/bpf/core.o
CC drivers/acpi/nvs.o
CC fs/proc/kmsg.o
CC drivers/acpi/acpica/exfldio.o
CC arch/x86/kernel/cpu/vortex.o
CC fs/ext4/balloc.o
CC fs/jbd2/transaction.o
CC drivers/pci/slot.o
CC lib/decompress.o
AR drivers/base/regmap/built-in.a
CC kernel/time/itimer.o
AR sound/core/built-in.a
CC lib/decompress_bunzip2.o
AR drivers/gpu/drm/display/built-in.a
CC drivers/macintosh/mac_hid.o
AR sound/pcmcia/vx/built-in.a
CC kernel/cgroup/cpuset.o
AR sound/pcmcia/pdaudiocf/built-in.a
CC kernel/cgroup/misc.o
AR sound/pcmcia/built-in.a
CC kernel/cgroup/debug.o
AR sound/mips/built-in.a
CC net/core/neighbour.o
AR sound/soc/built-in.a
CC net/netfilter/nf_conntrack_netlink.o
AR sound/atmel/built-in.a
CC sound/hda/hda_bus_type.o
CC crypto/crypto_null.o
CC net/core/rtnetlink.o
CC net/netfilter/nf_conntrack_ftp.o
CC io_uring/msg_ring.o
CC drivers/gpu/drm/ttm/ttm_device.o
CC arch/x86/kernel/cpu/perfctr-watchdog.o
CC drivers/acpi/acpica/exmisc.o
CC drivers/pci/pci-acpi.o
CC net/ipv6/netfilter/nf_conntrack_reasm.o
CC fs/ext4/bitmap.o
CC drivers/gpu/drm/i915/i915_params.o
CC drivers/acpi/wakeup.o
CC drivers/base/bus.o
CC block/blk-ioprio.o
CC arch/x86/kernel/idt.o
CC net/ethtool/tunnels.o
CC net/sunrpc/auth_gss/gss_rpc_xdr.o
AR drivers/gpu/drm/omapdrm/built-in.a
CC drivers/pci/iomap.o
CC fs/jbd2/commit.o
CC fs/proc/page.o
CC drivers/dma-buf/dma-fence.o
AR drivers/macintosh/built-in.a
CC net/sunrpc/socklib.o
CC crypto/md5.o
CC net/core/utils.o
CC drivers/acpi/acpica/exmutex.o
CC lib/decompress_inflate.o
CC sound/hda/hdac_bus.o
CC net/ipv4/tcp_input.o
CC drivers/gpu/drm/i915/i915_pci.o
CC block/blk-iolatency.o
CC drivers/tty/serial/8250/8250_pericom.o
CC io_uring/advise.o
CC kernel/time/clockevents.o
CC arch/x86/kernel/cpu/vmware.o
CC fs/netfs/buffered_write.o
CC net/netfilter/nf_conntrack_irc.o
CC net/wireless/radiotap.o
CC drivers/gpu/drm/ttm/ttm_sys_manager.o
CC fs/netfs/direct_read.o
CC drivers/acpi/sleep.o
CC drivers/acpi/acpica/exnames.o
CC net/sunrpc/auth_gss/trace.o
CC drivers/base/dd.o
CC crypto/sha256_generic.o
CC net/ethtool/fec.o
AR sound/x86/built-in.a
CC fs/jbd2/recovery.o
CC lib/decompress_unlz4.o
CC net/core/link_watch.o
AR fs/proc/built-in.a
CC sound/hda/hdac_device.o
CC kernel/time/tick-common.o
CC net/core/filter.o
CC drivers/dma-buf/dma-fence-array.o
CC mm/show_mem.o
CC drivers/pci/quirks.o
CC drivers/gpu/drm/ttm/ttm_backup.o
CC net/ipv6/ip6_output.o
CC drivers/acpi/acpica/exoparg1.o
CC fs/netfs/direct_write.o
CC net/netfilter/nf_conntrack_sip.o
CC fs/ext4/block_validity.o
AR drivers/tty/serial/8250/built-in.a
AR drivers/tty/serial/built-in.a
CC drivers/tty/n_tty.o
AR net/xfrm/built-in.a
CC kernel/trace/trace_output.o
CC drivers/base/syscore.o
AR drivers/scsi/pcmcia/built-in.a
CC drivers/scsi/scsi.o
CC drivers/gpu/drm/i915/i915_scatterlist.o
CC io_uring/statx.o
CC drivers/dma-buf/dma-fence-chain.o
CC arch/x86/kernel/cpu/hypervisor.o
CC lib/decompress_unlzma.o
CC crypto/sha512_generic.o
CC net/netfilter/nf_nat_core.o
CC net/ipv6/netfilter/nf_reject_ipv6.o
CC drivers/acpi/device_sysfs.o
CC drivers/base/driver.o
AR drivers/gpu/drm/tilcdc/built-in.a
CC net/netfilter/nf_nat_proto.o
CC kernel/trace/trace_seq.o
CC net/ethtool/eeprom.o
CC arch/x86/kernel/cpu/mshyperv.o
CC net/ipv6/ip6_input.o
CC net/wireless/util.o
AR kernel/cgroup/built-in.a
CC drivers/pci/pci-label.o
CC drivers/acpi/acpica/exoparg2.o
CC kernel/events/core.o
CC kernel/events/ring_buffer.o
CC drivers/gpu/drm/ttm/ttm_agp_backend.o
CC net/mac80211/sta_info.o
CC block/blk-iocost.o
CC kernel/events/callchain.o
CC drivers/dma-buf/dma-fence-unwrap.o
CC fs/jbd2/checkpoint.o
CC net/ethtool/stats.o
CC net/ipv6/addrconf.o
CC drivers/gpu/drm/i915/i915_switcheroo.o
CC drivers/gpu/drm/virtio/virtgpu_drv.o
CC mm/interval_tree.o
CC sound/hda/hdac_sysfs.o
CC kernel/time/tick-broadcast.o
CC fs/netfs/iterator.o
CC drivers/scsi/hosts.o
CC fs/ext4/dir.o
CC io_uring/timeout.o
CC io_uring/fdinfo.o
CC net/netlabel/netlabel_user.o
CC crypto/sha3_generic.o
AR sound/xen/built-in.a
CC arch/x86/kernel/irq.o
CC drivers/acpi/acpica/exoparg3.o
CC drivers/acpi/acpica/exoparg6.o
CC lib/decompress_unlzo.o
AR kernel/bpf/built-in.a
CC arch/x86/kernel/irq_32.o
CC drivers/base/class.o
AR drivers/gpu/drm/ttm/built-in.a
AR drivers/nvme/common/built-in.a
CC drivers/dma-buf/dma-resv.o
AR drivers/nvme/host/built-in.a
CC drivers/ata/libata-core.o
AR drivers/nvme/target/built-in.a
AR drivers/nvme/built-in.a
CC sound/hda/hdac_regmap.o
CC drivers/tty/tty_ioctl.o
CC arch/x86/kernel/cpu/debugfs.o
CC net/netfilter/nf_nat_helper.o
CC drivers/acpi/acpica/exprep.o
CC crypto/ecb.o
CC net/ipv6/addrlabel.o
CC net/netlabel/netlabel_kapi.o
CC block/mq-deadline.o
CC kernel/fork.o
CC drivers/gpu/drm/virtio/virtgpu_kms.o
CC kernel/time/tick-broadcast-hrtimer.o
CC kernel/time/tick-oneshot.o
CC kernel/trace/trace_stat.o
CC lib/decompress_unxz.o
CC net/ipv6/netfilter/ip6t_ipv6header.o
CC net/ipv4/tcp_output.o
CC mm/list_lru.o
CC drivers/scsi/scsi_ioctl.o
CC net/core/sock_diag.o
CC drivers/gpu/drm/i915/i915_sysfs.o
CC fs/jbd2/revoke.o
CC net/ipv6/route.o
CC drivers/dma-buf/sync_file.o
CC fs/netfs/locking.o
CC drivers/acpi/acpica/exregion.o
CC net/sunrpc/auth_gss/gss_krb5_mech.o
AR sound/virtio/built-in.a
CC drivers/base/platform.o
CC fs/netfs/main.o
CC io_uring/cancel.o
CC drivers/pci/vgaarb.o
CC fs/ext4/ext4_jbd2.o
CC crypto/cbc.o
CC arch/x86/kernel/cpu/bus_lock.o
CC net/ethtool/phc_vclocks.o
CC net/ipv6/netfilter/ip6t_REJECT.o
CC net/ipv6/ip6_fib.o
CC block/kyber-iosched.o
CC drivers/ata/libata-scsi.o
CC kernel/time/tick-sched.o
CC sound/hda/hdac_controller.o
CC drivers/acpi/device_pm.o
CC lib/decompress_unzstd.o
CC net/ipv6/ipv6_sockglue.o
CC drivers/acpi/acpica/exresnte.o
CC drivers/tty/tty_ldisc.o
CC drivers/gpu/drm/virtio/virtgpu_gem.o
CC crypto/ctr.o
AR drivers/dma-buf/built-in.a
CC net/rfkill/core.o
CC mm/workingset.o
CC kernel/trace/trace_printk.o
CC drivers/scsi/scsicam.o
CC fs/jbd2/journal.o
CC kernel/trace/pid_list.o
CC drivers/acpi/acpica/exresolv.o
CC net/sunrpc/auth_gss/gss_krb5_seal.o
AR drivers/net/phy/mediatek/built-in.a
CC net/sunrpc/auth_gss/gss_krb5_unseal.o
AR drivers/net/phy/qcom/built-in.a
CC drivers/net/phy/realtek/realtek_main.o
CC lib/dump_stack.o
CC net/sunrpc/auth_gss/gss_krb5_wrap.o
CC drivers/gpu/drm/i915/i915_utils.o
CC net/netfilter/nf_nat_masquerade.o
CC sound/sound_core.o
CC io_uring/waitid.o
CC net/netlabel/netlabel_domainhash.o
CC arch/x86/kernel/cpu/capflags.o
CC crypto/gcm.o
CC drivers/gpu/drm/virtio/virtgpu_vram.o
CC io_uring/register.o
AR arch/x86/kernel/cpu/built-in.a
CC net/ethtool/mm.o
CC arch/x86/kernel/dumpstack_32.o
CC kernel/trace/trace_sched_switch.o
CC sound/hda/hdac_stream.o
AR drivers/pci/built-in.a
CC drivers/base/cpu.o
CC net/wireless/reg.o
CC drivers/tty/tty_buffer.o
CC drivers/acpi/acpica/exresop.o
CC kernel/time/timer_migration.o
CC kernel/exec_domain.o
CC net/9p/mod.o
CC fs/netfs/misc.o
AR net/ipv6/netfilter/built-in.a
CC io_uring/truncate.o
CC drivers/scsi/scsi_error.o
CC fs/ramfs/inode.o
CC mm/debug.o
CC lib/earlycpio.o
CC net/netlabel/netlabel_addrlist.o
CC fs/ext4/extents.o
CC net/rfkill/input.o
CC lib/extable.o
CC drivers/acpi/acpica/exserial.o
CC net/core/dev_ioctl.o
CC drivers/gpu/drm/virtio/virtgpu_display.o
CC block/blk-mq-debugfs.o
CC arch/x86/kernel/time.o
CC net/ipv6/ndisc.o
CC sound/hda/array.o
CC drivers/gpu/drm/i915/intel_clock_gating.o
CC net/9p/client.o
CC drivers/ata/libata-eh.o
CC drivers/tty/tty_port.o
CC net/ipv4/tcp_timer.o
CC fs/hugetlbfs/inode.o
CC drivers/base/firmware.o
CC net/sunrpc/auth_gss/gss_krb5_crypto.o
CC net/sunrpc/auth_gss/gss_krb5_keys.o
CC net/ipv6/udp.o
CC drivers/acpi/acpica/exstore.o
CC lib/flex_proportions.o
CC crypto/ccm.o
CC fs/fat/cache.o
AR drivers/net/phy/realtek/built-in.a
CC drivers/net/phy/mdio-boardinfo.o
CC net/ethtool/module.o
CC kernel/time/vsyscall.o
CC block/blk-pm.o
CC fs/ramfs/file-mmu.o
CC drivers/tty/tty_mutex.o
AR net/rfkill/built-in.a
CC arch/x86/kernel/ioport.o
CC fs/fat/dir.o
CC net/9p/error.o
CC net/ethtool/cmis_fw_update.o
CC net/netfilter/nf_nat_ftp.o
CC sound/last.o
CC fs/netfs/objects.o
CC net/mac80211/wep.o
CC drivers/base/init.o
CC kernel/trace/trace_nop.o
CC mm/gup.o
CC lib/idr.o
CC drivers/acpi/acpica/exstoren.o
CC drivers/gpu/drm/virtio/virtgpu_vq.o
CC sound/hda/hdmi_chmap.o
CC drivers/gpu/drm/i915/intel_cpu_info.o
CC drivers/base/map.o
CC net/netlabel/netlabel_mgmt.o
CC net/mac80211/aead_api.o
CC fs/fat/fatent.o
CC net/core/tso.o
CC io_uring/memmap.o
CC net/ethtool/cmis_cdb.o
CC drivers/tty/tty_ldsem.o
CC block/holder.o
CC drivers/acpi/acpica/exstorob.o
CC drivers/scsi/scsi_lib.o
CC kernel/time/timekeeping_debug.o
AR fs/ramfs/built-in.a
CC drivers/net/phy/stubs.o
CC crypto/aes_generic.o
CC arch/x86/kernel/dumpstack.o
CC crypto/authenc.o
CC kernel/time/namespace.o
CC lib/iomem_copy.o
CC net/ipv4/tcp_ipv4.o
AR drivers/net/pse-pd/built-in.a
CC drivers/ata/libata-transport.o
CC mm/mmap_lock.o
CC drivers/acpi/proc.o
CC drivers/base/devres.o
CC lib/irq_regs.o
CC kernel/trace/blktrace.o
CC drivers/gpu/drm/i915/intel_device_info.o
AR fs/jbd2/built-in.a
CC fs/isofs/namei.o
CC drivers/acpi/acpica/exsystem.o
CC fs/nfs/client.o
CC kernel/panic.o
CC fs/netfs/read_collect.o
CC net/dns_resolver/dns_key.o
AR net/sunrpc/auth_gss/built-in.a
CC net/sunrpc/xprtsock.o
CC lib/is_single_threaded.o
CC net/handshake/alert.o
CC net/9p/protocol.o
CC net/netfilter/nf_nat_irc.o
CC drivers/tty/tty_baudrate.o
CC io_uring/alloc_cache.o
AR block/built-in.a
CC fs/nfs/dir.o
CC sound/hda/trace.o
CC net/core/sock_reuseport.o
CC net/mac80211/wpa.o
AR fs/hugetlbfs/built-in.a
CC net/core/fib_notifier.o
CC fs/isofs/inode.o
CC drivers/acpi/acpica/extrace.o
CC net/handshake/genl.o
AR kernel/time/built-in.a
CC arch/x86/kernel/nmi.o
CC lib/klist.o
CC kernel/cpu.o
CC kernel/events/hw_breakpoint.o
CC drivers/net/phy/mdio_devres.o
CC drivers/gpu/drm/virtio/virtgpu_fence.o
CC mm/highmem.o
CC net/devres.o
CC drivers/ata/libata-trace.o
CC fs/fat/file.o
CC net/dns_resolver/dns_query.o
CC io_uring/io-wq.o
CC net/ethtool/pse-pd.o
CC crypto/authencesn.o
CC drivers/tty/tty_jobctrl.o
CC drivers/base/attribute_container.o
CC kernel/exit.o
CC net/netlabel/netlabel_unlabeled.o
CC drivers/acpi/acpica/exutils.o
CC drivers/acpi/bus.o
CC lib/kobject.o
CC fs/netfs/read_pgpriv2.o
CC drivers/gpu/drm/virtio/virtgpu_object.o
CC drivers/base/transport_class.o
CC net/handshake/netlink.o
CC net/9p/trans_common.o
CC drivers/gpu/drm/i915/intel_memory_region.o
CC net/ipv6/udplite.o
CC net/handshake/request.o
CC drivers/acpi/acpica/hwacpi.o
CC fs/ext4/extents_status.o
CC sound/hda/hdac_component.o
CC net/netfilter/nf_nat_sip.o
CC drivers/net/mdio/acpi_mdio.o
CC drivers/scsi/constants.o
CC drivers/base/topology.o
CC drivers/tty/n_null.o
CC drivers/scsi/scsi_lib_dma.o
CC fs/exportfs/expfs.o
CC drivers/net/phy/phy.o
AR net/dns_resolver/built-in.a
CC mm/memory.o
CC net/mac80211/scan.o
CC fs/lockd/clntlock.o
CC net/wireless/scan.o
CC fs/nls/nls_base.o
CC mm/mincore.o
CC lib/kobject_uevent.o
CC fs/lockd/clntproc.o
CC arch/x86/kernel/ldt.o
CC kernel/trace/trace_events.o
CC net/9p/trans_fd.o
CC fs/nls/nls_cp437.o
CC drivers/acpi/acpica/hwesleep.o
CC fs/isofs/dir.o
CC drivers/ata/libata-sata.o
CC drivers/gpu/drm/virtio/virtgpu_debugfs.o
CC fs/fat/inode.o
CC kernel/events/uprobes.o
CC drivers/gpu/drm/i915/intel_pcode.o
CC net/ethtool/plca.o
CC fs/netfs/read_retry.o
CC crypto/lzo.o
CC net/ethtool/phy.o
CC drivers/tty/pty.o
CC net/core/xdp.o
AR drivers/gpu/drm/imx/built-in.a
CC net/ipv6/raw.o
CC net/netlabel/netlabel_cipso_v4.o
CC fs/nls/nls_ascii.o
CC kernel/trace/trace_export.o
CC sound/hda/hdac_i915.o
CC io_uring/futex.o
AR fs/exportfs/built-in.a
CC drivers/acpi/acpica/hwgpe.o
CC sound/hda/intel-dsp-config.o
CC drivers/base/container.o
CC drivers/scsi/scsi_scan.o
CC io_uring/epoll.o
CC drivers/firewire/init_ohci1394_dma.o
CC drivers/cdrom/cdrom.o
CC drivers/net/mdio/fwnode_mdio.o
AR drivers/auxdisplay/built-in.a
CC lib/logic_pio.o
AR drivers/gpu/drm/panel/built-in.a
CC drivers/acpi/glue.o
CC io_uring/napi.o
CC crypto/lzo-rle.o
CC fs/nls/nls_iso8859-1.o
CC fs/isofs/util.o
CC drivers/net/phy/phy-c45.o
CC drivers/gpu/drm/virtio/virtgpu_plane.o
CC drivers/base/property.o
CC arch/x86/kernel/setup.o
CC drivers/acpi/acpica/hwregs.o
CC drivers/gpu/drm/i915/intel_region_ttm.o
CC net/netfilter/x_tables.o
CC net/handshake/tlshd.o
CC fs/netfs/read_single.o
CC fs/fat/misc.o
CC drivers/tty/tty_audit.o
CC net/ipv4/tcp_minisocks.o
CC net/mac80211/offchannel.o
CC net/netfilter/xt_tcpudp.o
CC drivers/base/cacheinfo.o
CC fs/nls/nls_utf8.o
CC lib/maple_tree.o
CC sound/hda/intel-nhlt.o
CC net/ipv6/icmp.o
CC drivers/acpi/scan.o
AR drivers/firewire/built-in.a
CC net/handshake/trace.o
CC drivers/ata/libata-sff.o
CC drivers/gpu/drm/virtio/virtgpu_ioctl.o
CC net/9p/trans_virtio.o
CC net/ethtool/tsconfig.o
CC net/socket.o
CC fs/lockd/clntxdr.o
CC net/wireless/nl80211.o
CC drivers/ata/libata-pmp.o
CC net/sunrpc/sched.o
CC crypto/rng.o
CC drivers/acpi/acpica/hwsleep.o
CC fs/isofs/rock.o
CC sound/hda/intel-sdw-acpi.o
AR drivers/net/mdio/built-in.a
CC fs/fat/nfs.o
AR fs/nls/built-in.a
CC mm/mlock.o
CC fs/ext4/file.o
CC net/netlabel/netlabel_calipso.o
CC kernel/trace/trace_event_perf.o
CC drivers/base/swnode.o
GEN drivers/scsi/scsi_devinfo_tbl.c
CC drivers/scsi/scsi_devinfo.o
CC fs/nfs/file.o
CC fs/nfs/getroot.o
CC net/core/flow_offload.o
CC drivers/tty/sysrq.o
CC drivers/acpi/acpica/hwvalid.o
CC fs/netfs/rolling_buffer.o
CC net/core/gro.o
CC drivers/gpu/drm/i915/intel_runtime_pm.o
CC fs/nfs/inode.o
CC arch/x86/kernel/x86_init.o
AR kernel/events/built-in.a
CC fs/nfs/super.o
AR sound/hda/built-in.a
AR sound/built-in.a
CC lib/memcat_p.o
AR fs/unicode/built-in.a
CC net/mac80211/ht.o
CC drivers/ata/libata-acpi.o
CC drivers/net/phy/phy-core.o
CC drivers/gpu/drm/virtio/virtgpu_prime.o
CC drivers/acpi/acpica/hwxface.o
CC crypto/drbg.o
AR io_uring/built-in.a
CC net/sunrpc/auth.o
CC net/wireless/mlme.o
CC fs/fat/namei_vfat.o
CC fs/isofs/export.o
CC net/netfilter/xt_CONNSECMARK.o
CC drivers/acpi/mipi-disco-img.o
AR drivers/cdrom/built-in.a
AR drivers/net/pcs/built-in.a
CC mm/mmap.o
CC net/ipv4/tcp_cong.o
AR net/ethtool/built-in.a
CC drivers/gpu/drm/i915/intel_sbi.o
CC fs/lockd/host.o
AR drivers/gpu/drm/bridge/analogix/built-in.a
CC net/mac80211/agg-tx.o
AR drivers/gpu/drm/bridge/cadence/built-in.a
AR drivers/gpu/drm/bridge/imx/built-in.a
AR drivers/gpu/drm/bridge/synopsys/built-in.a
AR drivers/gpu/drm/bridge/built-in.a
CC kernel/softirq.o
CC drivers/scsi/scsi_sysctl.o
CC kernel/trace/trace_events_filter.o
CC fs/ext4/fsmap.o
AR net/9p/built-in.a
CC drivers/base/faux.o
CC fs/lockd/svc.o
CC drivers/acpi/acpica/hwxfsleep.o
CC arch/x86/kernel/i8259.o
CC crypto/jitterentropy.o
CC fs/netfs/write_collect.o
AR net/handshake/built-in.a
CC net/ipv6/mcast.o
AR net/netlabel/built-in.a
CC drivers/ata/libata-pata-timings.o
CC kernel/trace/trace_events_trigger.o
CC fs/isofs/joliet.o
AR drivers/tty/built-in.a
CC crypto/jitterentropy-kcapi.o
CC kernel/resource.o
CC fs/autofs/init.o
CC fs/autofs/inode.o
CC kernel/trace/trace_eprobe.o
CC net/mac80211/agg-rx.o
CC drivers/gpu/drm/virtio/virtgpu_trace_points.o
CC lib/nmi_backtrace.o
CC drivers/base/auxiliary.o
CC drivers/scsi/scsi_proc.o
CC drivers/acpi/acpica/hwpci.o
CC drivers/base/devtmpfs.o
CC net/netfilter/xt_NFLOG.o
CC drivers/ata/ahci.o
CC fs/lockd/svclock.o
CC drivers/net/phy/phy_device.o
AR drivers/net/ethernet/3com/built-in.a
CC drivers/net/ethernet/8390/ne2k-pci.o
CC arch/x86/kernel/irqinit.o
CC crypto/ghash-generic.o
CC net/ipv4/tcp_metrics.o
CC drivers/scsi/scsi_debugfs.o
CC drivers/gpu/drm/i915/intel_step.o
CC fs/isofs/compress.o
CC fs/netfs/write_issue.o
CC drivers/acpi/acpica/nsaccess.o
CC lib/objpool.o
AR drivers/net/wireless/admtek/built-in.a
CC drivers/pcmcia/cs.o
AR drivers/net/wireless/ath/built-in.a
CC net/core/netdev-genl.o
CC drivers/usb/common/common.o
AR drivers/net/wireless/atmel/built-in.a
AR drivers/net/wireless/broadcom/built-in.a
AR drivers/net/wireless/intel/built-in.a
AR drivers/net/wireless/intersil/built-in.a
CC fs/fat/namei_msdos.o
AR drivers/net/wireless/marvell/built-in.a
CC drivers/input/serio/serio.o
CC drivers/input/keyboard/atkbd.o
AR drivers/net/wireless/mediatek/built-in.a
AR drivers/net/wireless/microchip/built-in.a
AR drivers/net/wireless/purelifi/built-in.a
AR drivers/net/wireless/quantenna/built-in.a
CC fs/autofs/root.o
AR drivers/net/wireless/ralink/built-in.a
CC fs/autofs/symlink.o
AR drivers/net/wireless/realtek/built-in.a
CC drivers/rtc/lib.o
AR drivers/net/wireless/rsi/built-in.a
CC fs/autofs/waitq.o
AR drivers/net/wireless/silabs/built-in.a
AR drivers/net/wireless/st/built-in.a
CC crypto/hash_info.o
AR drivers/net/wireless/ti/built-in.a
AR drivers/net/wireless/zydas/built-in.a
CC crypto/rsapubkey.asn1.o
AR drivers/net/wireless/virtual/built-in.a
AR drivers/net/wireless/built-in.a
AR drivers/gpu/drm/hisilicon/built-in.a
CC crypto/rsaprivkey.asn1.o
CC net/ipv6/reassembly.o
CC drivers/usb/core/usb.o
CC drivers/acpi/resource.o
AR crypto/built-in.a
CC net/mac80211/vht.o
CC fs/autofs/expire.o
CC drivers/gpu/drm/virtio/virtgpu_submit.o
AR drivers/net/ethernet/adaptec/built-in.a
CC fs/autofs/dev-ioctl.o
CC drivers/acpi/acpica/nsalloc.o
CC mm/mmu_gather.o
CC drivers/input/serio/i8042.o
CC fs/nfs/io.o
CC kernel/sysctl.o
CC net/netfilter/xt_SECMARK.o
CC drivers/base/module.o
CC drivers/input/serio/serport.o
CC drivers/scsi/scsi_trace.o
CC arch/x86/kernel/jump_label.o
CC net/wireless/ibss.o
AR drivers/net/ethernet/agere/built-in.a
CC fs/9p/vfs_super.o
CC kernel/trace/trace_kprobe.o
CC fs/ext4/fsync.o
AR fs/isofs/built-in.a
CC drivers/usb/common/debug.o
AR drivers/gpu/drm/mxsfb/built-in.a
CC fs/lockd/svcshare.o
CC drivers/net/ethernet/8390/8390.o
AR drivers/usb/phy/built-in.a
CC drivers/input/mouse/psmouse-base.o
CC drivers/rtc/class.o
AR drivers/input/joystick/built-in.a
CC drivers/acpi/acpica/nsarguments.o
CC drivers/usb/core/hub.o
CC drivers/ata/libahci.o
AR drivers/usb/common/built-in.a
CC drivers/gpu/drm/i915/intel_uncore.o
CC net/ipv6/tcp_ipv6.o
CC drivers/ata/ata_piix.o
CC drivers/pcmcia/socket_sysfs.o
CC drivers/base/auxiliary_sysfs.o
CC drivers/acpi/acpi_processor.o
CC net/ipv4/tcp_fastopen.o
CC lib/plist.o
CC net/netfilter/xt_TCPMSS.o
AR fs/fat/built-in.a
AR drivers/net/usb/built-in.a
CC drivers/gpu/drm/i915/intel_uncore_trace.o
CC arch/x86/kernel/irq_work.o
CC drivers/usb/mon/mon_main.o
CC fs/netfs/write_retry.o
CC net/ipv6/ping.o
AR drivers/input/keyboard/built-in.a
CC drivers/scsi/scsi_logging.o
CC fs/ext4/hash.o
AR drivers/net/ethernet/alacritech/built-in.a
CC drivers/i2c/algos/i2c-algo-bit.o
AR drivers/gpu/drm/virtio/built-in.a
CC drivers/acpi/acpica/nsconvert.o
CC drivers/i2c/busses/i2c-i801.o
AR drivers/i2c/muxes/built-in.a
CC lib/radix-tree.o
AR fs/autofs/built-in.a
CC mm/mprotect.o
CC net/mac80211/he.o
CC net/core/netdev-genl-gen.o
CC drivers/gpu/drm/i915/intel_wakeref.o
CC drivers/base/devcoredump.o
CC fs/9p/vfs_inode.o
CC net/core/gso.o
CC drivers/net/phy/linkmode.o
CC drivers/rtc/interface.o
AR drivers/gpu/drm/sysfb/built-in.a
CC net/core/net-sysfs.o
CC fs/nfs/direct.o
CC drivers/pcmcia/cardbus.o
CC drivers/pcmcia/ds.o
CC drivers/usb/host/pci-quirks.o
CC drivers/acpi/acpica/nsdump.o
AR drivers/input/tablet/built-in.a
CC kernel/capability.o
CC drivers/i2c/i2c-boardinfo.o
CC drivers/input/serio/libps2.o
CC fs/lockd/svcproc.o
CC drivers/usb/mon/mon_stat.o
AR drivers/net/ethernet/8390/built-in.a
AR drivers/net/ethernet/alteon/built-in.a
CC drivers/net/mii.o
AR drivers/net/ethernet/amazon/built-in.a
AR drivers/net/ethernet/amd/built-in.a
AR drivers/net/ethernet/aquantia/built-in.a
AR drivers/net/ethernet/arc/built-in.a
CC drivers/input/mouse/synaptics.o
AR drivers/net/ethernet/asix/built-in.a
CC fs/ext4/ialloc.o
AR drivers/net/ethernet/atheros/built-in.a
AR drivers/net/ethernet/cadence/built-in.a
CC drivers/net/ethernet/broadcom/bnx2.o
AR drivers/net/ethernet/brocade/built-in.a
CC net/sysctl_net.o
CC net/core/hotdata.o
CC drivers/acpi/acpica/nseval.o
CC drivers/usb/core/hcd.o
CC drivers/base/platform-msi.o
CC arch/x86/kernel/probe_roms.o
AR drivers/net/ethernet/cavium/common/built-in.a
CC drivers/scsi/scsi_pm.o
AR drivers/net/ethernet/cavium/thunder/built-in.a
AR drivers/net/ethernet/cavium/liquidio/built-in.a
AR fs/netfs/built-in.a
AR drivers/net/ethernet/chelsio/built-in.a
AR drivers/net/ethernet/cavium/octeon/built-in.a
CC net/ipv4/tcp_rate.o
AR drivers/net/ethernet/cavium/built-in.a
CC drivers/usb/class/usblp.o
AR drivers/net/ethernet/cisco/built-in.a
CC drivers/input/mouse/focaltech.o
AR drivers/i2c/algos/built-in.a
CC fs/nfs/pagelist.o
CC drivers/usb/core/urb.o
CC drivers/usb/host/ehci-hcd.o
CC drivers/net/ethernet/broadcom/tg3.o
CC drivers/net/phy/phy_link_topology.o
CC net/sunrpc/auth_null.o
CC net/wireless/sme.o
CC drivers/usb/mon/mon_text.o
CC drivers/acpi/acpica/nsinit.o
CC net/netfilter/xt_conntrack.o
AR drivers/i2c/busses/built-in.a
CC drivers/usb/mon/mon_bin.o
CC mm/mremap.o
CC drivers/i2c/i2c-core-base.o
CC drivers/ata/pata_amd.o
CC drivers/base/physical_location.o
CC drivers/input/mouse/alps.o
AR drivers/input/serio/built-in.a
CC net/core/netdev_rx_queue.o
CC fs/9p/vfs_inode_dotl.o
CC net/netfilter/xt_policy.o
CC drivers/usb/storage/scsiglue.o
CC arch/x86/kernel/sys_ia32.o
CC kernel/trace/error_report-traces.o
CC net/ipv4/tcp_recovery.o
CC drivers/pcmcia/pcmcia_resource.o
CC net/netfilter/xt_state.o
CC drivers/net/loopback.o
CC drivers/scsi/scsi_bsg.o
CC drivers/usb/core/message.o
CC drivers/acpi/acpica/nsload.o
CC drivers/rtc/nvmem.o
CC drivers/base/trace.o
CC fs/lockd/svcsubs.o
AR drivers/usb/misc/built-in.a
CC drivers/i2c/i2c-core-smbus.o
AR drivers/usb/class/built-in.a
AR drivers/gpu/drm/tiny/built-in.a
CC arch/x86/kernel/ksysfs.o
AR drivers/net/ethernet/cortina/built-in.a
CC fs/ext4/indirect.o
CC drivers/usb/storage/protocol.o
CC drivers/gpu/drm/i915/vlv_sideband.o
CC drivers/net/phy/phy_package.o
CC drivers/net/netconsole.o
CC drivers/acpi/acpica/nsnames.o
CC [M] net/netfilter/nf_log_syslog.o
CC drivers/ata/pata_oldpiix.o
CC lib/ratelimit.o
CC net/mac80211/s1g.o
CC drivers/i2c/i2c-core-acpi.o
AR drivers/input/touchscreen/built-in.a
CC kernel/trace/power-traces.o
CC drivers/rtc/dev.o
CC drivers/usb/core/driver.o
CC drivers/usb/storage/transport.o
CC drivers/acpi/acpica/nsobject.o
CC net/ipv6/exthdrs.o
CC net/mac80211/ibss.o
AR drivers/usb/mon/built-in.a
CC drivers/scsi/scsi_common.o
CC net/wireless/chan.o
CC [M] net/netfilter/xt_mark.o
CC [M] net/netfilter/xt_nat.o
CC fs/9p/vfs_addr.o
CC lib/rbtree.o
CC net/core/net-procfs.o
CC net/ipv4/tcp_ulp.o
CC mm/msync.o
CC drivers/usb/host/ehci-pci.o
CC fs/nfs/read.o
AR drivers/gpu/drm/xlnx/built-in.a
CC net/mac80211/iface.o
CC arch/x86/kernel/bootflag.o
CC drivers/net/phy/phy_caps.o
AR drivers/base/built-in.a
CC net/mac80211/link.o
CC drivers/pcmcia/cistpl.o
CC drivers/acpi/acpica/nsparse.o
CC net/mac80211/rate.o
CC fs/9p/vfs_file.o
CC drivers/scsi/scsi_transport_spi.o
AR fs/hostfs/built-in.a
CC fs/lockd/mon.o
CC lib/seq_buf.o
AR drivers/gpu/drm/gud/built-in.a
CC lib/siphash.o
CC drivers/ata/pata_sch.o
CC drivers/rtc/proc.o
CC [M] net/netfilter/xt_LOG.o
CC kernel/trace/rpm-traces.o
CC drivers/input/mouse/byd.o
CC drivers/gpu/drm/i915/vlv_suspend.o
CC net/wireless/ethtool.o
CC net/sunrpc/auth_tls.o
CC drivers/usb/storage/usb.o
CC net/ipv4/tcp_offload.o
CC net/mac80211/michael.o
CC drivers/acpi/acpica/nspredef.o
CC lib/string.o
CC fs/debugfs/inode.o
CC fs/lockd/trace.o
CC arch/x86/kernel/e820.o
CC mm/page_vma_mapped.o
CC net/ipv4/tcp_plb.o
CC drivers/net/phy/mdio_bus.o
CC drivers/gpu/drm/i915/soc/intel_dram.o
CC drivers/i2c/i2c-smbus.o
CC net/wireless/mesh.o
CC drivers/input/mouse/logips2pp.o
CC drivers/usb/core/config.o
CC drivers/rtc/sysfs.o
CC drivers/acpi/acpica/nsprepkg.o
CC fs/9p/vfs_dir.o
CC drivers/gpu/drm/i915/soc/intel_gmch.o
CC lib/timerqueue.o
CC net/core/netpoll.o
CC [M] net/netfilter/xt_MASQUERADE.o
CC fs/nfs/symlink.o
CC drivers/ata/pata_mpiix.o
CC fs/ext4/inline.o
CC drivers/acpi/acpica/nsrepair.o
CC lib/union_find.o
CC fs/lockd/xdr.o
CC lib/vsprintf.o
CC drivers/usb/host/ohci-hcd.o
CC kernel/trace/trace_dynevent.o
CC drivers/usb/early/ehci-dbgp.o
CC drivers/acpi/acpica/nsrepair2.o
CC net/ipv6/datagram.o
CC drivers/input/mouse/lifebook.o
CC mm/pagewalk.o
CC drivers/pcmcia/pcmcia_cis.o
CC drivers/acpi/acpica/nssearch.o
AR drivers/net/ethernet/dec/tulip/built-in.a
AR drivers/net/ethernet/dec/built-in.a
CC drivers/usb/storage/initializers.o
CC [M] net/netfilter/xt_addrtype.o
CC drivers/rtc/rtc-mc146818-lib.o
CC drivers/net/virtio_net.o
CC net/ipv6/ip6_flowlabel.o
CC net/ipv6/inet6_connection_sock.o
CC fs/nfs/unlink.o
CC fs/debugfs/file.o
CC net/sunrpc/auth_unix.o
AR drivers/i2c/built-in.a
CC drivers/ata/ata_generic.o
CC drivers/pcmcia/rsrc_mgr.o
CC fs/9p/vfs_dentry.o
CC drivers/scsi/virtio_scsi.o
CC drivers/scsi/sd.o
CC fs/tracefs/inode.o
CC arch/x86/kernel/pci-dma.o
CC net/ipv4/datagram.o
CC drivers/usb/core/file.o
CC drivers/acpi/acpica/nsutils.o
CC kernel/trace/trace_probe.o
CC net/sunrpc/svc.o
CC drivers/gpu/drm/i915/soc/intel_rom.o
AR drivers/i3c/built-in.a
AR drivers/media/i2c/built-in.a
AR drivers/media/tuners/built-in.a
AR drivers/media/rc/keymaps/built-in.a
CC drivers/net/phy/mdio_device.o
AR drivers/media/rc/built-in.a
CC drivers/input/mouse/trackpoint.o
AR drivers/media/common/b2c2/built-in.a
AR drivers/media/common/saa7146/built-in.a
AR drivers/media/common/siano/built-in.a
CC drivers/input/mouse/cypress_ps2.o
AR drivers/media/common/v4l2-tpg/built-in.a
AR drivers/media/common/videobuf2/built-in.a
AR drivers/media/common/built-in.a
AR drivers/pps/clients/built-in.a
CC drivers/pps/pps.o
CC drivers/ptp/ptp_clock.o
AR drivers/media/platform/allegro-dvt/built-in.a
CC drivers/rtc/rtc-cmos.o
CC drivers/usb/storage/sierra_ms.o
AR drivers/media/platform/amlogic/meson-ge2d/built-in.a
AR drivers/media/platform/amlogic/built-in.a
CC drivers/power/supply/power_supply_core.o
AR drivers/media/platform/amphion/built-in.a
AR drivers/media/platform/aspeed/built-in.a
CC drivers/ptp/ptp_chardev.o
AR drivers/media/platform/atmel/built-in.a
AR drivers/media/platform/broadcom/built-in.a
AR drivers/media/platform/cadence/built-in.a
AR drivers/usb/early/built-in.a
CC drivers/hwmon/hwmon.o
CC drivers/usb/storage/option_ms.o
AR drivers/media/platform/chips-media/coda/built-in.a
AR drivers/media/platform/chips-media/wave5/built-in.a
AR drivers/media/platform/chips-media/built-in.a
AR drivers/media/platform/imagination/built-in.a
AR drivers/thermal/broadcom/built-in.a
AR drivers/media/platform/intel/built-in.a
AR drivers/watchdog/built-in.a
CC fs/lockd/netlink.o
CC lib/win_minmax.o
AR drivers/thermal/renesas/built-in.a
CC fs/9p/v9fs.o
CC lib/xarray.o
AR drivers/media/platform/marvell/built-in.a
AR drivers/thermal/samsung/built-in.a
CC drivers/acpi/acpica/nswalk.o
AR drivers/media/platform/mediatek/jpeg/built-in.a
CC drivers/thermal/intel/intel_tcc.o
AR drivers/media/platform/mediatek/mdp/built-in.a
CC mm/pgtable-generic.o
AR drivers/ata/built-in.a
AR drivers/media/platform/mediatek/vcodec/common/built-in.a
CC drivers/thermal/intel/therm_throt.o
CC drivers/usb/host/ohci-pci.o
AR drivers/media/platform/mediatek/vcodec/encoder/built-in.a
CC drivers/pcmcia/rsrc_nonstatic.o
AR drivers/media/platform/mediatek/vcodec/decoder/built-in.a
AR drivers/media/platform/mediatek/vcodec/built-in.a
AR drivers/media/platform/mediatek/vpu/built-in.a
AR drivers/media/platform/mediatek/mdp3/built-in.a
CC drivers/usb/core/buffer.o
AR drivers/media/platform/mediatek/built-in.a
AR drivers/media/platform/microchip/built-in.a
AR drivers/media/platform/nuvoton/built-in.a
AR drivers/media/platform/nvidia/tegra-vde/built-in.a
AR drivers/media/platform/nvidia/built-in.a
CC arch/x86/kernel/quirks.o
AR drivers/media/platform/nxp/dw100/built-in.a
AR drivers/media/platform/nxp/imx-jpeg/built-in.a
CC net/core/fib_rules.o
AR drivers/media/platform/nxp/imx8-isi/built-in.a
AR drivers/media/platform/nxp/built-in.a
AR drivers/media/platform/qcom/camss/built-in.a
CC fs/tracefs/event_inode.o
AR drivers/media/platform/qcom/iris/built-in.a
CC drivers/ptp/ptp_sysfs.o
AR drivers/media/platform/qcom/venus/built-in.a
CC fs/ext4/inode.o
AR drivers/media/platform/qcom/built-in.a
AR drivers/net/ethernet/dlink/built-in.a
CC fs/ext4/ioctl.o
AR drivers/media/platform/raspberrypi/pisp_be/built-in.a
CC drivers/md/md.o
CC net/mac80211/tkip.o
CC drivers/cpufreq/cpufreq.o
AR drivers/media/platform/raspberrypi/rp1-cfe/built-in.a
AR drivers/media/platform/raspberrypi/built-in.a
CC drivers/cpuidle/governors/menu.o
AR fs/debugfs/built-in.a
CC drivers/cpuidle/governors/haltpoll.o
CC drivers/pps/kapi.o
AR drivers/media/platform/renesas/rcar-vin/built-in.a
CC drivers/usb/host/uhci-hcd.o
AR drivers/media/platform/renesas/rzg2l-cru/built-in.a
CC fs/9p/fid.o
CC drivers/acpi/acpica/nsxfeval.o
AR drivers/media/platform/renesas/vsp1/built-in.a
AR drivers/media/platform/renesas/built-in.a
CC drivers/md/md-bitmap.o
AR drivers/media/platform/rockchip/rga/built-in.a
CC drivers/input/mouse/psmouse-smbus.o
AR drivers/media/platform/rockchip/rkisp1/built-in.a
AR net/netfilter/built-in.a
AR drivers/media/platform/rockchip/built-in.a
CC drivers/gpu/drm/i915/i915_memcpy.o
CC drivers/usb/host/xhci.o
AR drivers/media/platform/samsung/exynos-gsc/built-in.a
AR drivers/media/platform/samsung/exynos4-is/built-in.a
AR drivers/media/platform/samsung/s3c-camif/built-in.a
CC net/ipv4/raw.o
AR drivers/media/platform/samsung/s5p-g2d/built-in.a
CC drivers/net/net_failover.o
CC net/ipv6/udp_offload.o
CC drivers/net/phy/swphy.o
AR drivers/media/platform/samsung/s5p-jpeg/built-in.a
AR drivers/media/platform/samsung/s5p-mfc/built-in.a
AR drivers/media/platform/samsung/built-in.a
CC drivers/usb/storage/usual-tables.o
AR drivers/media/platform/st/sti/bdisp/built-in.a
CC drivers/gpu/drm/i915/i915_mm.o
AR drivers/media/platform/st/sti/c8sectpfe/built-in.a
AR drivers/media/platform/st/sti/delta/built-in.a
AR drivers/media/platform/st/sti/hva/built-in.a
CC mm/rmap.o
AR drivers/media/platform/st/stm32/built-in.a
AR drivers/media/platform/st/built-in.a
AR drivers/media/platform/sunxi/sun4i-csi/built-in.a
AR drivers/media/platform/sunxi/sun6i-csi/built-in.a
CC drivers/power/supply/power_supply_sysfs.o
CC fs/nfs/write.o
AR drivers/media/platform/sunxi/sun6i-mipi-csi2/built-in.a
CC fs/lockd/clnt4xdr.o
AR drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/built-in.a
CC drivers/scsi/sr.o
AR drivers/media/platform/sunxi/sun8i-di/built-in.a
AR drivers/rtc/built-in.a
AR drivers/media/pci/ttpci/built-in.a
AR drivers/media/platform/sunxi/sun8i-rotate/built-in.a
AR drivers/media/platform/sunxi/built-in.a
AR drivers/media/pci/b2c2/built-in.a
AR drivers/media/usb/b2c2/built-in.a
CC drivers/usb/core/sysfs.o
AR drivers/media/usb/dvb-usb/built-in.a
CC drivers/acpi/processor_core.o
AR drivers/media/pci/pluto2/built-in.a
AR drivers/media/usb/dvb-usb-v2/built-in.a
AR drivers/media/mmc/siano/built-in.a
AR drivers/media/pci/dm1105/built-in.a
AR drivers/media/platform/synopsys/hdmirx/built-in.a
AR drivers/media/mmc/built-in.a
AR drivers/media/platform/synopsys/built-in.a
AR drivers/media/usb/s2255/built-in.a
AR drivers/media/pci/pt1/built-in.a
AR drivers/media/pci/pt3/built-in.a
AR drivers/media/usb/siano/built-in.a
CC drivers/pcmcia/yenta_socket.o
AR drivers/media/platform/ti/am437x/built-in.a
AR drivers/media/pci/mantis/built-in.a
AR drivers/media/usb/ttusb-budget/built-in.a
AR drivers/media/platform/ti/cal/built-in.a
AR drivers/media/pci/ngene/built-in.a
CC drivers/power/supply/power_supply_leds.o
AR drivers/media/usb/ttusb-dec/built-in.a
AR drivers/media/pci/ddbridge/built-in.a
AR drivers/media/platform/ti/vpe/built-in.a
AR drivers/media/usb/built-in.a
CC drivers/acpi/acpica/nsxfname.o
AR drivers/media/platform/ti/davinci/built-in.a
AR drivers/media/pci/saa7146/built-in.a
AR drivers/input/misc/built-in.a
CC drivers/md/md-autodetect.o
CC fs/9p/xattr.o
AR drivers/media/platform/ti/j721e-csi2rx/built-in.a
AR drivers/media/pci/smipcie/built-in.a
AR drivers/media/platform/ti/omap/built-in.a
AR drivers/media/pci/netup_unidvb/built-in.a
CC drivers/cpufreq/freq_table.o
AR drivers/media/platform/ti/omap3isp/built-in.a
AR drivers/media/platform/ti/built-in.a
AR drivers/media/pci/intel/ipu3/built-in.a
CC arch/x86/kernel/kdebugfs.o
AR drivers/media/pci/intel/ivsc/built-in.a
AR drivers/media/pci/intel/built-in.a
AR drivers/media/platform/verisilicon/built-in.a
AR drivers/media/pci/built-in.a
AR drivers/media/platform/via/built-in.a
AR drivers/media/platform/xilinx/built-in.a
CC drivers/cpufreq/cpufreq_performance.o
AR drivers/media/platform/built-in.a
CC drivers/usb/host/xhci-mem.o
CC drivers/pps/sysfs.o
AR drivers/media/firewire/built-in.a
CC kernel/trace/trace_uprobe.o
AR drivers/media/spi/built-in.a
AR drivers/media/test-drivers/built-in.a
AR drivers/media/built-in.a
CC kernel/trace/rethook.o
CC [M] drivers/thermal/intel/x86_pkg_temp_thermal.o
AR drivers/usb/storage/built-in.a
CC kernel/ptrace.o
CC drivers/ptp/ptp_vclock.o
CC drivers/scsi/sr_ioctl.o
AR fs/tracefs/built-in.a
CC drivers/acpi/processor_pdc.o
AR drivers/input/mouse/built-in.a
AR drivers/hwmon/built-in.a
CC drivers/acpi/acpica/nsxfobj.o
CC drivers/input/input.o
CC net/core/net-traces.o
AR drivers/cpuidle/governors/built-in.a
CC drivers/cpuidle/cpuidle.o
CC drivers/power/supply/power_supply_hwmon.o
CC drivers/md/dm.o
CC drivers/net/phy/fixed_phy.o
CC net/sunrpc/svcsock.o
AR drivers/gpu/drm/solomon/built-in.a
CC arch/x86/kernel/alternative.o
AR drivers/pps/built-in.a
CC drivers/scsi/sr_vendor.o
CC drivers/input/input-compat.o
AR drivers/net/ethernet/emulex/built-in.a
CC net/core/selftests.o
CC lib/lockref.o
CC lib/bcd.o
AR fs/9p/built-in.a
CC drivers/gpu/drm/i915/i915_sw_fence.o
CC [M] fs/efivarfs/inode.o
CC kernel/user.o
CC drivers/acpi/acpica/psargs.o
CC drivers/acpi/acpica/psloop.o
CC [M] fs/efivarfs/file.o
CC mm/vmalloc.o
AR drivers/mmc/built-in.a
CC net/ipv6/seg6.o
CC fs/lockd/xdr4.o
CC drivers/usb/core/endpoint.o
CC net/wireless/ap.o
CC arch/x86/kernel/i8253.o
CC lib/sort.o
CC net/core/ptp_classifier.o
AR drivers/power/supply/built-in.a
AR drivers/thermal/intel/built-in.a
AR drivers/power/built-in.a
AR drivers/thermal/st/built-in.a
CC fs/ext4/mballoc.o
AR drivers/thermal/qcom/built-in.a
CC drivers/usb/core/devio.o
AR drivers/thermal/tegra/built-in.a
CC net/sunrpc/svcauth.o
AR drivers/thermal/mediatek/built-in.a
CC drivers/thermal/thermal_core.o
CC drivers/ptp/ptp_kvm_x86.o
CC fs/nfs/namespace.o
CC fs/open.o
CC drivers/cpufreq/cpufreq_userspace.o
CC lib/parser.o
CC drivers/acpi/acpica/psobject.o
CC drivers/cpufreq/cpufreq_ondemand.o
AR drivers/pcmcia/built-in.a
CC drivers/input/input-mt.o
CC net/ipv4/udp.o
CC drivers/scsi/sg.o
CC lib/debug_locks.o
CC drivers/thermal/thermal_sysfs.o
CC drivers/ptp/ptp_kvm_common.o
CC drivers/cpuidle/driver.o
CC drivers/gpu/drm/i915/i915_sw_fence_work.o
CC net/mac80211/aes_cmac.o
CC lib/random32.o
AR drivers/ufs/built-in.a
CC mm/vma.o
CC [M] fs/efivarfs/super.o
AR drivers/net/phy/built-in.a
CC drivers/thermal/thermal_trip.o
CC net/ipv4/udplite.o
CC drivers/gpu/drm/i915/i915_syncmap.o
CC drivers/cpufreq/cpufreq_governor.o
CC drivers/input/input-poller.o
CC net/core/netprio_cgroup.o
CC net/ipv6/fib6_notifier.o
CC drivers/acpi/acpica/psopcode.o
CC net/wireless/trace.o
CC arch/x86/kernel/hw_breakpoint.o
CC lib/bust_spinlocks.o
CC drivers/usb/host/xhci-ext-caps.o
CC drivers/cpuidle/governor.o
CC drivers/cpuidle/sysfs.o
CC drivers/md/dm-table.o
CC net/core/netclassid_cgroup.o
CC drivers/acpi/ec.o
AR kernel/trace/built-in.a
CC drivers/gpu/drm/i915/i915_user_extensions.o
CC kernel/signal.o
AR drivers/firmware/arm_ffa/built-in.a
CC drivers/usb/core/notify.o
CC fs/ext4/migrate.o
CC drivers/acpi/acpica/psopinfo.o
AR drivers/firmware/arm_scmi/built-in.a
AR drivers/firmware/broadcom/built-in.a
CC net/ipv4/udp_offload.o
AR drivers/ptp/built-in.a
CC fs/lockd/svc4proc.o
AR drivers/firmware/cirrus/test/built-in.a
AR drivers/firmware/meson/built-in.a
CC drivers/usb/core/generic.o
AR drivers/firmware/cirrus/built-in.a
CC drivers/usb/core/quirks.o
AR drivers/firmware/microchip/built-in.a
AR drivers/firmware/imx/built-in.a
CC fs/lockd/procfs.o
CC drivers/input/ff-core.o
CC drivers/firmware/efi/libstub/efi-stub-helper.o
CC drivers/input/touchscreen.o
CC drivers/cpufreq/cpufreq_governor_attr_set.o
CC net/ipv4/arp.o
CC fs/nfs/mount_clnt.o
CC lib/kasprintf.o
CC lib/bitmap.o
CC drivers/gpu/drm/i915/i915_debugfs.o
CC net/mac80211/aes_gmac.o
CC [M] fs/efivarfs/vars.o
CC drivers/acpi/acpica/psparse.o
CC lib/scatterlist.o
CC net/ipv4/icmp.o
CC drivers/usb/host/xhci-ring.o
CC drivers/cpuidle/poll_state.o
CC drivers/usb/core/devices.o
CC drivers/thermal/thermal_helpers.o
CC arch/x86/kernel/tsc.o
CC net/ipv6/rpl.o
CC drivers/firmware/efi/efi-bgrt.o
CC drivers/usb/host/xhci-hub.o
CC [M] drivers/gpu/drm/scheduler/sched_main.o
CC drivers/acpi/dock.o
CC fs/read_write.o
CC drivers/cpuidle/cpuidle-haltpoll.o
CC drivers/usb/host/xhci-dbg.o
HOSTCC drivers/gpu/drm/xe/xe_gen_wa_oob
CC drivers/cpufreq/acpi-cpufreq.o
CC drivers/input/ff-memless.o
CC kernel/sys.o
CC drivers/acpi/acpica/psscope.o
CC net/ipv4/devinet.o
CC drivers/scsi/scsi_sysfs.o
CC net/ipv6/ioam6.o
CC drivers/usb/host/xhci-trace.o
GEN xe_wa_oob.c xe_wa_oob.h
CC [M] drivers/gpu/drm/xe/xe_bb.o
CC [M] drivers/gpu/drm/xe/xe_bo.o
CC net/sunrpc/svcauth_unix.o
CC drivers/firmware/efi/libstub/gop.o
CC drivers/thermal/thermal_thresholds.o
CC mm/process_vm_access.o
CC drivers/input/sparse-keymap.o
LD [M] fs/efivarfs/efivarfs.o
CC drivers/thermal/thermal_netlink.o
CC net/ipv6/sysctl_net_ipv6.o
AR fs/lockd/built-in.a
CC drivers/gpu/drm/i915/i915_debugfs_params.o
CC drivers/md/dm-target.o
AR drivers/cpuidle/built-in.a
CC drivers/acpi/acpica/pstree.o
CC drivers/gpu/drm/drm_atomic.o
CC net/wireless/ocb.o
CC net/core/dst_cache.o
CC drivers/usb/core/phy.o
CC drivers/firmware/efi/efi.o
CC drivers/cpufreq/amd-pstate.o
CC net/mac80211/fils_aead.o
CC fs/nfs/nfstrace.o
CC kernel/umh.o
AR drivers/net/ethernet/engleder/built-in.a
CC [M] drivers/gpu/drm/xe/xe_bo_evict.o
CC drivers/gpu/drm/i915/i915_pmu.o
AR drivers/firmware/psci/built-in.a
CC lib/list_sort.o
CC drivers/acpi/pci_root.o
CC drivers/acpi/acpica/psutils.o
CC [M] drivers/gpu/drm/scheduler/sched_fence.o
CC fs/ext4/mmp.o
CC arch/x86/kernel/tsc_msr.o
CC lib/uuid.o
CC drivers/input/vivaldi-fmap.o
CC drivers/firmware/efi/libstub/secureboot.o
CC mm/page_alloc.o
CC lib/iov_iter.o
CC arch/x86/kernel/io_delay.o
CC [M] drivers/gpu/drm/xe/xe_devcoredump.o
CC drivers/md/dm-linear.o
AR drivers/crypto/stm32/built-in.a
AR drivers/crypto/inside-secure/eip93/built-in.a
AR drivers/crypto/inside-secure/built-in.a
AR drivers/crypto/xilinx/built-in.a
CC drivers/acpi/acpica/pswalk.o
AR drivers/crypto/hisilicon/built-in.a
AR drivers/crypto/intel/keembay/built-in.a
CC drivers/usb/core/port.o
AR drivers/crypto/intel/ixp4xx/built-in.a
CC drivers/clocksource/acpi_pm.o
AR drivers/crypto/intel/built-in.a
CC drivers/hid/usbhid/hid-core.o
AR drivers/crypto/starfive/built-in.a
CC drivers/clocksource/i8253.o
AR drivers/scsi/built-in.a
CC drivers/hid/hid-core.o
AR drivers/crypto/built-in.a
CC drivers/acpi/pci_link.o
CC [M] drivers/gpu/drm/scheduler/sched_entity.o
CC net/ipv6/xfrm6_policy.o
CC drivers/input/input-leds.o
CC lib/clz_ctz.o
CC arch/x86/kernel/rtc.o
CC drivers/gpu/drm/drm_atomic_uapi.o
CC net/mac80211/cfg.o
CC [M] drivers/gpu/drm/xe/xe_device.o
CC drivers/firmware/efi/libstub/tpm.o
AR drivers/net/ethernet/broadcom/built-in.a
AR drivers/net/ethernet/ezchip/built-in.a
AR drivers/net/ethernet/fujitsu/built-in.a
AR drivers/net/ethernet/fungible/built-in.a
CC drivers/cpufreq/amd-pstate-trace.o
AR drivers/net/ethernet/google/built-in.a
CC net/ipv6/xfrm6_state.o
CC mm/page_frag_cache.o
AR drivers/net/ethernet/hisilicon/built-in.a
CC drivers/acpi/acpica/psxface.o
AR drivers/net/ethernet/huawei/built-in.a
CC drivers/acpi/acpica/rsaddr.o
CC drivers/net/ethernet/intel/e1000/e1000_main.o
CC drivers/acpi/acpica/rscalc.o
CC drivers/thermal/thermal_hwmon.o
CC fs/ext4/move_extent.o
AR drivers/net/ethernet/i825xx/built-in.a
CC kernel/workqueue.o
CC net/core/gro_cells.o
CC drivers/net/ethernet/intel/e1000e/82571.o
CC drivers/hid/usbhid/hiddev.o
CC kernel/pid.o
CC drivers/gpu/drm/i915/gt/gen2_engine_cs.o
AR drivers/net/ethernet/microsoft/built-in.a
CC fs/file_table.o
CC fs/super.o
CC fs/ext4/namei.o
CC net/core/failover.o
CC mm/init-mm.o
CC drivers/input/evdev.o
AR drivers/clocksource/built-in.a
CC fs/nfs/export.o
AR drivers/net/ethernet/litex/built-in.a
CC net/ipv6/xfrm6_input.o
CC drivers/cpufreq/intel_pstate.o
CC drivers/acpi/pci_irq.o
CC arch/x86/kernel/resource.o
LD [M] drivers/gpu/drm/scheduler/gpu-sched.o
CC drivers/acpi/acpica/rscreate.o
CC fs/char_dev.o
CC drivers/firmware/efi/vars.o
CC drivers/hid/hid-input.o
CC drivers/thermal/gov_step_wise.o
CC net/sunrpc/addr.o
CC net/mac80211/ethtool.o
CC drivers/usb/core/hcd-pci.o
AS arch/x86/kernel/irqflags.o
CC drivers/md/dm-stripe.o
CC net/ipv4/af_inet.o
CC arch/x86/kernel/static_call.o
CC drivers/firmware/efi/libstub/file.o
CC drivers/usb/core/usb-acpi.o
CC drivers/usb/host/xhci-debugfs.o
CC net/sunrpc/rpcb_clnt.o
AR drivers/net/ethernet/marvell/octeon_ep/built-in.a
AR drivers/net/ethernet/marvell/octeon_ep_vf/built-in.a
AR drivers/net/ethernet/marvell/octeontx2/built-in.a
AR drivers/net/ethernet/marvell/prestera/built-in.a
CC drivers/firmware/efi/reboot.o
CC drivers/net/ethernet/marvell/sky2.o
CC drivers/usb/host/xhci-pci.o
CC drivers/acpi/acpica/rsdumpinfo.o
CC net/ipv6/xfrm6_output.o
CC net/wireless/pmsr.o
CC drivers/net/ethernet/intel/e100.o
CC mm/memblock.o
CC fs/stat.o
AR drivers/thermal/built-in.a
CC drivers/gpu/drm/i915/gt/gen6_engine_cs.o
CC kernel/task_work.o
CC arch/x86/kernel/process.o
CC fs/nfs/sysfs.o
CC drivers/firmware/efi/memattr.o
CC drivers/net/ethernet/intel/e1000/e1000_hw.o
GEN net/wireless/shipped-certs.c
CC drivers/gpu/drm/i915/gt/gen6_ppgtt.o
CC drivers/gpu/drm/drm_auth.o
CC kernel/extable.o
CC drivers/acpi/acpica/rsinfo.o
CC drivers/hid/usbhid/hid-pidff.o
CC [M] drivers/gpu/drm/xe/xe_device_sysfs.o
CC net/mac80211/rx.o
AR net/core/built-in.a
CC drivers/net/ethernet/intel/e1000e/ich8lan.o
AR drivers/input/built-in.a
CC drivers/firmware/efi/libstub/mem.o
CC drivers/firmware/efi/libstub/random.o
CC fs/exec.o
CC drivers/hid/hid-quirks.o
AR drivers/usb/core/built-in.a
AR drivers/net/ethernet/mellanox/built-in.a
CC drivers/md/dm-ioctl.o
AR drivers/firmware/qcom/built-in.a
CC drivers/net/ethernet/intel/e1000/e1000_ethtool.o
CC net/ipv6/xfrm6_protocol.o
CC drivers/net/ethernet/intel/e1000e/80003es2lan.o
CC drivers/net/ethernet/intel/e1000e/mac.o
CC lib/bsearch.o
CC drivers/acpi/acpica/rsio.o
CC arch/x86/kernel/ptrace.o
CC drivers/acpi/acpi_apd.o
CC net/ipv6/netfilter.o
CC mm/slub.o
CC net/sunrpc/timer.o
CC drivers/gpu/drm/drm_blend.o
CC drivers/net/ethernet/intel/e1000e/manage.o
CC drivers/acpi/acpica/rsirq.o
CC [M] drivers/gpu/drm/xe/xe_dma_buf.o
CC drivers/firmware/efi/libstub/randomalloc.o
CC net/ipv4/igmp.o
CC drivers/hid/hid-debug.o
CC fs/pipe.o
AR drivers/usb/host/built-in.a
AR drivers/usb/built-in.a
CC net/mac80211/spectmgmt.o
CC lib/find_bit.o
CC net/sunrpc/xdr.o
AR drivers/platform/x86/amd/built-in.a
CC [M] drivers/gpu/drm/xe/xe_drm_client.o
AR drivers/platform/x86/intel/built-in.a
CC drivers/platform/x86/wmi.o
CC drivers/platform/x86/wmi-bmof.o
CC drivers/firmware/efi/libstub/pci.o
CC drivers/acpi/acpica/rslist.o
CC net/sunrpc/sunrpc_syms.o
CC drivers/gpu/drm/i915/gt/gen7_renderclear.o
AR drivers/hid/usbhid/built-in.a
CC fs/ext4/page-io.o
CC arch/x86/kernel/tls.o
AR drivers/cpufreq/built-in.a
CC lib/llist.o
CC net/wireless/shipped-certs.o
CC net/ipv4/fib_frontend.o
CC drivers/net/ethernet/intel/e1000e/nvm.o
CC drivers/net/ethernet/intel/e1000/e1000_param.o
CC lib/lwq.o
CC lib/memweight.o
CC drivers/firmware/efi/tpm.o
CC fs/ext4/readpage.o
CC drivers/acpi/acpica/rsmemory.o
CC drivers/acpi/acpica/rsmisc.o
CC drivers/firmware/efi/libstub/skip_spaces.o
CC drivers/acpi/acpica/rsserial.o
CC net/ipv6/proc.o
CC drivers/platform/x86/eeepc-laptop.o
CC drivers/platform/x86/p2sb.o
CC fs/ext4/resize.o
CC net/ipv4/fib_semantics.o
CC lib/kfifo.o
CC arch/x86/kernel/step.o
CC fs/nfs/fs_context.o
AR drivers/net/ethernet/meta/built-in.a
CC kernel/params.o
CC drivers/mailbox/mailbox.o
CC fs/namei.o
CC drivers/md/dm-io.o
CC drivers/firmware/efi/libstub/lib-cmdline.o
CC net/ipv4/fib_trie.o
CC fs/fcntl.o
CC drivers/hid/hidraw.o
CC net/sunrpc/cache.o
CC drivers/mailbox/pcc.o
CC drivers/firmware/efi/libstub/lib-ctype.o
CC mm/madvise.o
CC mm/page_io.o
AR drivers/platform/surface/built-in.a
CC drivers/firmware/efi/libstub/alignedmem.o
CC drivers/gpu/drm/drm_bridge.o
CC drivers/acpi/acpica/rsutils.o
CC drivers/md/dm-kcopyd.o
CC lib/percpu-refcount.o
CC drivers/hid/hid-generic.o
AR drivers/net/ethernet/micrel/built-in.a
CC net/ipv4/fib_notifier.o
CC drivers/acpi/acpi_platform.o
CC net/ipv6/syncookies.o
CC arch/x86/kernel/i8237.o
CC drivers/hid/hid-a4tech.o
CC drivers/gpu/drm/i915/gt/gen8_engine_cs.o
CC [M] drivers/gpu/drm/xe/xe_eu_stall.o
CC drivers/gpu/drm/i915/gt/gen8_ppgtt.o
CC mm/swap_state.o
CC fs/ioctl.o
CC drivers/net/ethernet/intel/e1000e/phy.o
CC net/ipv6/calipso.o
CC drivers/md/dm-sysfs.o
CC drivers/gpu/drm/i915/gt/intel_breadcrumbs.o
CC mm/swapfile.o
CC net/mac80211/tx.o
CC drivers/acpi/acpica/rsxface.o
CC fs/readdir.o
CC arch/x86/kernel/stacktrace.o
CC net/ipv4/inet_fragment.o
AR drivers/mailbox/built-in.a
CC drivers/firmware/efi/libstub/relocate.o
AR drivers/net/ethernet/marvell/built-in.a
CC drivers/firmware/efi/memmap.o
AR drivers/platform/x86/built-in.a
CC drivers/hid/hid-apple.o
AR drivers/platform/built-in.a
CC drivers/md/dm-stats.o
AR drivers/net/ethernet/intel/e1000/built-in.a
CC net/sunrpc/rpc_pipe.o
CC arch/x86/kernel/reboot.o
CC drivers/acpi/acpica/tbdata.o
CC lib/rhashtable.o
CC kernel/kthread.o
AR drivers/firmware/samsung/built-in.a
CC kernel/sys_ni.o
CC mm/dmapool.o
CC fs/ext4/super.o
AR drivers/net/ethernet/microchip/built-in.a
CC drivers/gpu/drm/drm_cache.o
CC drivers/firmware/efi/libstub/printk.o
CC net/ipv4/ping.o
CC drivers/firmware/efi/capsule.o
CC drivers/firmware/efi/esrt.o
CC net/sunrpc/sysfs.o
CC fs/nfs/nfsroot.o
AR drivers/perf/built-in.a
CC drivers/net/ethernet/intel/e1000e/param.o
CC drivers/firmware/efi/libstub/vsprintf.o
CC arch/x86/kernel/msr.o
CC lib/base64.o
CC fs/ext4/symlink.o
CC drivers/firmware/efi/runtime-wrappers.o
CC drivers/acpi/acpica/tbfadt.o
CC drivers/firmware/efi/capsule-loader.o
CC drivers/acpi/acpi_pnp.o
CC drivers/md/dm-rq.o
CC net/sunrpc/svc_xprt.o
CC arch/x86/kernel/cpuid.o
CC drivers/net/ethernet/intel/e1000e/ethtool.o
AR drivers/firmware/smccc/built-in.a
CC drivers/hid/hid-belkin.o
CC drivers/acpi/power.o
CC net/ipv6/ah6.o
CC net/ipv4/ip_tunnel_core.o
CC net/sunrpc/xprtmultipath.o
CC drivers/firmware/efi/earlycon.o
CC fs/ext4/sysfs.o
CC [M] drivers/gpu/drm/xe/xe_exec.o
AR drivers/firmware/tegra/built-in.a
CC net/sunrpc/stats.o
AR drivers/hwtracing/intel_th/built-in.a
CC drivers/firmware/efi/libstub/x86-stub.o
CC fs/nfs/sysctl.o
CC fs/ext4/xattr.o
CC drivers/hid/hid-cherry.o
AR drivers/net/ethernet/mscc/built-in.a
CC drivers/net/ethernet/intel/e1000e/netdev.o
CC drivers/acpi/acpica/tbfind.o
AR drivers/firmware/xilinx/built-in.a
CC arch/x86/kernel/early-quirks.o
CC net/ipv6/esp6.o
CC fs/select.o
CC drivers/gpu/drm/i915/gt/intel_context.o
CC drivers/gpu/drm/i915/gt/intel_context_sseu.o
CC lib/once.o
CC drivers/md/dm-io-rewind.o
AR drivers/android/built-in.a
CC drivers/hid/hid-chicony.o
CC net/sunrpc/sysctl.o
CC fs/dcache.o
CC drivers/acpi/acpica/tbinstal.o
CC mm/hugetlb.o
CC mm/mmu_notifier.o
CC drivers/acpi/event.o
CC drivers/gpu/drm/drm_color_mgmt.o
CC net/ipv6/sit.o
CC [M] drivers/gpu/drm/xe/xe_exec_queue.o
CC drivers/firmware/efi/libstub/smbios.o
CC arch/x86/kernel/smp.o
CC kernel/nsproxy.o
CC kernel/notifier.o
CC arch/x86/kernel/smpboot.o
CC arch/x86/kernel/tsc_sync.o
CC drivers/md/dm-builtin.o
CC drivers/hid/hid-cypress.o
CC net/ipv6/addrconf_core.o
CC net/ipv4/gre_offload.o
CC lib/refcount.o
CC fs/nfs/nfs3super.o
CC fs/nfs/nfs3client.o
CC drivers/acpi/acpica/tbprint.o
CC drivers/firmware/dmi_scan.o
AR drivers/net/ethernet/myricom/built-in.a
CC fs/inode.o
AR drivers/net/ethernet/natsemi/built-in.a
CC lib/rcuref.o
CC drivers/gpu/drm/drm_connector.o
CC [M] drivers/gpu/drm/xe/xe_execlist.o
AR drivers/nvmem/layouts/built-in.a
CC drivers/nvmem/core.o
CC net/ipv6/exthdrs_core.o
CC net/mac80211/key.o
CC fs/nfs/nfs3proc.o
CC lib/usercopy.o
CC fs/attr.o
CC fs/ext4/xattr_hurd.o
STUBCPY drivers/firmware/efi/libstub/alignedmem.stub.o
CC net/ipv6/ip6_checksum.o
CC fs/nfs/nfs3xdr.o
STUBCPY drivers/firmware/efi/libstub/efi-stub-helper.stub.o
STUBCPY drivers/firmware/efi/libstub/file.stub.o
STUBCPY drivers/firmware/efi/libstub/gop.stub.o
CC drivers/acpi/acpica/tbutils.o
STUBCPY drivers/firmware/efi/libstub/lib-cmdline.stub.o
STUBCPY drivers/firmware/efi/libstub/lib-ctype.stub.o
STUBCPY drivers/firmware/efi/libstub/mem.stub.o
STUBCPY drivers/firmware/efi/libstub/pci.stub.o
CC mm/migrate.o
STUBCPY drivers/firmware/efi/libstub/printk.stub.o
STUBCPY drivers/firmware/efi/libstub/random.stub.o
CC net/mac80211/util.o
STUBCPY drivers/firmware/efi/libstub/randomalloc.stub.o
AR drivers/net/ethernet/neterion/built-in.a
STUBCPY drivers/firmware/efi/libstub/relocate.stub.o
CC drivers/gpu/drm/drm_crtc.o
STUBCPY drivers/firmware/efi/libstub/secureboot.stub.o
CC drivers/firmware/dmi-id.o
STUBCPY drivers/firmware/efi/libstub/skip_spaces.stub.o
AR drivers/net/ethernet/netronome/built-in.a
CC drivers/firmware/memmap.o
STUBCPY drivers/firmware/efi/libstub/smbios.stub.o
STUBCPY drivers/firmware/efi/libstub/tpm.stub.o
STUBCPY drivers/firmware/efi/libstub/vsprintf.stub.o
STUBCPY drivers/firmware/efi/libstub/x86-stub.stub.o
AR drivers/firmware/efi/libstub/lib.a
CC lib/errseq.o
CC drivers/acpi/acpica/tbxface.o
CC mm/page_counter.o
CC drivers/md/dm-raid1.o
CC drivers/hid/hid-ezkey.o
AR drivers/firmware/efi/built-in.a
CC arch/x86/kernel/setup_percpu.o
CC kernel/ksysfs.o
CC lib/bucket_locks.o
CC mm/hugetlb_cgroup.o
CC drivers/gpu/drm/i915/gt/intel_engine_cs.o
CC kernel/cred.o
CC [M] drivers/gpu/drm/xe/xe_force_wake.o
CC arch/x86/kernel/mpparse.o
CC fs/ext4/xattr_trusted.o
CC drivers/md/dm-log.o
AR drivers/net/ethernet/ni/built-in.a
CC net/ipv4/metrics.o
CC drivers/gpu/drm/i915/gt/intel_engine_heartbeat.o
CC drivers/hid/hid-gyration.o
CC fs/bad_inode.o
CC fs/ext4/xattr_user.o
CC drivers/net/ethernet/intel/e1000e/ptp.o
CC mm/early_ioremap.o
CC drivers/acpi/acpica/tbxfload.o
CC net/mac80211/parse.o
CC fs/ext4/fast_commit.o
CC drivers/md/dm-region-hash.o
AR drivers/firmware/built-in.a
CC net/mac80211/wme.o
CC drivers/net/ethernet/nvidia/forcedeth.o
CC kernel/reboot.o
AR drivers/net/ethernet/oki-semi/built-in.a
CC net/ipv4/netlink.o
CC net/ipv6/ip6_icmp.o
AR drivers/net/ethernet/packetengines/built-in.a
CC drivers/acpi/acpica/tbxfroot.o
CC net/ipv6/output_core.o
CC net/ipv4/nexthop.o
AR net/sunrpc/built-in.a
CC fs/nfs/nfs3acl.o
CC fs/file.o
CC drivers/acpi/acpica/utaddress.o
CC lib/generic-radix-tree.o
AR drivers/nvmem/built-in.a
CC kernel/async.o
CC arch/x86/kernel/trace_clock.o
CC lib/bitmap-str.o
CC net/mac80211/chan.o
CC drivers/acpi/evged.o
CC net/ipv4/udp_tunnel_stub.o
CC [M] drivers/gpu/drm/xe/xe_ggtt.o
CC kernel/range.o
AR drivers/net/ethernet/qlogic/built-in.a
CC [M] drivers/gpu/drm/xe/xe_gpu_scheduler.o
CC drivers/acpi/sysfs.o
CC mm/secretmem.o
CC drivers/hid/hid-ite.o
CC drivers/md/dm-zero.o
CC net/ipv6/protocol.o
CC drivers/acpi/acpica/utalloc.o
CC drivers/gpu/drm/i915/gt/intel_engine_pm.o
AR drivers/net/ethernet/qualcomm/emac/built-in.a
AR drivers/net/ethernet/qualcomm/built-in.a
CC lib/string_helpers.o
CC fs/filesystems.o
CC drivers/acpi/acpica/utascii.o
CC mm/hmm.o
CC drivers/net/ethernet/realtek/8139too.o
CC arch/x86/kernel/trace.o
AR drivers/net/ethernet/renesas/built-in.a
AR drivers/net/ethernet/rdc/built-in.a
CC kernel/smpboot.o
CC [M] drivers/gpu/drm/xe/xe_gsc.o
CC drivers/net/ethernet/realtek/r8169_main.o
CC drivers/net/ethernet/realtek/r8169_firmware.o
CC lib/hexdump.o
CC mm/memfd.o
CC net/ipv6/ip6_offload.o
CC arch/x86/kernel/rethook.o
CC fs/namespace.o
CC drivers/acpi/acpica/utbuffer.o
CC fs/nfs/nfs4proc.o
CC net/mac80211/trace.o
CC arch/x86/kernel/vmcore_info_32.o
CC fs/ext4/orphan.o
CC kernel/ucount.o
AR drivers/net/ethernet/rocker/built-in.a
CC [M] drivers/gpu/drm/xe/xe_gsc_debugfs.o
CC kernel/regset.o
AR drivers/md/built-in.a
AR drivers/net/ethernet/samsung/built-in.a
CC drivers/net/ethernet/realtek/r8169_phy_config.o
CC arch/x86/kernel/machine_kexec_32.o
CC fs/seq_file.o
CC drivers/acpi/acpica/utcksum.o
CC lib/kstrtox.o
CC drivers/hid/hid-kensington.o
CC drivers/gpu/drm/drm_displayid.o
CC drivers/acpi/property.o
CC [M] drivers/gpu/drm/xe/xe_gsc_proxy.o
AR drivers/net/ethernet/seeq/built-in.a
CC mm/execmem.o
CC drivers/acpi/debugfs.o
AR net/wireless/built-in.a
CC net/ipv6/tcpv6_offload.o
CC kernel/ksyms_common.o
AS arch/x86/kernel/relocate_kernel_32.o
CC net/mac80211/mlme.o
CC net/ipv4/ip_tunnel.o
CC fs/ext4/acl.o
CC lib/iomap.o
CC fs/ext4/xattr_security.o
CC drivers/gpu/drm/drm_drv.o
CC drivers/acpi/acpi_lpat.o
CC arch/x86/kernel/module.o
AR drivers/net/ethernet/silan/built-in.a
CC drivers/acpi/acpica/utcopy.o
CC net/ipv4/sysctl_net_ipv4.o
CC drivers/gpu/drm/drm_dumb_buffers.o
CC net/mac80211/tdls.o
CC drivers/hid/hid-microsoft.o
CC drivers/hid/hid-monterey.o
CC net/mac80211/ocb.o
CC drivers/gpu/drm/i915/gt/intel_engine_user.o
CC [M] drivers/gpu/drm/xe/xe_gsc_submit.o
AR drivers/net/ethernet/sis/built-in.a
CC arch/x86/kernel/doublefault_32.o
CC net/ipv6/exthdrs_offload.o
CC fs/nfs/nfs4xdr.o
CC [M] drivers/gpu/drm/xe/xe_gt.o
CC net/ipv4/proc.o
CC kernel/groups.o
CC drivers/hid/hid-ntrig.o
CC [M] drivers/gpu/drm/xe/xe_gt_ccs_mode.o
CC drivers/acpi/acpica/utexcep.o
CC net/mac80211/airtime.o
CC lib/iomap_copy.o
CC fs/xattr.o
CC drivers/gpu/drm/drm_edid.o
AR mm/built-in.a
AR drivers/net/ethernet/sfc/built-in.a
CC net/ipv6/inet6_hashtables.o
CC drivers/hid/hid-pl.o
CC drivers/gpu/drm/i915/gt/intel_execlists_submission.o
CC lib/devres.o
CC fs/nfs/nfs4state.o
CC net/ipv4/fib_rules.o
CC net/mac80211/eht.o
CC kernel/kcmp.o
CC net/ipv6/mcast_snoop.o
CC arch/x86/kernel/early_printk.o
CC drivers/hid/hid-petalynx.o
CC drivers/acpi/acpica/utdebug.o
CC fs/nfs/nfs4renewd.o
CC drivers/acpi/acpica/utdecode.o
CC kernel/freezer.o
CC fs/libfs.o
CC drivers/gpu/drm/drm_eld.o
CC drivers/hid/hid-redragon.o
CC fs/fs-writeback.o
CC fs/nfs/nfs4super.o
CC drivers/acpi/acpi_pcc.o
CC drivers/gpu/drm/i915/gt/intel_ggtt.o
CC lib/check_signature.o
AR drivers/net/ethernet/smsc/built-in.a
CC drivers/acpi/ac.o
CC net/mac80211/led.o
AR drivers/net/ethernet/intel/e1000e/built-in.a
CC fs/nfs/nfs4file.o
AR drivers/net/ethernet/intel/built-in.a
CC drivers/acpi/button.o
CC drivers/gpu/drm/drm_encoder.o
CC fs/pnode.o
CC drivers/acpi/acpica/utdelete.o
CC drivers/hid/hid-samsung.o
CC [M] drivers/gpu/drm/xe/xe_gt_clock.o
CC lib/interval_tree.o
CC lib/assoc_array.o
CC net/mac80211/pm.o
CC arch/x86/kernel/hpet.o
CC arch/x86/kernel/amd_nb.o
CC drivers/hid/hid-sony.o
CC drivers/acpi/fan_core.o
CC lib/bitrev.o
AR drivers/net/ethernet/socionext/built-in.a
AR drivers/net/ethernet/nvidia/built-in.a
CC drivers/hid/hid-sunplus.o
CC kernel/profile.o
CC net/ipv4/ipmr.o
CC drivers/gpu/drm/i915/gt/intel_ggtt_fencing.o
CC drivers/acpi/acpica/uterror.o
CC [M] drivers/gpu/drm/xe/xe_gt_freq.o
CC kernel/stacktrace.o
CC arch/x86/kernel/amd_node.o
CC fs/splice.o
CC drivers/hid/hid-topseed.o
CC drivers/gpu/drm/i915/gt/intel_gt.o
CC drivers/acpi/acpica/uteval.o
CC fs/nfs/delegation.o
CC [M] drivers/gpu/drm/xe/xe_gt_idle.o
CC fs/sync.o
CC lib/crc-ccitt.o
CC drivers/acpi/fan_attr.o
CC fs/nfs/nfs4idmap.o
AR drivers/net/ethernet/stmicro/built-in.a
AR drivers/net/ethernet/sun/built-in.a
CC arch/x86/kernel/kvm.o
CC drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.o
CC net/ipv4/ipmr_base.o
CC [M] drivers/gpu/drm/xe/xe_gt_mcr.o
AR net/ipv6/built-in.a
CC fs/utimes.o
CC lib/crc16.o
CC kernel/dma.o
CC arch/x86/kernel/kvmclock.o
CC drivers/acpi/acpica/utglobal.o
HOSTCC lib/gen_crc32table
AR drivers/net/ethernet/realtek/built-in.a
CC drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.o
CC net/mac80211/rc80211_minstrel_ht.o
AR drivers/net/ethernet/tehuti/built-in.a
AR drivers/net/ethernet/ti/built-in.a
AR drivers/net/ethernet/vertexcom/built-in.a
CC drivers/gpu/drm/drm_file.o
AR drivers/net/ethernet/via/built-in.a
AR drivers/net/ethernet/wangxun/built-in.a
CC drivers/gpu/drm/drm_fourcc.o
AR drivers/net/ethernet/wiznet/built-in.a
CC drivers/acpi/fan_hwmon.o
AR drivers/net/ethernet/xilinx/built-in.a
CC kernel/smp.o
AR drivers/net/ethernet/xircom/built-in.a
CC net/mac80211/wbrf.o
AR drivers/net/ethernet/synopsys/built-in.a
CC drivers/acpi/acpica/uthex.o
CC drivers/acpi/acpi_video.o
AR drivers/net/ethernet/pensando/built-in.a
CC drivers/acpi/acpica/utids.o
AR drivers/net/ethernet/built-in.a
CC fs/d_path.o
CC lib/xxhash.o
AR drivers/net/built-in.a
CC lib/genalloc.o
CC net/ipv4/syncookies.o
CC drivers/gpu/drm/drm_framebuffer.o
CC [M] drivers/gpu/drm/xe/xe_gt_pagefault.o
CC drivers/gpu/drm/i915/gt/intel_gt_clock_utils.o
CC fs/nfs/callback.o
CC drivers/acpi/video_detect.o
CC fs/stack.o
CC lib/percpu_counter.o
CC arch/x86/kernel/paravirt.o
AR drivers/hid/built-in.a
CC [M] drivers/gpu/drm/xe/xe_gt_sysfs.o
CC net/ipv4/tunnel4.o
CC drivers/acpi/acpica/utinit.o
CC kernel/uid16.o
CC drivers/gpu/drm/i915/gt/intel_gt_debugfs.o
CC drivers/gpu/drm/drm_gem.o
CC fs/nfs/callback_xdr.o
CC drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.o
CC fs/nfs/callback_proc.o
CC lib/audit.o
CC drivers/acpi/processor_driver.o
CC net/ipv4/ipconfig.o
CC drivers/gpu/drm/i915/gt/intel_gt_irq.o
CC fs/fs_struct.o
CC fs/nfs/nfs4namespace.o
CC lib/syscall.o
CC drivers/acpi/acpica/utlock.o
CC drivers/gpu/drm/drm_ioctl.o
CC kernel/kallsyms.o
CC drivers/acpi/processor_thermal.o
CC net/ipv4/netfilter.o
CC drivers/gpu/drm/i915/gt/intel_gt_mcr.o
CC fs/statfs.o
CC drivers/acpi/processor_idle.o
CC drivers/gpu/drm/i915/gt/intel_gt_pm.o
CC drivers/acpi/acpica/utmath.o
CC kernel/acct.o
CC drivers/gpu/drm/drm_lease.o
CC drivers/acpi/processor_throttling.o
CC drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.o
CC kernel/vmcore_info.o
CC net/ipv4/tcp_cubic.o
CC drivers/acpi/acpica/utmisc.o
CC kernel/elfcorehdr.o
CC arch/x86/kernel/pvclock.o
CC drivers/acpi/acpica/utmutex.o
CC fs/nfs/nfs4getroot.o
CC drivers/acpi/processor_perflib.o
CC [M] drivers/gpu/drm/xe/xe_gt_throttle.o
CC drivers/acpi/acpica/utnonansi.o
CC drivers/acpi/container.o
CC drivers/gpu/drm/i915/gt/intel_gt_pm_irq.o
CC drivers/gpu/drm/drm_managed.o
CC [M] drivers/gpu/drm/xe/xe_gt_tlb_invalidation.o
CC arch/x86/kernel/pcspeaker.o
CC fs/nfs/nfs4client.o
CC fs/fs_pin.o
CC lib/errname.o
CC drivers/gpu/drm/drm_mm.o
CC kernel/kexec_core.o
CC net/ipv4/tcp_sigpool.o
CC [M] drivers/gpu/drm/xe/xe_gt_topology.o
CC lib/nlattr.o
CC drivers/acpi/thermal_lib.o
CC arch/x86/kernel/check.o
CC drivers/gpu/drm/i915/gt/intel_gt_requests.o
CC fs/nsfs.o
CC drivers/acpi/acpica/utobject.o
CC net/ipv4/cipso_ipv4.o
CC drivers/gpu/drm/drm_mode_config.o
CC drivers/acpi/acpica/utosi.o
CC drivers/gpu/drm/drm_mode_object.o
CC kernel/kexec.o
CC fs/nfs/nfs4session.o
CC [M] drivers/gpu/drm/xe/xe_guc.o
CC drivers/gpu/drm/drm_modes.o
CC lib/cpu_rmap.o
CC net/ipv4/xfrm4_policy.o
CC drivers/acpi/thermal.o
CC drivers/gpu/drm/drm_modeset_lock.o
CC arch/x86/kernel/uprobes.o
CC lib/dynamic_queue_limits.o
CC [M] drivers/gpu/drm/xe/xe_guc_ads.o
CC fs/fs_types.o
CC kernel/utsname.o
CC fs/nfs/dns_resolve.o
CC drivers/acpi/nhlt.o
CC arch/x86/kernel/perf_regs.o
CC fs/nfs/nfs4trace.o
CC [M] drivers/gpu/drm/xe/xe_guc_buf.o
CC drivers/gpu/drm/drm_plane.o
CC fs/fs_context.o
CC drivers/gpu/drm/i915/gt/intel_gt_sysfs.o
AR fs/ext4/built-in.a
CC drivers/acpi/acpica/utownerid.o
CC drivers/acpi/acpi_memhotplug.o
CC drivers/acpi/acpica/utpredef.o
CC [M] drivers/gpu/drm/xe/xe_guc_capture.o
CC kernel/pid_namespace.o
CC net/ipv4/xfrm4_state.o
CC arch/x86/kernel/tracepoint.o
CC fs/nfs/nfs4sysctl.o
CC drivers/gpu/drm/drm_prime.o
CC lib/glob.o
CC drivers/acpi/acpica/utresdecode.o
CC fs/fs_parser.o
CC drivers/acpi/ioapic.o
CC [M] drivers/gpu/drm/xe/xe_guc_ct.o
CC arch/x86/kernel/itmt.o
CC net/ipv4/xfrm4_input.o
CC drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.o
CC drivers/gpu/drm/drm_print.o
CC lib/strncpy_from_user.o
CC arch/x86/kernel/umip.o
CC [M] drivers/gpu/drm/xe/xe_guc_db_mgr.o
CC net/ipv4/xfrm4_output.o
CC kernel/stop_machine.o
CC [M] drivers/gpu/drm/xe/xe_guc_engine_activity.o
CC drivers/gpu/drm/i915/gt/intel_gtt.o
CC lib/strnlen_user.o
CC kernel/audit.o
CC fs/fsopen.o
CC drivers/acpi/acpica/utresrc.o
CC arch/x86/kernel/unwind_frame.o
CC drivers/gpu/drm/drm_property.o
CC net/ipv4/xfrm4_protocol.o
CC [M] drivers/gpu/drm/xe/xe_guc_hwconfig.o
CC drivers/acpi/battery.o
CC [M] drivers/gpu/drm/xe/xe_guc_id_mgr.o
CC fs/init.o
CC drivers/gpu/drm/i915/gt/intel_llc.o
CC fs/kernel_read_file.o
CC drivers/gpu/drm/i915/gt/intel_lrc.o
CC drivers/acpi/acpica/utstate.o
CC kernel/auditfilter.o
CC fs/mnt_idmapping.o
CC kernel/auditsc.o
CC fs/remap_range.o
CC drivers/acpi/bgrt.o
CC lib/net_utils.o
CC drivers/acpi/acpica/utstring.o
CC drivers/gpu/drm/drm_rect.o
CC kernel/audit_watch.o
CC drivers/acpi/spcr.o
CC drivers/gpu/drm/drm_syncobj.o
CC drivers/gpu/drm/i915/gt/intel_migrate.o
CC lib/sg_pool.o
CC fs/pidfs.o
CC drivers/gpu/drm/drm_sysfs.o
CC drivers/acpi/acpica/utstrsuppt.o
CC kernel/audit_fsnotify.o
CC [M] drivers/gpu/drm/xe/xe_guc_klv_helpers.o
CC drivers/acpi/acpica/utstrtoul64.o
CC drivers/gpu/drm/drm_trace_points.o
CC kernel/audit_tree.o
CC drivers/acpi/acpica/utxface.o
AR arch/x86/kernel/built-in.a
CC [M] drivers/gpu/drm/xe/xe_guc_log.o
AR arch/x86/built-in.a
CC [M] drivers/gpu/drm/xe/xe_guc_pc.o
CC drivers/acpi/acpica/utxfinit.o
CC [M] drivers/gpu/drm/xe/xe_guc_submit.o
CC drivers/gpu/drm/i915/gt/intel_mocs.o
CC drivers/gpu/drm/drm_vblank.o
CC fs/buffer.o
CC lib/stackdepot.o
CC drivers/gpu/drm/drm_vblank_work.o
CC fs/mpage.o
CC [M] drivers/gpu/drm/xe/xe_heci_gsc.o
CC kernel/kprobes.o
CC drivers/gpu/drm/i915/gt/intel_ppgtt.o
CC fs/proc_namespace.o
CC drivers/acpi/acpica/utxferror.o
CC lib/asn1_decoder.o
CC fs/direct-io.o
CC kernel/seccomp.o
CC [M] drivers/gpu/drm/xe/xe_huc.o
CC drivers/acpi/acpica/utxfmutex.o
GEN lib/oid_registry_data.c
CC fs/eventpoll.o
CC drivers/gpu/drm/drm_vma_manager.o
CC [M] drivers/gpu/drm/xe/xe_hw_engine.o
CC kernel/relay.o
CC kernel/utsname_sysctl.o
CC drivers/gpu/drm/i915/gt/intel_rc6.o
CC lib/ucs2_string.o
CC fs/anon_inodes.o
CC lib/sbitmap.o
AR net/ipv4/built-in.a
CC [M] drivers/gpu/drm/xe/xe_hw_engine_class_sysfs.o
CC [M] drivers/gpu/drm/xe/xe_hw_engine_group.o
CC kernel/delayacct.o
CC fs/signalfd.o
CC kernel/taskstats.o
CC lib/group_cpus.o
CC drivers/gpu/drm/drm_writeback.o
CC [M] drivers/gpu/drm/xe/xe_hw_fence.o
AR drivers/acpi/acpica/built-in.a
CC drivers/gpu/drm/drm_panel.o
AR drivers/acpi/built-in.a
CC kernel/tsacct.o
CC fs/timerfd.o
CC lib/fw_table.o
CC [M] drivers/gpu/drm/xe/xe_irq.o
CC kernel/tracepoint.o
CC fs/eventfd.o
CC [M] drivers/gpu/drm/xe/xe_lrc.o
CC drivers/gpu/drm/i915/gt/intel_region_lmem.o
CC [M] drivers/gpu/drm/xe/xe_migrate.o
CC kernel/irq_work.o
CC kernel/static_call.o
CC fs/aio.o
CC [M] drivers/gpu/drm/xe/xe_mmio.o
CC kernel/padata.o
CC drivers/gpu/drm/i915/gt/intel_renderstate.o
CC drivers/gpu/drm/drm_pci.o
AR lib/lib.a
CC fs/locks.o
CC [M] drivers/gpu/drm/xe/xe_mocs.o
GEN lib/crc32table.h
CC kernel/jump_label.o
CC [M] drivers/gpu/drm/xe/xe_module.o
CC drivers/gpu/drm/i915/gt/intel_reset.o
CC drivers/gpu/drm/drm_debugfs.o
CC drivers/gpu/drm/i915/gt/intel_ring.o
CC fs/binfmt_misc.o
CC [M] drivers/gpu/drm/xe/xe_oa.o
CC kernel/context_tracking.o
CC lib/oid_registry.o
CC kernel/iomem.o
CC [M] drivers/gpu/drm/xe/xe_observation.o
CC fs/binfmt_script.o
CC drivers/gpu/drm/drm_debugfs_crc.o
CC [M] drivers/gpu/drm/xe/xe_pat.o
CC kernel/rseq.o
CC drivers/gpu/drm/drm_panel_orientation_quirks.o
CC drivers/gpu/drm/drm_buddy.o
CC [M] drivers/gpu/drm/xe/xe_pci.o
CC fs/binfmt_elf.o
CC drivers/gpu/drm/i915/gt/intel_ring_submission.o
CC drivers/gpu/drm/drm_gem_shmem_helper.o
CC fs/mbcache.o
CC drivers/gpu/drm/drm_atomic_helper.o
CC [M] drivers/gpu/drm/xe/xe_pcode.o
CC drivers/gpu/drm/i915/gt/intel_rps.o
CC [M] drivers/gpu/drm/xe/xe_pm.o
CC drivers/gpu/drm/drm_atomic_state_helper.o
CC fs/posix_acl.o
CC lib/crc32.o
CC drivers/gpu/drm/i915/gt/intel_sa_media.o
CC drivers/gpu/drm/drm_bridge_helper.o
CC [M] drivers/gpu/drm/xe/xe_preempt_fence.o
AR fs/nfs/built-in.a
CC fs/coredump.o
CC drivers/gpu/drm/i915/gt/intel_sseu.o
CC [M] drivers/gpu/drm/xe/xe_pt.o
CC drivers/gpu/drm/drm_crtc_helper.o
CC fs/drop_caches.o
CC [M] drivers/gpu/drm/xe/xe_pt_walk.o
CC drivers/gpu/drm/i915/gt/intel_sseu_debugfs.o
CC drivers/gpu/drm/drm_damage_helper.o
AR net/mac80211/built-in.a
CC drivers/gpu/drm/drm_flip_work.o
AR net/built-in.a
CC [M] drivers/gpu/drm/xe/xe_pxp.o
CC fs/sysctls.o
CC drivers/gpu/drm/drm_format_helper.o
CC drivers/gpu/drm/i915/gt/intel_timeline.o
CC drivers/gpu/drm/drm_gem_atomic_helper.o
AR lib/built-in.a
CC [M] drivers/gpu/drm/xe/xe_pxp_debugfs.o
CC [M] drivers/gpu/drm/xe/xe_pxp_submit.o
CC drivers/gpu/drm/i915/gt/intel_tlb.o
CC drivers/gpu/drm/drm_gem_framebuffer_helper.o
CC fs/fhandle.o
CC [M] drivers/gpu/drm/xe/xe_query.o
CC drivers/gpu/drm/i915/gt/intel_wopcm.o
CC drivers/gpu/drm/drm_kms_helper_common.o
CC [M] drivers/gpu/drm/xe/xe_range_fence.o
CC drivers/gpu/drm/i915/gt/intel_workarounds.o
CC drivers/gpu/drm/i915/gt/shmem_utils.o
AR kernel/built-in.a
CC drivers/gpu/drm/drm_modeset_helper.o
CC drivers/gpu/drm/i915/gt/sysfs_engines.o
CC drivers/gpu/drm/drm_plane_helper.o
CC [M] drivers/gpu/drm/xe/xe_reg_sr.o
CC [M] drivers/gpu/drm/xe/xe_reg_whitelist.o
CC drivers/gpu/drm/i915/gt/intel_ggtt_gmch.o
CC [M] drivers/gpu/drm/xe/xe_ring_ops.o
CC drivers/gpu/drm/i915/gt/gen6_renderstate.o
CC drivers/gpu/drm/drm_probe_helper.o
CC [M] drivers/gpu/drm/xe/xe_rtp.o
CC drivers/gpu/drm/i915/gt/gen7_renderstate.o
CC [M] drivers/gpu/drm/xe/xe_sa.o
CC [M] drivers/gpu/drm/xe/xe_sched_job.o
CC drivers/gpu/drm/drm_self_refresh_helper.o
CC drivers/gpu/drm/drm_simple_kms_helper.o
CC [M] drivers/gpu/drm/xe/xe_shrinker.o
CC drivers/gpu/drm/i915/gt/gen8_renderstate.o
CC [M] drivers/gpu/drm/xe/xe_step.o
CC drivers/gpu/drm/bridge/panel.o
CC [M] drivers/gpu/drm/xe/xe_survivability_mode.o
CC [M] drivers/gpu/drm/xe/xe_sync.o
CC drivers/gpu/drm/i915/gt/gen9_renderstate.o
CC drivers/gpu/drm/drm_mipi_dsi.o
CC [M] drivers/gpu/drm/xe/xe_tile.o
CC [M] drivers/gpu/drm/drm_exec.o
CC [M] drivers/gpu/drm/drm_gpuvm.o
CC drivers/gpu/drm/i915/gem/i915_gem_busy.o
CC [M] drivers/gpu/drm/xe/xe_tile_sysfs.o
CC drivers/gpu/drm/i915/gem/i915_gem_clflush.o
CC [M] drivers/gpu/drm/xe/xe_trace.o
CC drivers/gpu/drm/i915/gem/i915_gem_context.o
CC [M] drivers/gpu/drm/drm_suballoc.o
CC [M] drivers/gpu/drm/xe/xe_trace_bo.o
CC drivers/gpu/drm/i915/gem/i915_gem_create.o
CC [M] drivers/gpu/drm/xe/xe_trace_guc.o
CC drivers/gpu/drm/i915/gem/i915_gem_dmabuf.o
CC [M] drivers/gpu/drm/drm_gem_ttm_helper.o
CC drivers/gpu/drm/i915/gem/i915_gem_domain.o
CC [M] drivers/gpu/drm/xe/xe_trace_lrc.o
CC drivers/gpu/drm/i915/gem/i915_gem_execbuffer.o
CC [M] drivers/gpu/drm/xe/xe_ttm_stolen_mgr.o
CC drivers/gpu/drm/i915/gem/i915_gem_internal.o
CC [M] drivers/gpu/drm/xe/xe_ttm_sys_mgr.o
CC drivers/gpu/drm/i915/gem/i915_gem_lmem.o
CC drivers/gpu/drm/i915/gem/i915_gem_mman.o
CC [M] drivers/gpu/drm/xe/xe_ttm_vram_mgr.o
CC [M] drivers/gpu/drm/xe/xe_tuning.o
CC drivers/gpu/drm/i915/gem/i915_gem_object.o
CC [M] drivers/gpu/drm/xe/xe_uc.o
AR fs/built-in.a
CC drivers/gpu/drm/i915/gem/i915_gem_pages.o
CC [M] drivers/gpu/drm/xe/xe_uc_fw.o
CC drivers/gpu/drm/i915/gem/i915_gem_phys.o
CC drivers/gpu/drm/i915/gem/i915_gem_pm.o
CC [M] drivers/gpu/drm/xe/xe_vm.o
CC drivers/gpu/drm/i915/gem/i915_gem_region.o
CC [M] drivers/gpu/drm/xe/xe_vram.o
CC drivers/gpu/drm/i915/gem/i915_gem_shmem.o
CC [M] drivers/gpu/drm/xe/xe_vram_freq.o
CC [M] drivers/gpu/drm/xe/xe_vsec.o
CC [M] drivers/gpu/drm/xe/xe_wa.o
CC drivers/gpu/drm/i915/gem/i915_gem_shrinker.o
CC [M] drivers/gpu/drm/xe/xe_wait_user_fence.o
CC drivers/gpu/drm/i915/gem/i915_gem_stolen.o
CC [M] drivers/gpu/drm/xe/xe_wopcm.o
CC [M] drivers/gpu/drm/xe/xe_hmm.o
LD [M] drivers/gpu/drm/drm_suballoc_helper.o
CC [M] drivers/gpu/drm/xe/xe_hwmon.o
CC drivers/gpu/drm/i915/gem/i915_gem_throttle.o
CC [M] drivers/gpu/drm/xe/xe_pmu.o
CC drivers/gpu/drm/i915/gem/i915_gem_tiling.o
CC [M] drivers/gpu/drm/xe/xe_gt_sriov_vf.o
LD [M] drivers/gpu/drm/drm_ttm_helper.o
CC drivers/gpu/drm/i915/gem/i915_gem_ttm.o
CC [M] drivers/gpu/drm/xe/xe_guc_relay.o
CC drivers/gpu/drm/i915/gem/i915_gem_ttm_move.o
CC [M] drivers/gpu/drm/xe/xe_memirq.o
CC [M] drivers/gpu/drm/xe/xe_sriov.o
CC drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.o
CC drivers/gpu/drm/i915/gem/i915_gem_userptr.o
CC [M] drivers/gpu/drm/xe/xe_sriov_vf.o
CC drivers/gpu/drm/i915/gem/i915_gem_wait.o
CC [M] drivers/gpu/drm/xe/display/ext/i915_irq.o
CC drivers/gpu/drm/i915/gem/i915_gemfs.o
CC [M] drivers/gpu/drm/xe/display/ext/i915_utils.o
CC drivers/gpu/drm/i915/i915_active.o
CC drivers/gpu/drm/i915/i915_cmd_parser.o
CC [M] drivers/gpu/drm/xe/display/intel_bo.o
CC drivers/gpu/drm/i915/i915_deps.o
CC [M] drivers/gpu/drm/xe/display/intel_fb_bo.o
CC drivers/gpu/drm/i915/i915_gem.o
CC [M] drivers/gpu/drm/xe/display/intel_fbdev_fb.o
CC [M] drivers/gpu/drm/xe/display/xe_display.o
CC [M] drivers/gpu/drm/xe/display/xe_display_misc.o
CC [M] drivers/gpu/drm/xe/display/xe_display_rpm.o
CC [M] drivers/gpu/drm/xe/display/xe_display_rps.o
CC drivers/gpu/drm/i915/i915_gem_evict.o
CC [M] drivers/gpu/drm/xe/display/xe_display_wa.o
CC drivers/gpu/drm/i915/i915_gem_gtt.o
CC [M] drivers/gpu/drm/xe/display/xe_dsb_buffer.o
CC drivers/gpu/drm/i915/i915_gem_ww.o
CC [M] drivers/gpu/drm/xe/display/xe_fb_pin.o
CC drivers/gpu/drm/i915/i915_query.o
CC [M] drivers/gpu/drm/xe/display/xe_hdcp_gsc.o
CC drivers/gpu/drm/i915/i915_request.o
CC [M] drivers/gpu/drm/xe/display/xe_plane_initial.o
CC drivers/gpu/drm/i915/i915_scheduler.o
CC drivers/gpu/drm/i915/i915_trace_points.o
CC [M] drivers/gpu/drm/xe/display/xe_tdf.o
CC [M] drivers/gpu/drm/xe/i915-soc/intel_dram.o
CC [M] drivers/gpu/drm/xe/i915-soc/intel_rom.o
CC drivers/gpu/drm/i915/i915_ttm_buddy_manager.o
CC [M] drivers/gpu/drm/xe/i915-display/icl_dsi.o
CC drivers/gpu/drm/i915/i915_vma.o
CC drivers/gpu/drm/i915/i915_vma_resource.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_alpm.o
CC drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_atomic.o
CC drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_atomic_plane.o
CC drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_audio.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_backlight.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_bios.o
CC drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_debugfs.o
CC drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_bw.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_cdclk.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_ads.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_capture.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_ct.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_cmtg.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_fw.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_color.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_combo_phy.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_connector.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_crtc.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_crtc_state_dump.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_cursor.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_log.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_cx0_phy.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_ddi.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_ddi_buf_trans.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_rc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_conversion.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_submission.o
CC drivers/gpu/drm/i915/gt/uc/intel_huc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_device.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_driver.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_irq.o
CC drivers/gpu/drm/i915/gt/uc/intel_huc_debugfs.o
CC drivers/gpu/drm/i915/gt/uc/intel_huc_fw.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_params.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_power.o
CC drivers/gpu/drm/i915/gt/uc/intel_uc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_power_map.o
CC drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.o
CC drivers/gpu/drm/i915/gt/uc/intel_uc_fw.o
CC drivers/gpu/drm/i915/gt/intel_gsc.o
CC drivers/gpu/drm/i915/i915_hwmon.o
CC drivers/gpu/drm/i915/display/hsw_ips.o
CC drivers/gpu/drm/i915/display/i9xx_plane.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_power_well.o
CC drivers/gpu/drm/i915/display/i9xx_display_sr.o
CC drivers/gpu/drm/i915/display/i9xx_wm.o
CC drivers/gpu/drm/i915/display/intel_alpm.o
CC drivers/gpu/drm/i915/display/intel_atomic.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_trace.o
CC drivers/gpu/drm/i915/display/intel_atomic_plane.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_wa.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dkl_phy.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dmc.o
CC drivers/gpu/drm/i915/display/intel_audio.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dmc_wl.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp.o
CC drivers/gpu/drm/i915/display/intel_bios.o
CC drivers/gpu/drm/i915/display/intel_bo.o
CC drivers/gpu/drm/i915/display/intel_bw.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_aux.o
CC drivers/gpu/drm/i915/display/intel_cdclk.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_aux_backlight.o
CC drivers/gpu/drm/i915/display/intel_cmtg.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_hdcp.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_link_training.o
CC drivers/gpu/drm/i915/display/intel_color.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_mst.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_test.o
CC drivers/gpu/drm/i915/display/intel_combo_phy.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dpll.o
CC drivers/gpu/drm/i915/display/intel_connector.o
CC drivers/gpu/drm/i915/display/intel_crtc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dpll_mgr.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dpt_common.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_drrs.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dsb.o
CC drivers/gpu/drm/i915/display/intel_crtc_state_dump.o
CC drivers/gpu/drm/i915/display/intel_cursor.o
CC drivers/gpu/drm/i915/display/intel_display.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dsi.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dsi_dcs_backlight.o
CC drivers/gpu/drm/i915/display/intel_display_conversion.o
CC drivers/gpu/drm/i915/display/intel_display_driver.o
CC drivers/gpu/drm/i915/display/intel_display_irq.o
CC drivers/gpu/drm/i915/display/intel_display_params.o
CC drivers/gpu/drm/i915/display/intel_display_power.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dsi_vbt.o
CC drivers/gpu/drm/i915/display/intel_display_power_map.o
CC drivers/gpu/drm/i915/display/intel_display_power_well.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_encoder.o
CC drivers/gpu/drm/i915/display/intel_display_reset.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_fb.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_fbc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_fdi.o
CC drivers/gpu/drm/i915/display/intel_display_rpm.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_fifo_underrun.o
CC drivers/gpu/drm/i915/display/intel_display_rps.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_frontbuffer.o
CC drivers/gpu/drm/i915/display/intel_display_snapshot.o
CC drivers/gpu/drm/i915/display/intel_display_wa.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_global_state.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_gmbus.o
CC drivers/gpu/drm/i915/display/intel_dmc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_hdcp.o
CC drivers/gpu/drm/i915/display/intel_dmc_wl.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_hdcp_gsc_message.o
CC drivers/gpu/drm/i915/display/intel_dpio_phy.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_hdmi.o
CC drivers/gpu/drm/i915/display/intel_dpll.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_hotplug.o
CC drivers/gpu/drm/i915/display/intel_dpll_mgr.o
CC drivers/gpu/drm/i915/display/intel_dpt.o
CC drivers/gpu/drm/i915/display/intel_dpt_common.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_hotplug_irq.o
CC drivers/gpu/drm/i915/display/intel_drrs.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_hti.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_link_bw.o
CC drivers/gpu/drm/i915/display/intel_dsb.o
CC drivers/gpu/drm/i915/display/intel_dsb_buffer.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_lspcon.o
CC drivers/gpu/drm/i915/display/intel_fb.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_modeset_lock.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_modeset_setup.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_modeset_verify.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_panel.o
CC drivers/gpu/drm/i915/display/intel_fb_bo.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_pfit.o
CC drivers/gpu/drm/i915/display/intel_fb_pin.o
CC drivers/gpu/drm/i915/display/intel_fbc.o
CC drivers/gpu/drm/i915/display/intel_fdi.o
CC drivers/gpu/drm/i915/display/intel_fifo_underrun.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_pmdemand.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_pch.o
CC drivers/gpu/drm/i915/display/intel_frontbuffer.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_pps.o
CC drivers/gpu/drm/i915/display/intel_global_state.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_psr.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_qp_tables.o
CC drivers/gpu/drm/i915/display/intel_hdcp.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_quirks.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_snps_hdmi_pll.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_snps_phy.o
CC drivers/gpu/drm/i915/display/intel_hdcp_gsc.o
CC drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.o
CC drivers/gpu/drm/i915/display/intel_hotplug.o
CC drivers/gpu/drm/i915/display/intel_hotplug_irq.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_tc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_vblank.o
CC drivers/gpu/drm/i915/display/intel_hti.o
CC drivers/gpu/drm/i915/display/intel_link_bw.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_vdsc.o
CC drivers/gpu/drm/i915/display/intel_load_detect.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_vga.o
CC drivers/gpu/drm/i915/display/intel_lpe_audio.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_vrr.o
CC drivers/gpu/drm/i915/display/intel_modeset_lock.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_wm.o
CC [M] drivers/gpu/drm/xe/i915-display/skl_scaler.o
CC [M] drivers/gpu/drm/xe/i915-display/skl_universal_plane.o
CC drivers/gpu/drm/i915/display/intel_modeset_setup.o
CC [M] drivers/gpu/drm/xe/i915-display/skl_watermark.o
CC drivers/gpu/drm/i915/display/intel_modeset_verify.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_acpi.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_opregion.o
CC drivers/gpu/drm/i915/display/intel_overlay.o
CC drivers/gpu/drm/i915/display/intel_pch.o
CC [M] drivers/gpu/drm/xe/xe_debugfs.o
CC [M] drivers/gpu/drm/xe/xe_gt_debugfs.o
CC drivers/gpu/drm/i915/display/intel_pch_display.o
CC [M] drivers/gpu/drm/xe/xe_gt_sriov_vf_debugfs.o
CC drivers/gpu/drm/i915/display/intel_pch_refclk.o
CC [M] drivers/gpu/drm/xe/xe_gt_stats.o
CC drivers/gpu/drm/i915/display/intel_plane_initial.o
CC [M] drivers/gpu/drm/xe/xe_guc_debugfs.o
CC drivers/gpu/drm/i915/display/intel_pmdemand.o
CC drivers/gpu/drm/i915/display/intel_psr.o
CC [M] drivers/gpu/drm/xe/xe_huc_debugfs.o
CC [M] drivers/gpu/drm/xe/xe_uc_debugfs.o
CC drivers/gpu/drm/i915/display/intel_quirks.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_debugfs.o
CC drivers/gpu/drm/i915/display/intel_sprite.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_debugfs_params.o
CC drivers/gpu/drm/i915/display/intel_sprite_uapi.o
CC drivers/gpu/drm/i915/display/intel_tc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_pipe_crc.o
CC drivers/gpu/drm/i915/display/intel_vblank.o
CC drivers/gpu/drm/i915/display/intel_vga.o
CC drivers/gpu/drm/i915/display/intel_wm.o
CC drivers/gpu/drm/i915/display/skl_scaler.o
CC drivers/gpu/drm/i915/display/skl_universal_plane.o
CC drivers/gpu/drm/i915/display/skl_watermark.o
CC drivers/gpu/drm/i915/display/intel_acpi.o
CC drivers/gpu/drm/i915/display/intel_opregion.o
CC drivers/gpu/drm/i915/display/intel_display_debugfs.o
CC drivers/gpu/drm/i915/display/intel_display_debugfs_params.o
CC drivers/gpu/drm/i915/display/intel_pipe_crc.o
CC drivers/gpu/drm/i915/display/dvo_ch7017.o
CC drivers/gpu/drm/i915/display/dvo_ch7xxx.o
CC drivers/gpu/drm/i915/display/dvo_ivch.o
CC drivers/gpu/drm/i915/display/dvo_ns2501.o
CC drivers/gpu/drm/i915/display/dvo_sil164.o
CC drivers/gpu/drm/i915/display/dvo_tfp410.o
CC drivers/gpu/drm/i915/display/g4x_dp.o
CC drivers/gpu/drm/i915/display/g4x_hdmi.o
CC drivers/gpu/drm/i915/display/icl_dsi.o
CC drivers/gpu/drm/i915/display/intel_backlight.o
CC drivers/gpu/drm/i915/display/intel_crt.o
CC drivers/gpu/drm/i915/display/intel_cx0_phy.o
CC drivers/gpu/drm/i915/display/intel_ddi.o
CC drivers/gpu/drm/i915/display/intel_ddi_buf_trans.o
CC drivers/gpu/drm/i915/display/intel_display_device.o
CC drivers/gpu/drm/i915/display/intel_display_trace.o
CC drivers/gpu/drm/i915/display/intel_dkl_phy.o
CC drivers/gpu/drm/i915/display/intel_dp.o
CC drivers/gpu/drm/i915/display/intel_dp_aux.o
CC drivers/gpu/drm/i915/display/intel_dp_aux_backlight.o
CC drivers/gpu/drm/i915/display/intel_dp_hdcp.o
CC drivers/gpu/drm/i915/display/intel_dp_link_training.o
CC drivers/gpu/drm/i915/display/intel_dp_mst.o
CC drivers/gpu/drm/i915/display/intel_dp_test.o
CC drivers/gpu/drm/i915/display/intel_dsi.o
CC drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.o
CC drivers/gpu/drm/i915/display/intel_dsi_vbt.o
CC drivers/gpu/drm/i915/display/intel_dvo.o
CC drivers/gpu/drm/i915/display/intel_encoder.o
CC drivers/gpu/drm/i915/display/intel_gmbus.o
CC drivers/gpu/drm/i915/display/intel_hdmi.o
CC drivers/gpu/drm/i915/display/intel_lspcon.o
CC drivers/gpu/drm/i915/display/intel_lvds.o
CC drivers/gpu/drm/i915/display/intel_panel.o
CC drivers/gpu/drm/i915/display/intel_pfit.o
CC drivers/gpu/drm/i915/display/intel_pps.o
CC drivers/gpu/drm/i915/display/intel_qp_tables.o
CC drivers/gpu/drm/i915/display/intel_sdvo.o
CC drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.o
CC drivers/gpu/drm/i915/display/intel_snps_phy.o
CC drivers/gpu/drm/i915/display/intel_tv.o
CC drivers/gpu/drm/i915/display/intel_vdsc.o
CC drivers/gpu/drm/i915/display/intel_vrr.o
CC drivers/gpu/drm/i915/display/vlv_dsi.o
CC drivers/gpu/drm/i915/display/vlv_dsi_pll.o
CC drivers/gpu/drm/i915/i915_perf.o
CC drivers/gpu/drm/i915/pxp/intel_pxp.o
CC drivers/gpu/drm/i915/pxp/intel_pxp_huc.o
CC drivers/gpu/drm/i915/pxp/intel_pxp_tee.o
CC drivers/gpu/drm/i915/i915_gpu_error.o
CC drivers/gpu/drm/i915/i915_vgpu.o
LD [M] drivers/gpu/drm/xe/xe.o
AR drivers/gpu/drm/i915/built-in.a
AR drivers/gpu/drm/built-in.a
AR drivers/gpu/built-in.a
AR drivers/built-in.a
AR built-in.a
AR vmlinux.a
LD vmlinux.o
OBJCOPY modules.builtin.modinfo
GEN modules.builtin
MODPOST Module.symvers
CC .vmlinux.export.o
CC [M] fs/efivarfs/efivarfs.mod.o
CC [M] .module-common.o
CC [M] drivers/gpu/drm/drm_exec.mod.o
CC [M] drivers/gpu/drm/drm_gpuvm.mod.o
CC [M] drivers/gpu/drm/drm_suballoc_helper.mod.o
CC [M] drivers/gpu/drm/drm_ttm_helper.mod.o
CC [M] drivers/gpu/drm/scheduler/gpu-sched.mod.o
CC [M] drivers/gpu/drm/xe/xe.mod.o
CC [M] drivers/thermal/intel/x86_pkg_temp_thermal.mod.o
CC [M] net/netfilter/nf_log_syslog.mod.o
CC [M] net/netfilter/xt_mark.mod.o
CC [M] net/netfilter/xt_nat.mod.o
CC [M] net/netfilter/xt_LOG.mod.o
CC [M] net/netfilter/xt_MASQUERADE.mod.o
CC [M] net/netfilter/xt_addrtype.mod.o
CC [M] net/ipv4/netfilter/iptable_nat.mod.o
LD [M] fs/efivarfs/efivarfs.ko
LD [M] drivers/gpu/drm/drm_exec.ko
LD [M] net/netfilter/xt_mark.ko
LD [M] drivers/gpu/drm/xe/xe.ko
LD [M] net/netfilter/nf_log_syslog.ko
LD [M] net/netfilter/xt_nat.ko
LD [M] net/netfilter/xt_MASQUERADE.ko
LD [M] drivers/gpu/drm/drm_gpuvm.ko
LD [M] drivers/gpu/drm/drm_ttm_helper.ko
LD [M] drivers/gpu/drm/scheduler/gpu-sched.ko
LD [M] net/netfilter/xt_LOG.ko
LD [M] net/netfilter/xt_addrtype.ko
LD [M] net/ipv4/netfilter/iptable_nat.ko
LD [M] drivers/thermal/intel/x86_pkg_temp_thermal.ko
LD [M] drivers/gpu/drm/drm_suballoc_helper.ko
UPD include/generated/utsversion.h
CC init/version-timestamp.o
KSYMS .tmp_vmlinux0.kallsyms.S
AS .tmp_vmlinux0.kallsyms.o
LD .tmp_vmlinux1
NM .tmp_vmlinux1.syms
KSYMS .tmp_vmlinux1.kallsyms.S
AS .tmp_vmlinux1.kallsyms.o
LD .tmp_vmlinux2
NM .tmp_vmlinux2.syms
KSYMS .tmp_vmlinux2.kallsyms.S
AS .tmp_vmlinux2.kallsyms.o
LD vmlinux.unstripped
NM System.map
SORTTAB vmlinux.unstripped
RSTRIP vmlinux
CC arch/x86/boot/a20.o
AS arch/x86/boot/bioscall.o
CC arch/x86/boot/cmdline.o
AS arch/x86/boot/copy.o
HOSTCC arch/x86/boot/mkcpustr
CC arch/x86/boot/cpuflags.o
CC arch/x86/boot/cpucheck.o
CC arch/x86/boot/early_serial_console.o
CC arch/x86/boot/edd.o
CC arch/x86/boot/main.o
CC arch/x86/boot/memory.o
CC arch/x86/boot/pm.o
AS arch/x86/boot/pmjump.o
CC arch/x86/boot/printf.o
CC arch/x86/boot/regs.o
CC arch/x86/boot/string.o
CC arch/x86/boot/tty.o
CC arch/x86/boot/video.o
CC arch/x86/boot/video-mode.o
CC arch/x86/boot/version.o
CC arch/x86/boot/video-vga.o
CC arch/x86/boot/video-vesa.o
CC arch/x86/boot/video-bios.o
LDS arch/x86/boot/compressed/vmlinux.lds
AS arch/x86/boot/compressed/kernel_info.o
AS arch/x86/boot/compressed/head_32.o
VOFFSET arch/x86/boot/compressed/../voffset.h
CC arch/x86/boot/compressed/string.o
CC arch/x86/boot/compressed/cmdline.o
CC arch/x86/boot/compressed/error.o
OBJCOPY arch/x86/boot/compressed/vmlinux.bin
RELOCS arch/x86/boot/compressed/vmlinux.relocs
HOSTCC arch/x86/boot/compressed/mkpiggy
CPUSTR arch/x86/boot/cpustr.h
CC arch/x86/boot/compressed/cpuflags.o
CC arch/x86/boot/compressed/early_serial_console.o
CC arch/x86/boot/compressed/kaslr.o
CC arch/x86/boot/cpu.o
CC arch/x86/boot/compressed/acpi.o
CC arch/x86/boot/compressed/efi.o
GZIP arch/x86/boot/compressed/vmlinux.bin.gz
CC arch/x86/boot/compressed/misc.o
MKPIGGY arch/x86/boot/compressed/piggy.S
AS arch/x86/boot/compressed/piggy.o
LD arch/x86/boot/compressed/vmlinux
ZOFFSET arch/x86/boot/zoffset.h
OBJCOPY arch/x86/boot/vmlinux.bin
AS arch/x86/boot/header.o
LD arch/x86/boot/setup.elf
OBJCOPY arch/x86/boot/setup.bin
BUILD arch/x86/boot/bzImage
Kernel: arch/x86/boot/bzImage is ready (#1)
run-parts: executing /workspace/ci/hooks/20-kernel-doc
+ SRC_DIR=/workspace/kernel
+ cd /workspace/kernel
+ find drivers/gpu/drm/xe/ -name '*.[ch]' -not -path 'drivers/gpu/drm/xe/display/*'
+ xargs ./scripts/kernel-doc -Werror -none include/uapi/drm/xe_drm.h
All hooks done
^ permalink raw reply [flat|nested] 13+ messages in thread
* ✓ CI.checksparse: success for drm/i915: i915_reg.h display split (rev2)
2025-04-15 10:51 [PATCH v2 0/3] drm/i915: i915_reg.h display split Jani Nikula
` (7 preceding siblings ...)
2025-04-15 11:55 ` ✓ CI.Hooks: " Patchwork
@ 2025-04-15 11:56 ` Patchwork
2025-04-15 12:52 ` ✓ Xe.CI.BAT: " Patchwork
2025-04-15 17:29 ` ✗ Xe.CI.Full: failure " Patchwork
10 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2025-04-15 11:56 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-xe
== Series Details ==
Series: drm/i915: i915_reg.h display split (rev2)
URL : https://patchwork.freedesktop.org/series/144506/
State : success
== Summary ==
+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast 22c34bd976f4b047263dafa7b88f60f953ccddd3
Sparse version: 0.6.4 (Ubuntu: 0.6.4-4ubuntu3)
Fast mode used, each commit won't be checked separately.
Okay!
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 13+ messages in thread
* ✓ Xe.CI.BAT: success for drm/i915: i915_reg.h display split (rev2)
2025-04-15 10:51 [PATCH v2 0/3] drm/i915: i915_reg.h display split Jani Nikula
` (8 preceding siblings ...)
2025-04-15 11:56 ` ✓ CI.checksparse: " Patchwork
@ 2025-04-15 12:52 ` Patchwork
2025-04-15 17:29 ` ✗ Xe.CI.Full: failure " Patchwork
10 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2025-04-15 12:52 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 1525 bytes --]
== Series Details ==
Series: drm/i915: i915_reg.h display split (rev2)
URL : https://patchwork.freedesktop.org/series/144506/
State : success
== Summary ==
CI Bug Log - changes from xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65_BAT -> xe-pw-144506v2_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (8 -> 8)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in xe-pw-144506v2_BAT that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@intel_sysfs_debugfs@xe-forcewake:
- bat-lnl-1: [PASS][1] -> [ABORT][2] ([Intel XE#4624])
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/bat-lnl-1/igt@intel_sysfs_debugfs@xe-forcewake.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/bat-lnl-1/igt@intel_sysfs_debugfs@xe-forcewake.html
[Intel XE#4624]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4624
Build changes
-------------
* Linux: xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65 -> xe-pw-144506v2
IGT_8319: db9eca9df70fbb72589fcaf689dd92784b06a9c0 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65: 4e52f6bddf99cb28ed0279d56bb8286a8bbfda65
xe-pw-144506v2: 144506v2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/index.html
[-- Attachment #2: Type: text/html, Size: 2090 bytes --]
^ permalink raw reply [flat|nested] 13+ messages in thread
* ✗ Xe.CI.Full: failure for drm/i915: i915_reg.h display split (rev2)
2025-04-15 10:51 [PATCH v2 0/3] drm/i915: i915_reg.h display split Jani Nikula
` (9 preceding siblings ...)
2025-04-15 12:52 ` ✓ Xe.CI.BAT: " Patchwork
@ 2025-04-15 17:29 ` Patchwork
10 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2025-04-15 17:29 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 99495 bytes --]
== Series Details ==
Series: drm/i915: i915_reg.h display split (rev2)
URL : https://patchwork.freedesktop.org/series/144506/
State : failure
== Summary ==
CI Bug Log - changes from xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65_FULL -> xe-pw-144506v2_FULL
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-144506v2_FULL absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-144506v2_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (4 -> 4)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-144506v2_FULL:
### IGT changes ###
#### Possible regressions ####
* igt@kms_async_flips@async-flip-with-page-flip-events-atomic:
- shard-bmg: ([PASS][1], [PASS][2]) -> [DMESG-FAIL][3]
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-2/igt@kms_async_flips@async-flip-with-page-flip-events-atomic.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-4/igt@kms_async_flips@async-flip-with-page-flip-events-atomic.html
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-6/igt@kms_async_flips@async-flip-with-page-flip-events-atomic.html
* igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions:
- shard-bmg: ([PASS][4], [PASS][5]) -> [DMESG-WARN][6] +2 other tests dmesg-warn
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-4/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-2/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-6/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html
* igt@xe_pmu@gt-frequency:
- shard-dg2-set2: ([PASS][7], [PASS][8]) -> [FAIL][9]
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-464/igt@xe_pmu@gt-frequency.html
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-434/igt@xe_pmu@gt-frequency.html
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-436/igt@xe_pmu@gt-frequency.html
#### Warnings ####
* igt@xe_exec_queue_property@timeslice_duration_us-property-min-max@rcs:
- shard-lnl: ([PASS][10], [FAIL][11]) -> [FAIL][12] +1 other test fail
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-lnl-8/igt@xe_exec_queue_property@timeslice_duration_us-property-min-max@rcs.html
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-lnl-6/igt@xe_exec_queue_property@timeslice_duration_us-property-min-max@rcs.html
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-lnl-5/igt@xe_exec_queue_property@timeslice_duration_us-property-min-max@rcs.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@xe_pmu@gt-frequency@gt0}:
- shard-dg2-set2: ([PASS][13], [PASS][14]) -> [FAIL][15]
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-434/igt@xe_pmu@gt-frequency@gt0.html
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-464/igt@xe_pmu@gt-frequency@gt0.html
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-436/igt@xe_pmu@gt-frequency@gt0.html
Known issues
------------
Here are the changes found in xe-pw-144506v2_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-b-dp-2-linear:
- shard-bmg: [PASS][16] -> [FAIL][17] ([Intel XE#911]) +2 other tests fail
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-2/igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-b-dp-2-linear.html
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-6/igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-b-dp-2-linear.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-270:
- shard-dg2-set2: NOTRUN -> [SKIP][18] ([Intel XE#1124])
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-463/igt@kms_big_fb@y-tiled-64bpp-rotate-270.html
* igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-6:
- shard-dg2-set2: NOTRUN -> [SKIP][19] ([Intel XE#787]) +81 other tests skip
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-463/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-6.html
* igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs:
- shard-bmg: NOTRUN -> [SKIP][20] ([Intel XE#2887])
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-7/igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs@pipe-d-dp-2:
- shard-dg2-set2: NOTRUN -> [SKIP][21] ([Intel XE#455] / [Intel XE#787]) +15 other tests skip
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-432/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs@pipe-d-dp-2.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-dp-4:
- shard-dg2-set2: [PASS][22] -> [INCOMPLETE][23] ([Intel XE#4212])
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-dp-4.html
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-dp-4.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
- shard-dg2-set2: ([PASS][24], [PASS][25]) -> [INCOMPLETE][26] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#3124] / [Intel XE#4345])
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-dp-4:
- shard-dg2-set2: ([PASS][27], [PASS][28]) -> [INCOMPLETE][29] ([Intel XE#2705] / [Intel XE#4212])
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-dp-4.html
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-dp-4.html
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-dp-4.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-6:
- shard-dg2-set2: [PASS][30] -> [INCOMPLETE][31] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#3124])
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-6.html
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-6.html
* igt@kms_chamelium_color@ctm-0-25:
- shard-dg2-set2: NOTRUN -> [SKIP][32] ([Intel XE#306])
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-463/igt@kms_chamelium_color@ctm-0-25.html
* igt@kms_chamelium_hpd@dp-hpd:
- shard-dg2-set2: NOTRUN -> [SKIP][33] ([Intel XE#373]) +1 other test skip
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-463/igt@kms_chamelium_hpd@dp-hpd.html
* igt@kms_chamelium_hpd@hdmi-hpd-storm-disable:
- shard-bmg: NOTRUN -> [SKIP][34] ([Intel XE#2252])
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-7/igt@kms_chamelium_hpd@hdmi-hpd-storm-disable.html
* igt@kms_content_protection@atomic@pipe-a-dp-4:
- shard-dg2-set2: NOTRUN -> [FAIL][35] ([Intel XE#1178])
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-433/igt@kms_content_protection@atomic@pipe-a-dp-4.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-bmg: ([PASS][36], [PASS][37]) -> [SKIP][38] ([Intel XE#2291]) +3 other tests skip
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-3/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-4/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
- shard-dg2-set2: NOTRUN -> [SKIP][39] ([Intel XE#323])
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-463/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
* igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size:
- shard-lnl: [PASS][40] -> [INCOMPLETE][41] ([Intel XE#3226])
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-lnl-5/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-lnl-2/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions:
- shard-dg2-set2: ([PASS][42], [PASS][43]) -> [SKIP][44] ([Intel XE#309]) +4 other tests skip
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-433/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions.html
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-463/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions.html
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-464/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions.html
* igt@kms_feature_discovery@display-2x:
- shard-bmg: ([PASS][45], [PASS][46]) -> [SKIP][47] ([Intel XE#2373])
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-3/igt@kms_feature_discovery@display-2x.html
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-2/igt@kms_feature_discovery@display-2x.html
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-4/igt@kms_feature_discovery@display-2x.html
* igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible:
- shard-bmg: ([PASS][48], [PASS][49]) -> [SKIP][50] ([Intel XE#2316]) +4 other tests skip
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-3/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-2/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-4/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html
* igt@kms_flip@2x-plain-flip-fb-recreate:
- shard-dg2-set2: ([PASS][51], [PASS][52]) -> [SKIP][53] ([Intel XE#310]) +7 other tests skip
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-463/igt@kms_flip@2x-plain-flip-fb-recreate.html
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-433/igt@kms_flip@2x-plain-flip-fb-recreate.html
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-464/igt@kms_flip@2x-plain-flip-fb-recreate.html
* igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1:
- shard-lnl: ([PASS][54], [PASS][55]) -> [FAIL][56] ([Intel XE#886]) +1 other test fail
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-lnl-5/igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1.html
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-lnl-3/igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1.html
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-lnl-3/igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-bmg: ([PASS][57], [PASS][58]) -> [FAIL][59] ([Intel XE#3321]) +1 other test fail
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp4:
- shard-dg2-set2: ([PASS][60], [PASS][61]) -> [FAIL][62] ([Intel XE#301]) +2 other tests fail
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-434/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp4.html
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-466/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp4.html
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-434/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp4.html
* igt@kms_flip@flip-vs-expired-vblank@a-dp4:
- shard-dg2-set2: ([PASS][63], [PASS][64]) -> [FAIL][65] ([Intel XE#301] / [Intel XE#3321])
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-463/igt@kms_flip@flip-vs-expired-vblank@a-dp4.html
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-466/igt@kms_flip@flip-vs-expired-vblank@a-dp4.html
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-436/igt@kms_flip@flip-vs-expired-vblank@a-dp4.html
* igt@kms_flip@wf_vblank-ts-check-interruptible@c-dp2:
- shard-bmg: [PASS][66] -> [FAIL][67] ([Intel XE#2882]) +1 other test fail
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-7/igt@kms_flip@wf_vblank-ts-check-interruptible@c-dp2.html
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-3/igt@kms_flip@wf_vblank-ts-check-interruptible@c-dp2.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt:
- shard-dg2-set2: ([PASS][68], [PASS][69]) -> [SKIP][70] ([Intel XE#656]) +7 other tests skip
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-463/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-436/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-464/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-tiling-y:
- shard-dg2-set2: NOTRUN -> [SKIP][71] ([Intel XE#658])
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-463/igt@kms_frontbuffer_tracking@fbc-tiling-y.html
* igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-onoff:
- shard-dg2-set2: NOTRUN -> [SKIP][72] ([Intel XE#651]) +4 other tests skip
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-463/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-onoff:
- shard-bmg: NOTRUN -> [SKIP][73] ([Intel XE#2311]) +1 other test skip
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbcpsr-modesetfrombusy:
- shard-dg2-set2: NOTRUN -> [SKIP][74] ([Intel XE#653]) +4 other tests skip
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-463/igt@kms_frontbuffer_tracking@fbcpsr-modesetfrombusy.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt:
- shard-bmg: NOTRUN -> [SKIP][75] ([Intel XE#2313])
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html
* igt@kms_hdr@static-swap:
- shard-bmg: [PASS][76] -> [SKIP][77] ([Intel XE#1503])
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-8/igt@kms_hdr@static-swap.html
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-6/igt@kms_hdr@static-swap.html
* igt@kms_joiner@basic-force-big-joiner:
- shard-dg2-set2: ([PASS][78], [PASS][79]) -> [SKIP][80] ([Intel XE#4328])
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-433/igt@kms_joiner@basic-force-big-joiner.html
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-432/igt@kms_joiner@basic-force-big-joiner.html
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-464/igt@kms_joiner@basic-force-big-joiner.html
* igt@kms_plane_multiple@2x-tiling-4:
- shard-dg2-set2: ([PASS][81], [PASS][82]) -> [SKIP][83] ([Intel XE#4596])
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-436/igt@kms_plane_multiple@2x-tiling-4.html
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-463/igt@kms_plane_multiple@2x-tiling-4.html
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-464/igt@kms_plane_multiple@2x-tiling-4.html
* igt@kms_plane_multiple@2x-tiling-none:
- shard-bmg: ([PASS][84], [PASS][85]) -> [SKIP][86] ([Intel XE#4596])
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-3/igt@kms_plane_multiple@2x-tiling-none.html
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-8/igt@kms_plane_multiple@2x-tiling-none.html
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-4/igt@kms_plane_multiple@2x-tiling-none.html
* igt@kms_pm_rpm@modeset-non-lpsp:
- shard-dg2-set2: ([PASS][87], [PASS][88]) -> [SKIP][89] ([Intel XE#836])
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-436/igt@kms_pm_rpm@modeset-non-lpsp.html
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-463/igt@kms_pm_rpm@modeset-non-lpsp.html
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-464/igt@kms_pm_rpm@modeset-non-lpsp.html
* igt@kms_pm_rpm@system-suspend-modeset:
- shard-bmg: ([PASS][90], [PASS][91]) -> [DMESG-WARN][92] ([Intel XE#3428])
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-4/igt@kms_pm_rpm@system-suspend-modeset.html
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-2/igt@kms_pm_rpm@system-suspend-modeset.html
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-6/igt@kms_pm_rpm@system-suspend-modeset.html
* igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf:
- shard-dg2-set2: NOTRUN -> [SKIP][93] ([Intel XE#1489])
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-463/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf.html
* igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf:
- shard-bmg: NOTRUN -> [SKIP][94] ([Intel XE#1489])
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-7/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf.html
* igt@kms_psr@fbc-pr-cursor-plane-move:
- shard-dg2-set2: NOTRUN -> [SKIP][95] ([Intel XE#2850] / [Intel XE#929]) +1 other test skip
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-463/igt@kms_psr@fbc-pr-cursor-plane-move.html
* igt@kms_psr@psr-cursor-blt:
- shard-bmg: NOTRUN -> [SKIP][96] ([Intel XE#2234] / [Intel XE#2850])
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-7/igt@kms_psr@psr-cursor-blt.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-dg2-set2: NOTRUN -> [SKIP][97] ([Intel XE#2939])
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-463/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@kms_setmode@basic@pipe-a-hdmi-a-6:
- shard-dg2-set2: ([PASS][98], [PASS][99]) -> [FAIL][100] ([Intel XE#2883]) +1 other test fail
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-434/igt@kms_setmode@basic@pipe-a-hdmi-a-6.html
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-466/igt@kms_setmode@basic@pipe-a-hdmi-a-6.html
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-434/igt@kms_setmode@basic@pipe-a-hdmi-a-6.html
* igt@kms_setmode@clone-exclusive-crtc:
- shard-dg2-set2: ([PASS][101], [PASS][102]) -> [SKIP][103] ([Intel XE#455])
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-433/igt@kms_setmode@clone-exclusive-crtc.html
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-432/igt@kms_setmode@clone-exclusive-crtc.html
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-464/igt@kms_setmode@clone-exclusive-crtc.html
* igt@kms_setmode@invalid-clone-single-crtc-stealing:
- shard-bmg: ([PASS][104], [PASS][105]) -> [SKIP][106] ([Intel XE#1435])
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-8/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-3/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-4/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
* igt@kms_writeback@writeback-check-output-xrgb2101010:
- shard-dg2-set2: NOTRUN -> [SKIP][107] ([Intel XE#756])
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-463/igt@kms_writeback@writeback-check-output-xrgb2101010.html
* igt@xe_eudebug@basic-vm-access-parameters-userptr:
- shard-bmg: NOTRUN -> [SKIP][108] ([Intel XE#2905] / [Intel XE#3889])
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-7/igt@xe_eudebug@basic-vm-access-parameters-userptr.html
* igt@xe_eudebug@discovery-empty:
- shard-dg2-set2: NOTRUN -> [SKIP][109] ([Intel XE#2905]) +2 other tests skip
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-463/igt@xe_eudebug@discovery-empty.html
* igt@xe_exec_basic@multigpu-many-execqueues-many-vm-basic-defer-mmap:
- shard-dg2-set2: ([PASS][110], [PASS][111]) -> [SKIP][112] ([Intel XE#1392]) +2 other tests skip
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-463/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-basic-defer-mmap.html
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-464/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-basic-defer-mmap.html
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-432/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-basic-defer-mmap.html
* igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate-race:
- shard-dg2-set2: [PASS][113] -> [SKIP][114] ([Intel XE#1392]) +2 other tests skip
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-464/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate-race.html
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-432/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate-race.html
* igt@xe_exec_fault_mode@once-userptr:
- shard-dg2-set2: NOTRUN -> [SKIP][115] ([Intel XE#288]) +4 other tests skip
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-463/igt@xe_exec_fault_mode@once-userptr.html
* igt@xe_media_fill@media-fill:
- shard-dg2-set2: NOTRUN -> [SKIP][116] ([Intel XE#560])
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-463/igt@xe_media_fill@media-fill.html
* igt@xe_oa@disabled-read-error:
- shard-dg2-set2: NOTRUN -> [SKIP][117] ([Intel XE#2541] / [Intel XE#3573])
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-463/igt@xe_oa@disabled-read-error.html
* igt@xe_pm_residency@cpg-basic:
- shard-bmg: [PASS][118] -> [DMESG-WARN][119] ([Intel XE#3428]) +7 other tests dmesg-warn
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-8/igt@xe_pm_residency@cpg-basic.html
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-6/igt@xe_pm_residency@cpg-basic.html
* igt@xe_pxp@pxp-stale-bo-bind-post-rpm:
- shard-dg2-set2: NOTRUN -> [SKIP][120] ([Intel XE#4733])
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-463/igt@xe_pxp@pxp-stale-bo-bind-post-rpm.html
* igt@xe_pxp@pxp-termination-key-update-post-suspend:
- shard-bmg: NOTRUN -> [SKIP][121] ([Intel XE#4733])
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-7/igt@xe_pxp@pxp-termination-key-update-post-suspend.html
* igt@xe_query@multigpu-query-invalid-cs-cycles:
- shard-dg2-set2: NOTRUN -> [SKIP][122] ([Intel XE#944])
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-463/igt@xe_query@multigpu-query-invalid-cs-cycles.html
#### Possible fixes ####
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
- shard-adlp: ([PASS][123], [DMESG-FAIL][124]) ([Intel XE#4543]) -> [PASS][125] +2 other tests pass
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-adlp-1/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-adlp-8/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
[125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-adlp-4/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
* igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p:
- shard-dg2-set2: ([PASS][126], [SKIP][127]) ([Intel XE#2191]) -> [PASS][128]
[126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-463/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html
[127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-464/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html
[128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-432/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html
- shard-bmg: [SKIP][129] ([Intel XE#2314] / [Intel XE#2894]) -> [PASS][130]
[129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-4/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html
[130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-6/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs:
- shard-dg2-set2: ([PASS][131], [INCOMPLETE][132]) ([Intel XE#3862]) -> [PASS][133]
[131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-436/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs.html
[132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-432/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs.html
[133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-464/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs.html
* igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
- shard-bmg: ([SKIP][134], [PASS][135]) ([Intel XE#2291]) -> [PASS][136] +1 other test pass
[134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-4/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html
[135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-1/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html
[136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-2/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@cursora-vs-flipb-varying-size:
- shard-bmg: [SKIP][137] ([Intel XE#2291]) -> [PASS][138]
[137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-4/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html
[138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-6/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
- shard-dg2-set2: [SKIP][139] ([Intel XE#309]) -> [PASS][140] +1 other test pass
[139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-464/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
[140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-433/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-toggle:
- shard-dg2-set2: ([SKIP][141], [PASS][142]) ([Intel XE#309]) -> [PASS][143] +4 other tests pass
[141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-464/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html
[142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-436/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html
[143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-436/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc:
- shard-bmg: [SKIP][144] ([Intel XE#1340]) -> [PASS][145]
[144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-6/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
[145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-7/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
* igt@kms_dp_link_training@non-uhbr-sst:
- shard-bmg: ([PASS][146], [SKIP][147]) ([Intel XE#4354]) -> [PASS][148]
[146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-2/igt@kms_dp_link_training@non-uhbr-sst.html
[147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-4/igt@kms_dp_link_training@non-uhbr-sst.html
[148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-6/igt@kms_dp_link_training@non-uhbr-sst.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-dg2-set2: ([FAIL][149], [PASS][150]) ([Intel XE#4164]) -> [PASS][151]
[149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-464/igt@kms_fbcon_fbt@fbc-suspend.html
[150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-434/igt@kms_fbcon_fbt@fbc-suspend.html
[151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-436/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bd-dp2-hdmi-a3:
- shard-bmg: [FAIL][152] ([Intel XE#3321]) -> [PASS][153] +2 other tests pass
[152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-7/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bd-dp2-hdmi-a3.html
[153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-3/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bd-dp2-hdmi-a3.html
* igt@kms_flip@2x-modeset-vs-vblank-race:
- shard-dg2-set2: ([SKIP][154], [PASS][155]) ([Intel XE#310]) -> [PASS][156] +1 other test pass
[154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-464/igt@kms_flip@2x-modeset-vs-vblank-race.html
[155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-434/igt@kms_flip@2x-modeset-vs-vblank-race.html
[156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-436/igt@kms_flip@2x-modeset-vs-vblank-race.html
* igt@kms_flip@2x-modeset-vs-vblank-race-interruptible:
- shard-bmg: ([SKIP][157], [PASS][158]) ([Intel XE#2316]) -> [PASS][159] +3 other tests pass
[157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-4/igt@kms_flip@2x-modeset-vs-vblank-race-interruptible.html
[158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-2/igt@kms_flip@2x-modeset-vs-vblank-race-interruptible.html
[159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-6/igt@kms_flip@2x-modeset-vs-vblank-race-interruptible.html
* igt@kms_flip@2x-nonexisting-fb-interruptible:
- shard-dg2-set2: [SKIP][160] ([Intel XE#310]) -> [PASS][161] +4 other tests pass
[160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-464/igt@kms_flip@2x-nonexisting-fb-interruptible.html
[161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-432/igt@kms_flip@2x-nonexisting-fb-interruptible.html
* igt@kms_flip@2x-plain-flip:
- shard-bmg: [SKIP][162] ([Intel XE#2316]) -> [PASS][163]
[162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-6/igt@kms_flip@2x-plain-flip.html
[163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-7/igt@kms_flip@2x-plain-flip.html
* igt@kms_flip@blocking-wf_vblank:
- shard-adlp: [FAIL][164] ([Intel XE#2882]) -> [PASS][165]
[164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-adlp-9/igt@kms_flip@blocking-wf_vblank.html
[165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-adlp-1/igt@kms_flip@blocking-wf_vblank.html
* igt@kms_flip@blocking-wf_vblank@a-hdmi-a1:
- shard-adlp: ([PASS][166], [FAIL][167]) ([Intel XE#2882]) -> [PASS][168]
[166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-adlp-8/igt@kms_flip@blocking-wf_vblank@a-hdmi-a1.html
[167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-adlp-9/igt@kms_flip@blocking-wf_vblank@a-hdmi-a1.html
[168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-adlp-1/igt@kms_flip@blocking-wf_vblank@a-hdmi-a1.html
* igt@kms_flip@flip-vs-blocking-wf-vblank:
- shard-bmg: ([PASS][169], [FAIL][170]) ([Intel XE#2882]) -> [PASS][171] +2 other tests pass
[169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-1/igt@kms_flip@flip-vs-blocking-wf-vblank.html
[170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-4/igt@kms_flip@flip-vs-blocking-wf-vblank.html
[171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-2/igt@kms_flip@flip-vs-blocking-wf-vblank.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@d-dp4:
- shard-dg2-set2: ([PASS][172], [FAIL][173]) ([Intel XE#301]) -> [PASS][174] +2 other tests pass
[172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-466/igt@kms_flip@flip-vs-expired-vblank-interruptible@d-dp4.html
[173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-434/igt@kms_flip@flip-vs-expired-vblank-interruptible@d-dp4.html
[174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-434/igt@kms_flip@flip-vs-expired-vblank-interruptible@d-dp4.html
* igt@kms_flip@flip-vs-expired-vblank@c-dp4:
- shard-dg2-set2: ([PASS][175], [FAIL][176]) ([Intel XE#301] / [Intel XE#3321]) -> [PASS][177]
[175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-463/igt@kms_flip@flip-vs-expired-vblank@c-dp4.html
[176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-466/igt@kms_flip@flip-vs-expired-vblank@c-dp4.html
[177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-436/igt@kms_flip@flip-vs-expired-vblank@c-dp4.html
* igt@kms_flip@flip-vs-expired-vblank@d-dp4:
- shard-dg2-set2: ([FAIL][178], [FAIL][179]) ([Intel XE#301] / [Intel XE#3321]) -> [PASS][180]
[178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-466/igt@kms_flip@flip-vs-expired-vblank@d-dp4.html
[179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-463/igt@kms_flip@flip-vs-expired-vblank@d-dp4.html
[180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-436/igt@kms_flip@flip-vs-expired-vblank@d-dp4.html
* igt@kms_flip@flip-vs-expired-vblank@d-hdmi-a6:
- shard-dg2-set2: ([FAIL][181], [FAIL][182]) ([Intel XE#301]) -> [PASS][183]
[181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-463/igt@kms_flip@flip-vs-expired-vblank@d-hdmi-a6.html
[182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-466/igt@kms_flip@flip-vs-expired-vblank@d-hdmi-a6.html
[183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-436/igt@kms_flip@flip-vs-expired-vblank@d-hdmi-a6.html
* igt@kms_flip@flip-vs-suspend:
- shard-dg2-set2: ([PASS][184], [INCOMPLETE][185]) ([Intel XE#2049] / [Intel XE#2597]) -> [PASS][186]
[184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-433/igt@kms_flip@flip-vs-suspend.html
[185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-432/igt@kms_flip@flip-vs-suspend.html
[186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-434/igt@kms_flip@flip-vs-suspend.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-dg2-set2: ([INCOMPLETE][187], [INCOMPLETE][188]) ([Intel XE#2049] / [Intel XE#2597]) -> [PASS][189] +1 other test pass
[187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-434/igt@kms_flip@flip-vs-suspend-interruptible.html
[188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-436/igt@kms_flip@flip-vs-suspend-interruptible.html
[189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-463/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_flip@wf_vblank-ts-check-interruptible@a-edp1:
- shard-lnl: ([FAIL][190], [FAIL][191]) ([Intel XE#886]) -> [PASS][192] +1 other test pass
[190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-lnl-2/igt@kms_flip@wf_vblank-ts-check-interruptible@a-edp1.html
[191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-lnl-5/igt@kms_flip@wf_vblank-ts-check-interruptible@a-edp1.html
[192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-lnl-2/igt@kms_flip@wf_vblank-ts-check-interruptible@a-edp1.html
* igt@kms_flip@wf_vblank-ts-check-interruptible@b-edp1:
- shard-lnl: ([FAIL][193], [PASS][194]) ([Intel XE#886]) -> [PASS][195]
[193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-lnl-2/igt@kms_flip@wf_vblank-ts-check-interruptible@b-edp1.html
[194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-lnl-5/igt@kms_flip@wf_vblank-ts-check-interruptible@b-edp1.html
[195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-lnl-2/igt@kms_flip@wf_vblank-ts-check-interruptible@b-edp1.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-onoff:
- shard-dg2-set2: [SKIP][196] ([Intel XE#656]) -> [PASS][197] +4 other tests pass
[196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-464/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-onoff.html
[197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-433/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
- shard-dg2-set2: ([SKIP][198], [PASS][199]) ([Intel XE#656]) -> [PASS][200] +4 other tests pass
[198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-464/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html
[199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-463/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html
[200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-432/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_hdr@invalid-hdr:
- shard-dg2-set2: ([SKIP][201], [SKIP][202]) ([Intel XE#455]) -> [PASS][203]
[201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-466/igt@kms_hdr@invalid-hdr.html
[202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-436/igt@kms_hdr@invalid-hdr.html
[203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-463/igt@kms_hdr@invalid-hdr.html
* igt@kms_hdr@invalid-metadata-sizes:
- shard-bmg: [SKIP][204] ([Intel XE#1503]) -> [PASS][205]
[204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-4/igt@kms_hdr@invalid-metadata-sizes.html
[205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-6/igt@kms_hdr@invalid-metadata-sizes.html
* igt@kms_joiner@invalid-modeset-force-big-joiner:
- shard-bmg: ([SKIP][206], [PASS][207]) ([Intel XE#3012]) -> [PASS][208]
[206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-4/igt@kms_joiner@invalid-modeset-force-big-joiner.html
[207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-3/igt@kms_joiner@invalid-modeset-force-big-joiner.html
[208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-8/igt@kms_joiner@invalid-modeset-force-big-joiner.html
* igt@kms_pm_rpm@basic-pci-d3-state:
- shard-dg2-set2: ([FAIL][209], [PASS][210]) ([Intel XE#4741]) -> [PASS][211]
[209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-463/igt@kms_pm_rpm@basic-pci-d3-state.html
[210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-433/igt@kms_pm_rpm@basic-pci-d3-state.html
[211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-432/igt@kms_pm_rpm@basic-pci-d3-state.html
* igt@kms_pm_rpm@dpms-non-lpsp:
- shard-dg2-set2: [SKIP][212] ([Intel XE#836]) -> [PASS][213]
[212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-464/igt@kms_pm_rpm@dpms-non-lpsp.html
[213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-433/igt@kms_pm_rpm@dpms-non-lpsp.html
* igt@kms_pm_rpm@legacy-planes-dpms@plane-68:
- shard-bmg: ([PASS][214], [DMESG-WARN][215]) ([Intel XE#3428]) -> [PASS][216] +2 other tests pass
[214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-8/igt@kms_pm_rpm@legacy-planes-dpms@plane-68.html
[215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-6/igt@kms_pm_rpm@legacy-planes-dpms@plane-68.html
[216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-1/igt@kms_pm_rpm@legacy-planes-dpms@plane-68.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-dg2-set2: ([SKIP][217], [PASS][218]) ([Intel XE#836]) -> [PASS][219]
[217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-464/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
[218]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-436/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
[219]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-436/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@kms_vblank@ts-continuation-suspend:
- shard-adlp: ([PASS][220], [DMESG-WARN][221]) ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][222] +2 other tests pass
[220]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-adlp-6/igt@kms_vblank@ts-continuation-suspend.html
[221]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-adlp-4/igt@kms_vblank@ts-continuation-suspend.html
[222]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-adlp-6/igt@kms_vblank@ts-continuation-suspend.html
* igt@kms_vrr@cmrr@pipe-a-edp-1:
- shard-lnl: ([FAIL][223], [PASS][224]) ([Intel XE#4459]) -> [PASS][225] +1 other test pass
[223]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-lnl-6/igt@kms_vrr@cmrr@pipe-a-edp-1.html
[224]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-lnl-8/igt@kms_vrr@cmrr@pipe-a-edp-1.html
[225]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-lnl-5/igt@kms_vrr@cmrr@pipe-a-edp-1.html
* igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-rebind:
- shard-dg2-set2: ([PASS][226], [SKIP][227]) ([Intel XE#1392]) -> [PASS][228] +6 other tests pass
[226]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-436/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-rebind.html
[227]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-432/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-rebind.html
[228]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-464/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-rebind.html
* igt@xe_exec_threads@threads-hang-userptr-invalidate:
- shard-bmg: [DMESG-WARN][229] ([Intel XE#3428]) -> [PASS][230] +2 other tests pass
[229]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-6/igt@xe_exec_threads@threads-hang-userptr-invalidate.html
[230]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-7/igt@xe_exec_threads@threads-hang-userptr-invalidate.html
* igt@xe_fault_injection@vm-create-fail-xe_vm_create_scratch:
- shard-adlp: ([PASS][231], [DMESG-WARN][232]) ([Intel XE#4173]) -> [PASS][233] +6 other tests pass
[231]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-adlp-1/igt@xe_fault_injection@vm-create-fail-xe_vm_create_scratch.html
[232]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-adlp-3/igt@xe_fault_injection@vm-create-fail-xe_vm_create_scratch.html
[233]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-adlp-3/igt@xe_fault_injection@vm-create-fail-xe_vm_create_scratch.html
* igt@xe_module_load@load:
- shard-dg2-set2: ([PASS][234], [PASS][235], [PASS][236], [PASS][237], [PASS][238], [PASS][239], [PASS][240], [PASS][241], [PASS][242], [PASS][243], [PASS][244], [PASS][245], [PASS][246], [PASS][247], [PASS][248], [PASS][249], [PASS][250], [PASS][251], [SKIP][252], [PASS][253], [PASS][254], [PASS][255], [PASS][256], [PASS][257], [PASS][258], [PASS][259], [PASS][260], [PASS][261], [PASS][262], [PASS][263], [PASS][264], [PASS][265], [PASS][266], [PASS][267], [PASS][268], [PASS][269], [PASS][270], [PASS][271], [PASS][272], [PASS][273], [PASS][274], [PASS][275], [PASS][276], [PASS][277], [PASS][278], [PASS][279], [PASS][280], [PASS][281]) ([Intel XE#378]) -> ([PASS][282], [PASS][283], [PASS][284], [PASS][285], [PASS][286], [PASS][287], [PASS][288], [PASS][289], [PASS][290], [PASS][291], [PASS][292], [PASS][293], [PASS][294], [PASS][295], [PASS][296], [PASS][297], [PASS][298], [PASS][299], [PASS][300], [PASS][301], [PASS][302], [PASS][303], [PASS][304], [PASS][305], [PASS][306])
[234]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-463/igt@xe_module_load@load.html
[235]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-463/igt@xe_module_load@load.html
[236]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-464/igt@xe_module_load@load.html
[237]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-464/igt@xe_module_load@load.html
[238]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-463/igt@xe_module_load@load.html
[239]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-436/igt@xe_module_load@load.html
[240]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-436/igt@xe_module_load@load.html
[241]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-464/igt@xe_module_load@load.html
[242]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-464/igt@xe_module_load@load.html
[243]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-433/igt@xe_module_load@load.html
[244]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-432/igt@xe_module_load@load.html
[245]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-432/igt@xe_module_load@load.html
[246]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-436/igt@xe_module_load@load.html
[247]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-436/igt@xe_module_load@load.html
[248]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-436/igt@xe_module_load@load.html
[249]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-464/igt@xe_module_load@load.html
[250]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-434/igt@xe_module_load@load.html
[251]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-432/igt@xe_module_load@load.html
[252]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-432/igt@xe_module_load@load.html
[253]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-432/igt@xe_module_load@load.html
[254]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-433/igt@xe_module_load@load.html
[255]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-433/igt@xe_module_load@load.html
[256]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-466/igt@xe_module_load@load.html
[257]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-463/igt@xe_module_load@load.html
[258]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-464/igt@xe_module_load@load.html
[259]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-466/igt@xe_module_load@load.html
[260]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-466/igt@xe_module_load@load.html
[261]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-463/igt@xe_module_load@load.html
[262]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-434/igt@xe_module_load@load.html
[263]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-434/igt@xe_module_load@load.html
[264]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-463/igt@xe_module_load@load.html
[265]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-433/igt@xe_module_load@load.html
[266]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-433/igt@xe_module_load@load.html
[267]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-436/igt@xe_module_load@load.html
[268]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-436/igt@xe_module_load@load.html
[269]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-466/igt@xe_module_load@load.html
[270]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-434/igt@xe_module_load@load.html
[271]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-434/igt@xe_module_load@load.html
[272]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-434/igt@xe_module_load@load.html
[273]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-434/igt@xe_module_load@load.html
[274]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-432/igt@xe_module_load@load.html
[275]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-433/igt@xe_module_load@load.html
[276]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-466/igt@xe_module_load@load.html
[277]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-466/igt@xe_module_load@load.html
[278]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-466/igt@xe_module_load@load.html
[279]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-463/igt@xe_module_load@load.html
[280]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-463/igt@xe_module_load@load.html
[281]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-434/igt@xe_module_load@load.html
[282]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-434/igt@xe_module_load@load.html
[283]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-434/igt@xe_module_load@load.html
[284]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-432/igt@xe_module_load@load.html
[285]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-432/igt@xe_module_load@load.html
[286]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-463/igt@xe_module_load@load.html
[287]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-463/igt@xe_module_load@load.html
[288]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-436/igt@xe_module_load@load.html
[289]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-436/igt@xe_module_load@load.html
[290]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-436/igt@xe_module_load@load.html
[291]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-436/igt@xe_module_load@load.html
[292]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-436/igt@xe_module_load@load.html
[293]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-433/igt@xe_module_load@load.html
[294]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-433/igt@xe_module_load@load.html
[295]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-432/igt@xe_module_load@load.html
[296]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-433/igt@xe_module_load@load.html
[297]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-434/igt@xe_module_load@load.html
[298]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-434/igt@xe_module_load@load.html
[299]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-433/igt@xe_module_load@load.html
[300]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-463/igt@xe_module_load@load.html
[301]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-464/igt@xe_module_load@load.html
[302]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-464/igt@xe_module_load@load.html
[303]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-432/igt@xe_module_load@load.html
[304]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-464/igt@xe_module_load@load.html
[305]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-464/igt@xe_module_load@load.html
[306]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-464/igt@xe_module_load@load.html
* igt@xe_oa@buffer-fill@rcs-0:
- shard-lnl: ([FAIL][307], [PASS][308]) ([Intel XE#4565]) -> [PASS][309] +1 other test pass
[307]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-lnl-2/igt@xe_oa@buffer-fill@rcs-0.html
[308]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-lnl-8/igt@xe_oa@buffer-fill@rcs-0.html
[309]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-lnl-8/igt@xe_oa@buffer-fill@rcs-0.html
* igt@xe_pm@s4-mocs:
- shard-lnl: ([ABORT][310], [PASS][311]) ([Intel XE#1794]) -> [PASS][312]
[310]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-lnl-2/igt@xe_pm@s4-mocs.html
[311]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-lnl-5/igt@xe_pm@s4-mocs.html
[312]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-lnl-1/igt@xe_pm@s4-mocs.html
* igt@xe_pm@s4-vm-bind-prefetch:
- shard-adlp: ([ABORT][313], [PASS][314]) ([Intel XE#1794]) -> [PASS][315]
[313]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-adlp-9/igt@xe_pm@s4-vm-bind-prefetch.html
[314]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-adlp-8/igt@xe_pm@s4-vm-bind-prefetch.html
[315]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-adlp-1/igt@xe_pm@s4-vm-bind-prefetch.html
#### Warnings ####
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-adlp: ([DMESG-FAIL][316], [DMESG-FAIL][317]) ([Intel XE#4173] / [Intel XE#4543]) -> [DMESG-FAIL][318] ([Intel XE#4543])
[316]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-adlp-1/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
[317]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-adlp-3/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
[318]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-adlp-3/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_ccs@bad-rotation-90-y-tiled-gen12-mc-ccs@pipe-d-hdmi-a-6:
- shard-dg2-set2: ([SKIP][319], [SKIP][320]) ([Intel XE#787]) -> [SKIP][321] ([Intel XE#455] / [Intel XE#787]) +10 other tests skip
[319]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-433/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-mc-ccs@pipe-d-hdmi-a-6.html
[320]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-463/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-mc-ccs@pipe-d-hdmi-a-6.html
[321]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-464/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-mc-ccs@pipe-d-hdmi-a-6.html
* igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-6:
- shard-dg2-set2: [SKIP][322] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][323] ([Intel XE#787]) +3 other tests skip
[322]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-464/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-6.html
[323]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-433/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-6.html
* igt@kms_ccs@crc-primary-suspend-y-tiled-ccs@pipe-d-hdmi-a-6:
- shard-dg2-set2: [SKIP][324] ([Intel XE#787]) -> [SKIP][325] ([Intel XE#455] / [Intel XE#787]) +5 other tests skip
[324]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-433/igt@kms_ccs@crc-primary-suspend-y-tiled-ccs@pipe-d-hdmi-a-6.html
[325]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-464/igt@kms_ccs@crc-primary-suspend-y-tiled-ccs@pipe-d-hdmi-a-6.html
* igt@kms_ccs@crc-sprite-planes-basic-y-tiled-ccs@pipe-d-hdmi-a-6:
- shard-dg2-set2: ([SKIP][326], [SKIP][327]) ([Intel XE#455] / [Intel XE#787]) -> [SKIP][328] ([Intel XE#787]) +6 other tests skip
[326]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-464/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-ccs@pipe-d-hdmi-a-6.html
[327]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-434/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-ccs@pipe-d-hdmi-a-6.html
[328]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-436/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-ccs@pipe-d-hdmi-a-6.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
- shard-dg2-set2: ([INCOMPLETE][329], [PASS][330]) ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#3124]) -> [INCOMPLETE][331] ([Intel XE#2705] / [Intel XE#4212] / [Intel XE#4345])
[329]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
[330]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
[331]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
- shard-dg2-set2: ([PASS][332], [INCOMPLETE][333]) ([Intel XE#2705] / [Intel XE#4212] / [Intel XE#4522]) -> [INCOMPLETE][334] ([Intel XE#2705] / [Intel XE#4212])
[332]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
[333]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
[334]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
* igt@kms_cdclk@mode-transition-all-outputs:
- shard-dg2-set2: ([SKIP][335], [SKIP][336]) ([Intel XE#4418]) -> [SKIP][337] ([Intel XE#4440])
[335]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-433/igt@kms_cdclk@mode-transition-all-outputs.html
[336]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-432/igt@kms_cdclk@mode-transition-all-outputs.html
[337]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-464/igt@kms_cdclk@mode-transition-all-outputs.html
* igt@kms_content_protection@atomic:
- shard-dg2-set2: [SKIP][338] ([Intel XE#455]) -> [FAIL][339] ([Intel XE#1178])
[338]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-464/igt@kms_content_protection@atomic.html
[339]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-433/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@legacy:
- shard-dg2-set2: ([SKIP][340], [FAIL][341]) ([Intel XE#1178] / [Intel XE#455]) -> [FAIL][342] ([Intel XE#1178])
[340]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-464/igt@kms_content_protection@legacy.html
[341]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-436/igt@kms_content_protection@legacy.html
[342]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-436/igt@kms_content_protection@legacy.html
* igt@kms_content_protection@lic-type-0@pipe-a-dp-2:
- shard-bmg: [TIMEOUT][343] -> [FAIL][344] ([Intel XE#1178]) +1 other test fail
[343]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-6/igt@kms_content_protection@lic-type-0@pipe-a-dp-2.html
[344]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-7/igt@kms_content_protection@lic-type-0@pipe-a-dp-2.html
* igt@kms_content_protection@srm:
- shard-dg2-set2: ([FAIL][345], [FAIL][346]) ([Intel XE#1178]) -> [SKIP][347] ([Intel XE#455])
[345]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-436/igt@kms_content_protection@srm.html
[346]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-432/igt@kms_content_protection@srm.html
[347]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-464/igt@kms_content_protection@srm.html
* igt@kms_content_protection@uevent:
- shard-dg2-set2: ([FAIL][348], [FAIL][349]) ([Intel XE#1188]) -> [SKIP][350] ([Intel XE#455])
[348]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-463/igt@kms_content_protection@uevent.html
[349]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-466/igt@kms_content_protection@uevent.html
[350]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-464/igt@kms_content_protection@uevent.html
* igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic:
- shard-bmg: ([PASS][351], [SKIP][352]) ([Intel XE#2291]) -> [SKIP][353] ([Intel XE#2291]) +1 other test skip
[351]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-1/igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic.html
[352]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-4/igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic.html
[353]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-4/igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-dg2-set2: ([FAIL][354], [PASS][355]) ([Intel XE#301]) -> [SKIP][356] ([Intel XE#310])
[354]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-432/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
[355]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-433/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
[356]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-464/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@2x-plain-flip-ts-check-interruptible:
- shard-bmg: ([PASS][357], [SKIP][358]) ([Intel XE#2316]) -> [SKIP][359] ([Intel XE#2316]) +4 other tests skip
[357]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-1/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html
[358]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-4/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html
[359]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-4/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-dg2-set2: ([PASS][360], [FAIL][361]) ([Intel XE#301]) -> [FAIL][362] ([Intel XE#301]) +3 other tests fail
[360]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-466/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[361]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-434/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[362]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-434/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank@b-dp4:
- shard-dg2-set2: ([PASS][363], [FAIL][364]) ([Intel XE#301] / [Intel XE#3321]) -> [FAIL][365] ([Intel XE#301] / [Intel XE#3321])
[363]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-463/igt@kms_flip@flip-vs-expired-vblank@b-dp4.html
[364]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-466/igt@kms_flip@flip-vs-expired-vblank@b-dp4.html
[365]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-436/igt@kms_flip@flip-vs-expired-vblank@b-dp4.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-blt:
- shard-bmg: ([SKIP][366], [SKIP][367]) ([Intel XE#2311] / [Intel XE#2312]) -> [SKIP][368] ([Intel XE#2311]) +5 other tests skip
[366]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-blt.html
[367]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-blt.html
[368]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-render:
- shard-bmg: ([SKIP][369], [SKIP][370]) ([Intel XE#2311] / [Intel XE#2312]) -> [SKIP][371] ([Intel XE#2312]) +8 other tests skip
[369]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-1/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-render.html
[370]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-render.html
[371]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-onoff:
- shard-dg2-set2: ([SKIP][372], [SKIP][373]) ([Intel XE#651]) -> [SKIP][374] ([Intel XE#656]) +17 other tests skip
[372]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-466/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-onoff.html
[373]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-463/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-onoff.html
[374]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-464/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-onoff.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-move:
- shard-bmg: [SKIP][375] ([Intel XE#2311]) -> [SKIP][376] ([Intel XE#2312])
[375]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-8/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-move.html
[376]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-move.html
* igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-draw-render:
- shard-bmg: [SKIP][377] ([Intel XE#2312]) -> [SKIP][378] ([Intel XE#2311]) +3 other tests skip
[377]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-draw-render.html
[378]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-render:
- shard-dg2-set2: ([SKIP][379], [SKIP][380]) ([Intel XE#651] / [Intel XE#656]) -> [SKIP][381] ([Intel XE#651]) +10 other tests skip
[379]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-464/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-render.html
[380]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-436/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-render.html
[381]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-436/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc:
- shard-bmg: ([SKIP][382], [SKIP][383]) ([Intel XE#2312] / [Intel XE#4141]) -> [SKIP][384] ([Intel XE#4141]) +2 other tests skip
[382]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html
[383]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html
[384]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-pgflip-blt:
- shard-bmg: ([SKIP][385], [SKIP][386]) ([Intel XE#2312] / [Intel XE#4141]) -> [SKIP][387] ([Intel XE#2312]) +2 other tests skip
[385]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-pgflip-blt.html
[386]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-pgflip-blt.html
[387]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render:
- shard-bmg: ([SKIP][388], [SKIP][389]) ([Intel XE#4141]) -> [SKIP][390] ([Intel XE#2312]) +3 other tests skip
[388]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html
[389]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html
[390]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][391] ([Intel XE#2312]) -> [SKIP][392] ([Intel XE#4141]) +3 other tests skip
[391]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html
[392]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc:
- shard-bmg: ([SKIP][393], [SKIP][394]) ([Intel XE#2311]) -> [SKIP][395] ([Intel XE#2312]) +7 other tests skip
[393]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html
[394]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html
[395]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-plflip-blt:
- shard-dg2-set2: [SKIP][396] ([Intel XE#656]) -> [SKIP][397] ([Intel XE#651]) +8 other tests skip
[396]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-plflip-blt.html
[397]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-433/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-wc:
- shard-bmg: ([SKIP][398], [SKIP][399]) ([Intel XE#2312] / [Intel XE#2313]) -> [SKIP][400] ([Intel XE#2312]) +7 other tests skip
[398]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-wc.html
[399]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-wc.html
[400]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-plflip-blt:
- shard-bmg: ([SKIP][401], [SKIP][402]) ([Intel XE#2313]) -> [SKIP][403] ([Intel XE#2312]) +6 other tests skip
[401]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-plflip-blt.html
[402]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-plflip-blt.html
[403]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-wc:
- shard-dg2-set2: ([SKIP][404], [SKIP][405]) ([Intel XE#653]) -> [SKIP][406] ([Intel XE#656]) +16 other tests skip
[404]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-436/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-wc.html
[405]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-463/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-wc.html
[406]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt:
- shard-bmg: [SKIP][407] ([Intel XE#2312]) -> [SKIP][408] ([Intel XE#2313]) +6 other tests skip
[407]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-4/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
[408]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-pgflip-blt:
- shard-dg2-set2: [SKIP][409] ([Intel XE#656]) -> [SKIP][410] ([Intel XE#653]) +7 other tests skip
[409]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-464/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-pgflip-blt.html
[410]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-433/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-plflip-blt:
- shard-dg2-set2: ([SKIP][411], [SKIP][412]) ([Intel XE#653] / [Intel XE#656]) -> [SKIP][413] ([Intel XE#653]) +10 other tests skip
[411]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-434/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-plflip-blt.html
[412]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-464/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-plflip-blt.html
[413]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-436/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc:
- shard-bmg: ([SKIP][414], [SKIP][415]) ([Intel XE#2312] / [Intel XE#2313]) -> [SKIP][416] ([Intel XE#2313]) +4 other tests skip
[414]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-2/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc.html
[415]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-bmg-4/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc.html
[416]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-dg2-set2: ([FAIL][417], [FAIL][418]) ([Intel XE#1729]) -> [SKIP][419] ([Intel XE#362])
[417]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-432/igt@kms_tiled_display@basic-test-pattern.html
[418]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-436/igt@kms_tiled_display@basic-test-pattern.html
[419]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-464/igt@kms_tiled_display@basic-test-pattern.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-dg2-set2: ([SKIP][420], [SKIP][421]) ([Intel XE#1500] / [Intel XE#362]) -> [SKIP][422] ([Intel XE#1500])
[420]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-434/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
[421]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-464/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
[422]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-436/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@xe_exec_basic@multigpu-once-basic-defer-mmap:
- shard-dg2-set2: ([PASS][423], [SKIP][424]) ([Intel XE#1392]) -> [SKIP][425] ([Intel XE#1392]) +2 other tests skip
[423]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-433/igt@xe_exec_basic@multigpu-once-basic-defer-mmap.html
[424]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-432/igt@xe_exec_basic@multigpu-once-basic-defer-mmap.html
[425]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-432/igt@xe_exec_basic@multigpu-once-basic-defer-mmap.html
* igt@xe_exec_queue_property@timeslice_duration_us-property-min-max:
- shard-lnl: ([PASS][426], [ABORT][427]) ([Intel XE#4624]) -> [ABORT][428] ([Intel XE#4624]) +1 other test abort
[426]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-lnl-8/igt@xe_exec_queue_property@timeslice_duration_us-property-min-max.html
[427]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-lnl-6/igt@xe_exec_queue_property@timeslice_duration_us-property-min-max.html
[428]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-lnl-5/igt@xe_exec_queue_property@timeslice_duration_us-property-min-max.html
* igt@xe_fault_injection@inject-fault-probe-function-xe_guc_ads_init:
- shard-adlp: ([PASS][429], [DMESG-WARN][430]) ([Intel XE#4173]) -> [DMESG-WARN][431] ([Intel XE#4173])
[429]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-adlp-1/igt@xe_fault_injection@inject-fault-probe-function-xe_guc_ads_init.html
[430]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-adlp-3/igt@xe_fault_injection@inject-fault-probe-function-xe_guc_ads_init.html
[431]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-adlp-3/igt@xe_fault_injection@inject-fault-probe-function-xe_guc_ads_init.html
* igt@xe_live_ktest@xe_mocs@xe_live_mocs_kernel_kunit:
- shard-dg2-set2: ([PASS][432], [FAIL][433]) ([Intel XE#1999]) -> [FAIL][434] ([Intel XE#1999]) +2 other tests fail
[432]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-432/igt@xe_live_ktest@xe_mocs@xe_live_mocs_kernel_kunit.html
[433]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-433/igt@xe_live_ktest@xe_mocs@xe_live_mocs_kernel_kunit.html
[434]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-464/igt@xe_live_ktest@xe_mocs@xe_live_mocs_kernel_kunit.html
* igt@xe_peer2peer@read:
- shard-dg2-set2: [FAIL][435] ([Intel XE#1173]) -> [SKIP][436] ([Intel XE#1061])
[435]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-464/igt@xe_peer2peer@read.html
[436]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-432/igt@xe_peer2peer@read.html
* igt@xe_peer2peer@write:
- shard-dg2-set2: ([FAIL][437], [FAIL][438]) ([Intel XE#1173]) -> [SKIP][439] ([Intel XE#1061])
[437]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-463/igt@xe_peer2peer@write.html
[438]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-dg2-464/igt@xe_peer2peer@write.html
[439]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-dg2-432/igt@xe_peer2peer@write.html
* igt@xe_pm@s4-vm-bind-userptr:
- shard-adlp: ([PASS][440], [ABORT][441]) ([Intel XE#1794]) -> [ABORT][442] ([Intel XE#1794])
[440]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-adlp-4/igt@xe_pm@s4-vm-bind-userptr.html
[441]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65/shard-adlp-9/igt@xe_pm@s4-vm-bind-userptr.html
[442]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/shard-adlp-9/igt@xe_pm@s4-vm-bind-userptr.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel XE#1061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1061
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1173
[Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
[Intel XE#1188]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1188
[Intel XE#1340]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1340
[Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
[Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1500]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1500
[Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
[Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
[Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
[Intel XE#1794]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1794
[Intel XE#1999]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1999
[Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
[Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
[Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
[Intel XE#2373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2373
[Intel XE#2541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2541
[Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
[Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
[Intel XE#2882]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2882
[Intel XE#2883]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2883
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
[Intel XE#2905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2905
[Intel XE#2939]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2939
[Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#3012]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3012
[Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
[Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
[Intel XE#310]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/310
[Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
[Intel XE#3124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3124
[Intel XE#3226]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3226
[Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
[Intel XE#3321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3321
[Intel XE#3428]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3428
[Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
[Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362
[Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
[Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
[Intel XE#3862]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3862
[Intel XE#3889]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3889
[Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
[Intel XE#4164]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4164
[Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
[Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
[Intel XE#4328]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4328
[Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
[Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
[Intel XE#4418]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4418
[Intel XE#4440]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4440
[Intel XE#4459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4459
[Intel XE#4522]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4522
[Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
[Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
[Intel XE#4565]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4565
[Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
[Intel XE#4624]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4624
[Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
[Intel XE#4741]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4741
[Intel XE#560]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/560
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
[Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
[Intel XE#658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/658
[Intel XE#756]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/756
[Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
[Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
[Intel XE#886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/886
[Intel XE#911]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/911
[Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
Build changes
-------------
* Linux: xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65 -> xe-pw-144506v2
IGT_8319: db9eca9df70fbb72589fcaf689dd92784b06a9c0 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-2953-4e52f6bddf99cb28ed0279d56bb8286a8bbfda65: 4e52f6bddf99cb28ed0279d56bb8286a8bbfda65
xe-pw-144506v2: 144506v2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144506v2/index.html
[-- Attachment #2: Type: text/html, Size: 114247 bytes --]
^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH v2 3/3] drm/i915: split out display register macros to a separate file
2025-04-15 10:51 ` [PATCH v2 3/3] drm/i915: split out display register macros to a separate file Jani Nikula
@ 2025-04-17 8:33 ` Kandpal, Suraj
0 siblings, 0 replies; 13+ messages in thread
From: Kandpal, Suraj @ 2025-04-17 8:33 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com
> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Tuesday, April 15, 2025 4:21 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; ville.syrjala@linux.intel.com; Kandpal,
> Suraj <suraj.kandpal@intel.com>
> Subject: [PATCH v2 3/3] drm/i915: split out display register macros to a separate
> file
>
> This is a scripted split of the display related register macros from
> i915_reg.h to display/intel_display_regs.h. As a starting point, move
> all the macros that are only used in display code (or GVT). If there are
> users in core i915 code or soc/, or no users anywhere, keep the macros
> in i915_reg.h. This is done in groups of macros separated by blank
> lines, moving the comments along with the groups.
>
> Some manually picked macro groups are kept/moved regardless of the
> heuristics above.
>
> This is obviously a very crude approach. It's not perfect. But there are
> 4.2k lines in i915_reg.h, and its refactoring has ground to a halt. This
> is the big hammer that splits the file to two, and enables further
> cleanup.
>
> Cc: Suraj Kandpal <suraj.kandpal@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
>
> ---
>
> All moved lines are moved verbatim, with no additional changes, so 'git
> show --color-moved' will be helpful for review.
>
> I've added a way to manually indicate register macro groups that should
> be moved or kept. I've added some to the list. I hope the end result is
> better than last time. It's trivial to amend those move/keep lists and
> re-run this if you spot something that's not right.
> ---
> drivers/gpu/drm/i915/display/g4x_dp.c | 1 +
> drivers/gpu/drm/i915/display/g4x_hdmi.c | 1 +
> drivers/gpu/drm/i915/display/hsw_ips.c | 1 +
> .../gpu/drm/i915/display/i9xx_display_sr.c | 1 +
> drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +
> drivers/gpu/drm/i915/display/i9xx_wm.c | 1 +
> drivers/gpu/drm/i915/display/icl_dsi.c | 1 +
> .../gpu/drm/i915/display/intel_backlight.c | 2 +-
> drivers/gpu/drm/i915/display/intel_bw.c | 3 +-
> drivers/gpu/drm/i915/display/intel_cdclk.c | 1 +
> drivers/gpu/drm/i915/display/intel_cmtg.c | 3 +-
> .../gpu/drm/i915/display/intel_combo_phy.c | 1 +
> drivers/gpu/drm/i915/display/intel_crt.c | 1 +
> drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
> drivers/gpu/drm/i915/display/intel_display.c | 3 +-
> .../drm/i915/display/intel_display_debugfs.c | 1 +
> .../drm/i915/display/intel_display_device.c | 6 +-
> .../gpu/drm/i915/display/intel_display_irq.c | 2 +
> .../drm/i915/display/intel_display_power.c | 1 +
> .../i915/display/intel_display_power_map.c | 1 +
> .../i915/display/intel_display_power_well.c | 1 +
> .../gpu/drm/i915/display/intel_display_regs.h | 2878 +++++++++++++++++
> .../gpu/drm/i915/display/intel_display_wa.c | 1 +
> drivers/gpu/drm/i915/display/intel_dmc.c | 3 +-
> drivers/gpu/drm/i915/display/intel_dmc_wl.c | 1 +
> drivers/gpu/drm/i915/display/intel_dp.c | 4 +-
> drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 1 +
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 1 +
> drivers/gpu/drm/i915/display/intel_dp_test.c | 1 +
> drivers/gpu/drm/i915/display/intel_dpio_phy.c | 1 +
> drivers/gpu/drm/i915/display/intel_dpll.c | 1 +
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 +
> .../gpu/drm/i915/display/intel_dpt_common.c | 1 +
> drivers/gpu/drm/i915/display/intel_drrs.c | 1 +
> drivers/gpu/drm/i915/display/intel_dsb.c | 1 +
> drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 3 +-
> drivers/gpu/drm/i915/display/intel_dvo.c | 1 +
> drivers/gpu/drm/i915/display/intel_fbc.c | 3 +
> drivers/gpu/drm/i915/display/intel_fdi.c | 3 +-
> .../drm/i915/display/intel_fifo_underrun.c | 1 +
> drivers/gpu/drm/i915/display/intel_gmbus.c | 1 +
> drivers/gpu/drm/i915/display/intel_hdcp.c | 1 +
> drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
> .../gpu/drm/i915/display/intel_hotplug_irq.c | 1 +
> drivers/gpu/drm/i915/display/intel_lspcon.c | 1 +
> .../drm/i915/display/intel_modeset_setup.c | 3 +-
> drivers/gpu/drm/i915/display/intel_overlay.c | 2 +
> .../gpu/drm/i915/display/intel_pch_display.c | 1 +
> .../gpu/drm/i915/display/intel_pch_refclk.c | 1 +
> drivers/gpu/drm/i915/display/intel_pfit.c | 1 +
> drivers/gpu/drm/i915/display/intel_pipe_crc.c | 1 +
> drivers/gpu/drm/i915/display/intel_pmdemand.c | 1 +
> drivers/gpu/drm/i915/display/intel_pps.c | 1 +
> drivers/gpu/drm/i915/display/intel_psr.c | 1 +
> drivers/gpu/drm/i915/display/intel_sdvo.c | 1 +
> drivers/gpu/drm/i915/display/intel_snps_phy.c | 1 +
> drivers/gpu/drm/i915/display/intel_tc.c | 1 +
> drivers/gpu/drm/i915/display/intel_vblank.c | 1 +
> drivers/gpu/drm/i915/display/intel_vga.c | 2 +
> drivers/gpu/drm/i915/display/intel_vrr.c | 1 +
> drivers/gpu/drm/i915/display/skl_scaler.c | 1 +
> .../drm/i915/display/skl_universal_plane.c | 4 +-
> drivers/gpu/drm/i915/display/skl_watermark.c | 1 +
> drivers/gpu/drm/i915/display/vlv_dsi.c | 1 +
> drivers/gpu/drm/i915/gvt/cmd_parser.c | 1 +
> drivers/gpu/drm/i915/gvt/display.c | 1 +
> drivers/gpu/drm/i915/gvt/fb_decoder.c | 1 +
> drivers/gpu/drm/i915/gvt/handlers.c | 1 +
> drivers/gpu/drm/i915/gvt/interrupt.c | 1 +
> drivers/gpu/drm/i915/gvt/mmio.c | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 2867 ----------------
> drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1 +
> drivers/gpu/drm/xe/display/xe_plane_initial.c | 1 +
> 73 files changed, 2967 insertions(+), 2882 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_display_regs.h
>
> diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c
> b/drivers/gpu/drm/i915/display/g4x_dp.c
> index 9b6792c701d1..646ff7d1c53b 100644
> --- a/drivers/gpu/drm/i915/display/g4x_dp.c
> +++ b/drivers/gpu/drm/i915/display/g4x_dp.c
> @@ -16,6 +16,7 @@
> #include "intel_crtc.h"
> #include "intel_de.h"
> #include "intel_display_power.h"
> +#include "intel_display_regs.h"
> #include "intel_display_types.h"
> #include "intel_dp.h"
> #include "intel_dp_aux.h"
> diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c
> b/drivers/gpu/drm/i915/display/g4x_hdmi.c
> index 21b5db2fa203..863fea23dd08 100644
> --- a/drivers/gpu/drm/i915/display/g4x_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c
> @@ -14,6 +14,7 @@
> #include "intel_crtc.h"
> #include "intel_de.h"
> #include "intel_display_power.h"
> +#include "intel_display_regs.h"
> #include "intel_display_types.h"
> #include "intel_dp_aux.h"
> #include "intel_dpio_phy.h"
> diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c
> b/drivers/gpu/drm/i915/display/hsw_ips.c
> index 4307e2ed03d9..0d33782f11be 100644
> --- a/drivers/gpu/drm/i915/display/hsw_ips.c
> +++ b/drivers/gpu/drm/i915/display/hsw_ips.c
> @@ -10,6 +10,7 @@
> #include "i915_reg.h"
> #include "intel_color_regs.h"
> #include "intel_de.h"
> +#include "intel_display_regs.h"
> #include "intel_display_rpm.h"
> #include "intel_display_types.h"
> #include "intel_pcode.h"
> diff --git a/drivers/gpu/drm/i915/display/i9xx_display_sr.c
> b/drivers/gpu/drm/i915/display/i9xx_display_sr.c
> index 32abe9743014..357212f09a0f 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_display_sr.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_display_sr.c
> @@ -9,6 +9,7 @@
> #include "i9xx_display_sr.h"
> #include "i9xx_wm_regs.h"
> #include "intel_de.h"
> +#include "intel_display_regs.h"
> #include "intel_gmbus.h"
> #include "intel_pci_config.h"
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
> b/drivers/gpu/drm/i915/display/i9xx_plane.c
> index 5e8344fdfc28..b7248ae98ad1 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> @@ -2,6 +2,7 @@
> /*
> * Copyright © 2020 Intel Corporation
> */
> +
> #include <linux/kernel.h>
>
> #include <drm/drm_atomic_helper.h>
> @@ -16,6 +17,7 @@
> #include "intel_atomic_plane.h"
> #include "intel_de.h"
> #include "intel_display_irq.h"
> +#include "intel_display_regs.h"
> #include "intel_display_types.h"
> #include "intel_fb.h"
> #include "intel_fbc.h"
> diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c
> b/drivers/gpu/drm/i915/display/i9xx_wm.c
> index 40751f1547b7..9f0509a5d2c1 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_wm.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
> @@ -11,6 +11,7 @@
> #include "intel_bo.h"
> #include "intel_de.h"
> #include "intel_display.h"
> +#include "intel_display_regs.h"
> #include "intel_display_trace.h"
> #include "intel_fb.h"
> #include "intel_mchbar_regs.h"
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index ca7033251e91..c62e97e494c2 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -45,6 +45,7 @@
> #include "intel_crtc.h"
> #include "intel_ddi.h"
> #include "intel_de.h"
> +#include "intel_display_regs.h"
> #include "intel_dsi.h"
> #include "intel_dsi_vbt.h"
> #include "intel_panel.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c
> b/drivers/gpu/drm/i915/display/intel_backlight.c
> index 4f3fa966c537..3e9e0b2b4a53 100644
> --- a/drivers/gpu/drm/i915/display/intel_backlight.c
> +++ b/drivers/gpu/drm/i915/display/intel_backlight.c
> @@ -7,7 +7,6 @@
> #include <linux/kernel.h>
> #include <linux/pwm.h>
> #include <linux/string_helpers.h>
> -
> #include <acpi/video.h>
>
> #include "i915_drv.h"
> @@ -16,6 +15,7 @@
> #include "intel_backlight_regs.h"
> #include "intel_connector.h"
> #include "intel_de.h"
> +#include "intel_display_regs.h"
> #include "intel_display_rpm.h"
> #include "intel_display_types.h"
> #include "intel_dp_aux_backlight.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index a5dd2932b852..23712f38d368 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -12,10 +12,11 @@
> #include "intel_bw.h"
> #include "intel_cdclk.h"
> #include "intel_display_core.h"
> +#include "intel_display_regs.h"
> #include "intel_display_types.h"
> -#include "skl_watermark.h"
> #include "intel_mchbar_regs.h"
> #include "intel_pcode.h"
> +#include "skl_watermark.h"
>
> /* Parameters for Qclk Geyserville (QGV) */
> struct intel_qgv_point {
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 6830950aae3f..e9f315f6a5a1 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -38,6 +38,7 @@
> #include "intel_cdclk.h"
> #include "intel_crtc.h"
> #include "intel_de.h"
> +#include "intel_display_regs.h"
> #include "intel_display_types.h"
> #include "intel_mchbar_regs.h"
> #include "intel_pci_config.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index 07d7f4e8f60f..e9d03daec80d 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -11,12 +11,13 @@
>
> #include "i915_drv.h"
> #include "i915_reg.h"
> -#include "intel_crtc.h"
> #include "intel_cmtg.h"
> #include "intel_cmtg_regs.h"
> +#include "intel_crtc.h"
> #include "intel_de.h"
> #include "intel_display_device.h"
> #include "intel_display_power.h"
> +#include "intel_display_regs.h"
>
> /**
> * DOC: Common Primary Timing Generator (CMTG)
> diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> index f5cc38dbe559..b1bff2f0b020 100644
> --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> @@ -10,6 +10,7 @@
> #include "intel_combo_phy.h"
> #include "intel_combo_phy_regs.h"
> #include "intel_de.h"
> +#include "intel_display_regs.h"
> #include "intel_display_types.h"
>
> #define for_each_combo_phy(__display, __phy) \
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c
> b/drivers/gpu/drm/i915/display/intel_crt.c
> index cca22d2402e8..20eafd2a48fd 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -44,6 +44,7 @@
> #include "intel_ddi_buf_trans.h"
> #include "intel_de.h"
> #include "intel_display_driver.h"
> +#include "intel_display_regs.h"
> #include "intel_display_types.h"
> #include "intel_fdi.h"
> #include "intel_fdi_regs.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index b48ed5df7a96..def7ce928782 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -48,6 +48,7 @@
> #include "intel_ddi_buf_trans.h"
> #include "intel_de.h"
> #include "intel_display_power.h"
> +#include "intel_display_regs.h"
> #include "intel_display_types.h"
> #include "intel_dkl_phy.h"
> #include "intel_dkl_phy_regs.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index db524d01e574..dfe9972f602e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -66,13 +66,14 @@
> #include "intel_crt.h"
> #include "intel_crtc.h"
> #include "intel_crtc_state_dump.h"
> +#include "intel_cursor.h"
> #include "intel_cursor_regs.h"
> #include "intel_cx0_phy.h"
> -#include "intel_cursor.h"
> #include "intel_ddi.h"
> #include "intel_de.h"
> #include "intel_display_driver.h"
> #include "intel_display_power.h"
> +#include "intel_display_regs.h"
> #include "intel_display_rpm.h"
> #include "intel_display_types.h"
> #include "intel_dmc.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 3f7c605d47d3..7d70918903e3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -24,6 +24,7 @@
> #include "intel_display_debugfs_params.h"
> #include "intel_display_power.h"
> #include "intel_display_power_well.h"
> +#include "intel_display_regs.h"
> #include "intel_display_rpm.h"
> #include "intel_display_types.h"
> #include "intel_dmc.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
> b/drivers/gpu/drm/i915/display/intel_display_device.c
> index 738ae522c8f4..cf4ab425984b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -3,10 +3,11 @@
> * Copyright © 2023 Intel Corporation
> */
>
> -#include <drm/intel/pciids.h>
> -#include <drm/drm_color_mgmt.h>
> #include <linux/pci.h>
>
> +#include <drm/drm_color_mgmt.h>
> +#include <drm/intel/pciids.h>
> +
> #include "i915_drv.h"
> #include "i915_reg.h"
> #include "intel_cx0_phy_regs.h"
> @@ -16,6 +17,7 @@
> #include "intel_display_params.h"
> #include "intel_display_power.h"
> #include "intel_display_reg_defs.h"
> +#include "intel_display_regs.h"
> #include "intel_display_types.h"
> #include "intel_fbc.h"
> #include "intel_step.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c
> b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index 5d07b6a9e59e..30bf80bb576b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -6,6 +6,7 @@
> #include <drm/drm_vblank.h>
>
> #include "gt/intel_rps.h"
> +
> #include "i915_drv.h"
> #include "i915_irq.h"
> #include "i915_reg.h"
> @@ -14,6 +15,7 @@
> #include "intel_crtc.h"
> #include "intel_de.h"
> #include "intel_display_irq.h"
> +#include "intel_display_regs.h"
> #include "intel_display_rpm.h"
> #include "intel_display_trace.h"
> #include "intel_display_types.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index c78315eb44fa..592f6d0cce97 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -16,6 +16,7 @@
> #include "intel_display_power.h"
> #include "intel_display_power_map.h"
> #include "intel_display_power_well.h"
> +#include "intel_display_regs.h"
> #include "intel_display_rpm.h"
> #include "intel_display_types.h"
> #include "intel_dmc.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c
> b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> index ab1163744bc5..adbe321cb70b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> @@ -9,6 +9,7 @@
> #include "intel_display_core.h"
> #include "intel_display_power_map.h"
> #include "intel_display_power_well.h"
> +#include "intel_display_regs.h"
> #include "intel_display_types.h"
> #include "vlv_sideband_reg.h"
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index b9b4359751cc..c360d8365c84 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -13,6 +13,7 @@
> #include "intel_de.h"
> #include "intel_display_irq.h"
> #include "intel_display_power_well.h"
> +#include "intel_display_regs.h"
> #include "intel_display_rpm.h"
> #include "intel_display_types.h"
> #include "intel_dkl_phy.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h
> b/drivers/gpu/drm/i915/display/intel_display_regs.h
> new file mode 100644
> index 000000000000..19c02a2e3198
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -0,0 +1,2878 @@
> +/* SPDX-License-Identifier: MIT */
> +/* Copyright © 2025 Intel Corporation */
> +
> +#ifndef __INTEL_DISPLAY_REGS_H__
> +#define __INTEL_DISPLAY_REGS_H__
> +
> +#include "intel_display_reg_defs.h"
> +
> +#define _GEN7_PIPEA_DE_LOAD_SL 0x70068
> +#define _GEN7_PIPEB_DE_LOAD_SL 0x71068
> +#define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe,
> _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
> +
> +#define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110)
> +#define DPIO_MODSEL1 (1 << 3) /* if ref clk b == 27 */
> +#define DPIO_MODSEL0 (1 << 2) /* if ref clk a == 27 */
> +#define DPIO_SFR_BYPASS (1 << 1)
> +#define DPIO_CMNRST (1 << 0)
> +
> +#define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090)
> +#define MIPIO_RST_CTRL (1 << 2)
> +
> +#define _BXT_PHY_CTL_DDI_A 0x64C00
> +#define _BXT_PHY_CTL_DDI_B 0x64C10
> +#define _BXT_PHY_CTL_DDI_C 0x64C20
> +#define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10)
> +#define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9)
> +#define BXT_PHY_LANE_ENABLED (1 << 8)
> +#define BXT_PHY_CTL(port) _MMIO_PORT(port,
> _BXT_PHY_CTL_DDI_A, \
> +
> _BXT_PHY_CTL_DDI_B)
> +
> +#define _PHY_CTL_FAMILY_DDI 0x64C90
> +#define _PHY_CTL_FAMILY_EDP 0x64C80
> +#define _PHY_CTL_FAMILY_DDI_C 0x64CA0
> +#define COMMON_RESET_DIS (1 << 31)
> +#define BXT_PHY_CTL_FAMILY(phy)
> \
> + _MMIO(_PICK_EVEN_2RANGES(phy, 1,
> \
> + _PHY_CTL_FAMILY_DDI,
> _PHY_CTL_FAMILY_DDI, \
> + _PHY_CTL_FAMILY_EDP,
> _PHY_CTL_FAMILY_DDI_C))
> +
> +/* UAIMI scratch pad register 1 */
> +#define UAIMI_SPR1 _MMIO(0x4F074)
> +/* SKL VccIO mask */
> +#define SKL_VCCIO_MASK 0x1
> +/* SKL balance leg register */
> +#define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C)
> +/* I_boost values */
> +#define BALANCE_LEG_SHIFT(port) (8 + 3 * (port))
> +#define BALANCE_LEG_MASK(port) (7 << (8 + 3 * (port)))
> +/* Balance leg disable bits */
> +#define BALANCE_LEG_DISABLE_SHIFT 23
> +#define BALANCE_LEG_DISABLE(port) (1 << (23 + (port)))
> +
> +#define ILK_GTT_FAULT _MMIO(0x44040) /* ilk/snb */
> +#define GTT_FAULT_INVALID_GTT_PTE (1 << 7)
> +#define GTT_FAULT_INVALID_PTE_DATA (1 << 6)
> +#define GTT_FAULT_CURSOR_B_FAULT (1 << 5)
> +#define GTT_FAULT_CURSOR_A_FAULT (1 << 4)
> +#define GTT_FAULT_SPRITE_B_FAULT (1 << 3)
> +#define GTT_FAULT_SPRITE_A_FAULT (1 << 2)
> +#define GTT_FAULT_PRIMARY_B_FAULT (1 << 1)
> +#define GTT_FAULT_PRIMARY_A_FAULT (1 << 0)
> +
> +#define VLV_IRQ_REGS I915_IRQ_REGS(VLV_IMR, \
> + VLV_IER, \
> + VLV_IIR)
> +
> +#define VLV_EIR _MMIO(VLV_DISPLAY_BASE + 0x20b0)
> +#define VLV_EMR _MMIO(VLV_DISPLAY_BASE + 0x20b4)
> +#define VLV_ESR _MMIO(VLV_DISPLAY_BASE + 0x20b8)
> +#define VLV_ERROR_GUNIT_TLB_DATA (1 << 6)
> +#define VLV_ERROR_GUNIT_TLB_PTE (1 << 5)
> +#define VLV_ERROR_PAGE_TABLE (1 << 4)
> +#define VLV_ERROR_CLAIM (1 << 0)
> +
> +#define VLV_ERROR_REGS I915_ERROR_REGS(VLV_EMR,
> VLV_EIR)
> +
> +#define _MBUS_ABOX0_CTL 0x45038
> +#define _MBUS_ABOX1_CTL 0x45048
> +#define _MBUS_ABOX2_CTL 0x4504C
> +#define MBUS_ABOX_CTL(x)
> \
> + _MMIO(_PICK_EVEN_2RANGES(x, 2,
> \
> + _MBUS_ABOX0_CTL, _MBUS_ABOX1_CTL,
> \
> + _MBUS_ABOX2_CTL, _MBUS_ABOX2_CTL))
> +
> +#define MBUS_ABOX_BW_CREDIT_MASK (3 << 20)
> +#define MBUS_ABOX_BW_CREDIT(x) ((x) << 20)
> +#define MBUS_ABOX_B_CREDIT_MASK (0xF << 16)
> +#define MBUS_ABOX_B_CREDIT(x) ((x) << 16)
> +#define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8)
> +#define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8)
> +#define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0)
> +#define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0)
> +
> +#define IPS_CTL _MMIO(0x43408)
> +#define IPS_ENABLE REG_BIT(31)
> +#define IPS_FALSE_COLOR REG_BIT(4)
> +
> +/*
> + * Clock control & power management
> + */
> +#define _DPLL_A 0x6014
> +#define _DPLL_B 0x6018
> +#define _CHV_DPLL_C 0x6030
> +#define DPLL(dev_priv, pipe)
> _MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \
> + (pipe), _DPLL_A, _DPLL_B,
> _CHV_DPLL_C)
> +
> +#define VGA0 _MMIO(0x6000)
> +#define VGA1 _MMIO(0x6004)
> +#define VGA_PD _MMIO(0x6010)
> +#define VGA0_PD_P2_DIV_4 (1 << 7)
> +#define VGA0_PD_P1_DIV_2 (1 << 5)
> +#define VGA0_PD_P1_SHIFT 0
> +#define VGA0_PD_P1_MASK (0x1f << 0)
> +#define VGA1_PD_P2_DIV_4 (1 << 15)
> +#define VGA1_PD_P1_DIV_2 (1 << 13)
> +#define VGA1_PD_P1_SHIFT 8
> +#define VGA1_PD_P1_MASK (0x1f << 8)
> +#define DPLL_VCO_ENABLE (1 << 31)
> +#define DPLL_SDVO_HIGH_SPEED (1 << 30)
> +#define DPLL_DVO_2X_MODE (1 << 30)
> +#define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
> +#define DPLL_SYNCLOCK_ENABLE (1 << 29)
> +#define DPLL_REF_CLK_ENABLE_VLV (1 << 29)
> +#define DPLL_VGA_MODE_DIS (1 << 28)
> +#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
> +#define DPLLB_MODE_LVDS (2 << 26) /* i915 */
> +#define DPLL_MODE_MASK (3 << 26)
> +#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
> +#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
> +#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
> +#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
> +#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
> +#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
> +#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /*
> Pineview */
> +#define DPLL_LOCK_VLV (1 << 15)
> +#define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14)
> +#define DPLL_INTEGRATED_REF_CLK_VLV (1 << 13)
> +#define DPLL_SSC_REF_CLK_CHV (1 << 13)
> +#define DPLL_PORTC_READY_MASK (0xf << 4)
> +#define DPLL_PORTB_READY_MASK (0xf)
> +
> +#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
> +
> +/* Additional CHV pll/phy registers */
> +#define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE +
> 0x6240)
> +#define DPLL_PORTD_READY_MASK (0xf)
> +#define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
> +#define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2 * (phy) + (ch) +
> 27))
> +#define PHY_LDO_DELAY_0NS 0x0
> +#define PHY_LDO_DELAY_200NS 0x1
> +#define PHY_LDO_DELAY_600NS 0x2
> +#define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2 * (phy) +
> 23))
> +#define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 *
> (phy) + 4 * (ch) + 11))
> +#define PHY_CH_SU_PSR 0x1
> +#define PHY_CH_DEEP_PSR 0x7
> +#define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6 * (phy) +
> 3 * (ch) + 2))
> +#define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))
> +#define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
> +#define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1
> << 30))
> +#define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 *
> (ch))))
> +#define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3
> * (ch) + (spline))))
> +
> +/*
> + * The i830 generation, in LVDS mode, defines P1 as the bit number set within
> + * this field (only one bit may be set).
> + */
> +#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
> +#define DPLL_FPA01_P1_POST_DIV_SHIFT 16
> +#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
> +/* i830, required in DVO non-gang */
> +#define PLL_P2_DIVIDE_BY_4 (1 << 23)
> +#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
> +#define PLL_REF_INPUT_DREFCLK (0 << 13)
> +#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
> +#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
> +#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
> +#define PLL_REF_INPUT_MASK (3 << 13)
> +#define PLL_LOAD_PULSE_PHASE_SHIFT 9
> +/* Ironlake */
> +# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
> +# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
> +# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9)
> +# define DPLL_FPA1_P1_POST_DIV_SHIFT 0
> +# define DPLL_FPA1_P1_POST_DIV_MASK 0xff
> +
> +/*
> + * Parallel to Serial Load Pulse phase selection.
> + * Selects the phase for the 10X DPLL clock for the PCIe
> + * digital display port. The range is 4 to 13; 10 or more
> + * is just a flip delay. The default is 6
> + */
> +#define PLL_LOAD_PULSE_PHASE_MASK (0xf <<
> PLL_LOAD_PULSE_PHASE_SHIFT)
> +#define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
> +/*
> + * SDVO multiplier for 945G/GM. Not used on 965.
> + */
> +#define SDVO_MULTIPLIER_MASK 0x000000ff
> +#define SDVO_MULTIPLIER_SHIFT_HIRES 4
> +#define SDVO_MULTIPLIER_SHIFT_VGA 0
> +
> +#define _DPLL_A_MD 0x601c
> +#define _DPLL_B_MD 0x6020
> +#define _CHV_DPLL_C_MD 0x603c
> +#define DPLL_MD(dev_priv, pipe)
> _MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \
> + (pipe), _DPLL_A_MD,
> _DPLL_B_MD, _CHV_DPLL_C_MD)
> +
> +/*
> + * UDI pixel divider, controlling how many pixels are stuffed into a packet.
> + *
> + * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
> + */
> +#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
> +#define DPLL_MD_UDI_DIVIDER_SHIFT 24
> +/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
> +#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
> +#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
> +/*
> + * SDVO/UDI pixel multiplier.
> + *
> + * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
> + * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
> + * modes, the bus rate would be below the limits, so SDVO allows for stuffing
> + * dummy bytes in the datastream at an increased clock rate, with both sides
> of
> + * the link knowing how many bytes are fill.
> + *
> + * So, for a mode with a dotclock of 65Mhz, we would want to double the
> clock
> + * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
> + * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
> + * through an SDVO command.
> + *
> + * This register field has values of multiplication factor minus 1, with
> + * a maximum multiplier of 5 for SDVO.
> + */
> +#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
> +#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
> +/*
> + * SDVO/UDI pixel multiplier for VGA, same as
> DPLL_MD_UDI_MULTIPLIER_MASK.
> + * This best be set to the default value (3) or the CRT won't work. No,
> + * I don't entirely understand what this does...
> + */
> +#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
> +#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
> +
> +#define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024)
> +
> +#define _FPA0 0x6040
> +#define _FPA1 0x6044
> +#define _FPB0 0x6048
> +#define _FPB1 0x604c
> +#define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0)
> +#define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1)
> +#define FP_N_DIV_MASK 0x003f0000
> +#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
> +#define FP_N_DIV_SHIFT 16
> +#define FP_M1_DIV_MASK 0x00003f00
> +#define FP_M1_DIV_SHIFT 8
> +#define FP_M2_DIV_MASK 0x0000003f
> +#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
> +#define FP_M2_DIV_SHIFT 0
> +
> +#define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500)
> +#define FW_CSPWRDWNEN (1 << 15)
> +
> +#define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)
> +
> +#define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508)
> +#define CDCLK_FREQ_SHIFT 4
> +#define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT)
> +#define CZCLK_FREQ_MASK 0xf
> +
> +#define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C)
> +#define PFI_CREDIT_63 (9 << 28) /* chv only */
> +#define PFI_CREDIT_31 (8 << 28) /* chv only */
> +#define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */
> +#define PFI_CREDIT_RESEND (1 << 27)
> +#define VGA_FAST_MODE_DISABLE (1 << 14)
> +
> +#define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510)
> +
> +#define PEG_BAND_GAP_DATA _MMIO(0x14d68)
> +
> +/*
> + * Overlay regs
> + */
> +#define OVADD _MMIO(0x30000)
> +#define DOVSTA _MMIO(0x30008)
> +#define OC_BUF (0x3 << 20)
> +#define OGAMC5 _MMIO(0x30010)
> +#define OGAMC4 _MMIO(0x30014)
> +#define OGAMC3 _MMIO(0x30018)
> +#define OGAMC2 _MMIO(0x3001c)
> +#define OGAMC1 _MMIO(0x30020)
> +#define OGAMC0 _MMIO(0x30024)
> +
> +#define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
> +#define BXT_GMBUS_GATING_DIS (1 << 14)
> +#define DG2_DPFC_GATING_DIS REG_BIT(31)
> +
> +#define GEN9_CLKGATE_DIS_5 _MMIO(0x46540)
> +#define DPCE_GATING_DIS REG_BIT(17)
> +
> +#define _CLKGATE_DIS_PSL_A 0x46520
> +#define _CLKGATE_DIS_PSL_B 0x46524
> +#define _CLKGATE_DIS_PSL_C 0x46528
> +#define DUPS1_GATING_DIS (1 << 15)
> +#define DUPS2_GATING_DIS (1 << 19)
> +#define DUPS3_GATING_DIS (1 << 23)
> +#define CURSOR_GATING_DIS REG_BIT(28)
> +#define DPF_GATING_DIS (1 << 10)
> +#define DPF_RAM_GATING_DIS (1 << 9)
> +#define DPFR_GATING_DIS (1 << 8)
> +
> +#define CLKGATE_DIS_PSL(pipe) \
> + _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B)
> +
> +#define _CLKGATE_DIS_PSL_EXT_A 0x4654C
> +#define _CLKGATE_DIS_PSL_EXT_B 0x46550
> +#define PIPEDMC_GATING_DIS REG_BIT(12)
> +
> +#define CLKGATE_DIS_PSL_EXT(pipe) \
> + _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_EXT_A,
> _CLKGATE_DIS_PSL_EXT_B)
> +
> +/*
> + * Display engine regs
> + */
> +/* Pipe/transcoder A timing regs */
> +#define _TRANS_HTOTAL_A 0x60000
> +#define _TRANS_HTOTAL_B 0x61000
> +#define TRANS_HTOTAL(dev_priv, trans) _MMIO_TRANS2(dev_priv,
> (trans), _TRANS_HTOTAL_A)
> +#define HTOTAL_MASK REG_GENMASK(31, 16)
> +#define HTOTAL(htotal) REG_FIELD_PREP(HTOTAL_MASK,
> (htotal))
> +#define HACTIVE_MASK REG_GENMASK(15, 0)
> +#define HACTIVE(hdisplay) REG_FIELD_PREP(HACTIVE_MASK,
> (hdisplay))
> +
> +#define _TRANS_HBLANK_A 0x60004
> +#define _TRANS_HBLANK_B 0x61004
> +#define TRANS_HBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv,
> (trans), _TRANS_HBLANK_A)
> +#define HBLANK_END_MASK REG_GENMASK(31, 16)
> +#define HBLANK_END(hblank_end)
> REG_FIELD_PREP(HBLANK_END_MASK, (hblank_end))
> +#define HBLANK_START_MASK REG_GENMASK(15, 0)
> +#define HBLANK_START(hblank_start)
> REG_FIELD_PREP(HBLANK_START_MASK, (hblank_start))
> +
> +#define _TRANS_HSYNC_A 0x60008
> +#define _TRANS_HSYNC_B 0x61008
> +#define TRANS_HSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans),
> _TRANS_HSYNC_A)
> +#define HSYNC_END_MASK REG_GENMASK(31, 16)
> +#define HSYNC_END(hsync_end)
> REG_FIELD_PREP(HSYNC_END_MASK, (hsync_end))
> +#define HSYNC_START_MASK REG_GENMASK(15, 0)
> +#define HSYNC_START(hsync_start)
> REG_FIELD_PREP(HSYNC_START_MASK, (hsync_start))
> +
> +#define _TRANS_VTOTAL_A 0x6000c
> +#define _TRANS_VTOTAL_B 0x6100c
> +#define TRANS_VTOTAL(dev_priv, trans) _MMIO_TRANS2(dev_priv,
> (trans), _TRANS_VTOTAL_A)
> +#define VTOTAL_MASK REG_GENMASK(31, 16)
> +#define VTOTAL(vtotal) REG_FIELD_PREP(VTOTAL_MASK,
> (vtotal))
> +#define VACTIVE_MASK REG_GENMASK(15, 0)
> +#define VACTIVE(vdisplay) REG_FIELD_PREP(VACTIVE_MASK,
> (vdisplay))
> +
> +#define _TRANS_VBLANK_A 0x60010
> +#define _TRANS_VBLANK_B 0x61010
> +#define TRANS_VBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv,
> (trans), _TRANS_VBLANK_A)
> +#define VBLANK_END_MASK REG_GENMASK(31, 16)
> +#define VBLANK_END(vblank_end)
> REG_FIELD_PREP(VBLANK_END_MASK, (vblank_end))
> +#define VBLANK_START_MASK REG_GENMASK(15, 0)
> +#define VBLANK_START(vblank_start)
> REG_FIELD_PREP(VBLANK_START_MASK, (vblank_start))
> +
> +#define _TRANS_VSYNC_A 0x60014
> +#define _TRANS_VSYNC_B 0x61014
> +#define TRANS_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans),
> _TRANS_VSYNC_A)
> +#define VSYNC_END_MASK REG_GENMASK(31, 16)
> +#define VSYNC_END(vsync_end)
> REG_FIELD_PREP(VSYNC_END_MASK, (vsync_end))
> +#define VSYNC_START_MASK REG_GENMASK(15, 0)
> +#define VSYNC_START(vsync_start)
> REG_FIELD_PREP(VSYNC_START_MASK, (vsync_start))
> +
> +#define _PIPEASRC 0x6001c
> +#define _PIPEBSRC 0x6101c
> +#define PIPESRC(dev_priv, pipe) _MMIO_TRANS2(dev_priv,
> (pipe), _PIPEASRC)
> +#define PIPESRC_WIDTH_MASK REG_GENMASK(31, 16)
> +#define PIPESRC_WIDTH(w) REG_FIELD_PREP(PIPESRC_WIDTH_MASK, (w))
> +#define PIPESRC_HEIGHT_MASK REG_GENMASK(15, 0)
> +#define PIPESRC_HEIGHT(h) REG_FIELD_PREP(PIPESRC_HEIGHT_MASK, (h))
> +
> +#define _BCLRPAT_A 0x60020
> +#define _BCLRPAT_B 0x61020
> +#define BCLRPAT(dev_priv, trans) _MMIO_TRANS2(dev_priv,
> (trans), _BCLRPAT_A)
> +
> +#define _TRANS_VSYNCSHIFT_A 0x60028
> +#define _TRANS_VSYNCSHIFT_B 0x61028
> +#define TRANS_VSYNCSHIFT(dev_priv, trans) _MMIO_TRANS2(dev_priv,
> (trans), _TRANS_VSYNCSHIFT_A)
> +
> +#define _TRANS_MULT_A 0x6002c
> +#define _TRANS_MULT_B 0x6102c
> +#define TRANS_MULT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans),
> _TRANS_MULT_A)
> +
> +/* Hotplug control (945+ only) */
> +#define PORT_HOTPLUG_EN(dev_priv)
> _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
> +#define PORTB_HOTPLUG_INT_EN (1 << 29)
> +#define PORTC_HOTPLUG_INT_EN (1 << 28)
> +#define PORTD_HOTPLUG_INT_EN (1 << 27)
> +#define SDVOB_HOTPLUG_INT_EN (1 << 26)
> +#define SDVOC_HOTPLUG_INT_EN (1 << 25)
> +#define TV_HOTPLUG_INT_EN (1 << 18)
> +#define CRT_HOTPLUG_INT_EN (1 << 9)
> +#define HOTPLUG_INT_EN_MASK
> (PORTB_HOTPLUG_INT_EN | \
> + PORTC_HOTPLUG_INT_EN | \
> + PORTD_HOTPLUG_INT_EN | \
> + SDVOC_HOTPLUG_INT_EN | \
> + SDVOB_HOTPLUG_INT_EN | \
> + CRT_HOTPLUG_INT_EN)
> +#define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
> +#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
> +/* must use period 64 on GM45 according to docs */
> +#define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
> +#define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
> +#define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
> +#define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
> +#define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
> +#define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
> +#define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
> +#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
> +#define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
> +#define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
> +#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
> +#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
> +
> +#define PORT_HOTPLUG_STAT(dev_priv)
> _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114)
> +/* HDMI/DP bits are g4x+ */
> +#define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27)
> +#define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28)
> +#define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29)
> +#define PORTD_HOTPLUG_INT_STATUS (3 << 21)
> +#define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21)
> +#define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21)
> +#define PORTC_HOTPLUG_INT_STATUS (3 << 19)
> +#define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19)
> +#define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19)
> +#define PORTB_HOTPLUG_INT_STATUS (3 << 17)
> +#define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17)
> +#define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17)
> +/* CRT/TV common between gen3+ */
> +#define CRT_HOTPLUG_INT_STATUS (1 << 11)
> +#define TV_HOTPLUG_INT_STATUS (1 << 10)
> +#define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
> +#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
> +#define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
> +#define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
> +#define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6)
> +#define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5)
> +#define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4)
> +#define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4)
> +
> +/* SDVO is different across gen3/4 */
> +#define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
> +#define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
> +/*
> + * Bspec seems to be seriously misleaded about the SDVO hpd bits on
> i965g/gm,
> + * since reality corrobates that they're the same as on gen3. But keep these
> + * bits here (and the comment!) to help any other lost wanderers back onto
> the
> + * right tracks.
> + */
> +#define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
> +#define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
> +#define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
> +#define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
> +#define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS |
> \
> +
> SDVOB_HOTPLUG_INT_STATUS_G4X | \
> +
> SDVOC_HOTPLUG_INT_STATUS_G4X | \
> +
> PORTB_HOTPLUG_INT_STATUS | \
> +
> PORTC_HOTPLUG_INT_STATUS | \
> +
> PORTD_HOTPLUG_INT_STATUS)
> +
> +#define HOTPLUG_INT_STATUS_I915
> (CRT_HOTPLUG_INT_STATUS | \
> +
> SDVOB_HOTPLUG_INT_STATUS_I915 | \
> +
> SDVOC_HOTPLUG_INT_STATUS_I915 | \
> +
> PORTB_HOTPLUG_INT_STATUS | \
> +
> PORTC_HOTPLUG_INT_STATUS | \
> +
> PORTD_HOTPLUG_INT_STATUS)
> +
> +/* SDVO and HDMI port control.
> + * The same register may be used for SDVO or HDMI */
> +#define _GEN3_SDVOB 0x61140
> +#define _GEN3_SDVOC 0x61160
> +#define GEN3_SDVOB _MMIO(_GEN3_SDVOB)
> +#define GEN3_SDVOC _MMIO(_GEN3_SDVOC)
> +#define GEN4_HDMIB GEN3_SDVOB
> +#define GEN4_HDMIC GEN3_SDVOC
> +#define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140)
> +#define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160)
> +#define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C)
> +#define PCH_SDVOB _MMIO(0xe1140)
> +#define PCH_HDMIB PCH_SDVOB
> +#define PCH_HDMIC _MMIO(0xe1150)
> +#define PCH_HDMID _MMIO(0xe1160)
> +
> +#define PORT_DFT_I9XX _MMIO(0x61150)
> +#define DC_BALANCE_RESET (1 << 25)
> +#define PORT_DFT2_G4X(dev_priv)
> _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154)
> +#define DC_BALANCE_RESET_VLV (1 << 31)
> +#define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0))
> +#define PIPE_C_SCRAMBLE_RESET REG_BIT(14) /* chv */
> +#define PIPE_B_SCRAMBLE_RESET REG_BIT(1)
> +#define PIPE_A_SCRAMBLE_RESET REG_BIT(0)
> +
> +/* Gen 3 SDVO bits: */
> +#define SDVO_ENABLE (1 << 31)
> +#define SDVO_PIPE_SEL_SHIFT 30
> +#define SDVO_PIPE_SEL_MASK (1 << 30)
> +#define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
> +#define SDVO_STALL_SELECT (1 << 29)
> +#define SDVO_INTERRUPT_ENABLE (1 << 26)
> +/*
> + * 915G/GM SDVO pixel multiplier.
> + * Programmed value is multiplier - 1, up to 5x.
> + * \sa DPLL_MD_UDI_MULTIPLIER_MASK
> + */
> +#define SDVO_PORT_MULTIPLY_MASK (7 << 23)
> +#define SDVO_PORT_MULTIPLY_SHIFT 23
> +#define SDVO_PHASE_SELECT_MASK (15 << 19)
> +#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
> +#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
> +#define SDVOC_GANG_MODE (1 << 16) /* Port C
> only */
> +#define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only
> */
> +#define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */
> +#define SDVO_DETECTED (1 << 2)
> +/* Bits to be preserved when writing */
> +#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
> + SDVO_INTERRUPT_ENABLE)
> +#define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
> +
> +/* Gen 4 SDVO/HDMI bits: */
> +#define SDVO_COLOR_FORMAT_8bpc (0 << 26)
> +#define SDVO_COLOR_FORMAT_MASK (7 << 26)
> +#define SDVO_ENCODING_SDVO (0 << 10)
> +#define SDVO_ENCODING_HDMI (2 << 10)
> +#define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only
> */
> +#define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only
> */
> +#define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only
> */
> +#define HDMI_AUDIO_ENABLE (1 << 6) /* HDMI only
> */
> +/* VSYNC/HSYNC bits new with 965, default is to be set */
> +#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
> +#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
> +
> +/* Gen 5 (IBX) SDVO/HDMI bits: */
> +#define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only
> */
> +#define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only
> */
> +
> +/* Gen 6 (CPT) SDVO/HDMI bits: */
> +#define SDVO_PIPE_SEL_SHIFT_CPT 29
> +#define SDVO_PIPE_SEL_MASK_CPT (3 << 29)
> +#define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
> +
> +/* CHV SDVO/HDMI bits: */
> +#define SDVO_PIPE_SEL_SHIFT_CHV 24
> +#define SDVO_PIPE_SEL_MASK_CHV (3 << 24)
> +#define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24)
> +
> +/* Video Data Island Packet control */
> +#define VIDEO_DIP_DATA _MMIO(0x61178)
> +/* Read the description of VIDEO_DIP_DATA (before Haswell) or
> VIDEO_DIP_ECC
> + * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to
> each byte
> + * of the infoframe structure specified by CEA-861. */
> +#define VIDEO_DIP_DATA_SIZE 32
> +#define VIDEO_DIP_ASYNC_DATA_SIZE 36
> +#define VIDEO_DIP_GMP_DATA_SIZE 36
> +#define VIDEO_DIP_VSC_DATA_SIZE 36
> +#define VIDEO_DIP_PPS_DATA_SIZE 132
> +#define VIDEO_DIP_CTL _MMIO(0x61170)
> +/* Pre HSW: */
> +#define VIDEO_DIP_ENABLE (1 << 31)
> +#define VIDEO_DIP_PORT(port) ((port) << 29)
> +#define VIDEO_DIP_PORT_MASK (3 << 29)
> +#define VIDEO_DIP_ENABLE_GCP (1 << 25) /* ilk+ */
> +#define VIDEO_DIP_ENABLE_AVI (1 << 21)
> +#define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
> +#define VIDEO_DIP_ENABLE_GAMUT (4 << 21) /* ilk+ */
> +#define VIDEO_DIP_ENABLE_SPD (8 << 21)
> +#define VIDEO_DIP_SELECT_AVI (0 << 19)
> +#define VIDEO_DIP_SELECT_VENDOR (1 << 19)
> +#define VIDEO_DIP_SELECT_GAMUT (2 << 19)
> +#define VIDEO_DIP_SELECT_SPD (3 << 19)
> +#define VIDEO_DIP_SELECT_MASK (3 << 19)
> +#define VIDEO_DIP_FREQ_ONCE (0 << 16)
> +#define VIDEO_DIP_FREQ_VSYNC (1 << 16)
> +#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
> +#define VIDEO_DIP_FREQ_MASK (3 << 16)
> +/* HSW and later: */
> +#define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28)
> +#define PSR_VSC_BIT_7_SET (1 << 27)
> +#define VSC_SELECT_MASK (0x3 << 25)
> +#define VSC_SELECT_SHIFT 25
> +#define VSC_DIP_HW_HEA_DATA (0 << 25)
> +#define VSC_DIP_HW_HEA_SW_DATA (1 << 25)
> +#define VSC_DIP_HW_DATA_SW_HEA (2 << 25)
> +#define VSC_DIP_SW_HEA_DATA (3 << 25)
> +#define VDIP_ENABLE_PPS (1 << 24)
> +#define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
> +#define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
> +#define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
> +#define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
> +#define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
> +#define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
> +/* ADL and later: */
> +#define VIDEO_DIP_ENABLE_AS_ADL REG_BIT(23)
> +
> +#define PCH_GTC_CTL _MMIO(0xe7000)
> +#define PCH_GTC_ENABLE (1 << 31)
> +
> +/* Display Port */
> +#define DP_A _MMIO(0x64000) /* eDP */
> +#define DP_B _MMIO(0x64100)
> +#define DP_C _MMIO(0x64200)
> +#define DP_D _MMIO(0x64300)
> +#define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100)
> +#define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200)
> +#define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300)
> +#define DP_PORT_EN REG_BIT(31)
> +#define DP_PIPE_SEL_MASK REG_GENMASK(30, 30)
> +#define DP_PIPE_SEL(pipe) REG_FIELD_PREP(DP_PIPE_SEL_MASK,
> (pipe))
> +#define DP_PIPE_SEL_MASK_IVB REG_GENMASK(30, 29)
> +#define DP_PIPE_SEL_IVB(pipe)
> REG_FIELD_PREP(DP_PIPE_SEL_MASK_IVB, (pipe))
> +#define DP_PIPE_SEL_SHIFT_CHV 16
> +#define DP_PIPE_SEL_MASK_CHV REG_GENMASK(17, 16)
> +#define DP_PIPE_SEL_CHV(pipe)
> REG_FIELD_PREP(DP_PIPE_SEL_MASK_CHV, (pipe))
> +#define DP_LINK_TRAIN_MASK REG_GENMASK(29, 28)
> +#define DP_LINK_TRAIN_PAT_1
> REG_FIELD_PREP(DP_LINK_TRAIN_MASK, 0)
> +#define DP_LINK_TRAIN_PAT_2
> REG_FIELD_PREP(DP_LINK_TRAIN_MASK, 1)
> +#define DP_LINK_TRAIN_PAT_IDLE
> REG_FIELD_PREP(DP_LINK_TRAIN_MASK, 2)
> +#define DP_LINK_TRAIN_OFF
> REG_FIELD_PREP(DP_LINK_TRAIN_MASK, 3)
> +#define DP_LINK_TRAIN_MASK_CPT REG_GENMASK(10, 8)
> +#define DP_LINK_TRAIN_PAT_1_CPT
> REG_FIELD_PREP(DP_LINK_TRAIN_MASK_CPT, 0)
> +#define DP_LINK_TRAIN_PAT_2_CPT
> REG_FIELD_PREP(DP_LINK_TRAIN_MASK_CPT, 1)
> +#define DP_LINK_TRAIN_PAT_IDLE_CPT
> REG_FIELD_PREP(DP_LINK_TRAIN_MASK_CPT, 2)
> +#define DP_LINK_TRAIN_OFF_CPT
> REG_FIELD_PREP(DP_LINK_TRAIN_MASK_CPT, 3)
> +#define DP_VOLTAGE_MASK REG_GENMASK(27, 25)
> +#define DP_VOLTAGE_0_4 REG_FIELD_PREP(DP_VOLTAGE_MASK,
> 0)
> +#define DP_VOLTAGE_0_6 REG_FIELD_PREP(DP_VOLTAGE_MASK,
> 1)
> +#define DP_VOLTAGE_0_8 REG_FIELD_PREP(DP_VOLTAGE_MASK,
> 2)
> +#define DP_VOLTAGE_1_2 REG_FIELD_PREP(DP_VOLTAGE_MASK,
> 3)
> +#define DP_PRE_EMPHASIS_MASK REG_GENMASK(24, 22)
> +#define DP_PRE_EMPHASIS_0
> REG_FIELD_PREP(DP_PRE_EMPHASIS_MASK, 0)
> +#define DP_PRE_EMPHASIS_3_5
> REG_FIELD_PREP(DP_PRE_EMPHASIS_MASK, 1)
> +#define DP_PRE_EMPHASIS_6
> REG_FIELD_PREP(DP_PRE_EMPHASIS_MASK, 2)
> +#define DP_PRE_EMPHASIS_9_5
> REG_FIELD_PREP(DP_PRE_EMPHASIS_MASK, 3)
> +#define DP_PORT_WIDTH_MASK REG_GENMASK(21, 19)
> +#define DP_PORT_WIDTH(width)
> REG_FIELD_PREP(DP_PORT_WIDTH_MASK, (width) - 1)
> +#define DP_ENHANCED_FRAMING REG_BIT(18)
> +#define EDP_PLL_FREQ_MASK REG_GENMASK(17, 16)
> +#define EDP_PLL_FREQ_270MHZ
> REG_FIELD_PREP(EDP_PLL_FREQ_MASK, 0)
> +#define EDP_PLL_FREQ_162MHZ
> REG_FIELD_PREP(EDP_PLL_FREQ_MASK, 1)
> +#define DP_PORT_REVERSAL REG_BIT(15)
> +#define EDP_PLL_ENABLE REG_BIT(14)
> +#define DP_CLOCK_OUTPUT_ENABLE REG_BIT(13)
> +#define DP_SCRAMBLING_DISABLE REG_BIT(12)
> +#define DP_SCRAMBLING_DISABLE_ILK REG_BIT(7)
> +#define DP_COLOR_RANGE_16_235 REG_BIT(8)
> +#define DP_AUDIO_OUTPUT_ENABLE REG_BIT(6)
> +#define DP_SYNC_VS_HIGH REG_BIT(4)
> +#define DP_SYNC_HS_HIGH REG_BIT(3)
> +#define DP_DETECTED REG_BIT(2)
> +
> +/*
> + * Computing GMCH M and N values for the Display Port link
> + *
> + * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
> + *
> + * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
> + *
> + * The GMCH value is used internally
> + *
> + * bytes_per_pixel is the number of bytes coming out of the plane,
> + * which is after the LUTs, so we want the bytes for our color format.
> + * For our current usage, this is always 3, one byte for R, G and B.
> + */
> +#define _PIPEA_DATA_M_G4X 0x70050
> +#define _PIPEB_DATA_M_G4X 0x71050
> +#define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X,
> _PIPEB_DATA_M_G4X)
> +/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
> +#define TU_SIZE_MASK REG_GENMASK(30, 25)
> +#define TU_SIZE(x) REG_FIELD_PREP(TU_SIZE_MASK, (x) - 1) /*
> default size 64 */
> +#define DATA_LINK_M_N_MASK REG_GENMASK(23, 0)
> +#define DATA_LINK_N_MAX (0x800000)
> +
> +#define _PIPEA_DATA_N_G4X 0x70054
> +#define _PIPEB_DATA_N_G4X 0x71054
> +#define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X,
> _PIPEB_DATA_N_G4X)
> +
> +/*
> + * Computing Link M and N values for the Display Port link
> + *
> + * Link M / N = pixel_clock / ls_clk
> + *
> + * (the DP spec calls pixel_clock the 'strm_clk')
> + *
> + * The Link value is transmitted in the Main Stream
> + * Attributes and VB-ID.
> + */
> +#define _PIPEA_LINK_M_G4X 0x70060
> +#define _PIPEB_LINK_M_G4X 0x71060
> +#define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X,
> _PIPEB_LINK_M_G4X)
> +
> +#define _PIPEA_LINK_N_G4X 0x70064
> +#define _PIPEB_LINK_N_G4X 0x71064
> +#define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X,
> _PIPEB_LINK_N_G4X)
> +
> +/* Pipe A */
> +#define _PIPEADSL 0x70000
> +#define PIPEDSL(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe,
> _PIPEADSL)
> +#define PIPEDSL_CURR_FIELD REG_BIT(31) /* ctg+ */
> +#define PIPEDSL_LINE_MASK REG_GENMASK(19, 0)
> +
> +#define _TRANSACONF 0x70008
> +#define TRANSCONF(dev_priv, trans) _MMIO_PIPE2(dev_priv, (trans),
> _TRANSACONF)
> +#define TRANSCONF_ENABLE REG_BIT(31)
> +#define TRANSCONF_DOUBLE_WIDE REG_BIT(30) /* pre-
> i965 */
> +#define TRANSCONF_STATE_ENABLE REG_BIT(30) /* i965+
> */
> +#define TRANSCONF_DSI_PLL_LOCKED REG_BIT(29) /* vlv &
> pipe A only */
> +#define TRANSCONF_FRAME_START_DELAY_MASK REG_GENMASK(28,
> 27) /* pre-hsw */
> +#define TRANSCONF_FRAME_START_DELAY(x)
> REG_FIELD_PREP(TRANSCONF_FRAME_START_DELAY_MASK, (x)) /*
> pre-hsw: 0-3 */
> +#define TRANSCONF_PIPE_LOCKED REG_BIT(25)
> +#define TRANSCONF_FORCE_BORDER REG_BIT(25)
> +#define TRANSCONF_GAMMA_MODE_MASK_I9XX REG_BIT(24)
> /* gmch */
> +#define TRANSCONF_GAMMA_MODE_MASK_ILK
> REG_GENMASK(25, 24) /* ilk-ivb */
> +#define TRANSCONF_GAMMA_MODE_8BIT
> REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 0)
> +#define TRANSCONF_GAMMA_MODE_10BIT
> REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 1)
> +#define TRANSCONF_GAMMA_MODE_12BIT
> REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-
> ivb */
> +#define TRANSCONF_GAMMA_MODE_SPLIT
> REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 3) /* ivb */
> +#define TRANSCONF_GAMMA_MODE(x)
> REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, (x)) /* pass
> in GAMMA_MODE_MODE_* */
> +#define TRANSCONF_INTERLACE_MASK REG_GENMASK(23,
> 21) /* gen3+ */
> +#define TRANSCONF_INTERLACE_PROGRESSIVE
> REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 0)
> +#define TRANSCONF_INTERLACE_W_SYNC_SHIFT_PANEL
> REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 4) /* gen4 only */
> +#define TRANSCONF_INTERLACE_W_SYNC_SHIFT
> REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 5) /* gen4 only */
> +#define TRANSCONF_INTERLACE_W_FIELD_INDICATION
> REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 6)
> +#define TRANSCONF_INTERLACE_FIELD_0_ONLY
> REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 7) /* gen3 only */
> +/*
> + * ilk+: PF/D=progressive fetch/display, IF/D=interlaced fetch/display,
> + * DBL=power saving pixel doubling, PF-ID* requires panel fitter
> + */
> +#define TRANSCONF_INTERLACE_MASK_ILK REG_GENMASK(23,
> 21) /* ilk+ */
> +#define TRANSCONF_INTERLACE_MASK_HSW REG_GENMASK(22,
> 21) /* hsw+ */
> +#define TRANSCONF_INTERLACE_PF_PD_ILK
> REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 0)
> +#define TRANSCONF_INTERLACE_PF_ID_ILK
> REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 1)
> +#define TRANSCONF_INTERLACE_IF_ID_ILK
> REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 3)
> +#define TRANSCONF_INTERLACE_IF_ID_DBL_ILK
> REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 4) /* ilk/snb
> only */
> +#define TRANSCONF_INTERLACE_PF_ID_DBL_ILK
> REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 5) /* ilk/snb
> only */
> +#define TRANSCONF_REFRESH_RATE_ALT_ILK REG_BIT(20)
> +#define TRANSCONF_MSA_TIMING_DELAY_MASK REG_GENMASK(19,
> 18) /* ilk/snb/ivb */
> +#define TRANSCONF_MSA_TIMING_DELAY(x)
> REG_FIELD_PREP(TRANSCONF_MSA_TIMING_DELAY_MASK, (x))
> +#define TRANSCONF_CXSR_DOWNCLOCK REG_BIT(16)
> +#define TRANSCONF_WGC_ENABLE REG_BIT(15) /* vlv/chv
> only */
> +#define TRANSCONF_REFRESH_RATE_ALT_VLV REG_BIT(14)
> +#define TRANSCONF_COLOR_RANGE_SELECT REG_BIT(13)
> +#define TRANSCONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12,
> 11) /* ilk-ivb */
> +#define TRANSCONF_OUTPUT_COLORSPACE_RGB
> REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-
> ivb */
> +#define TRANSCONF_OUTPUT_COLORSPACE_YUV601
> REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-
> ivb */
> +#define TRANSCONF_OUTPUT_COLORSPACE_YUV709
> REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-
> ivb */
> +#define TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW REG_BIT(11)
> /* hsw only */
> +#define TRANSCONF_BPC_MASK REG_GENMASK(7, 5)
> /* ctg-ivb */
> +#define TRANSCONF_BPC_8
> REG_FIELD_PREP(TRANSCONF_BPC_MASK, 0)
> +#define TRANSCONF_BPC_10
> REG_FIELD_PREP(TRANSCONF_BPC_MASK, 1)
> +#define TRANSCONF_BPC_6
> REG_FIELD_PREP(TRANSCONF_BPC_MASK, 2)
> +#define TRANSCONF_BPC_12
> REG_FIELD_PREP(TRANSCONF_BPC_MASK, 3)
> +#define TRANSCONF_DITHER_EN REG_BIT(4)
> +#define TRANSCONF_DITHER_TYPE_MASK REG_GENMASK(3, 2)
> +#define TRANSCONF_DITHER_TYPE_SP
> REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 0)
> +#define TRANSCONF_DITHER_TYPE_ST1
> REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 1)
> +#define TRANSCONF_DITHER_TYPE_ST2
> REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 2)
> +#define TRANSCONF_DITHER_TYPE_TEMP
> REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 3)
> +#define TRANSCONF_PIXEL_COUNT_SCALING_MASK REG_GENMASK(1, 0)
> +#define TRANSCONF_PIXEL_COUNT_SCALING_X4 1
> +
> +#define _PIPE_ARB_CTL_A 0x70028 /* icl+ */
> +#define PIPE_ARB_CTL(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe,
> _PIPE_ARB_CTL_A)
> +#define PIPE_ARB_USE_PROG_SLOTS REG_BIT(13)
> +
> +#define _PIPE_MISC_A 0x70030
> +#define _PIPE_MISC_B 0x71030
> +#define PIPE_MISC(pipe) _MMIO_PIPE(pipe,
> _PIPE_MISC_A, _PIPE_MISC_B)
> +#define PIPE_MISC_YUV420_ENABLE REG_BIT(27) /* glk+ */
> +#define PIPE_MISC_YUV420_MODE_FULL_BLEND REG_BIT(26) /* glk+ */
> +#define PIPE_MISC_HDR_MODE_PRECISION REG_BIT(23) /* icl+ */
> +#define PIPE_MISC_PSR_MASK_PRIMARY_FLIP REG_BIT(23) /* bdw */
> +#define PIPE_MISC_PSR_MASK_SPRITE_ENABLE REG_BIT(22) /* bdw */
> +#define PIPE_MISC_PSR_MASK_PIPE_REG_WRITE REG_BIT(21) /* skl+ */
> +#define PIPE_MISC_PSR_MASK_CURSOR_MOVE REG_BIT(21) /* bdw */
> +#define PIPE_MISC_PSR_MASK_VBLANK_VSYNC_INT REG_BIT(20)
> +#define PIPE_MISC_OUTPUT_COLORSPACE_YUV REG_BIT(11)
> +#define PIPE_MISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */
> +/*
> + * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with
> + * valid values of: 6, 8, 10 BPC.
> + * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of:
> + * 6, 8, 10, 12 BPC.
> + */
> +#define PIPE_MISC_BPC_MASK REG_GENMASK(7, 5)
> +#define PIPE_MISC_BPC_8
> REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 0)
> +#define PIPE_MISC_BPC_10
> REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 1)
> +#define PIPE_MISC_BPC_6
> REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 2)
> +#define PIPE_MISC_BPC_12_ADLP
> REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 4) /* adlp+ */
> +#define PIPE_MISC_DITHER_ENABLE REG_BIT(4)
> +#define PIPE_MISC_DITHER_TYPE_MASK REG_GENMASK(3, 2)
> +#define PIPE_MISC_DITHER_TYPE_SP
> REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 0)
> +#define PIPE_MISC_DITHER_TYPE_ST1
> REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 1)
> +#define PIPE_MISC_DITHER_TYPE_ST2
> REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 2)
> +#define PIPE_MISC_DITHER_TYPE_TEMP
> REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 3)
> +
> +#define _PIPE_MISC2_A 0x7002C
> +#define _PIPE_MISC2_B 0x7102C
> +#define PIPE_MISC2(pipe) _MMIO_PIPE(pipe, _PIPE_MISC2_A,
> _PIPE_MISC2_B)
> +#define PIPE_MISC2_BUBBLE_COUNTER_MASK REG_GENMASK(31,
> 24)
> +#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN
> REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 80)
> +#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS
> REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 20)
> +#define PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK
> REG_GENMASK(2, 0) /* tgl+ */
> +#define PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id)
> REG_FIELD_PREP(PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK,
> (plane_id))
> +
> +#define DPINVGTT _MMIO(VLV_DISPLAY_BASE +
> 0x7002c) /* VLV/CHV only */
> +#define DPINVGTT_EN_MASK_CHV
> REG_GENMASK(27, 16)
> +#define DPINVGTT_EN_MASK_VLV
> REG_GENMASK(23, 16)
> +#define SPRITEF_INVALID_GTT_INT_EN REG_BIT(27)
> +#define SPRITEE_INVALID_GTT_INT_EN REG_BIT(26)
> +#define PLANEC_INVALID_GTT_INT_EN REG_BIT(25)
> +#define CURSORC_INVALID_GTT_INT_EN REG_BIT(24)
> +#define CURSORB_INVALID_GTT_INT_EN REG_BIT(23)
> +#define CURSORA_INVALID_GTT_INT_EN REG_BIT(22)
> +#define SPRITED_INVALID_GTT_INT_EN REG_BIT(21)
> +#define SPRITEC_INVALID_GTT_INT_EN REG_BIT(20)
> +#define PLANEB_INVALID_GTT_INT_EN REG_BIT(19)
> +#define SPRITEB_INVALID_GTT_INT_EN REG_BIT(18)
> +#define SPRITEA_INVALID_GTT_INT_EN REG_BIT(17)
> +#define PLANEA_INVALID_GTT_INT_EN REG_BIT(16)
> +#define DPINVGTT_STATUS_MASK_CHV
> REG_GENMASK(11, 0)
> +#define DPINVGTT_STATUS_MASK_VLV
> REG_GENMASK(7, 0)
> +#define SPRITEF_INVALID_GTT_STATUS REG_BIT(11)
> +#define SPRITEE_INVALID_GTT_STATUS REG_BIT(10)
> +#define PLANEC_INVALID_GTT_STATUS REG_BIT(9)
> +#define CURSORC_INVALID_GTT_STATUS REG_BIT(8)
> +#define CURSORB_INVALID_GTT_STATUS REG_BIT(7)
> +#define CURSORA_INVALID_GTT_STATUS REG_BIT(6)
> +#define SPRITED_INVALID_GTT_STATUS REG_BIT(5)
> +#define SPRITEC_INVALID_GTT_STATUS REG_BIT(4)
> +#define PLANEB_INVALID_GTT_STATUS REG_BIT(3)
> +#define SPRITEB_INVALID_GTT_STATUS REG_BIT(2)
> +#define SPRITEA_INVALID_GTT_STATUS REG_BIT(1)
> +#define PLANEA_INVALID_GTT_STATUS REG_BIT(0)
> +
> +#define CBR1_VLV _MMIO(VLV_DISPLAY_BASE +
> 0x70400)
> +#define CBR_PND_DEADLINE_DISABLE (1 << 31)
> +#define CBR_PWM_CLOCK_MUX_SELECT (1 << 30)
> +
> +#define CBR4_VLV _MMIO(VLV_DISPLAY_BASE +
> 0x70450)
> +#define CBR_DPLLBMD_PIPE(pipe) (1 << (7 + (pipe) * 11)) /* pipes
> B and C */
> +
> +/*
> + * The two pipe frame counter registers are not synchronized, so
> + * reading a stable value is somewhat tricky. The following code
> + * should work:
> + *
> + * do {
> + * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
> + * PIPE_FRAME_HIGH_SHIFT;
> + * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
> + * PIPE_FRAME_LOW_SHIFT);
> + * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
> + * PIPE_FRAME_HIGH_SHIFT);
> + * } while (high1 != high2);
> + * frame = (high1 << 8) | low1;
> + */
> +#define _PIPEAFRAMEHIGH 0x70040
> +#define PIPEFRAME(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe,
> _PIPEAFRAMEHIGH)
> +#define PIPE_FRAME_HIGH_MASK 0x0000ffff
> +#define PIPE_FRAME_HIGH_SHIFT 0
> +
> +#define _PIPEAFRAMEPIXEL 0x70044
> +#define PIPEFRAMEPIXEL(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe,
> _PIPEAFRAMEPIXEL)
> +#define PIPE_FRAME_LOW_MASK 0xff000000
> +#define PIPE_FRAME_LOW_SHIFT 24
> +#define PIPE_PIXEL_MASK 0x00ffffff
> +#define PIPE_PIXEL_SHIFT 0
> +
> +/* GM45+ just has to be different */
> +#define _PIPEA_FRMCOUNT_G4X 0x70040
> +#define PIPE_FRMCOUNT_G4X(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe,
> _PIPEA_FRMCOUNT_G4X)
> +
> +#define _PIPEA_FLIPCOUNT_G4X 0x70044
> +#define PIPE_FLIPCOUNT_G4X(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe,
> _PIPEA_FLIPCOUNT_G4X)
> +
> +/* CHV pipe B blender */
> +#define _CHV_BLEND_A 0x60a00
> +#define CHV_BLEND(dev_priv, pipe) _MMIO_TRANS2(dev_priv,
> pipe, _CHV_BLEND_A)
> +#define CHV_BLEND_MASK REG_GENMASK(31, 30)
> +#define CHV_BLEND_LEGACY REG_FIELD_PREP(CHV_BLEND_MASK, 0)
> +#define CHV_BLEND_ANDROID REG_FIELD_PREP(CHV_BLEND_MASK,
> 1)
> +#define CHV_BLEND_MPO REG_FIELD_PREP(CHV_BLEND_MASK,
> 2)
> +
> +#define _CHV_CANVAS_A 0x60a04
> +#define CHV_CANVAS(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe,
> _CHV_CANVAS_A)
> +#define CHV_CANVAS_RED_MASK REG_GENMASK(29, 20)
> +#define CHV_CANVAS_GREEN_MASK REG_GENMASK(19, 10)
> +#define CHV_CANVAS_BLUE_MASK REG_GENMASK(9, 0)
> +
> +/* Display/Sprite base address macros */
> +#define DISP_BASEADDR_MASK (0xfffff000)
> +#define I915_LO_DISPBASE(val) ((val) & ~DISP_BASEADDR_MASK)
> +#define I915_HI_DISPBASE(val) ((val) & DISP_BASEADDR_MASK)
> +
> +/*
> + * VBIOS flags
> + * gen2:
> + * [00:06] alm,mgm
> + * [10:16] all
> + * [30:32] alm,mgm
> + * gen3+:
> + * [00:0f] all
> + * [10:1f] all
> + * [30:32] all
> + */
> +#define SWF0(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) +
> 0x70410 + (i) * 4)
> +#define SWF1(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) +
> 0x71410 + (i) * 4)
> +#define SWF3(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) +
> 0x72414 + (i) * 4)
> +#define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)
> +
> +/* VBIOS regs */
> +#define VGACNTRL _MMIO(0x71400)
> +# define VGA_DISP_DISABLE (1 << 31)
> +# define VGA_2X_MODE (1 << 30)
> +# define VGA_PIPE_B_SELECT (1 << 29)
> +
> +#define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE +
> 0x71400)
> +
> +#define CPU_VGACNTRL _MMIO(0x41000)
> +
> +#define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030)
> +#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
> +#define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */
> +#define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */
> +#define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */
> +#define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */
> +#define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */
> +#define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0)
> +#define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0)
> +#define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0)
> +#define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0)
> +
> +/* refresh rate hardware control */
> +#define RR_HW_CTL _MMIO(0x45300)
> +#define RR_HW_LOW_POWER_FRAMES_MASK 0xff
> +#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
> +
> +#define _PIPEA_DATA_M1 0x60030
> +#define _PIPEB_DATA_M1 0x61030
> +#define PIPE_DATA_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran,
> _PIPEA_DATA_M1)
> +
> +#define _PIPEA_DATA_N1 0x60034
> +#define _PIPEB_DATA_N1 0x61034
> +#define PIPE_DATA_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran,
> _PIPEA_DATA_N1)
> +
> +#define _PIPEA_DATA_M2 0x60038
> +#define _PIPEB_DATA_M2 0x61038
> +#define PIPE_DATA_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran,
> _PIPEA_DATA_M2)
> +
> +#define _PIPEA_DATA_N2 0x6003c
> +#define _PIPEB_DATA_N2 0x6103c
> +#define PIPE_DATA_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran,
> _PIPEA_DATA_N2)
> +
> +#define _PIPEA_LINK_M1 0x60040
> +#define _PIPEB_LINK_M1 0x61040
> +#define PIPE_LINK_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran,
> _PIPEA_LINK_M1)
> +
> +#define _PIPEA_LINK_N1 0x60044
> +#define _PIPEB_LINK_N1 0x61044
> +#define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran,
> _PIPEA_LINK_N1)
> +
> +#define _PIPEA_LINK_M2 0x60048
> +#define _PIPEB_LINK_M2 0x61048
> +#define PIPE_LINK_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran,
> _PIPEA_LINK_M2)
> +
> +#define _PIPEA_LINK_N2 0x6004c
> +#define _PIPEB_LINK_N2 0x6104c
> +#define PIPE_LINK_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran,
> _PIPEA_LINK_N2)
> +
> +/*
> + * Skylake scalers
> + */
> +#define _ID(id, a, b) _PICK_EVEN(id, a, b)
> +#define _PS_1A_CTRL 0x68180
> +#define _PS_2A_CTRL 0x68280
> +#define _PS_1B_CTRL 0x68980
> +#define _PS_2B_CTRL 0x68A80
> +#define _PS_1C_CTRL 0x69180
> +#define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \
> + _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \
> + _ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
> +#define PS_SCALER_EN REG_BIT(31)
> +#define PS_SCALER_TYPE_MASK REG_BIT(30) /* icl+ */
> +#define PS_SCALER_TYPE_NON_LINEAR
> REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 0)
> +#define PS_SCALER_TYPE_LINEAR
> REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 1)
> +#define SKL_PS_SCALER_MODE_MASK REG_GENMASK(29,
> 28) /* skl/bxt */
> +#define SKL_PS_SCALER_MODE_DYN
> REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 0)
> +#define SKL_PS_SCALER_MODE_HQ
> REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 1)
> +#define SKL_PS_SCALER_MODE_NV12
> REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 2)
> +#define PS_SCALER_MODE_MASK REG_BIT(29) /* glk-tgl
> */
> +#define PS_SCALER_MODE_NORMAL
> REG_FIELD_PREP(PS_SCALER_MODE_MASK, 0)
> +#define PS_SCALER_MODE_PLANAR
> REG_FIELD_PREP(PS_SCALER_MODE_MASK, 1)
> +#define PS_ADAPTIVE_FILTERING_EN REG_BIT(28) /* icl+ */
> +#define PS_BINDING_MASK REG_GENMASK(27, 25)
> +#define PS_BINDING_PIPE
> REG_FIELD_PREP(PS_BINDING_MASK, 0)
> +#define PS_BINDING_PLANE(plane_id)
> REG_FIELD_PREP(PS_BINDING_MASK, (plane_id) + 1)
> +#define PS_FILTER_MASK REG_GENMASK(24, 23)
> +#define PS_FILTER_MEDIUM
> REG_FIELD_PREP(PS_FILTER_MASK, 0)
> +#define PS_FILTER_PROGRAMMED
> REG_FIELD_PREP(PS_FILTER_MASK, 1)
> +#define PS_FILTER_EDGE_ENHANCE
> REG_FIELD_PREP(PS_FILTER_MASK, 2)
> +#define PS_FILTER_BILINEAR
> REG_FIELD_PREP(PS_FILTER_MASK, 3)
> +#define PS_ADAPTIVE_FILTER_MASK REG_BIT(22) /* icl+ */
> +#define PS_ADAPTIVE_FILTER_MEDIUM
> REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 0)
> +#define PS_ADAPTIVE_FILTER_EDGE_ENHANCE
> REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 1)
> +#define PS_PIPE_SCALER_LOC_MASK REG_BIT(21) /* icl+ */
> +#define PS_PIPE_SCALER_LOC_AFTER_OUTPUT_CSC
> REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 0) /* non-linear */
> +#define PS_PIPE_SCALER_LOC_AFTER_CSC
> REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 1) /* linear */
> +#define PS_VERT3TAP REG_BIT(21) /* skl/bxt
> */
> +#define PS_VERT_INT_INVERT_FIELD REG_BIT(20)
> +#define PS_PROG_SCALE_FACTOR REG_BIT(19) /* tgl+ */
> +#define PS_PWRUP_PROGRESS REG_BIT(17)
> +#define PS_V_FILTER_BYPASS REG_BIT(8)
> +#define PS_VADAPT_EN REG_BIT(7) /* skl/bxt
> */
> +#define PS_VADAPT_MODE_MASK REG_GENMASK(6, 5)
> /* skl/bxt */
> +#define PS_VADAPT_MODE_LEAST_ADAPT
> REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 0)
> +#define PS_VADAPT_MODE_MOD_ADAPT
> REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 1)
> +#define PS_VADAPT_MODE_MOST_ADAPT
> REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 3)
> +#define PS_BINDING_Y_MASK REG_GENMASK(7, 5)
> /* icl-tgl */
> +#define PS_BINDING_Y_PLANE(plane_id)
> REG_FIELD_PREP(PS_BINDING_Y_MASK, (plane_id) + 1)
> +#define PS_Y_VERT_FILTER_SELECT_MASK REG_BIT(4) /* glk+ */
> +#define PS_Y_VERT_FILTER_SELECT(set)
> REG_FIELD_PREP(PS_Y_VERT_FILTER_SELECT_MASK, (set))
> +#define PS_Y_HORZ_FILTER_SELECT_MASK REG_BIT(3) /* glk+ */
> +#define PS_Y_HORZ_FILTER_SELECT(set)
> REG_FIELD_PREP(PS_Y_HORZ_FILTER_SELECT_MASK, (set))
> +#define PS_UV_VERT_FILTER_SELECT_MASK REG_BIT(2) /* glk+ */
> +#define PS_UV_VERT_FILTER_SELECT(set)
> REG_FIELD_PREP(PS_UV_VERT_FILTER_SELECT_MASK, (set))
> +#define PS_UV_HORZ_FILTER_SELECT_MASK REG_BIT(1) /* glk+ */
> +#define PS_UV_HORZ_FILTER_SELECT(set)
> REG_FIELD_PREP(PS_UV_HORZ_FILTER_SELECT_MASK, (set))
> +
> +#define _PS_PWR_GATE_1A 0x68160
> +#define _PS_PWR_GATE_2A 0x68260
> +#define _PS_PWR_GATE_1B 0x68960
> +#define _PS_PWR_GATE_2B 0x68A60
> +#define _PS_PWR_GATE_1C 0x69160
> +#define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \
> + _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \
> + _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))
> +#define PS_PWR_GATE_DIS_OVERRIDE REG_BIT(31)
> +#define PS_PWR_GATE_SETTLING_TIME_MASK REG_GENMASK(4, 3)
> +#define PS_PWR_GATE_SETTLING_TIME_32
> REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 0)
> +#define PS_PWR_GATE_SETTLING_TIME_64
> REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 1)
> +#define PS_PWR_GATE_SETTLING_TIME_96
> REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 2)
> +#define PS_PWR_GATE_SETTLING_TIME_128
> REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 3)
> +#define PS_PWR_GATE_SLPEN_MASK REG_GENMASK(1, 0)
> +#define PS_PWR_GATE_SLPEN_8
> REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 0)
> +#define PS_PWR_GATE_SLPEN_16
> REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 1)
> +#define PS_PWR_GATE_SLPEN_24
> REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 2)
> +#define PS_PWR_GATE_SLPEN_32
> REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 3)
> +
> +#define _PS_WIN_POS_1A 0x68170
> +#define _PS_WIN_POS_2A 0x68270
> +#define _PS_WIN_POS_1B 0x68970
> +#define _PS_WIN_POS_2B 0x68A70
> +#define _PS_WIN_POS_1C 0x69170
> +#define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \
> + _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \
> + _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))
> +#define PS_WIN_XPOS_MASK REG_GENMASK(31, 16)
> +#define PS_WIN_XPOS(x)
> REG_FIELD_PREP(PS_WIN_XPOS_MASK, (x))
> +#define PS_WIN_YPOS_MASK REG_GENMASK(15, 0)
> +#define PS_WIN_YPOS(y)
> REG_FIELD_PREP(PS_WIN_YPOS_MASK, (y))
> +
> +#define _PS_WIN_SZ_1A 0x68174
> +#define _PS_WIN_SZ_2A 0x68274
> +#define _PS_WIN_SZ_1B 0x68974
> +#define _PS_WIN_SZ_2B 0x68A74
> +#define _PS_WIN_SZ_1C 0x69174
> +#define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \
> + _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \
> + _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))
> +#define PS_WIN_XSIZE_MASK REG_GENMASK(31, 16)
> +#define PS_WIN_XSIZE(w)
> REG_FIELD_PREP(PS_WIN_XSIZE_MASK, (w))
> +#define PS_WIN_YSIZE_MASK REG_GENMASK(15, 0)
> +#define PS_WIN_YSIZE(h)
> REG_FIELD_PREP(PS_WIN_YSIZE_MASK, (h))
> +
> +#define _PS_VSCALE_1A 0x68184
> +#define _PS_VSCALE_2A 0x68284
> +#define _PS_VSCALE_1B 0x68984
> +#define _PS_VSCALE_2B 0x68A84
> +#define _PS_VSCALE_1C 0x69184
> +#define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \
> + _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \
> + _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))
> +
> +#define _PS_HSCALE_1A 0x68190
> +#define _PS_HSCALE_2A 0x68290
> +#define _PS_HSCALE_1B 0x68990
> +#define _PS_HSCALE_2B 0x68A90
> +#define _PS_HSCALE_1C 0x69190
> +#define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \
> + _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \
> + _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))
> +
> +#define _PS_VPHASE_1A 0x68188
> +#define _PS_VPHASE_2A 0x68288
> +#define _PS_VPHASE_1B 0x68988
> +#define _PS_VPHASE_2B 0x68A88
> +#define _PS_VPHASE_1C 0x69188
> +#define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \
> + _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \
> + _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))
> +#define PS_Y_PHASE_MASK REG_GENMASK(31, 16)
> +#define PS_Y_PHASE(x)
> REG_FIELD_PREP(PS_Y_PHASE_MASK, (x))
> +#define PS_UV_RGB_PHASE_MASK REG_GENMASK(15, 0)
> +#define PS_UV_RGB_PHASE(x)
> REG_FIELD_PREP(PS_UV_RGB_PHASE_MASK, (x))
> +#define PS_PHASE_MASK (0x7fff << 1) /* u2.13
> */
> +#define PS_PHASE_TRIP (1 << 0)
> +
> +#define _PS_HPHASE_1A 0x68194
> +#define _PS_HPHASE_2A 0x68294
> +#define _PS_HPHASE_1B 0x68994
> +#define _PS_HPHASE_2B 0x68A94
> +#define _PS_HPHASE_1C 0x69194
> +#define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \
> + _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \
> + _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))
> +
> +#define _PS_ECC_STAT_1A 0x681D0
> +#define _PS_ECC_STAT_2A 0x682D0
> +#define _PS_ECC_STAT_1B 0x689D0
> +#define _PS_ECC_STAT_2B 0x68AD0
> +#define _PS_ECC_STAT_1C 0x691D0
> +#define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \
> + _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
> + _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
> +
> +#define _PS_COEF_SET0_INDEX_1A 0x68198
> +#define _PS_COEF_SET0_INDEX_2A 0x68298
> +#define _PS_COEF_SET0_INDEX_1B 0x68998
> +#define _PS_COEF_SET0_INDEX_2B 0x68A98
> +#define GLK_PS_COEF_INDEX_SET(pipe, id, set) _MMIO_PIPE(pipe, \
> + _ID(id, _PS_COEF_SET0_INDEX_1A,
> _PS_COEF_SET0_INDEX_2A) + (set) * 8, \
> + _ID(id, _PS_COEF_SET0_INDEX_1B,
> _PS_COEF_SET0_INDEX_2B) + (set) * 8)
> +#define PS_COEF_INDEX_AUTO_INC REG_BIT(10)
> +
> +#define _PS_COEF_SET0_DATA_1A 0x6819C
> +#define _PS_COEF_SET0_DATA_2A 0x6829C
> +#define _PS_COEF_SET0_DATA_1B 0x6899C
> +#define _PS_COEF_SET0_DATA_2B 0x68A9C
> +#define GLK_PS_COEF_DATA_SET(pipe, id, set) _MMIO_PIPE(pipe, \
> + _ID(id, _PS_COEF_SET0_DATA_1A,
> _PS_COEF_SET0_DATA_2A) + (set) * 8, \
> + _ID(id, _PS_COEF_SET0_DATA_1B,
> _PS_COEF_SET0_DATA_2B) + (set) * 8)
> +
> +/* More Ivybridge lolz */
> +#define DE_ERR_INT_IVB (1 << 30)
> +#define DE_GSE_IVB (1 << 29)
> +#define DE_PCH_EVENT_IVB (1 << 28)
> +#define DE_DP_A_HOTPLUG_IVB (1 << 27)
> +#define DE_AUX_CHANNEL_A_IVB (1 << 26)
> +#define DE_EDP_PSR_INT_HSW (1 << 19)
> +#define DE_SPRITEC_FLIP_DONE_IVB (1 << 14)
> +#define DE_PLANEC_FLIP_DONE_IVB (1 << 13)
> +#define DE_PIPEC_VBLANK_IVB (1 << 10)
> +#define DE_SPRITEB_FLIP_DONE_IVB (1 << 9)
> +#define DE_PLANEB_FLIP_DONE_IVB (1 << 8)
> +#define DE_PIPEB_VBLANK_IVB (1 << 5)
> +#define DE_SPRITEA_FLIP_DONE_IVB (1 << 4)
> +#define DE_PLANEA_FLIP_DONE_IVB (1 << 3)
> +#define DE_PLANE_FLIP_DONE_IVB(plane) (1 << (3 + 5 * (plane)))
> +#define DE_PIPEA_VBLANK_IVB (1 << 0)
> +#define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5))
> +
> +#define XELPD_DISPLAY_ERR_FATAL_MASK _MMIO(0x4421c)
> +
> +#define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))
> +#define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))
> +#define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))
> +#define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))
> +#define GEN8_PIPE_FIFO_UNDERRUN REG_BIT(31)
> +#define GEN8_PIPE_CDCLK_CRC_ERROR REG_BIT(29)
> +#define GEN8_PIPE_CDCLK_CRC_DONE REG_BIT(28)
> +#define GEN12_PIPEDMC_INTERRUPT REG_BIT(26) /* tgl+ */
> +#define GEN12_PIPEDMC_FAULT REG_BIT(25) /* tgl+ */
> +#define MTL_PIPEDMC_ATS_FAULT REG_BIT(24) /* mtl+ */
> +#define GEN11_PIPE_PLANE7_FAULT REG_BIT(22) /* icl/tgl */
> +#define GEN11_PIPE_PLANE6_FAULT REG_BIT(21) /* icl/tgl */
> +#define GEN11_PIPE_PLANE5_FAULT REG_BIT(20) /* icl+ */
> +#define GEN12_PIPE_VBLANK_UNMOD REG_BIT(19) /* tgl+ */
> +#define MTL_PLANE_ATS_FAULT REG_BIT(18) /* mtl+ */
> +#define GEN11_PIPE_PLANE7_FLIP_DONE REG_BIT(18) /* icl/tgl */
> +#define GEN11_PIPE_PLANE6_FLIP_DONE REG_BIT(17) /* icl/tgl */
> +#define GEN11_PIPE_PLANE5_FLIP_DONE REG_BIT(16) /* icl+ */
> +#define GEN12_DSB_2_INT REG_BIT(15) /* tgl+ */
> +#define GEN12_DSB_1_INT REG_BIT(14) /* tgl+ */
> +#define GEN12_DSB_0_INT REG_BIT(13) /* tgl+ */
> +#define GEN12_DSB_INT(dsb_id) REG_BIT(13 + (dsb_id))
> +#define GEN9_PIPE_CURSOR_FAULT REG_BIT(11) /* skl+ */
> +#define GEN9_PIPE_PLANE4_FAULT REG_BIT(10) /* skl+ */
> +#define GEN8_PIPE_CURSOR_FAULT REG_BIT(10) /* bdw */
> +#define GEN9_PIPE_PLANE3_FAULT REG_BIT(9) /* skl+ */
> +#define GEN8_PIPE_SPRITE_FAULT REG_BIT(9) /* bdw */
> +#define GEN9_PIPE_PLANE2_FAULT REG_BIT(8) /* skl+ */
> +#define GEN8_PIPE_PRIMARY_FAULT REG_BIT(8) /* bdw */
> +#define GEN9_PIPE_PLANE1_FAULT REG_BIT(7) /* skl+ */
> +#define GEN9_PIPE_PLANE4_FLIP_DONE REG_BIT(6) /* skl+ */
> +#define GEN9_PIPE_PLANE3_FLIP_DONE REG_BIT(5) /* skl+ */
> +#define GEN8_PIPE_SPRITE_FLIP_DONE REG_BIT(5) /* bdw */
> +#define GEN9_PIPE_PLANE2_FLIP_DONE REG_BIT(4) /* skl+ */
> +#define GEN8_PIPE_PRIMARY_FLIP_DONE REG_BIT(4) /* bdw */
> +#define GEN9_PIPE_PLANE1_FLIP_DONE REG_BIT(3) /* skl+ */
> +#define GEN9_PIPE_PLANE_FLIP_DONE(plane_id) \
> + REG_BIT(((plane_id) >= PLANE_5 ? 16 - PLANE_5 : 3 - PLANE_1) +
> (plane_id)) /* skl+ */
> +#define GEN8_PIPE_SCAN_LINE_EVENT REG_BIT(2)
> +#define GEN8_PIPE_VSYNC REG_BIT(1)
> +#define GEN8_PIPE_VBLANK REG_BIT(0)
> +
> +#define GEN8_DE_PIPE_IRQ_REGS(pipe)
> I915_IRQ_REGS(GEN8_DE_PIPE_IMR(pipe), \
> + GEN8_DE_PIPE_IER(pipe), \
> + GEN8_DE_PIPE_IIR(pipe))
> +
> +#define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A)
> +#define _HPD_PIN_TC(hpd_pin) ((hpd_pin) - HPD_PORT_TC1)
> +
> +#define GEN8_DE_PORT_ISR _MMIO(0x44440)
> +#define GEN8_DE_PORT_IMR _MMIO(0x44444)
> +#define GEN8_DE_PORT_IIR _MMIO(0x44448)
> +#define GEN8_DE_PORT_IER _MMIO(0x4444c)
> +#define DSI1_NON_TE (1 << 31)
> +#define DSI0_NON_TE (1 << 30)
> +#define ICL_AUX_CHANNEL_E (1 << 29)
> +#define ICL_AUX_CHANNEL_F (1 << 28)
> +#define GEN9_AUX_CHANNEL_D (1 << 27)
> +#define GEN9_AUX_CHANNEL_C (1 << 26)
> +#define GEN9_AUX_CHANNEL_B (1 << 25)
> +#define DSI1_TE (1 << 24)
> +#define DSI0_TE (1 << 23)
> +#define GEN8_DE_PORT_HOTPLUG(hpd_pin) REG_BIT(3 +
> _HPD_PIN_DDI(hpd_pin))
> +#define BXT_DE_PORT_HOTPLUG_MASK
> (GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \
> +
> GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \
> +
> GEN8_DE_PORT_HOTPLUG(HPD_PORT_C))
> +#define BDW_DE_PORT_HOTPLUG_MASK
> GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)
> +#define BXT_DE_PORT_GMBUS (1 << 1)
> +#define GEN8_AUX_CHANNEL_A (1 << 0)
> +#define TGL_DE_PORT_AUX_USBC6 REG_BIT(13)
> +#define XELPD_DE_PORT_AUX_DDIE REG_BIT(13)
> +#define TGL_DE_PORT_AUX_USBC5 REG_BIT(12)
> +#define XELPD_DE_PORT_AUX_DDID REG_BIT(12)
> +#define TGL_DE_PORT_AUX_USBC4 REG_BIT(11)
> +#define TGL_DE_PORT_AUX_USBC3 REG_BIT(10)
> +#define TGL_DE_PORT_AUX_USBC2 REG_BIT(9)
> +#define TGL_DE_PORT_AUX_USBC1 REG_BIT(8)
> +#define TGL_DE_PORT_AUX_DDIC REG_BIT(2)
> +#define TGL_DE_PORT_AUX_DDIB REG_BIT(1)
> +#define TGL_DE_PORT_AUX_DDIA REG_BIT(0)
> +
> +#define GEN8_DE_PORT_IRQ_REGS
> I915_IRQ_REGS(GEN8_DE_PORT_IMR, \
> + GEN8_DE_PORT_IER, \
> + GEN8_DE_PORT_IIR)
> +
> +#define GEN8_DE_MISC_IRQ_REGS
> I915_IRQ_REGS(GEN8_DE_MISC_IMR, \
> + GEN8_DE_MISC_IER, \
> + GEN8_DE_MISC_IIR)
> +
> +#define GEN11_DISPLAY_INT_CTL _MMIO(0x44200)
> +#define GEN11_DISPLAY_IRQ_ENABLE (1 << 31)
> +#define GEN11_AUDIO_CODEC_IRQ (1 << 24)
> +#define GEN11_DE_PCH_IRQ (1 << 23)
> +#define GEN11_DE_MISC_IRQ (1 << 22)
> +#define GEN11_DE_HPD_IRQ (1 << 21)
> +#define GEN11_DE_PORT_IRQ (1 << 20)
> +#define GEN11_DE_PIPE_C (1 << 18)
> +#define GEN11_DE_PIPE_B (1 << 17)
> +#define GEN11_DE_PIPE_A (1 << 16)
> +
> +#define GEN11_DE_HPD_ISR _MMIO(0x44470)
> +#define GEN11_DE_HPD_IMR _MMIO(0x44474)
> +#define GEN11_DE_HPD_IIR _MMIO(0x44478)
> +#define GEN11_DE_HPD_IER _MMIO(0x4447c)
> +#define GEN11_TC_HOTPLUG(hpd_pin) REG_BIT(16 +
> _HPD_PIN_TC(hpd_pin))
> +#define GEN11_DE_TC_HOTPLUG_MASK
> (GEN11_TC_HOTPLUG(HPD_PORT_TC6) | \
> +
> GEN11_TC_HOTPLUG(HPD_PORT_TC5) | \
> +
> GEN11_TC_HOTPLUG(HPD_PORT_TC4) | \
> +
> GEN11_TC_HOTPLUG(HPD_PORT_TC3) | \
> +
> GEN11_TC_HOTPLUG(HPD_PORT_TC2) | \
> +
> GEN11_TC_HOTPLUG(HPD_PORT_TC1))
> +#define GEN11_TBT_HOTPLUG(hpd_pin)
> REG_BIT(_HPD_PIN_TC(hpd_pin))
> +#define GEN11_DE_TBT_HOTPLUG_MASK
> (GEN11_TBT_HOTPLUG(HPD_PORT_TC6) | \
> +
> GEN11_TBT_HOTPLUG(HPD_PORT_TC5) | \
> +
> GEN11_TBT_HOTPLUG(HPD_PORT_TC4) | \
> +
> GEN11_TBT_HOTPLUG(HPD_PORT_TC3) | \
> +
> GEN11_TBT_HOTPLUG(HPD_PORT_TC2) | \
> +
> GEN11_TBT_HOTPLUG(HPD_PORT_TC1))
> +
> +#define GEN11_DE_HPD_IRQ_REGS
> I915_IRQ_REGS(GEN11_DE_HPD_IMR, \
> + GEN11_DE_HPD_IER, \
> + GEN11_DE_HPD_IIR)
> +
> +#define GEN11_TBT_HOTPLUG_CTL
> _MMIO(0x44030)
> +#define GEN11_TC_HOTPLUG_CTL
> _MMIO(0x44038)
> +#define GEN11_HOTPLUG_CTL_ENABLE(hpd_pin) (8 <<
> (_HPD_PIN_TC(hpd_pin) * 4))
> +#define GEN11_HOTPLUG_CTL_LONG_DETECT(hpd_pin) (2 <<
> (_HPD_PIN_TC(hpd_pin) * 4))
> +#define GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin) (1 <<
> (_HPD_PIN_TC(hpd_pin) * 4))
> +#define GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin) (0 <<
> (_HPD_PIN_TC(hpd_pin) * 4))
> +
> +#define PICAINTERRUPT_ISR _MMIO(0x16FE50)
> +#define PICAINTERRUPT_IMR _MMIO(0x16FE54)
> +#define PICAINTERRUPT_IIR _MMIO(0x16FE58)
> +#define PICAINTERRUPT_IER _MMIO(0x16FE5C)
> +#define XELPDP_DP_ALT_HOTPLUG(hpd_pin) REG_BIT(16 +
> _HPD_PIN_TC(hpd_pin))
> +#define XELPDP_DP_ALT_HOTPLUG_MASK REG_GENMASK(19,
> 16)
> +#define XELPDP_AUX_TC(hpd_pin) REG_BIT(8 +
> _HPD_PIN_TC(hpd_pin))
> +#define XELPDP_AUX_TC_MASK REG_GENMASK(11, 8)
> +#define XE2LPD_AUX_DDI(hpd_pin) REG_BIT(6 +
> _HPD_PIN_DDI(hpd_pin))
> +#define XE2LPD_AUX_DDI_MASK REG_GENMASK(7, 6)
> +#define XELPDP_TBT_HOTPLUG(hpd_pin)
> REG_BIT(_HPD_PIN_TC(hpd_pin))
> +#define XELPDP_TBT_HOTPLUG_MASK REG_GENMASK(3, 0)
> +
> +#define PICAINTERRUPT_IRQ_REGS
> I915_IRQ_REGS(PICAINTERRUPT_IMR, \
> +
> PICAINTERRUPT_IER, \
> +
> PICAINTERRUPT_IIR)
> +
> +#define XELPDP_PORT_HOTPLUG_CTL(hpd_pin) _MMIO(0x16F270 +
> (_HPD_PIN_TC(hpd_pin) * 0x200))
> +#define XELPDP_TBT_HOTPLUG_ENABLE REG_BIT(6)
> +#define XELPDP_TBT_HPD_LONG_DETECT REG_BIT(5)
> +#define XELPDP_TBT_HPD_SHORT_DETECT REG_BIT(4)
> +#define XELPDP_DP_ALT_HOTPLUG_ENABLE REG_BIT(2)
> +#define XELPDP_DP_ALT_HPD_LONG_DETECT REG_BIT(1)
> +#define XELPDP_DP_ALT_HPD_SHORT_DETECT REG_BIT(0)
> +
> +#define XELPDP_INITIATE_PMDEMAND_REQUEST(dword)
> _MMIO(0x45230 + 4 * (dword))
> +#define XELPDP_PMDEMAND_QCLK_GV_BW_MASK
> REG_GENMASK(31, 16)
> +#define XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK
> REG_GENMASK(14, 12)
> +#define XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK
> REG_GENMASK(11, 8)
> +#define XE3_PMDEMAND_PIPES_MASK
> REG_GENMASK(7, 4)
> +#define XELPDP_PMDEMAND_PIPES_MASK
> REG_GENMASK(7, 6)
> +#define XELPDP_PMDEMAND_DBUFS_MASK
> REG_GENMASK(5, 4)
> +#define XELPDP_PMDEMAND_PHYS_MASK
> REG_GENMASK(2, 0)
> +
> +#define XELPDP_PMDEMAND_REQ_ENABLE REG_BIT(31)
> +#define XELPDP_PMDEMAND_CDCLK_FREQ_MASK
> REG_GENMASK(30, 20)
> +#define XELPDP_PMDEMAND_DDICLK_FREQ_MASK
> REG_GENMASK(18, 8)
> +#define XELPDP_PMDEMAND_SCALERS_MASK
> REG_GENMASK(6, 4)
> +#define XELPDP_PMDEMAND_PLLS_MASK
> REG_GENMASK(2, 0)
> +
> +#define GEN12_DCPR_STATUS_1
> _MMIO(0x46440)
> +#define XELPDP_PMDEMAND_INFLIGHT_STATUS REG_BIT(26)
> +
> +#define FUSE_STRAP _MMIO(0x42014)
> +#define ILK_INTERNAL_GRAPHICS_DISABLE REG_BIT(31)
> +#define ILK_INTERNAL_DISPLAY_DISABLE REG_BIT(30)
> +#define ILK_DISPLAY_DEBUG_DISABLE REG_BIT(29)
> +#define IVB_PIPE_C_DISABLE REG_BIT(28)
> +#define ILK_HDCP_DISABLE REG_BIT(25)
> +#define ILK_eDP_A_DISABLE REG_BIT(24)
> +#define HSW_CDCLK_LIMIT REG_BIT(24)
> +#define ILK_DESKTOP REG_BIT(23)
> +#define HSW_CPU_SSC_ENABLE REG_BIT(21)
> +
> +#define FUSE_STRAP3 _MMIO(0x42020)
> +#define HSW_REF_CLK_SELECT REG_BIT(1)
> +
> +#define CHICKEN_MISC_2 _MMIO(0x42084)
> +#define CHICKEN_MISC_DISABLE_DPT REG_BIT(30) /* adl,dg2 */
> +#define BMG_DARB_HALF_BLK_END_BURST REG_BIT(27)
> +#define KBL_ARB_FILL_SPARE_14 REG_BIT(14)
> +#define KBL_ARB_FILL_SPARE_13 REG_BIT(13)
> +#define GLK_CL2_PWR_DOWN REG_BIT(12)
> +#define GLK_CL1_PWR_DOWN REG_BIT(11)
> +#define GLK_CL0_PWR_DOWN REG_BIT(10)
> +
> +#define CHICKEN_MISC_3 _MMIO(0x42088)
> +#define DP_MST_DPT_DPTP_ALIGN_WA(trans) REG_BIT(9 + (trans) -
> TRANSCODER_A)
> +#define DP_MST_SHORT_HBLANK_WA(trans) REG_BIT(5 + (trans) -
> TRANSCODER_A)
> +#define DP_MST_FEC_BS_JITTER_WA(trans) REG_BIT(0 + (trans) -
> TRANSCODER_A)
> +
> +#define CHICKEN_MISC_4 _MMIO(0x4208c)
> +#define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13)
> +#define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0)
> +#define CHICKEN_FBC_STRIDE(x)
> REG_FIELD_PREP(CHICKEN_FBC_STRIDE_MASK, (x))
> +
> +#define _CHICKEN_TRANS_A 0x420c0
> +#define _CHICKEN_TRANS_B 0x420c4
> +#define _CHICKEN_TRANS_C 0x420c8
> +#define _CHICKEN_TRANS_EDP 0x420cc
> +#define _CHICKEN_TRANS_D 0x420d8
> +#define _CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \
> + [TRANSCODER_EDP] =
> _CHICKEN_TRANS_EDP, \
> + [TRANSCODER_A] =
> _CHICKEN_TRANS_A, \
> + [TRANSCODER_B] =
> _CHICKEN_TRANS_B, \
> + [TRANSCODER_C] =
> _CHICKEN_TRANS_C, \
> + [TRANSCODER_D] =
> _CHICKEN_TRANS_D))
> +#define _MTL_CHICKEN_TRANS_A 0x604e0
> +#define _MTL_CHICKEN_TRANS_B 0x614e0
> +#define _MTL_CHICKEN_TRANS(trans) _MMIO_TRANS((trans), \
> + _MTL_CHICKEN_TRANS_A, \
> + _MTL_CHICKEN_TRANS_B)
> +#define CHICKEN_TRANS(display, trans) (DISPLAY_VER(display) >= 14 ?
> _MTL_CHICKEN_TRANS(trans) : _CHICKEN_TRANS(trans))
> +#define PIPE_VBLANK_WITH_DELAY REG_BIT(31) /* tgl+ */
> +#define SKL_UNMASK_VBL_TO_PIPE_IN_SRD REG_BIT(30) /* skl+ */
> +#define HSW_FRAME_START_DELAY_MASK REG_GENMASK(28, 27)
> +#define HSW_FRAME_START_DELAY(x)
> REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x)
> +#define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */
> +#define FECSTALL_DIS_DPTSTREAM_DPTTG REG_BIT(23)
> +#define DDI_TRAINING_OVERRIDE_ENABLE REG_BIT(19)
> +#define ADLP_1_BASED_X_GRANULARITY REG_BIT(18)
> +#define DDI_TRAINING_OVERRIDE_VALUE REG_BIT(18)
> +#define DDIE_TRAINING_OVERRIDE_ENABLE REG_BIT(17) /*
> CHICKEN_TRANS_A only */
> +#define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /*
> CHICKEN_TRANS_A only */
> +#define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15)
> +#define DP_FEC_BS_JITTER_WA REG_BIT(15)
> +#define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12)
> +#define DP_DSC_INSERT_SF_AT_EOL_WA REG_BIT(4)
> +#define HDCP_LINE_REKEY_DISABLE REG_BIT(0)
> +
> +#define DISP_ARB_CTL2 _MMIO(0x45004)
> +#define DISP_DATA_PARTITION_5_6 REG_BIT(6)
> +#define DISP_IPC_ENABLE REG_BIT(3)
> +
> +#define GEN7_MSG_CTL _MMIO(0x45010)
> +#define WAIT_FOR_PCH_RESET_ACK (1 << 1)
> +#define WAIT_FOR_PCH_FLR_ACK (1 << 0)
> +
> +#define _BW_BUDDY0_CTL 0x45130
> +#define _BW_BUDDY1_CTL 0x45140
> +#define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \
> + _BW_BUDDY0_CTL, \
> + _BW_BUDDY1_CTL))
> +#define BW_BUDDY_DISABLE REG_BIT(31)
> +#define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16)
> +#define BW_BUDDY_TLB_REQ_TIMER(x)
> REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, x)
> +
> +#define _BW_BUDDY0_PAGE_MASK 0x45134
> +#define _BW_BUDDY1_PAGE_MASK 0x45144
> +#define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \
> +
> _BW_BUDDY0_PAGE_MASK, \
> +
> _BW_BUDDY1_PAGE_MASK))
> +
> +#define HSW_NDE_RSTWRN_OPT _MMIO(0x46408)
> +#define MTL_RESET_PICA_HANDSHAKE_EN REG_BIT(6)
> +#define RESET_PCH_HANDSHAKE_ENABLE REG_BIT(4)
> +
> +#define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434)
> +#define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27)
> +#define DCPR_MASK_LPMODE REG_BIT(26)
> +#define DCPR_SEND_RESP_IMM REG_BIT(25)
> +#define DCPR_CLEAR_MEMSTAT_DIS REG_BIT(24)
> +
> +#define XELPD_CHICKEN_DCPR_3 _MMIO(0x46438)
> +#define DMD_RSP_TIMEOUT_DISABLE REG_BIT(19)
> +
> +#define SKL_DFSM _MMIO(0x51000)
> +#define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27)
> +#define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25)
> +#define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
> +#define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
> +#define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
> +#define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
> +#define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
> +#define ICL_DFSM_DMC_DISABLE (1 << 23)
> +#define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
> +#define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
> +#define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
> +#define TGL_DFSM_PIPE_D_DISABLE (1 << 22)
> +#define GLK_DFSM_DISPLAY_DSC_DISABLE (1 << 7)
> +#define XE2LPD_DFSM_DBUF_OVERLAP_DISABLE (1 << 3)
> +
> +#define XE2LPD_DE_CAP _MMIO(0x41100)
> +#define XE2LPD_DE_CAP_3DLUT_MASK REG_GENMASK(31, 30)
> +#define XE2LPD_DE_CAP_DSC_MASK REG_GENMASK(29, 28)
> +#define XE2LPD_DE_CAP_DSC_REMOVED 1
> +#define XE2LPD_DE_CAP_SCALER_MASK REG_GENMASK(27, 26)
> +#define XE2LPD_DE_CAP_SCALER_SINGLE 1
> +
> +#define SKL_DSSM _MMIO(0x51004)
> +#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29)
> +#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29)
> +#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29)
> +#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29)
> +
> +/*GEN11 chicken */
> +#define _PIPEA_CHICKEN 0x70038
> +#define _PIPEB_CHICKEN 0x71038
> +#define _PIPEC_CHICKEN 0x72038
> +#define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe,
> _PIPEA_CHICKEN,\
> + _PIPEB_CHICKEN)
> +#define UNDERRUN_RECOVERY_DISABLE_ADLP REG_BIT(30)
> +#define UNDERRUN_RECOVERY_ENABLE_DG2 REG_BIT(30)
> +#define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU REG_BIT(15)
> +#define DG2_RENDER_CCSTAG_4_3_EN REG_BIT(12)
> +#define PER_PIXEL_ALPHA_BYPASS_EN REG_BIT(7)
> +
> +#define PCH_DISPLAY_BASE 0xc0000u
> +
> +/* south display engine interrupt: IBX */
> +#define SDE_AUDIO_POWER_D (1 << 27)
> +#define SDE_AUDIO_POWER_C (1 << 26)
> +#define SDE_AUDIO_POWER_B (1 << 25)
> +#define SDE_AUDIO_POWER_SHIFT (25)
> +#define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
> +#define SDE_GMBUS (1 << 24)
> +#define SDE_AUDIO_HDCP_TRANSB (1 << 23)
> +#define SDE_AUDIO_HDCP_TRANSA (1 << 22)
> +#define SDE_AUDIO_HDCP_MASK (3 << 22)
> +#define SDE_AUDIO_TRANSB (1 << 21)
> +#define SDE_AUDIO_TRANSA (1 << 20)
> +#define SDE_AUDIO_TRANS_MASK (3 << 20)
> +#define SDE_POISON (1 << 19)
> +/* 18 reserved */
> +#define SDE_FDI_RXB (1 << 17)
> +#define SDE_FDI_RXA (1 << 16)
> +#define SDE_FDI_MASK (3 << 16)
> +#define SDE_AUXD (1 << 15)
> +#define SDE_AUXC (1 << 14)
> +#define SDE_AUXB (1 << 13)
> +#define SDE_AUX_MASK (7 << 13)
> +/* 12 reserved */
> +#define SDE_CRT_HOTPLUG (1 << 11)
> +#define SDE_PORTD_HOTPLUG (1 << 10)
> +#define SDE_PORTC_HOTPLUG (1 << 9)
> +#define SDE_PORTB_HOTPLUG (1 << 8)
> +#define SDE_SDVOB_HOTPLUG (1 << 6)
> +#define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \
> + SDE_SDVOB_HOTPLUG | \
> + SDE_PORTB_HOTPLUG | \
> + SDE_PORTC_HOTPLUG | \
> + SDE_PORTD_HOTPLUG)
> +#define SDE_TRANSB_CRC_DONE (1 << 5)
> +#define SDE_TRANSB_CRC_ERR (1 << 4)
> +#define SDE_TRANSB_FIFO_UNDER (1 << 3)
> +#define SDE_TRANSA_CRC_DONE (1 << 2)
> +#define SDE_TRANSA_CRC_ERR (1 << 1)
> +#define SDE_TRANSA_FIFO_UNDER (1 << 0)
> +#define SDE_TRANS_MASK (0x3f)
> +
> +/* south display engine interrupt: CPT - CNP */
> +#define SDE_AUDIO_POWER_D_CPT (1 << 31)
> +#define SDE_AUDIO_POWER_C_CPT (1 << 30)
> +#define SDE_AUDIO_POWER_B_CPT (1 << 29)
> +#define SDE_AUDIO_POWER_SHIFT_CPT 29
> +#define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
> +#define SDE_AUXD_CPT (1 << 27)
> +#define SDE_AUXC_CPT (1 << 26)
> +#define SDE_AUXB_CPT (1 << 25)
> +#define SDE_AUX_MASK_CPT (7 << 25)
> +#define SDE_PORTE_HOTPLUG_SPT (1 << 25)
> +#define SDE_PORTA_HOTPLUG_SPT (1 << 24)
> +#define SDE_PORTD_HOTPLUG_CPT (1 << 23)
> +#define SDE_PORTC_HOTPLUG_CPT (1 << 22)
> +#define SDE_PORTB_HOTPLUG_CPT (1 << 21)
> +#define SDE_CRT_HOTPLUG_CPT (1 << 19)
> +#define SDE_SDVOB_HOTPLUG_CPT (1 << 18)
> +#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT |
> \
> + SDE_SDVOB_HOTPLUG_CPT | \
> + SDE_PORTD_HOTPLUG_CPT | \
> + SDE_PORTC_HOTPLUG_CPT | \
> + SDE_PORTB_HOTPLUG_CPT)
> +#define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \
> + SDE_PORTD_HOTPLUG_CPT | \
> + SDE_PORTC_HOTPLUG_CPT | \
> + SDE_PORTB_HOTPLUG_CPT | \
> + SDE_PORTA_HOTPLUG_SPT)
> +#define SDE_GMBUS_CPT (1 << 17)
> +#define SDE_ERROR_CPT (1 << 16)
> +#define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
> +#define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
> +#define SDE_FDI_RXC_CPT (1 << 8)
> +#define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
> +#define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
> +#define SDE_FDI_RXB_CPT (1 << 4)
> +#define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
> +#define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
> +#define SDE_FDI_RXA_CPT (1 << 0)
> +#define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
> + SDE_AUDIO_CP_REQ_B_CPT | \
> + SDE_AUDIO_CP_REQ_A_CPT)
> +#define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
> + SDE_AUDIO_CP_CHG_B_CPT | \
> + SDE_AUDIO_CP_CHG_A_CPT)
> +#define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
> + SDE_FDI_RXB_CPT | \
> + SDE_FDI_RXA_CPT)
> +
> +/* south display engine interrupt: ICP/TGP/MTP */
> +#define SDE_PICAINTERRUPT REG_BIT(31)
> +#define SDE_GMBUS_ICP (1 << 23)
> +#define SDE_TC_HOTPLUG_ICP(hpd_pin) REG_BIT(24 +
> _HPD_PIN_TC(hpd_pin))
> +#define SDE_TC_HOTPLUG_DG2(hpd_pin) REG_BIT(25 +
> _HPD_PIN_TC(hpd_pin)) /* sigh */
> +#define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 +
> _HPD_PIN_DDI(hpd_pin))
> +#define SDE_DDI_HOTPLUG_MASK_ICP
> (SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \
> +
> SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
> +
> SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
> +
> SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
> +#define SDE_TC_HOTPLUG_MASK_ICP
> (SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \
> +
> SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \
> +
> SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \
> +
> SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \
> +
> SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \
> +
> SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))
> +
> +/* digital port hotplug */
> +#define PCH_PORT_HOTPLUG _MMIO(0xc4030) /*
> SHOTPLUG_CTL */
> +#define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */
> +#define BXT_DDIA_HPD_INVERT (1 << 27)
> +#define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */
> +#define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */
> +#define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */
> +#define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */
> +#define PORTD_HOTPLUG_ENABLE (1 << 20)
> +#define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */
> +#define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */
> +#define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */
> +#define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */
> +#define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */
> +#define PORTD_HOTPLUG_STATUS_MASK (3 << 16)
> +#define PORTD_HOTPLUG_NO_DETECT (0 << 16)
> +#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
> +#define PORTD_HOTPLUG_LONG_DETECT (2 << 16)
> +#define PORTC_HOTPLUG_ENABLE (1 << 12)
> +#define BXT_DDIC_HPD_INVERT (1 << 11)
> +#define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */
> +#define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */
> +#define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */
> +#define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */
> +#define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */
> +#define PORTC_HOTPLUG_STATUS_MASK (3 << 8)
> +#define PORTC_HOTPLUG_NO_DETECT (0 << 8)
> +#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
> +#define PORTC_HOTPLUG_LONG_DETECT (2 << 8)
> +#define PORTB_HOTPLUG_ENABLE (1 << 4)
> +#define BXT_DDIB_HPD_INVERT (1 << 3)
> +#define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */
> +#define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */
> +#define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */
> +#define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */
> +#define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */
> +#define PORTB_HOTPLUG_STATUS_MASK (3 << 0)
> +#define PORTB_HOTPLUG_NO_DETECT (0 << 0)
> +#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
> +#define PORTB_HOTPLUG_LONG_DETECT (2 << 0)
> +#define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \
> + BXT_DDIB_HPD_INVERT | \
> + BXT_DDIC_HPD_INVERT)
> +
> +#define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /*
> SHOTPLUG_CTL2 SPT+ */
> +#define PORTE_HOTPLUG_ENABLE (1 << 4)
> +#define PORTE_HOTPLUG_STATUS_MASK (3 << 0)
> +#define PORTE_HOTPLUG_NO_DETECT (0 << 0)
> +#define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)
> +#define PORTE_HOTPLUG_LONG_DETECT (2 << 0)
> +
> +/* This register is a reuse of PCH_PORT_HOTPLUG register. The
> + * functionality covered in PCH_PORT_HOTPLUG is split into
> + * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
> + */
> +#define SHOTPLUG_CTL_DDI _MMIO(0xc4030)
> +#define SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin) (0x8
> << (_HPD_PIN_DDI(hpd_pin) * 4))
> +#define SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(hpd_pin) (0x4
> << (_HPD_PIN_DDI(hpd_pin) * 4))
> +#define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin) (0x3
> << (_HPD_PIN_DDI(hpd_pin) * 4))
> +#define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin) (0x0
> << (_HPD_PIN_DDI(hpd_pin) * 4))
> +#define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin) (0x1
> << (_HPD_PIN_DDI(hpd_pin) * 4))
> +#define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(hpd_pin) (0x2
> << (_HPD_PIN_DDI(hpd_pin) * 4))
> +#define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin) (0x3
> << (_HPD_PIN_DDI(hpd_pin) * 4))
> +
> +#define SHOTPLUG_CTL_TC _MMIO(0xc4034)
> +#define ICP_TC_HPD_ENABLE(hpd_pin) (8 <<
> (_HPD_PIN_TC(hpd_pin) * 4))
> +#define ICP_TC_HPD_LONG_DETECT(hpd_pin) (2 <<
> (_HPD_PIN_TC(hpd_pin) * 4))
> +#define ICP_TC_HPD_SHORT_DETECT(hpd_pin) (1 <<
> (_HPD_PIN_TC(hpd_pin) * 4))
> +
> +#define SHPD_FILTER_CNT _MMIO(0xc4038)
> +#define SHPD_FILTER_CNT_500_ADJ 0x001D9
> +#define SHPD_FILTER_CNT_250 0x000F8
> +
> +#define _PCH_DPLL_A 0xc6014
> +#define _PCH_DPLL_B 0xc6018
> +#define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
> +
> +#define _PCH_FPA0 0xc6040
> +#define _PCH_FPB0 0xc6048
> +#define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0)
> +#define FP_CB_TUNE (0x3 << 22)
> +
> +#define _PCH_FPA1 0xc6044
> +#define _PCH_FPB1 0xc604c
> +#define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1)
> +
> +#define PCH_DPLL_TEST _MMIO(0xc606c)
> +
> +#define PCH_DREF_CONTROL _MMIO(0xC6200)
> +#define DREF_CONTROL_MASK 0x7fc3
> +#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13)
> +#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13)
> +#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13)
> +#define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13)
> +#define DREF_SSC_SOURCE_DISABLE (0 << 11)
> +#define DREF_SSC_SOURCE_ENABLE (2 << 11)
> +#define DREF_SSC_SOURCE_MASK (3 << 11)
> +#define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9)
> +#define DREF_NONSPREAD_CK505_ENABLE (1 << 9)
> +#define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9)
> +#define DREF_NONSPREAD_SOURCE_MASK (3 << 9)
> +#define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7)
> +#define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7)
> +#define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7)
> +#define DREF_SSC4_DOWNSPREAD (0 << 6)
> +#define DREF_SSC4_CENTERSPREAD (1 << 6)
> +#define DREF_SSC1_DISABLE (0 << 1)
> +#define DREF_SSC1_ENABLE (1 << 1)
> +#define DREF_SSC4_DISABLE (0)
> +#define DREF_SSC4_ENABLE (1)
> +
> +#define PCH_RAWCLK_FREQ _MMIO(0xc6204)
> +#define FDL_TP1_TIMER_SHIFT 12
> +#define FDL_TP1_TIMER_MASK (3 << 12)
> +#define FDL_TP2_TIMER_SHIFT 10
> +#define FDL_TP2_TIMER_MASK (3 << 10)
> +#define RAWCLK_FREQ_MASK 0x3ff
> +#define CNP_RAWCLK_DIV_MASK (0x3ff << 16)
> +#define CNP_RAWCLK_DIV(div) ((div) << 16)
> +#define CNP_RAWCLK_FRAC_MASK (0xf << 26)
> +#define CNP_RAWCLK_DEN(den) ((den) << 26)
> +#define ICP_RAWCLK_NUM(num) ((num) << 11)
> +
> +#define PCH_DPLL_TMR_CFG _MMIO(0xc6208)
> +
> +#define PCH_SSC4_PARMS _MMIO(0xc6210)
> +#define PCH_SSC4_AUX_PARMS _MMIO(0xc6214)
> +
> +#define PCH_DPLL_SEL _MMIO(0xc7000)
> +#define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4))
> +#define TRANS_DPLLA_SEL(pipe) 0
> +#define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3))
> +
> +/* transcoder */
> +#define _PCH_TRANS_HTOTAL_A 0xe0000
> +#define _PCH_TRANS_HTOTAL_B 0xe1000
> +#define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe,
> _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
> +#define TRANS_HTOTAL_SHIFT 16
> +#define TRANS_HACTIVE_SHIFT 0
> +
> +#define _PCH_TRANS_HBLANK_A 0xe0004
> +#define _PCH_TRANS_HBLANK_B 0xe1004
> +#define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe,
> _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
> +#define TRANS_HBLANK_END_SHIFT 16
> +#define TRANS_HBLANK_START_SHIFT 0
> +
> +#define _PCH_TRANS_HSYNC_A 0xe0008
> +#define _PCH_TRANS_HSYNC_B 0xe1008
> +#define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe,
> _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
> +#define TRANS_HSYNC_END_SHIFT 16
> +#define TRANS_HSYNC_START_SHIFT 0
> +
> +#define _PCH_TRANS_VTOTAL_A 0xe000c
> +#define _PCH_TRANS_VTOTAL_B 0xe100c
> +#define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe,
> _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
> +#define TRANS_VTOTAL_SHIFT 16
> +#define TRANS_VACTIVE_SHIFT 0
> +
> +#define _PCH_TRANS_VBLANK_A 0xe0010
> +#define _PCH_TRANS_VBLANK_B 0xe1010
> +#define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe,
> _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
> +#define TRANS_VBLANK_END_SHIFT 16
> +#define TRANS_VBLANK_START_SHIFT 0
> +
> +#define _PCH_TRANS_VSYNC_A 0xe0014
> +#define _PCH_TRANS_VSYNC_B 0xe1014
> +#define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe,
> _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
> +#define TRANS_VSYNC_END_SHIFT 16
> +#define TRANS_VSYNC_START_SHIFT 0
> +
> +#define _PCH_TRANS_VSYNCSHIFT_A 0xe0028
> +#define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
> +#define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe,
> _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)
> +
> +#define _PCH_TRANSA_DATA_M1 0xe0030
> +#define _PCH_TRANSB_DATA_M1 0xe1030
> +#define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe,
> _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
> +
> +#define _PCH_TRANSA_DATA_N1 0xe0034
> +#define _PCH_TRANSB_DATA_N1 0xe1034
> +#define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe,
> _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
> +
> +#define _PCH_TRANSA_DATA_M2 0xe0038
> +#define _PCH_TRANSB_DATA_M2 0xe1038
> +#define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe,
> _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
> +
> +#define _PCH_TRANSA_DATA_N2 0xe003c
> +#define _PCH_TRANSB_DATA_N2 0xe103c
> +#define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe,
> _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
> +
> +#define _PCH_TRANSA_LINK_M1 0xe0040
> +#define _PCH_TRANSB_LINK_M1 0xe1040
> +#define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe,
> _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
> +
> +#define _PCH_TRANSA_LINK_N1 0xe0044
> +#define _PCH_TRANSB_LINK_N1 0xe1044
> +#define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe,
> _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
> +
> +#define _PCH_TRANSA_LINK_M2 0xe0048
> +#define _PCH_TRANSB_LINK_M2 0xe1048
> +#define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe,
> _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
> +
> +#define _PCH_TRANSA_LINK_N2 0xe004c
> +#define _PCH_TRANSB_LINK_N2 0xe104c
> +#define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe,
> _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
> +
> +/* Per-transcoder DIP controls (PCH) */
> +#define _VIDEO_DIP_CTL_A 0xe0200
> +#define _VIDEO_DIP_CTL_B 0xe1200
> +#define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A,
> _VIDEO_DIP_CTL_B)
> +
> +#define _VIDEO_DIP_DATA_A 0xe0208
> +#define _VIDEO_DIP_DATA_B 0xe1208
> +#define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A,
> _VIDEO_DIP_DATA_B)
> +
> +#define _VIDEO_DIP_GCP_A 0xe0210
> +#define _VIDEO_DIP_GCP_B 0xe1210
> +#define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A,
> _VIDEO_DIP_GCP_B)
> +#define GCP_COLOR_INDICATION (1 << 2)
> +#define GCP_DEFAULT_PHASE_ENABLE (1 << 1)
> +#define GCP_AV_MUTE (1 << 0)
> +
> +/* Per-transcoder DIP controls (VLV) */
> +#define _VLV_VIDEO_DIP_CTL_A 0x60200
> +#define _VLV_VIDEO_DIP_CTL_B 0x61170
> +#define _CHV_VIDEO_DIP_CTL_C 0x611f0
> +#define VLV_TVIDEO_DIP_CTL(pipe)
> _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \
> +
> _VLV_VIDEO_DIP_CTL_A, \
> +
> _VLV_VIDEO_DIP_CTL_B, \
> +
> _CHV_VIDEO_DIP_CTL_C)
> +
> +#define _VLV_VIDEO_DIP_DATA_A 0x60208
> +#define _VLV_VIDEO_DIP_DATA_B 0x61174
> +#define _CHV_VIDEO_DIP_DATA_C 0x611f4
> +#define VLV_TVIDEO_DIP_DATA(pipe)
> _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \
> +
> _VLV_VIDEO_DIP_DATA_A, \
> +
> _VLV_VIDEO_DIP_DATA_B, \
> +
> _CHV_VIDEO_DIP_DATA_C)
> +
> +#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A 0x60210
> +#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B 0x61178
> +#define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C 0x611f8
> +#define VLV_TVIDEO_DIP_GCP(pipe)
> _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \
> +
> _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
> +
> _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, \
> +
> _CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
> +
> +/* Haswell DIP controls */
> +#define _HSW_VIDEO_DIP_CTL_A 0x60200
> +#define _HSW_VIDEO_DIP_CTL_B 0x61200
> +#define HSW_TVIDEO_DIP_CTL(dev_priv, trans)
> _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_CTL_A)
> +
> +#define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220
> +#define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220
> +#define HSW_TVIDEO_DIP_AVI_DATA(dev_priv, trans, i)
> _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i)
> * 4)
> +
> +#define _HSW_VIDEO_DIP_VS_DATA_A 0x60260
> +#define _HSW_VIDEO_DIP_VS_DATA_B 0x61260
> +#define HSW_TVIDEO_DIP_VS_DATA(dev_priv, trans, i)
> _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) *
> 4)
> +
> +#define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
> +#define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
> +#define HSW_TVIDEO_DIP_SPD_DATA(dev_priv, trans, i)
> _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i)
> * 4)
> +
> +#define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
> +#define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
> +#define HSW_TVIDEO_DIP_GMP_DATA(dev_priv, trans, i)
> _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i)
> * 4)
> +
> +#define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320
> +#define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320
> +#define HSW_TVIDEO_DIP_VSC_DATA(dev_priv, trans, i)
> _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i)
> * 4)
> +
> +/*ADLP and later: */
> +#define _ADL_VIDEO_DIP_AS_DATA_A 0x60484
> +#define _ADL_VIDEO_DIP_AS_DATA_B 0x61484
> +#define ADL_TVIDEO_DIP_AS_SDP_DATA(dev_priv, trans, i)
> _MMIO_TRANS2(dev_priv, trans,\
> +
> _ADL_VIDEO_DIP_AS_DATA_A + (i) * 4)
> +
> +#define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440
> +#define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440
> +#define GLK_TVIDEO_DIP_DRM_DATA(dev_priv, trans, i)
> _MMIO_TRANS2(dev_priv, trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i)
> * 4)
> +
> +#define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240
> +#define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240
> +#define _HSW_VIDEO_DIP_VS_ECC_A 0x60280
> +#define _HSW_VIDEO_DIP_VS_ECC_B 0x61280
> +#define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
> +#define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
> +#define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300
> +#define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300
> +#define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344
> +#define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344
> +
> +#define _HSW_VIDEO_DIP_GCP_A 0x60210
> +#define _HSW_VIDEO_DIP_GCP_B 0x61210
> +#define HSW_TVIDEO_DIP_GCP(dev_priv, trans)
> _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GCP_A)
> +
> +#define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350
> +#define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350
> +#define ICL_VIDEO_DIP_PPS_DATA(dev_priv, trans, i)
> _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) *
> 4)
> +
> +#define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4
> +#define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4
> +#define ICL_VIDEO_DIP_PPS_ECC(dev_priv, trans, i)
> _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
> +
> +#define _HSW_STEREO_3D_CTL_A 0x70020
> +#define _HSW_STEREO_3D_CTL_B 0x71020
> +#define HSW_STEREO_3D_CTL(dev_priv, trans) _MMIO_PIPE2(dev_priv, trans,
> _HSW_STEREO_3D_CTL_A)
> +#define S3D_ENABLE (1 << 31)
> +
> +#define _PCH_TRANSACONF 0xf0008
> +#define _PCH_TRANSBCONF 0xf1008
> +#define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe,
> _PCH_TRANSACONF, _PCH_TRANSBCONF)
> +#define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has
> only one transcoder */
> +#define TRANS_ENABLE REG_BIT(31)
> +#define TRANS_STATE_ENABLE REG_BIT(30)
> +#define TRANS_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* ibx
> */
> +#define TRANS_FRAME_START_DELAY(x)
> REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3
> */
> +#define TRANS_INTERLACE_MASK REG_GENMASK(23, 21)
> +#define TRANS_INTERLACE_PROGRESSIVE
> REG_FIELD_PREP(TRANS_INTERLACE_MASK, 0)
> +#define TRANS_INTERLACE_LEGACY_VSYNC_IBX
> REG_FIELD_PREP(TRANS_INTERLACE_MASK, 2) /* ibx */
> +#define TRANS_INTERLACE_INTERLACED
> REG_FIELD_PREP(TRANS_INTERLACE_MASK, 3)
> +#define TRANS_BPC_MASK REG_GENMASK(7, 5) /* ibx */
> +#define TRANS_BPC_8
> REG_FIELD_PREP(TRANS_BPC_MASK, 0)
> +#define TRANS_BPC_10
> REG_FIELD_PREP(TRANS_BPC_MASK, 1)
> +#define TRANS_BPC_6
> REG_FIELD_PREP(TRANS_BPC_MASK, 2)
> +#define TRANS_BPC_12
> REG_FIELD_PREP(TRANS_BPC_MASK, 3)
> +
> +#define PCH_DP_B _MMIO(0xe4100)
> +#define PCH_DP_C _MMIO(0xe4200)
> +#define PCH_DP_D _MMIO(0xe4300)
> +
> +/* CPT */
> +#define _TRANS_DP_CTL_A 0xe0300
> +#define _TRANS_DP_CTL_B 0xe1300
> +#define _TRANS_DP_CTL_C 0xe2300
> +#define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A,
> _TRANS_DP_CTL_B)
> +#define TRANS_DP_OUTPUT_ENABLE REG_BIT(31)
> +#define TRANS_DP_PORT_SEL_MASK REG_GENMASK(30, 29)
> +#define TRANS_DP_PORT_SEL_NONE
> REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, 3)
> +#define TRANS_DP_PORT_SEL(port)
> REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, (port) - PORT_B)
> +#define TRANS_DP_AUDIO_ONLY REG_BIT(26)
> +#define TRANS_DP_ENH_FRAMING REG_BIT(18)
> +#define TRANS_DP_BPC_MASK REG_GENMASK(10, 9)
> +#define TRANS_DP_BPC_8
> REG_FIELD_PREP(TRANS_DP_BPC_MASK, 0)
> +#define TRANS_DP_BPC_10
> REG_FIELD_PREP(TRANS_DP_BPC_MASK, 1)
> +#define TRANS_DP_BPC_6
> REG_FIELD_PREP(TRANS_DP_BPC_MASK, 2)
> +#define TRANS_DP_BPC_12
> REG_FIELD_PREP(TRANS_DP_BPC_MASK, 3)
> +#define TRANS_DP_VSYNC_ACTIVE_HIGH REG_BIT(4)
> +#define TRANS_DP_HSYNC_ACTIVE_HIGH REG_BIT(3)
> +
> +#define _TRANS_DP2_CTL_A 0x600a0
> +#define _TRANS_DP2_CTL_B 0x610a0
> +#define _TRANS_DP2_CTL_C 0x620a0
> +#define _TRANS_DP2_CTL_D 0x630a0
> +#define TRANS_DP2_CTL(trans) _MMIO_TRANS(trans,
> _TRANS_DP2_CTL_A, _TRANS_DP2_CTL_B)
> +#define TRANS_DP2_128B132B_CHANNEL_CODING REG_BIT(31)
> +#define TRANS_DP2_PANEL_REPLAY_ENABLE REG_BIT(30)
> +#define TRANS_DP2_DEBUG_ENABLE REG_BIT(23)
> +
> +#define _TRANS_DP2_VFREQHIGH_A 0x600a4
> +#define _TRANS_DP2_VFREQHIGH_B 0x610a4
> +#define _TRANS_DP2_VFREQHIGH_C 0x620a4
> +#define _TRANS_DP2_VFREQHIGH_D 0x630a4
> +#define TRANS_DP2_VFREQHIGH(trans) _MMIO_TRANS(trans,
> _TRANS_DP2_VFREQHIGH_A, _TRANS_DP2_VFREQHIGH_B)
> +#define TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK REG_GENMASK(31, 8)
> +#define TRANS_DP2_VFREQ_PIXEL_CLOCK(clk_hz)
> REG_FIELD_PREP(TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK, (clk_hz))
> +
> +#define _TRANS_DP2_VFREQLOW_A 0x600a8
> +#define _TRANS_DP2_VFREQLOW_B 0x610a8
> +#define _TRANS_DP2_VFREQLOW_C 0x620a8
> +#define _TRANS_DP2_VFREQLOW_D 0x630a8
> +#define TRANS_DP2_VFREQLOW(trans) _MMIO_TRANS(trans,
> _TRANS_DP2_VFREQLOW_A, _TRANS_DP2_VFREQLOW_B)
> +
> +#define _DP_MIN_HBLANK_CTL_A 0x600ac
> +#define _DP_MIN_HBLANK_CTL_B 0x610ac
> +#define DP_MIN_HBLANK_CTL(trans) _MMIO_TRANS(trans,
> _DP_MIN_HBLANK_CTL_A, _DP_MIN_HBLANK_CTL_B)
> +
> +/* SNB eDP training params */
> +/* SNB A-stepping */
> +#define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22)
> +#define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22)
> +#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22)
> +#define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22)
> +/* SNB B-stepping */
> +#define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0 << 22)
> +#define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1 << 22)
> +#define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a << 22)
> +#define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39 << 22)
> +#define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38 << 22)
> +#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f << 22)
> +
> +/* IVB */
> +#define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 << 22)
> +#define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a << 22)
> +#define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f << 22)
> +#define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 << 22)
> +#define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 << 22)
> +#define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 << 22)
> +#define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e << 22)
> +
> +/* legacy values */
> +#define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 << 22)
> +#define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 << 22)
> +#define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 << 22)
> +#define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 << 22)
> +#define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 << 22)
> +
> +#define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f << 22)
> +
> +#define VLV_CHICKEN_3
> _MMIO(VLV_DISPLAY_BASE + 0x7040C)
> +#define PIXEL_OVERLAP_CNT_MASK (3 << 30)
> +#define PIXEL_OVERLAP_CNT_SHIFT 30
> +
> +/*
> + * HSW - ICL power wells
> + *
> + * Platforms have up to 3 power well control register sets, each set
> + * controlling up to 16 power wells via a request/status HW flag tuple:
> + * - main (HSW_PWR_WELL_CTL[1-4])
> + * - AUX (ICL_PWR_WELL_CTL_AUX[1-4])
> + * - DDI (ICL_PWR_WELL_CTL_DDI[1-4])
> + * Each control register set consists of up to 4 registers used by different
> + * sources that can request a power well to be enabled:
> + * - BIOS
> (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI
> 1)
> + * - DRIVER
> (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI
> 2)
> + * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set)
> + * - DEBUG
> (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI
> 4)
> + */
> +#define HSW_PWR_WELL_CTL1 _MMIO(0x45400)
> +#define HSW_PWR_WELL_CTL2 _MMIO(0x45404)
> +#define HSW_PWR_WELL_CTL3 _MMIO(0x45408)
> +#define HSW_PWR_WELL_CTL4 _MMIO(0x4540C)
> +#define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2))
> +#define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2))
> +
> +/* HSW/BDW power well */
> +#define HSW_PW_CTL_IDX_GLOBAL 15
> +
> +/* SKL/BXT/GLK power wells */
> +#define SKL_PW_CTL_IDX_PW_2 15
> +#define SKL_PW_CTL_IDX_PW_1 14
> +#define GLK_PW_CTL_IDX_AUX_C 10
> +#define GLK_PW_CTL_IDX_AUX_B 9
> +#define GLK_PW_CTL_IDX_AUX_A 8
> +#define SKL_PW_CTL_IDX_DDI_D 4
> +#define SKL_PW_CTL_IDX_DDI_C 3
> +#define SKL_PW_CTL_IDX_DDI_B 2
> +#define SKL_PW_CTL_IDX_DDI_A_E 1
> +#define GLK_PW_CTL_IDX_DDI_A 1
> +#define SKL_PW_CTL_IDX_MISC_IO 0
> +
> +/* ICL/TGL - power wells */
> +#define TGL_PW_CTL_IDX_PW_5 4
> +#define ICL_PW_CTL_IDX_PW_4 3
> +#define ICL_PW_CTL_IDX_PW_3 2
> +#define ICL_PW_CTL_IDX_PW_2 1
> +#define ICL_PW_CTL_IDX_PW_1 0
> +
> +/* XE_LPD - power wells */
> +#define XELPD_PW_CTL_IDX_PW_D 8
> +#define XELPD_PW_CTL_IDX_PW_C 7
> +#define XELPD_PW_CTL_IDX_PW_B 6
> +#define XELPD_PW_CTL_IDX_PW_A 5
> +
> +#define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440)
> +#define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444)
> +#define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C)
> +#define TGL_PW_CTL_IDX_AUX_TBT6 14
> +#define TGL_PW_CTL_IDX_AUX_TBT5 13
> +#define TGL_PW_CTL_IDX_AUX_TBT4 12
> +#define ICL_PW_CTL_IDX_AUX_TBT4 11
> +#define TGL_PW_CTL_IDX_AUX_TBT3 11
> +#define ICL_PW_CTL_IDX_AUX_TBT3 10
> +#define TGL_PW_CTL_IDX_AUX_TBT2 10
> +#define ICL_PW_CTL_IDX_AUX_TBT2 9
> +#define TGL_PW_CTL_IDX_AUX_TBT1 9
> +#define ICL_PW_CTL_IDX_AUX_TBT1 8
> +#define TGL_PW_CTL_IDX_AUX_TC6 8
> +#define XELPD_PW_CTL_IDX_AUX_E 8
> +#define TGL_PW_CTL_IDX_AUX_TC5 7
> +#define XELPD_PW_CTL_IDX_AUX_D 7
> +#define TGL_PW_CTL_IDX_AUX_TC4 6
> +#define ICL_PW_CTL_IDX_AUX_F 5
> +#define TGL_PW_CTL_IDX_AUX_TC3 5
> +#define ICL_PW_CTL_IDX_AUX_E 4
> +#define TGL_PW_CTL_IDX_AUX_TC2 4
> +#define ICL_PW_CTL_IDX_AUX_D 3
> +#define TGL_PW_CTL_IDX_AUX_TC1 3
> +#define ICL_PW_CTL_IDX_AUX_C 2
> +#define ICL_PW_CTL_IDX_AUX_B 1
> +#define ICL_PW_CTL_IDX_AUX_A 0
> +
> +#define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450)
> +#define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454)
> +#define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C)
> +#define XELPD_PW_CTL_IDX_DDI_E 8
> +#define TGL_PW_CTL_IDX_DDI_TC6 8
> +#define XELPD_PW_CTL_IDX_DDI_D 7
> +#define TGL_PW_CTL_IDX_DDI_TC5 7
> +#define TGL_PW_CTL_IDX_DDI_TC4 6
> +#define ICL_PW_CTL_IDX_DDI_F 5
> +#define TGL_PW_CTL_IDX_DDI_TC3 5
> +#define ICL_PW_CTL_IDX_DDI_E 4
> +#define TGL_PW_CTL_IDX_DDI_TC2 4
> +#define ICL_PW_CTL_IDX_DDI_D 3
> +#define TGL_PW_CTL_IDX_DDI_TC1 3
> +#define ICL_PW_CTL_IDX_DDI_C 2
> +#define ICL_PW_CTL_IDX_DDI_B 1
> +#define ICL_PW_CTL_IDX_DDI_A 0
> +
> +/* HSW - power well misc debug registers */
> +#define HSW_PWR_WELL_CTL5 _MMIO(0x45410)
> +#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31)
> +#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20)
> +#define HSW_PWR_WELL_FORCE_ON (1 << 19)
> +#define HSW_PWR_WELL_CTL6 _MMIO(0x45414)
> +
> +#define SKL_FUSE_STATUS _MMIO(0x42000)
> +#define SKL_FUSE_DOWNLOAD_STATUS (1 << 31)
> +/*
> + * PG0 is HW controlled, so doesn't have a corresponding power well control
> knob
> + * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2
> + */
> +#define SKL_PW_CTL_IDX_TO_PG(pw_idx) \
> + ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1)
> +/*
> + * PG0 is HW controlled, so doesn't have a corresponding power well control
> knob
> + * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4
> + */
> +#define ICL_PW_CTL_IDX_TO_PG(pw_idx) \
> + ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1)
> +#define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
> +
> +/* Per-pipe DDI Function Control */
> +#define _TRANS_DDI_FUNC_CTL_A 0x60400
> +#define _TRANS_DDI_FUNC_CTL_B 0x61400
> +#define _TRANS_DDI_FUNC_CTL_C 0x62400
> +#define _TRANS_DDI_FUNC_CTL_D 0x63400
> +#define _TRANS_DDI_FUNC_CTL_EDP 0x6F400
> +#define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400
> +#define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00
> +#define TRANS_DDI_FUNC_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv,
> tran, _TRANS_DDI_FUNC_CTL_A)
> +
> +#define TRANS_DDI_FUNC_ENABLE (1 << 31)
> +/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
> +#define TRANS_DDI_PORT_SHIFT 28
> +#define TGL_TRANS_DDI_PORT_SHIFT 27
> +#define TRANS_DDI_PORT_MASK (7 <<
> TRANS_DDI_PORT_SHIFT)
> +#define TGL_TRANS_DDI_PORT_MASK (0xf << TGL_TRANS_DDI_PORT_SHIFT)
> +#define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT)
> +#define TGL_TRANS_DDI_SELECT_PORT(x) (((x) + 1) <<
> TGL_TRANS_DDI_PORT_SHIFT)
> +#define TRANS_DDI_MODE_SELECT_MASK (7 << 24)
> +#define TRANS_DDI_MODE_SELECT_HDMI (0 << 24)
> +#define TRANS_DDI_MODE_SELECT_DVI (1 << 24)
> +#define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24)
> +#define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24)
> +#define TRANS_DDI_MODE_SELECT_FDI_OR_128B132B (4 << 24)
> +#define TRANS_DDI_BPC_MASK (7 << 20)
> +#define TRANS_DDI_BPC_8 (0 << 20)
> +#define TRANS_DDI_BPC_10 (1 << 20)
> +#define TRANS_DDI_BPC_6 (2 << 20)
> +#define TRANS_DDI_BPC_12 (3 << 20)
> +#define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK
> REG_GENMASK(19, 18)
> +#define TRANS_DDI_PORT_SYNC_MASTER_SELECT(x)
> REG_FIELD_PREP(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK,
> (x))
> +#define TRANS_DDI_PVSYNC (1 << 17)
> +#define TRANS_DDI_PHSYNC (1 << 16)
> +#define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15)
> +#define XE3_TRANS_DDI_HDCP_LINE_REKEY_DISABLE REG_BIT(15)
> +#define TRANS_DDI_EDP_INPUT_MASK (7 << 12)
> +#define TRANS_DDI_EDP_INPUT_A_ON (0 << 12)
> +#define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12)
> +#define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12)
> +#define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12)
> +#define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12)
> +#define TRANS_DDI_HDCP_LINE_REKEY_DISABLE REG_BIT(12)
> +#define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11,
> 10)
> +#define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \
> + REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans)
> +#define TRANS_DDI_HDCP_SIGNALLING (1 << 9)
> +#define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8)
> +#define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7)
> +#define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6)
> +#define TRANS_DDI_HDCP_SELECT REG_BIT(5)
> +#define TRANS_DDI_BFI_ENABLE (1 << 4)
> +#define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4)
> +#define TRANS_DDI_PORT_WIDTH_MASK REG_GENMASK(3, 1)
> +#define TRANS_DDI_PORT_WIDTH(width)
> REG_FIELD_PREP(TRANS_DDI_PORT_WIDTH_MASK, (width) - 1)
> +#define TRANS_DDI_HDMI_SCRAMBLING (1 << 0)
> +#define TRANS_DDI_HDMI_SCRAMBLING_MASK
> (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \
> + |
> TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \
> + | TRANS_DDI_HDMI_SCRAMBLING)
> +
> +#define _TRANS_DDI_FUNC_CTL2_A 0x60404
> +#define _TRANS_DDI_FUNC_CTL2_B 0x61404
> +#define _TRANS_DDI_FUNC_CTL2_C 0x62404
> +#define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404
> +#define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404
> +#define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04
> +#define TRANS_DDI_FUNC_CTL2(dev_priv, tran)
> _MMIO_TRANS2(dev_priv, tran, _TRANS_DDI_FUNC_CTL2_A)
> +#define PORT_SYNC_MODE_ENABLE REG_BIT(4)
> +#define CMTG_SECONDARY_MODE REG_BIT(3)
> +#define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0)
> +#define PORT_SYNC_MODE_MASTER_SELECT(x)
> REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x))
> +
> +#define TRANS_CMTG_CHICKEN _MMIO(0x6fa90)
> +#define DISABLE_DPT_CLK_GATING REG_BIT(1)
> +
> +/* DisplayPort Transport Control */
> +#define _DP_TP_CTL_A 0x64040
> +#define _DP_TP_CTL_B 0x64140
> +#define _TGL_DP_TP_CTL_A 0x60540
> +#define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A,
> _DP_TP_CTL_B)
> +#define TGL_DP_TP_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, (tran),
> _TGL_DP_TP_CTL_A)
> +#define DP_TP_CTL_ENABLE REG_BIT(31)
> +#define DP_TP_CTL_FEC_ENABLE REG_BIT(30)
> +#define DP_TP_CTL_MODE_MASK REG_BIT(27)
> +#define DP_TP_CTL_MODE_SST
> REG_FIELD_PREP(DP_TP_CTL_MODE_MASK, 0)
> +#define DP_TP_CTL_MODE_MST
> REG_FIELD_PREP(DP_TP_CTL_MODE_MASK, 1)
> +#define DP_TP_CTL_FORCE_ACT REG_BIT(25)
> +#define DP_TP_CTL_TRAIN_PAT4_SEL_MASK REG_GENMASK(20,
> 19)
> +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4A
> REG_FIELD_PREP(DP_TP_CTL_TRAIN_PAT4_SEL_MASK, 0)
> +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4B
> REG_FIELD_PREP(DP_TP_CTL_TRAIN_PAT4_SEL_MASK, 1)
> +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4C
> REG_FIELD_PREP(DP_TP_CTL_TRAIN_PAT4_SEL_MASK, 2)
> +#define DP_TP_CTL_ENHANCED_FRAME_ENABLE REG_BIT(18)
> +#define DP_TP_CTL_FDI_AUTOTRAIN REG_BIT(15)
> +#define DP_TP_CTL_LINK_TRAIN_MASK REG_GENMASK(10, 8)
> +#define DP_TP_CTL_LINK_TRAIN_PAT1
> REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 0)
> +#define DP_TP_CTL_LINK_TRAIN_PAT2
> REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 1)
> +#define DP_TP_CTL_LINK_TRAIN_PAT3
> REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 4)
> +#define DP_TP_CTL_LINK_TRAIN_PAT4
> REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 5)
> +#define DP_TP_CTL_LINK_TRAIN_IDLE
> REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 2)
> +#define DP_TP_CTL_LINK_TRAIN_NORMAL
> REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 3)
> +#define DP_TP_CTL_SCRAMBLE_DISABLE REG_BIT(7)
> +
> +/* DisplayPort Transport Status */
> +#define _DP_TP_STATUS_A 0x64044
> +#define _DP_TP_STATUS_B 0x64144
> +#define _TGL_DP_TP_STATUS_A 0x60544
> +#define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A,
> _DP_TP_STATUS_B)
> +#define TGL_DP_TP_STATUS(dev_priv, tran) _MMIO_TRANS2(dev_priv, (tran),
> _TGL_DP_TP_STATUS_A)
> +#define DP_TP_STATUS_FEC_ENABLE_LIVE REG_BIT(28)
> +#define DP_TP_STATUS_IDLE_DONE REG_BIT(25)
> +#define DP_TP_STATUS_ACT_SENT REG_BIT(24)
> +#define DP_TP_STATUS_MODE_STATUS_MST REG_BIT(23)
> +#define DP_TP_STATUS_STREAMS_ENABLED_MASK REG_GENMASK(18,
> 16) /* 17:16 on hsw but bit 18 mbz */
> +#define DP_TP_STATUS_AUTOTRAIN_DONE REG_BIT(12)
> +#define DP_TP_STATUS_PAYLOAD_MAPPING_VC2_MASK REG_GENMASK(9,
> 8)
> +#define DP_TP_STATUS_PAYLOAD_MAPPING_VC1_MASK
> REG_GENMASK(5, 4)
> +#define DP_TP_STATUS_PAYLOAD_MAPPING_VC0_MASK
> REG_GENMASK(1, 0)
> +
> +/* DDI Buffer Control */
> +#define _DDI_BUF_CTL_A 0x64000
> +#define _DDI_BUF_CTL_B 0x64100
> +/* Known as DDI_CTL_DE in MTL+ */
> +#define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A,
> _DDI_BUF_CTL_B)
> +#define DDI_BUF_CTL_ENABLE REG_BIT(31)
> +#define XE2LPD_DDI_BUF_D2D_LINK_ENABLE REG_BIT(29)
> +#define XE2LPD_DDI_BUF_D2D_LINK_STATE REG_BIT(28)
> +#define DDI_BUF_EMP_MASK REG_GENMASK(27, 24)
> +#define DDI_BUF_TRANS_SELECT(n)
> REG_FIELD_PREP(DDI_BUF_EMP_MASK, (n))
> +#define DDI_BUF_PHY_LINK_RATE_MASK REG_GENMASK(23,
> 20)
> +#define DDI_BUF_PHY_LINK_RATE(r)
> REG_FIELD_PREP(DDI_BUF_PHY_LINK_RATE_MASK, (r))
> +#define DDI_BUF_PORT_DATA_MASK REG_GENMASK(19,
> 18)
> +#define DDI_BUF_PORT_DATA_10BIT
> REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 0)
> +#define DDI_BUF_PORT_DATA_20BIT
> REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 1)
> +#define DDI_BUF_PORT_DATA_40BIT
> REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 2)
> +#define DDI_BUF_PORT_REVERSAL REG_BIT(16)
> +#define DDI_BUF_LANE_STAGGER_DELAY_MASK REG_GENMASK(15, 8)
> +#define DDI_BUF_LANE_STAGGER_DELAY(symbols)
> REG_FIELD_PREP(DDI_BUF_LANE_STAGGER_DELAY_MASK, \
> + (symbols))
> +#define DDI_BUF_IS_IDLE REG_BIT(7)
> +#define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6)
> +#define DDI_A_4_LANES REG_BIT(4)
> +#define DDI_PORT_WIDTH_MASK REG_GENMASK(3, 1)
> +#define DDI_PORT_WIDTH(width)
> REG_FIELD_PREP(DDI_PORT_WIDTH_MASK, \
> + ((width) == 3 ? 4 :
> (width) - 1))
> +#define DDI_PORT_WIDTH_SHIFT 1
> +#define DDI_INIT_DISPLAY_DETECTED REG_BIT(0)
> +
> +/* DDI Buffer Translations */
> +#define _DDI_BUF_TRANS_A 0x64E00
> +#define _DDI_BUF_TRANS_B 0x64E60
> +#define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port,
> _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)
> +#define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
> +#define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port,
> _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
> +
> +/* DDI DP Compliance Control */
> +#define _DDI_DP_COMP_CTL_A 0x605F0
> +#define _DDI_DP_COMP_CTL_B 0x615F0
> +#define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe,
> _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B)
> +#define DDI_DP_COMP_CTL_ENABLE (1 << 31)
> +#define DDI_DP_COMP_CTL_D10_2 (0 << 28)
> +#define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28)
> +#define DDI_DP_COMP_CTL_PRBS7 (2 << 28)
> +#define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28)
> +#define DDI_DP_COMP_CTL_HBR2 (4 << 28)
> +#define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28)
> +#define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0)
> +
> +/* DDI DP Compliance Pattern */
> +#define _DDI_DP_COMP_PAT_A 0x605F4
> +#define _DDI_DP_COMP_PAT_B 0x615F4
> +#define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe,
> _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4)
> +
> +/* SBI offsets */
> +#define SBI_SSCDIVINTPHASE 0x0200
> +#define SBI_SSCDIVINTPHASE6 0x0600
> +#define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1
> +#define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1)
> +#define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1)
> +#define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8
> +#define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8)
> +#define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8)
> +#define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15)
> +#define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0)
> +#define SBI_SSCDITHPHASE 0x0204
> +#define SBI_SSCCTL 0x020c
> +#define SBI_SSCCTL6 0x060C
> +#define SBI_SSCCTL_PATHALT (1 << 3)
> +#define SBI_SSCCTL_DISABLE (1 << 0)
> +#define SBI_SSCAUXDIV6 0x0610
> +#define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4
> +#define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4)
> +#define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4)
> +#define SBI_DBUFF0 0x2a00
> +#define SBI_GEN0 0x1f00
> +#define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0)
> +
> +/* LPT PIXCLK_GATE */
> +#define PIXCLK_GATE _MMIO(0xC6020)
> +#define PIXCLK_GATE_UNGATE (1 << 0)
> +#define PIXCLK_GATE_GATE (0 << 0)
> +
> +/* SPLL */
> +#define SPLL_CTL _MMIO(0x46020)
> +#define SPLL_PLL_ENABLE (1 << 31)
> +#define SPLL_REF_BCLK (0 << 28)
> +#define SPLL_REF_MUXED_SSC (1 << 28) /* CPU SSC if fused
> enabled, PCH SSC otherwise */
> +#define SPLL_REF_NON_SSC_HSW (2 << 28)
> +#define SPLL_REF_PCH_SSC_BDW (2 << 28)
> +#define SPLL_REF_LCPLL (3 << 28)
> +#define SPLL_REF_MASK (3 << 28)
> +#define SPLL_FREQ_810MHz (0 << 26)
> +#define SPLL_FREQ_1350MHz (1 << 26)
> +#define SPLL_FREQ_2700MHz (2 << 26)
> +#define SPLL_FREQ_MASK (3 << 26)
> +
> +/* WRPLL */
> +#define _WRPLL_CTL1 0x46040
> +#define _WRPLL_CTL2 0x46060
> +#define WRPLL_CTL(pll) _MMIO_PIPE(pll,
> _WRPLL_CTL1, _WRPLL_CTL2)
> +#define WRPLL_PLL_ENABLE (1 << 31)
> +#define WRPLL_REF_BCLK (0 << 28)
> +#define WRPLL_REF_PCH_SSC (1 << 28)
> +#define WRPLL_REF_MUXED_SSC_BDW (2 << 28) /* CPU SSC if fused
> enabled, PCH SSC otherwise */
> +#define WRPLL_REF_SPECIAL_HSW (2 << 28) /* muxed SSC (ULT),
> non-SSC (non-ULT) */
> +#define WRPLL_REF_LCPLL (3 << 28)
> +#define WRPLL_REF_MASK (3 << 28)
> +/* WRPLL divider programming */
> +#define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0)
> +#define WRPLL_DIVIDER_REF_MASK (0xff)
> +#define WRPLL_DIVIDER_POST(x) ((x) << 8)
> +#define WRPLL_DIVIDER_POST_MASK (0x3f << 8)
> +#define WRPLL_DIVIDER_POST_SHIFT 8
> +#define WRPLL_DIVIDER_FEEDBACK(x) ((x) << 16)
> +#define WRPLL_DIVIDER_FB_SHIFT 16
> +#define WRPLL_DIVIDER_FB_MASK (0xff << 16)
> +
> +/* Port clock selection */
> +#define _PORT_CLK_SEL_A 0x46100
> +#define _PORT_CLK_SEL_B 0x46104
> +#define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A,
> _PORT_CLK_SEL_B)
> +#define PORT_CLK_SEL_MASK REG_GENMASK(31, 29)
> +#define PORT_CLK_SEL_LCPLL_2700
> REG_FIELD_PREP(PORT_CLK_SEL_MASK, 0)
> +#define PORT_CLK_SEL_LCPLL_1350
> REG_FIELD_PREP(PORT_CLK_SEL_MASK, 1)
> +#define PORT_CLK_SEL_LCPLL_810
> REG_FIELD_PREP(PORT_CLK_SEL_MASK, 2)
> +#define PORT_CLK_SEL_SPLL
> REG_FIELD_PREP(PORT_CLK_SEL_MASK, 3)
> +#define PORT_CLK_SEL_WRPLL(pll)
> REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4 + (pll))
> +#define PORT_CLK_SEL_WRPLL1
> REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4)
> +#define PORT_CLK_SEL_WRPLL2
> REG_FIELD_PREP(PORT_CLK_SEL_MASK, 5)
> +#define PORT_CLK_SEL_NONE
> REG_FIELD_PREP(PORT_CLK_SEL_MASK, 7)
> +
> +/* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */
> +#define DDI_CLK_SEL(port) PORT_CLK_SEL(port)
> +#define DDI_CLK_SEL_MASK REG_GENMASK(31, 28)
> +#define DDI_CLK_SEL_NONE REG_FIELD_PREP(DDI_CLK_SEL_MASK,
> 0x0)
> +#define DDI_CLK_SEL_MG
> REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x8)
> +#define DDI_CLK_SEL_TBT_162
> REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xC)
> +#define DDI_CLK_SEL_TBT_270
> REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xD)
> +#define DDI_CLK_SEL_TBT_540
> REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xE)
> +#define DDI_CLK_SEL_TBT_810
> REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xF)
> +
> +/* Transcoder clock selection */
> +#define _TRANS_CLK_SEL_A 0x46140
> +#define _TRANS_CLK_SEL_B 0x46144
> +#define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A,
> _TRANS_CLK_SEL_B)
> +/* For each transcoder, we need to select the corresponding port clock */
> +#define TRANS_CLK_SEL_DISABLED (0x0 << 29)
> +#define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29)
> +#define TGL_TRANS_CLK_SEL_DISABLED (0x0 << 28)
> +#define TGL_TRANS_CLK_SEL_PORT(x) (((x) + 1) << 28)
> +
> +#define CDCLK_FREQ _MMIO(0x46200)
> +
> +#define _TRANSA_MSA_MISC 0x60410
> +#define _TRANSB_MSA_MISC 0x61410
> +#define _TRANSC_MSA_MISC 0x62410
> +#define _TRANS_EDP_MSA_MISC 0x6f410
> +#define TRANS_MSA_MISC(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran,
> _TRANSA_MSA_MISC)
> +/* See DP_MSA_MISC_* for the bit definitions */
> +
> +#define _TRANS_A_SET_CONTEXT_LATENCY 0x6007C
> +#define _TRANS_B_SET_CONTEXT_LATENCY 0x6107C
> +#define _TRANS_C_SET_CONTEXT_LATENCY 0x6207C
> +#define _TRANS_D_SET_CONTEXT_LATENCY 0x6307C
> +#define TRANS_SET_CONTEXT_LATENCY(dev_priv, tran)
> _MMIO_TRANS2(dev_priv, tran, _TRANS_A_SET_CONTEXT_LATENCY)
> +#define TRANS_SET_CONTEXT_LATENCY_MASK
> REG_GENMASK(15, 0)
> +#define TRANS_SET_CONTEXT_LATENCY_VALUE(x)
> REG_FIELD_PREP(TRANS_SET_CONTEXT_LATENCY_MASK, (x))
> +
> +/* LCPLL Control */
> +#define LCPLL_CTL _MMIO(0x130040)
> +#define LCPLL_PLL_DISABLE (1 << 31)
> +#define LCPLL_PLL_LOCK (1 << 30)
> +#define LCPLL_REF_NON_SSC (0 << 28)
> +#define LCPLL_REF_BCLK (2 << 28)
> +#define LCPLL_REF_PCH_SSC (3 << 28)
> +#define LCPLL_REF_MASK (3 << 28)
> +#define LCPLL_CLK_FREQ_MASK (3 << 26)
> +#define LCPLL_CLK_FREQ_450 (0 << 26)
> +#define LCPLL_CLK_FREQ_54O_BDW (1 << 26)
> +#define LCPLL_CLK_FREQ_337_5_BDW (2 << 26)
> +#define LCPLL_CLK_FREQ_675_BDW (3 << 26)
> +#define LCPLL_CD_CLOCK_DISABLE (1 << 25)
> +#define LCPLL_ROOT_CD_CLOCK_DISABLE (1 << 24)
> +#define LCPLL_CD2X_CLOCK_DISABLE (1 << 23)
> +#define LCPLL_POWER_DOWN_ALLOW (1 << 22)
> +#define LCPLL_CD_SOURCE_FCLK (1 << 21)
> +#define LCPLL_CD_SOURCE_FCLK_DONE (1 << 19)
> +
> +/*
> + * SKL Clocks
> + */
> +/* CDCLK_CTL */
> +#define CDCLK_CTL _MMIO(0x46000)
> +#define CDCLK_FREQ_SEL_MASK REG_GENMASK(27, 26)
> +#define CDCLK_FREQ_450_432
> REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 0)
> +#define CDCLK_FREQ_540
> REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1)
> +#define CDCLK_FREQ_337_308
> REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2)
> +#define CDCLK_FREQ_675_617
> REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3)
> +#define MDCLK_SOURCE_SEL_MASK REG_GENMASK(25, 25)
> +#define MDCLK_SOURCE_SEL_CD2XCLK
> REG_FIELD_PREP(MDCLK_SOURCE_SEL_MASK, 0)
> +#define MDCLK_SOURCE_SEL_CDCLK_PLL
> REG_FIELD_PREP(MDCLK_SOURCE_SEL_MASK, 1)
> +#define BXT_CDCLK_CD2X_DIV_SEL_MASK REG_GENMASK(23, 22)
> +#define BXT_CDCLK_CD2X_DIV_SEL_1
> REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0)
> +#define BXT_CDCLK_CD2X_DIV_SEL_1_5
> REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1)
> +#define BXT_CDCLK_CD2X_DIV_SEL_2
> REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 2)
> +#define BXT_CDCLK_CD2X_DIV_SEL_4
> REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 3)
> +#define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20)
> +#define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19)
> +#define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
> +#define ICL_CDCLK_CD2X_PIPE(pipe) (_PICK(pipe, 0, 2, 6) << 19)
> +#define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19)
> +#define TGL_CDCLK_CD2X_PIPE(pipe) BXT_CDCLK_CD2X_PIPE(pipe)
> +#define TGL_CDCLK_CD2X_PIPE_NONE ICL_CDCLK_CD2X_PIPE_NONE
> +#define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16)
> +#define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
> +
> +/* CDCLK_SQUASH_CTL */
> +#define CDCLK_SQUASH_CTL _MMIO(0x46008)
> +#define CDCLK_SQUASH_ENABLE REG_BIT(31)
> +#define CDCLK_SQUASH_WINDOW_SIZE_MASK REG_GENMASK(27,
> 24)
> +#define CDCLK_SQUASH_WINDOW_SIZE(x)
> REG_FIELD_PREP(CDCLK_SQUASH_WINDOW_SIZE_MASK, (x))
> +#define CDCLK_SQUASH_WAVEFORM_MASK REG_GENMASK(15, 0)
> +#define CDCLK_SQUASH_WAVEFORM(x)
> REG_FIELD_PREP(CDCLK_SQUASH_WAVEFORM_MASK, (x))
> +
> +/* LCPLL_CTL */
> +#define LCPLL1_CTL _MMIO(0x46010)
> +#define LCPLL2_CTL _MMIO(0x46014)
> +#define LCPLL_PLL_ENABLE (1 << 31)
> +
> +/* DPLL control1 */
> +#define DPLL_CTRL1 _MMIO(0x6C058)
> +#define DPLL_CTRL1_HDMI_MODE(id) (1 << ((id) * 6 + 5))
> +#define DPLL_CTRL1_SSC(id) (1 << ((id) * 6 + 4))
> +#define DPLL_CTRL1_LINK_RATE_MASK(id) (7 << ((id) * 6 + 1))
> +#define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id) * 6 + 1)
> +#define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate) << ((id) * 6 + 1))
> +#define DPLL_CTRL1_OVERRIDE(id) (1 << ((id) * 6))
> +#define DPLL_CTRL1_LINK_RATE_2700 0
> +#define DPLL_CTRL1_LINK_RATE_1350 1
> +#define DPLL_CTRL1_LINK_RATE_810 2
> +#define DPLL_CTRL1_LINK_RATE_1620 3
> +#define DPLL_CTRL1_LINK_RATE_1080 4
> +#define DPLL_CTRL1_LINK_RATE_2160 5
> +
> +/* DPLL control2 */
> +#define DPLL_CTRL2 _MMIO(0x6C05C)
> +#define DPLL_CTRL2_DDI_CLK_OFF(port) (1 << ((port) + 15))
> +#define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3 << ((port) * 3 + 1))
> +#define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port) * 3 + 1)
> +#define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk) << ((port) * 3 + 1))
> +#define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1 << ((port) * 3))
> +
> +/* DPLL Status */
> +#define DPLL_STATUS _MMIO(0x6C060)
> +#define DPLL_LOCK(id) (1 << ((id) * 8))
> +
> +/* DPLL cfg */
> +#define _DPLL1_CFGCR1 0x6C040
> +#define _DPLL2_CFGCR1 0x6C048
> +#define _DPLL3_CFGCR1 0x6C050
> +#define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1,
> _DPLL1_CFGCR1, _DPLL2_CFGCR1)
> +#define DPLL_CFGCR1_FREQ_ENABLE (1 << 31)
> +#define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff << 9)
> +#define DPLL_CFGCR1_DCO_FRACTION(x) ((x) << 9)
> +#define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff)
> +
> +#define _DPLL1_CFGCR2 0x6C044
> +#define _DPLL2_CFGCR2 0x6C04C
> +#define _DPLL3_CFGCR2 0x6C054
> +#define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1,
> _DPLL1_CFGCR2, _DPLL2_CFGCR2)
> +#define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff << 8)
> +#define DPLL_CFGCR2_QDIV_RATIO(x) ((x) << 8)
> +#define DPLL_CFGCR2_QDIV_MODE(x) ((x) << 7)
> +#define DPLL_CFGCR2_KDIV_MASK (3 << 5)
> +#define DPLL_CFGCR2_KDIV(x) ((x) << 5)
> +#define DPLL_CFGCR2_KDIV_5 (0 << 5)
> +#define DPLL_CFGCR2_KDIV_2 (1 << 5)
> +#define DPLL_CFGCR2_KDIV_3 (2 << 5)
> +#define DPLL_CFGCR2_KDIV_1 (3 << 5)
> +#define DPLL_CFGCR2_PDIV_MASK (7 << 2)
> +#define DPLL_CFGCR2_PDIV(x) ((x) << 2)
> +#define DPLL_CFGCR2_PDIV_1 (0 << 2)
> +#define DPLL_CFGCR2_PDIV_2 (1 << 2)
> +#define DPLL_CFGCR2_PDIV_3 (2 << 2)
> +#define DPLL_CFGCR2_PDIV_7 (4 << 2)
> +#define DPLL_CFGCR2_PDIV_7_INVALID (5 << 2)
> +#define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
> +
> +/* ICL Clocks */
> +#define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
> +#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10,
> 11, 24, 4, 5))
> +#define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10)
> +#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) <
> TC_PORT_4 ? \
> + (tc_port) + 12 : \
> + (tc_port) - TC_PORT_4 +
> 21))
> +#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2)
> +#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 <<
> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
> +#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) <<
> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
> +#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0,
> 2, 4, 27)
> +#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \
> + (3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
> +#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \
> + ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
> +
> +/*
> + * DG1 Clocks
> + * First registers controls the first A and B, while the second register
> + * controls the phy C and D. The bits on these registers are the
> + * same, but refer to different phys
> + */
> +#define _DG1_DPCLKA_CFGCR0 0x164280
> +#define _DG1_DPCLKA1_CFGCR0 0x16C280
> +#define _DG1_DPCLKA_PHY_IDX(phy) ((phy) % 2)
> +#define _DG1_DPCLKA_PLL_IDX(pll) ((pll) % 2)
> +#define DG1_DPCLKA_CFGCR0(phy)
> _MMIO_PHY((phy) / 2, \
> +
> _DG1_DPCLKA_CFGCR0, \
> +
> _DG1_DPCLKA1_CFGCR0)
> +#define DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)
> REG_BIT(_DG1_DPCLKA_PHY_IDX(phy) + 10)
> +#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)
> (_DG1_DPCLKA_PHY_IDX(phy) * 2)
> +#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy)
> (_DG1_DPCLKA_PLL_IDX(pll) <<
> DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
> +#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (0x3 <<
> DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
> +
> +/* ADLS Clocks */
> +#define _ADLS_DPCLKA_CFGCR0 0x164280
> +#define _ADLS_DPCLKA_CFGCR1 0x1642BC
> +#define ADLS_DPCLKA_CFGCR(phy) _MMIO_PHY((phy) / 3,
> \
> +
> _ADLS_DPCLKA_CFGCR0, \
> +
> _ADLS_DPCLKA_CFGCR1)
> +#define ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy) (((phy) % 3) *
> 2)
> +/* ADLS DPCLKA_CFGCR0 DDI mask */
> +#define ADLS_DPCLKA_DDII_SEL_MASK
> REG_GENMASK(5, 4)
> +#define ADLS_DPCLKA_DDIB_SEL_MASK
> REG_GENMASK(3, 2)
> +#define ADLS_DPCLKA_DDIA_SEL_MASK
> REG_GENMASK(1, 0)
> +/* ADLS DPCLKA_CFGCR1 DDI mask */
> +#define ADLS_DPCLKA_DDIK_SEL_MASK
> REG_GENMASK(3, 2)
> +#define ADLS_DPCLKA_DDIJ_SEL_MASK
> REG_GENMASK(1, 0)
> +#define ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy) _PICK((phy), \
> +
> ADLS_DPCLKA_DDIA_SEL_MASK, \
> +
> ADLS_DPCLKA_DDIB_SEL_MASK, \
> +
> ADLS_DPCLKA_DDII_SEL_MASK, \
> +
> ADLS_DPCLKA_DDIJ_SEL_MASK, \
> +
> ADLS_DPCLKA_DDIK_SEL_MASK)
> +
> +/* ICL PLL */
> +#define _DPLL0_ENABLE 0x46010
> +#define _DPLL1_ENABLE 0x46014
> +#define _ADLS_DPLL2_ENABLE 0x46018
> +#define _ADLS_DPLL3_ENABLE 0x46030
> +#define PLL_ENABLE REG_BIT(31)
> +#define PLL_LOCK REG_BIT(30)
> +#define PLL_POWER_ENABLE REG_BIT(27)
> +#define PLL_POWER_STATE REG_BIT(26)
> +#define ICL_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3,
> \
> + _DPLL0_ENABLE,
> _DPLL1_ENABLE, \
> +
> _ADLS_DPLL3_ENABLE, _ADLS_DPLL3_ENABLE))
> +
> +#define _DG2_PLL3_ENABLE 0x4601C
> +
> +#define DG2_PLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3,
> \
> + _DPLL0_ENABLE,
> _DPLL1_ENABLE, \
> + _DG2_PLL3_ENABLE,
> _DG2_PLL3_ENABLE))
> +
> +#define TBT_PLL_ENABLE _MMIO(0x46020)
> +
> +#define _MG_PLL1_ENABLE 0x46030
> +#define _MG_PLL2_ENABLE 0x46034
> +#define _MG_PLL3_ENABLE 0x46038
> +#define _MG_PLL4_ENABLE 0x4603C
> +/* Bits are the same as _DPLL0_ENABLE */
> +#define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port),
> _MG_PLL1_ENABLE, \
> + _MG_PLL2_ENABLE)
> +
> +/* DG1 PLL */
> +#define DG1_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2,
> \
> + _DPLL0_ENABLE,
> _DPLL1_ENABLE, \
> + _MG_PLL1_ENABLE,
> _MG_PLL2_ENABLE))
> +
> +/* ADL-P Type C PLL */
> +#define PORTTC1_PLL_ENABLE 0x46038
> +#define PORTTC2_PLL_ENABLE 0x46040
> +#define ADLP_PORTTC_PLL_ENABLE(tc_port)
> _MMIO_PORT((tc_port), \
> +
> PORTTC1_PLL_ENABLE, \
> +
> PORTTC2_PLL_ENABLE)
> +
> +#define _ICL_DPLL0_CFGCR0 0x164000
> +#define _ICL_DPLL1_CFGCR0 0x164080
> +#define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0,
> \
> + _ICL_DPLL1_CFGCR0)
> +#define DPLL_CFGCR0_HDMI_MODE (1 << 30)
> +#define DPLL_CFGCR0_SSC_ENABLE (1 << 29)
> +#define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25)
> +#define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25)
> +#define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25)
> +#define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25)
> +#define DPLL_CFGCR0_LINK_RATE_810 (2 << 25)
> +#define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25)
> +#define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25)
> +#define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25)
> +#define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25)
> +#define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25)
> +#define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10)
> +#define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10)
> +#define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10)
> +#define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff)
> +
> +#define _ICL_DPLL0_CFGCR1 0x164004
> +#define _ICL_DPLL1_CFGCR1 0x164084
> +#define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1,
> \
> + _ICL_DPLL1_CFGCR1)
> +#define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10)
> +#define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10)
> +#define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10)
> +#define DPLL_CFGCR1_QDIV_MODE_SHIFT (9)
> +#define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9)
> +#define DPLL_CFGCR1_KDIV_MASK (7 << 6)
> +#define DPLL_CFGCR1_KDIV_SHIFT (6)
> +#define DPLL_CFGCR1_KDIV(x) ((x) << 6)
> +#define DPLL_CFGCR1_KDIV_1 (1 << 6)
> +#define DPLL_CFGCR1_KDIV_2 (2 << 6)
> +#define DPLL_CFGCR1_KDIV_3 (4 << 6)
> +#define DPLL_CFGCR1_PDIV_MASK (0xf << 2)
> +#define DPLL_CFGCR1_PDIV_SHIFT (2)
> +#define DPLL_CFGCR1_PDIV(x) ((x) << 2)
> +#define DPLL_CFGCR1_PDIV_2 (1 << 2)
> +#define DPLL_CFGCR1_PDIV_3 (2 << 2)
> +#define DPLL_CFGCR1_PDIV_5 (4 << 2)
> +#define DPLL_CFGCR1_PDIV_7 (8 << 2)
> +#define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0)
> +#define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0)
> +#define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0)
> +
> +#define _TGL_DPLL0_CFGCR0 0x164284
> +#define _TGL_DPLL1_CFGCR0 0x16428C
> +#define _TGL_TBTPLL_CFGCR0 0x16429C
> +#define TGL_DPLL_CFGCR0(pll)
> _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
> + _TGL_DPLL0_CFGCR0,
> _TGL_DPLL1_CFGCR0, \
> + _TGL_TBTPLL_CFGCR0,
> _TGL_TBTPLL_CFGCR0))
> +#define RKL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0,
> \
> + _TGL_DPLL1_CFGCR0)
> +
> +#define _TGL_DPLL0_DIV0 0x164B00
> +#define _TGL_DPLL1_DIV0 0x164C00
> +#define TGL_DPLL0_DIV0(pll) _MMIO_PLL(pll,
> _TGL_DPLL0_DIV0, _TGL_DPLL1_DIV0)
> +#define TGL_DPLL0_DIV0_AFC_STARTUP_MASK
> REG_GENMASK(27, 25)
> +#define TGL_DPLL0_DIV0_AFC_STARTUP(val)
> REG_FIELD_PREP(TGL_DPLL0_DIV0_AFC_STARTUP_MASK, (val))
> +
> +#define _TGL_DPLL0_CFGCR1 0x164288
> +#define _TGL_DPLL1_CFGCR1 0x164290
> +#define _TGL_TBTPLL_CFGCR1 0x1642A0
> +#define TGL_DPLL_CFGCR1(pll)
> _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
> + _TGL_DPLL0_CFGCR1,
> _TGL_DPLL1_CFGCR1, \
> + _TGL_TBTPLL_CFGCR1,
> _TGL_TBTPLL_CFGCR1))
> +#define RKL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1,
> \
> + _TGL_DPLL1_CFGCR1)
> +
> +#define _DG1_DPLL2_CFGCR0 0x16C284
> +#define _DG1_DPLL3_CFGCR0 0x16C28C
> +#define DG1_DPLL_CFGCR0(pll)
> _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
> + _TGL_DPLL0_CFGCR0,
> _TGL_DPLL1_CFGCR0, \
> + _DG1_DPLL2_CFGCR0,
> _DG1_DPLL3_CFGCR0))
> +
> +#define _DG1_DPLL2_CFGCR1 0x16C288
> +#define _DG1_DPLL3_CFGCR1 0x16C290
> +#define DG1_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2,
> \
> + _TGL_DPLL0_CFGCR1,
> _TGL_DPLL1_CFGCR1, \
> + _DG1_DPLL2_CFGCR1,
> _DG1_DPLL3_CFGCR1))
> +
> +/* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */
> +#define _ADLS_DPLL4_CFGCR0 0x164294
> +#define _ADLS_DPLL3_CFGCR0 0x1642C0
> +#define ADLS_DPLL_CFGCR0(pll)
> _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
> + _TGL_DPLL0_CFGCR0,
> _TGL_DPLL1_CFGCR0, \
> + _ADLS_DPLL4_CFGCR0,
> _ADLS_DPLL3_CFGCR0))
> +
> +#define _ADLS_DPLL4_CFGCR1 0x164298
> +#define _ADLS_DPLL3_CFGCR1 0x1642C4
> +#define ADLS_DPLL_CFGCR1(pll)
> _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
> + _TGL_DPLL0_CFGCR1,
> _TGL_DPLL1_CFGCR1, \
> + _ADLS_DPLL4_CFGCR1,
> _ADLS_DPLL3_CFGCR1))
> +
> +/* BXT display engine PLL */
> +#define BXT_DE_PLL_CTL _MMIO(0x6d000)
> +#define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} *
> 19.2MHz */
> +#define BXT_DE_PLL_RATIO_MASK 0xff
> +
> +#define BXT_DE_PLL_ENABLE _MMIO(0x46070)
> +#define BXT_DE_PLL_PLL_ENABLE (1 << 31)
> +#define BXT_DE_PLL_LOCK (1 << 30)
> +#define BXT_DE_PLL_FREQ_REQ (1 << 23)
> +#define BXT_DE_PLL_FREQ_REQ_ACK (1 << 22)
> +#define ICL_CDCLK_PLL_RATIO(x) (x)
> +#define ICL_CDCLK_PLL_RATIO_MASK 0xff
> +
> +/* GEN9 DC */
> +#define DC_STATE_EN _MMIO(0x45504)
> +#define DC_STATE_DISABLE 0
> +#define DC_STATE_EN_DC3CO REG_BIT(30)
> +#define DC_STATE_DC3CO_STATUS REG_BIT(29)
> +#define HOLD_PHY_CLKREQ_PG1_LATCH REG_BIT(21)
> +#define HOLD_PHY_PG1_LATCH REG_BIT(20)
> +#define DC_STATE_EN_UPTO_DC5 (1 << 0)
> +#define DC_STATE_EN_DC9 (1 << 3)
> +#define DC_STATE_EN_UPTO_DC6 (2 << 0)
> +#define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3
> +
> +#define DC_STATE_DEBUG _MMIO(0x45520)
> +#define DC_STATE_DEBUG_MASK_CORES (1 << 0)
> +#define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1)
> +
> +#define D_COMP_BDW _MMIO(0x138144)
> +
> +/* Pipe WM_LINETIME - watermark line time */
> +#define _WM_LINETIME_A 0x45270
> +#define _WM_LINETIME_B 0x45274
> +#define WM_LINETIME(pipe) _MMIO_PIPE(pipe, _WM_LINETIME_A,
> _WM_LINETIME_B)
> +#define HSW_LINETIME_MASK REG_GENMASK(8, 0)
> +#define HSW_LINETIME(x) REG_FIELD_PREP(HSW_LINETIME_MASK, (x))
> +#define HSW_IPS_LINETIME_MASK REG_GENMASK(24, 16)
> +#define HSW_IPS_LINETIME(x)
> REG_FIELD_PREP(HSW_IPS_LINETIME_MASK, (x))
> +
> +/* SFUSE_STRAP */
> +#define SFUSE_STRAP _MMIO(0xc2014)
> +#define SFUSE_STRAP_FUSE_LOCK (1 << 13)
> +#define SFUSE_STRAP_RAW_FREQUENCY (1 << 8)
> +#define SFUSE_STRAP_DISPLAY_DISABLED (1 << 7)
> +#define SFUSE_STRAP_CRT_DISABLED (1 << 6)
> +#define SFUSE_STRAP_DDIF_DETECTED (1 << 3)
> +#define SFUSE_STRAP_DDIB_DETECTED (1 << 2)
> +#define SFUSE_STRAP_DDIC_DETECTED (1 << 1)
> +#define SFUSE_STRAP_DDID_DETECTED (1 << 0)
> +
> +/* Gen4+ Timestamp and Pipe Frame time stamp registers */
> +#define GEN4_TIMESTAMP _MMIO(0x2358)
> +#define ILK_TIMESTAMP_HI _MMIO(0x70070)
> +#define IVB_TIMESTAMP_CTR _MMIO(0x44070)
> +
> +/* g4x+, except vlv/chv! */
> +#define _PIPE_FRMTMSTMP_A 0x70048
> +#define _PIPE_FRMTMSTMP_B 0x71048
> +#define PIPE_FRMTMSTMP(pipe) \
> + _MMIO_PIPE(pipe, _PIPE_FRMTMSTMP_A, _PIPE_FRMTMSTMP_B)
> +
> +/* g4x+, except vlv/chv! */
> +#define _PIPE_FLIPTMSTMP_A 0x7004C
> +#define _PIPE_FLIPTMSTMP_B 0x7104C
> +#define PIPE_FLIPTMSTMP(pipe) \
> + _MMIO_PIPE(pipe, _PIPE_FLIPTMSTMP_A, _PIPE_FLIPTMSTMP_B)
> +
> +/* tgl+ */
> +#define _PIPE_FLIPDONETMSTMP_A 0x70054
> +#define _PIPE_FLIPDONETMSTMP_B 0x71054
> +#define PIPE_FLIPDONETIMSTMP(pipe) \
> + _MMIO_PIPE(pipe, _PIPE_FLIPDONETMSTMP_A,
> _PIPE_FLIPDONETMSTMP_B)
> +
> +#define _VLV_PIPE_MSA_MISC_A 0x70048
> +#define VLV_PIPE_MSA_MISC(__display, pipe) \
> + _MMIO_PIPE2(__display, pipe, _VLV_PIPE_MSA_MISC_A)
> +#define VLV_MSA_MISC1_HW_ENABLE REG_BIT(31)
> +#define VLV_MSA_MISC1_SW_S3D_MASK
> REG_GENMASK(2, 0) /* MSA MISC1 3:1 */
> +
> +#define _ICL_PHY_MISC_A 0x64C00
> +#define _ICL_PHY_MISC_B 0x64C04
> +#define _DG2_PHY_MISC_TC1 0x64C14 /* TC1="PHY E" but offset as if "PHY
> F" */
> +#define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A,
> _ICL_PHY_MISC_B)
> +#define DG2_PHY_MISC(port) ((port) == PHY_E ?
> _MMIO(_DG2_PHY_MISC_TC1) : \
> + ICL_PHY_MISC(port))
> +#define ICL_PHY_MISC_MUX_DDID (1 << 28)
> +#define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
> +#define DG2_PHY_DP_TX_ACK_MASK REG_GENMASK(23,
> 20)
> +
> +#define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia),
> 0x008A0)
> +#define MODULAR_FIA_MASK (1 << 4)
> +#define TC_LIVE_STATE_TBT(idx) (1 << ((idx) * 8 + 6))
> +#define TC_LIVE_STATE_TC(idx) (1 << ((idx) * 8 + 5))
> +#define DP_LANE_ASSIGNMENT_SHIFT(idx) ((idx) * 8)
> +#define DP_LANE_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 8))
> +#define DP_LANE_ASSIGNMENT(idx, x) ((x) << ((idx) * 8))
> +
> +#define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia),
> 0x00890)
> +#define DP_PHY_MODE_STATUS_COMPLETED(idx) (1 << (idx))
> +
> +#define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894)
> +#define DP_PHY_MODE_STATUS_NOT_SAFE(idx) (1 << (idx))
> +
> +#define PORT_TX_DFLEXPA1(fia) _MMIO_FIA((fia),
> 0x00880)
> +#define DP_PIN_ASSIGNMENT_SHIFT(idx) ((idx) * 4)
> +#define DP_PIN_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 4))
> +#define DP_PIN_ASSIGNMENT(idx, x) ((x) << ((idx) * 4))
> +
> +#define _TCSS_DDI_STATUS_1 0x161500
> +#define _TCSS_DDI_STATUS_2 0x161504
> +#define TCSS_DDI_STATUS(tc) _MMIO(_PICK_EVEN(tc, \
> +
> _TCSS_DDI_STATUS_1, \
> +
> _TCSS_DDI_STATUS_2))
> +#define TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK REG_GENMASK(28,
> 25)
> +#define TCSS_DDI_STATUS_READY REG_BIT(2)
> +#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1)
> +#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0)
> +
> +#define CLKREQ_POLICY _MMIO(0x101038)
> +#define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1)
> +
> +#define CLKGATE_DIS_MISC _MMIO(0x46534)
> +#define CLKGATE_DIS_MISC_DMASC_GATING_DIS REG_BIT(21)
> +
> +#define _MTL_CLKGATE_DIS_TRANS_A 0x604E8
> +#define _MTL_CLKGATE_DIS_TRANS_B 0x614E8
> +#define MTL_CLKGATE_DIS_TRANS(dev_priv, trans)
> _MMIO_TRANS2(dev_priv, trans, _MTL_CLKGATE_DIS_TRANS_A)
> +#define MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS
> REG_BIT(7)
> +
> +#define _MTL_PIPE_CLKGATE_DIS2_A 0x60114
> +#define _MTL_PIPE_CLKGATE_DIS2_B 0x61114
> +#define MTL_PIPE_CLKGATE_DIS2(pipe) _MMIO_PIPE(pipe,
> _MTL_PIPE_CLKGATE_DIS2_A, _MTL_PIPE_CLKGATE_DIS2_B)
> +#define MTL_DPFC_GATING_DIS REG_BIT(6)
> +
> +#define MTL_MEM_SS_INFO_QGV_POINT_OFFSET 0x45710
> +#define MTL_MEM_SS_INFO_QGV_POINT_LOW(point)
> _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8)
> +#define MTL_TRCD_MASK REG_GENMASK(31, 24)
> +#define MTL_TRP_MASK REG_GENMASK(23, 16)
> +#define MTL_DCLK_MASK REG_GENMASK(15, 0)
> +
> +#define MTL_MEM_SS_INFO_QGV_POINT_HIGH(point)
> _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8 + 4)
> +#define MTL_TRAS_MASK REG_GENMASK(16, 8)
> +#define MTL_TRDPRE_MASK REG_GENMASK(7, 0)
> +
> +
> +
> +#endif /* __INTEL_DISPLAY_REGS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c
> b/drivers/gpu/drm/i915/display/intel_display_wa.c
> index da429c332914..f57280e9d041 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_wa.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
> @@ -6,6 +6,7 @@
> #include "i915_reg.h"
> #include "intel_de.h"
> #include "intel_display_core.h"
> +#include "intel_display_regs.h"
> #include "intel_display_wa.h"
>
> static void gen11_display_wa_apply(struct intel_display *display)
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
> b/drivers/gpu/drm/i915/display/intel_dmc.c
> index 98f80a6c63e8..e516104ee069 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -28,8 +28,9 @@
> #include "i915_drv.h"
> #include "i915_reg.h"
> #include "intel_de.h"
> -#include "intel_display_rpm.h"
> #include "intel_display_power_well.h"
> +#include "intel_display_regs.h"
> +#include "intel_display_rpm.h"
> #include "intel_dmc.h"
> #include "intel_dmc_regs.h"
> #include "intel_step.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> index 7e2ce0c2f6c3..082cb5597c1a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> @@ -10,6 +10,7 @@
> #include "i915_drv.h"
> #include "i915_reg.h"
> #include "intel_de.h"
> +#include "intel_display_regs.h"
> #include "intel_dmc_regs.h"
> #include "intel_dmc_wl.h"
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index d7a30d0992b7..56224d9ffdc0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -34,7 +34,6 @@
> #include <linux/string_helpers.h>
> #include <linux/timekeeping.h>
> #include <linux/types.h>
> -
> #include <asm/byteorder.h>
>
> #include <drm/display/drm_dp_helper.h>
> @@ -58,10 +57,12 @@
> #include "intel_combo_phy_regs.h"
> #include "intel_connector.h"
> #include "intel_crtc.h"
> +#include "intel_crtc_state_dump.h"
> #include "intel_cx0_phy.h"
> #include "intel_ddi.h"
> #include "intel_de.h"
> #include "intel_display_driver.h"
> +#include "intel_display_regs.h"
> #include "intel_display_rpm.h"
> #include "intel_display_types.h"
> #include "intel_dp.h"
> @@ -92,7 +93,6 @@
> #include "intel_tc.h"
> #include "intel_vdsc.h"
> #include "intel_vrr.h"
> -#include "intel_crtc_state_dump.h"
>
> /* DP DSC throughput values used for slice count calculations KPixels/s */
> #define DP_DSC_PEAK_PIXEL_RATE 2720000
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> index cc312596fb77..23ea94ba4c6c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> @@ -14,6 +14,7 @@
> #include "i915_reg.h"
> #include "intel_ddi.h"
> #include "intel_de.h"
> +#include "intel_display_regs.h"
> #include "intel_display_types.h"
> #include "intel_dp.h"
> #include "intel_dp_hdcp.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 4c15dcb103aa..94064cb7be28 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -38,6 +38,7 @@
> #include "intel_ddi.h"
> #include "intel_de.h"
> #include "intel_display_driver.h"
> +#include "intel_display_regs.h"
> #include "intel_display_types.h"
> #include "intel_dp.h"
> #include "intel_dp_hdcp.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_test.c
> b/drivers/gpu/drm/i915/display/intel_dp_test.c
> index bd61f3c3ec91..82b74f109315 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_test.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_test.c
> @@ -13,6 +13,7 @@
> #include "i915_reg.h"
> #include "intel_ddi.h"
> #include "intel_de.h"
> +#include "intel_display_regs.h"
> #include "intel_display_types.h"
> #include "intel_dp.h"
> #include "intel_dp_link_training.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> index 1e1af7150723..ce6ccc14d093 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> @@ -28,6 +28,7 @@
> #include "intel_ddi_buf_trans.h"
> #include "intel_de.h"
> #include "intel_display_power_well.h"
> +#include "intel_display_regs.h"
> #include "intel_display_types.h"
> #include "intel_dp.h"
> #include "intel_dpio_phy.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c
> b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 0481b1365b85..c694be9521ae 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -13,6 +13,7 @@
> #include "intel_cx0_phy.h"
> #include "intel_de.h"
> #include "intel_display.h"
> +#include "intel_display_regs.h"
> #include "intel_display_types.h"
> #include "intel_dpio_phy.h"
> #include "intel_dpll.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 84df41086a89..18b79485b9dd 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -29,6 +29,7 @@
> #include "i915_reg.h"
> #include "intel_cx0_phy.h"
> #include "intel_de.h"
> +#include "intel_display_regs.h"
> #include "intel_display_types.h"
> #include "intel_dkl_phy.h"
> #include "intel_dkl_phy_regs.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_dpt_common.c
> b/drivers/gpu/drm/i915/display/intel_dpt_common.c
> index d2dede0a5229..4e05558d6b64 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpt_common.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpt_common.c
> @@ -6,6 +6,7 @@
> #include "i915_drv.h"
> #include "i915_reg.h"
> #include "intel_de.h"
> +#include "intel_display_regs.h"
> #include "intel_display_types.h"
> #include "intel_dpt_common.h"
> #include "skl_universal_plane_regs.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c
> b/drivers/gpu/drm/i915/display/intel_drrs.c
> index 05cd0f6e6d71..09ee2b157e2f 100644
> --- a/drivers/gpu/drm/i915/display/intel_drrs.c
> +++ b/drivers/gpu/drm/i915/display/intel_drrs.c
> @@ -9,6 +9,7 @@
> #include "i915_reg.h"
> #include "intel_atomic.h"
> #include "intel_de.h"
> +#include "intel_display_regs.h"
> #include "intel_display_types.h"
> #include "intel_drrs.h"
> #include "intel_frontbuffer.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
> b/drivers/gpu/drm/i915/display/intel_dsb.c
> index 72fe390c5af2..f6123081b6bd 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -11,6 +11,7 @@
> #include "i915_reg.h"
> #include "intel_crtc.h"
> #include "intel_de.h"
> +#include "intel_display_regs.h"
> #include "intel_display_rpm.h"
> #include "intel_display_types.h"
> #include "intel_dsb.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
> b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
> index 4e92504f5c14..ecebc3946cbb 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
> @@ -31,17 +31,16 @@
> #include <linux/pinctrl/machine.h>
> #include <linux/slab.h>
> #include <linux/string_helpers.h>
> -
> #include <linux/unaligned.h>
>
> #include <drm/drm_crtc.h>
> #include <drm/drm_edid.h>
> -
> #include <video/mipi_display.h>
>
> #include "i915_drv.h"
> #include "i915_reg.h"
> #include "intel_de.h"
> +#include "intel_display_regs.h"
> #include "intel_display_types.h"
> #include "intel_dsi.h"
> #include "intel_dsi_vbt.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c
> b/drivers/gpu/drm/i915/display/intel_dvo.c
> index b61520353c92..7cf3fb9163f4 100644
> --- a/drivers/gpu/drm/i915/display/intel_dvo.c
> +++ b/drivers/gpu/drm/i915/display/intel_dvo.c
> @@ -39,6 +39,7 @@
> #include "intel_connector.h"
> #include "intel_de.h"
> #include "intel_display_driver.h"
> +#include "intel_display_regs.h"
> #include "intel_display_types.h"
> #include "intel_dvo.h"
> #include "intel_dvo_dev.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index ce5b1e3f1c20..4665bce3487a 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -45,7 +45,9 @@
> #include <drm/drm_fourcc.h>
>
> #include "gem/i915_gem_stolen.h"
> +
> #include "gt/intel_gt_types.h"
> +
> #include "i915_drv.h"
> #include "i915_reg.h"
> #include "i915_utils.h"
> @@ -55,6 +57,7 @@
> #include "intel_cdclk.h"
> #include "intel_de.h"
> #include "intel_display_device.h"
> +#include "intel_display_regs.h"
> #include "intel_display_rpm.h"
> #include "intel_display_trace.h"
> #include "intel_display_types.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c
> b/drivers/gpu/drm/i915/display/intel_fdi.c
> index 40deee0769ae..7fdd2254eba6 100644
> --- a/drivers/gpu/drm/i915/display/intel_fdi.c
> +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
> @@ -13,8 +13,9 @@
> #include "intel_crtc.h"
> #include "intel_ddi.h"
> #include "intel_de.h"
> -#include "intel_dp.h"
> +#include "intel_display_regs.h"
> #include "intel_display_types.h"
> +#include "intel_dp.h"
> #include "intel_fdi.h"
> #include "intel_fdi_regs.h"
> #include "intel_link_bw.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> index 451cd26024f7..7356b1d48a4b 100644
> --- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> +++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> @@ -29,6 +29,7 @@
> #include "i915_reg.h"
> #include "intel_de.h"
> #include "intel_display_irq.h"
> +#include "intel_display_regs.h"
> #include "intel_display_trace.h"
> #include "intel_display_types.h"
> #include "intel_fbc.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c
> b/drivers/gpu/drm/i915/display/intel_gmbus.c
> index abf457e68ee9..c06eec0c654f 100644
> --- a/drivers/gpu/drm/i915/display/intel_gmbus.c
> +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
> @@ -37,6 +37,7 @@
> #include "i915_irq.h"
> #include "i915_reg.h"
> #include "intel_de.h"
> +#include "intel_display_regs.h"
> #include "intel_display_types.h"
> #include "intel_gmbus.h"
> #include "intel_gmbus_regs.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index 411f17655f89..e344fd1a4717 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -22,6 +22,7 @@
> #include "intel_de.h"
> #include "intel_display_power.h"
> #include "intel_display_power_well.h"
> +#include "intel_display_regs.h"
> #include "intel_display_rpm.h"
> #include "intel_display_types.h"
> #include "intel_dp_mst.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index f9fa17e1f584..fb8ead20e180 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -40,7 +40,6 @@
> #include <drm/drm_edid.h>
> #include <drm/drm_probe_helper.h>
> #include <drm/intel/intel_lpe_audio.h>
> -
> #include <media/cec-notifier.h>
>
> #include "g4x_hdmi.h"
> @@ -53,6 +52,7 @@
> #include "intel_ddi.h"
> #include "intel_de.h"
> #include "intel_display_driver.h"
> +#include "intel_display_regs.h"
> #include "intel_display_types.h"
> #include "intel_dp.h"
> #include "intel_gmbus.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> index 2463e61e7802..8486a378a0e6 100644
> --- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> @@ -7,6 +7,7 @@
> #include "i915_reg.h"
> #include "intel_de.h"
> #include "intel_display_irq.h"
> +#include "intel_display_regs.h"
> #include "intel_display_types.h"
> #include "intel_dp_aux.h"
> #include "intel_gmbus.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
> b/drivers/gpu/drm/i915/display/intel_lspcon.c
> index f94b7eeae20f..a874a28e4cf9 100644
> --- a/drivers/gpu/drm/i915/display/intel_lspcon.c
> +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
> @@ -32,6 +32,7 @@
> #include "i915_reg.h"
> #include "i915_utils.h"
> #include "intel_de.h"
> +#include "intel_display_regs.h"
> #include "intel_display_types.h"
> #include "intel_dp.h"
> #include "intel_hdmi.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> index 9e963bce340f..85b53a08daf8 100644
> --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> @@ -6,8 +6,8 @@
> * state.
> */
>
> -#include <drm/drm_atomic_uapi.h>
> #include <drm/drm_atomic_state_helper.h>
> +#include <drm/drm_atomic_uapi.h>
> #include <drm/drm_vblank.h>
>
> #include "i915_drv.h"
> @@ -23,6 +23,7 @@
> #include "intel_de.h"
> #include "intel_display.h"
> #include "intel_display_power.h"
> +#include "intel_display_regs.h"
> #include "intel_display_types.h"
> #include "intel_dmc.h"
> #include "intel_fifo_underrun.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c
> b/drivers/gpu/drm/i915/display/intel_overlay.c
> index aff9a3455c1b..ff5dc2515f55 100644
> --- a/drivers/gpu/drm/i915/display/intel_overlay.c
> +++ b/drivers/gpu/drm/i915/display/intel_overlay.c
> @@ -31,6 +31,7 @@
> #include "gem/i915_gem_internal.h"
> #include "gem/i915_gem_object_frontbuffer.h"
> #include "gem/i915_gem_pm.h"
> +
> #include "gt/intel_gpu_commands.h"
> #include "gt/intel_ring.h"
>
> @@ -38,6 +39,7 @@
> #include "i915_reg.h"
> #include "intel_color_regs.h"
> #include "intel_de.h"
> +#include "intel_display_regs.h"
> #include "intel_display_types.h"
> #include "intel_frontbuffer.h"
> #include "intel_overlay.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c
> b/drivers/gpu/drm/i915/display/intel_pch_display.c
> index b909ed18a5b2..567887a0cccf 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> @@ -9,6 +9,7 @@
> #include "intel_crt.h"
> #include "intel_crt_regs.h"
> #include "intel_de.h"
> +#include "intel_display_regs.h"
> #include "intel_display_types.h"
> #include "intel_dpll.h"
> #include "intel_fdi.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> index 1307a478861a..221bf8d49afb 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> @@ -6,6 +6,7 @@
> #include "i915_drv.h"
> #include "i915_reg.h"
> #include "intel_de.h"
> +#include "intel_display_regs.h"
> #include "intel_display_types.h"
> #include "intel_panel.h"
> #include "intel_pch_refclk.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_pfit.c
> b/drivers/gpu/drm/i915/display/intel_pfit.c
> index 3c3ecf288570..b615be868fd9 100644
> --- a/drivers/gpu/drm/i915/display/intel_pfit.c
> +++ b/drivers/gpu/drm/i915/display/intel_pfit.c
> @@ -10,6 +10,7 @@
> #include "intel_de.h"
> #include "intel_display_core.h"
> #include "intel_display_driver.h"
> +#include "intel_display_regs.h"
> #include "intel_display_types.h"
> #include "intel_lvds_regs.h"
> #include "intel_pfit.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc.c
> b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
> index 6182f484b5bd..6e4c65a08949 100644
> --- a/drivers/gpu/drm/i915/display/intel_pipe_crc.c
> +++ b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
> @@ -34,6 +34,7 @@
> #include "intel_atomic.h"
> #include "intel_de.h"
> #include "intel_display_irq.h"
> +#include "intel_display_regs.h"
> #include "intel_display_types.h"
> #include "intel_pipe_crc.h"
> #include "intel_pipe_crc_regs.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c
> b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> index d22b5469672d..86f924c2fe70 100644
> --- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
> +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> @@ -13,6 +13,7 @@
> #include "intel_bw.h"
> #include "intel_cdclk.h"
> #include "intel_de.h"
> +#include "intel_display_regs.h"
> #include "intel_display_trace.h"
> #include "intel_pmdemand.h"
> #include "intel_step.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
> b/drivers/gpu/drm/i915/display/intel_pps.c
> index 4d4e2b9f5f2d..f2c87deca30e 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.c
> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> @@ -10,6 +10,7 @@
> #include "i915_reg.h"
> #include "intel_de.h"
> #include "intel_display_power_well.h"
> +#include "intel_display_regs.h"
> #include "intel_display_types.h"
> #include "intel_dp.h"
> #include "intel_dpio_phy.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index eef48c014112..aa1915a30bea 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -36,6 +36,7 @@
> #include "intel_ddi.h"
> #include "intel_de.h"
> #include "intel_display_irq.h"
> +#include "intel_display_regs.h"
> #include "intel_display_rpm.h"
> #include "intel_display_types.h"
> #include "intel_dp.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c
> b/drivers/gpu/drm/i915/display/intel_sdvo.c
> index 757b9ce7e3b1..89b66473fd17 100644
> --- a/drivers/gpu/drm/i915/display/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
> @@ -46,6 +46,7 @@
> #include "intel_crtc.h"
> #include "intel_de.h"
> #include "intel_display_driver.h"
> +#include "intel_display_regs.h"
> #include "intel_display_types.h"
> #include "intel_fdi.h"
> #include "intel_fifo_underrun.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c
> b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> index 2b53ac9f4935..8edc9252276b 100644
> --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> @@ -12,6 +12,7 @@
> #include "intel_ddi.h"
> #include "intel_ddi_buf_trans.h"
> #include "intel_de.h"
> +#include "intel_display_regs.h"
> #include "intel_display_types.h"
> #include "intel_snps_hdmi_pll.h"
> #include "intel_snps_phy.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
> b/drivers/gpu/drm/i915/display/intel_tc.c
> index c1014e74791f..3bc57579fe53 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -14,6 +14,7 @@
> #include "intel_display.h"
> #include "intel_display_driver.h"
> #include "intel_display_power_map.h"
> +#include "intel_display_regs.h"
> #include "intel_display_types.h"
> #include "intel_dkl_phy_regs.h"
> #include "intel_dp.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c
> b/drivers/gpu/drm/i915/display/intel_vblank.c
> index 139fa5deba80..c1c6ce390bbc 100644
> --- a/drivers/gpu/drm/i915/display/intel_vblank.c
> +++ b/drivers/gpu/drm/i915/display/intel_vblank.c
> @@ -10,6 +10,7 @@
> #include "intel_color.h"
> #include "intel_crtc.h"
> #include "intel_de.h"
> +#include "intel_display_regs.h"
> #include "intel_display_types.h"
> #include "intel_vblank.h"
> #include "intel_vrr.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_vga.c
> b/drivers/gpu/drm/i915/display/intel_vga.c
> index 684b5d1bc87c..85ec1969d4dd 100644
> --- a/drivers/gpu/drm/i915/display/intel_vga.c
> +++ b/drivers/gpu/drm/i915/display/intel_vga.c
> @@ -7,11 +7,13 @@
> #include <linux/vgaarb.h>
>
> #include <video/vga.h>
> +
> #include "soc/intel_gmch.h"
>
> #include "i915_drv.h"
> #include "i915_reg.h"
> #include "intel_de.h"
> +#include "intel_display_regs.h"
> #include "intel_vga.h"
>
> static i915_reg_t intel_vga_cntrl_reg(struct intel_display *display)
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> b/drivers/gpu/drm/i915/display/intel_vrr.c
> index c6565baf815a..619a6b78a991 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -8,6 +8,7 @@
>
> #include "i915_reg.h"
> #include "intel_de.h"
> +#include "intel_display_regs.h"
> #include "intel_display_types.h"
> #include "intel_dp.h"
> #include "intel_vrr.h"
> diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c
> b/drivers/gpu/drm/i915/display/skl_scaler.c
> index ee81220a7c88..b3e41b342127 100644
> --- a/drivers/gpu/drm/i915/display/skl_scaler.c
> +++ b/drivers/gpu/drm/i915/display/skl_scaler.c
> @@ -6,6 +6,7 @@
> #include "i915_drv.h"
> #include "i915_reg.h"
> #include "intel_de.h"
> +#include "intel_display_regs.h"
> #include "intel_display_trace.h"
> #include "intel_display_types.h"
> #include "intel_fb.h"
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 8739195aba69..881a690c36e8 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -8,12 +8,15 @@
> #include <drm/drm_damage_helper.h>
> #include <drm/drm_fourcc.h>
>
> +#include "pxp/intel_pxp.h"
> +
> #include "i915_drv.h"
> #include "i915_reg.h"
> #include "intel_atomic_plane.h"
> #include "intel_bo.h"
> #include "intel_de.h"
> #include "intel_display_irq.h"
> +#include "intel_display_regs.h"
> #include "intel_display_types.h"
> #include "intel_dpt.h"
> #include "intel_fb.h"
> @@ -25,7 +28,6 @@
> #include "skl_universal_plane.h"
> #include "skl_universal_plane_regs.h"
> #include "skl_watermark.h"
> -#include "pxp/intel_pxp.h"
>
> static const u32 skl_plane_formats[] = {
> DRM_FORMAT_C8,
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 8080f777910a..689595693781 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -19,6 +19,7 @@
> #include "intel_de.h"
> #include "intel_display.h"
> #include "intel_display_power.h"
> +#include "intel_display_regs.h"
> #include "intel_display_rpm.h"
> #include "intel_display_types.h"
> #include "intel_fb.h"
> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c
> b/drivers/gpu/drm/i915/display/vlv_dsi.c
> index 346737f15fa9..cc16957da106 100644
> --- a/drivers/gpu/drm/i915/display/vlv_dsi.c
> +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
> @@ -39,6 +39,7 @@
> #include "intel_connector.h"
> #include "intel_crtc.h"
> #include "intel_de.h"
> +#include "intel_display_regs.h"
> #include "intel_display_types.h"
> #include "intel_dsi.h"
> #include "intel_dsi_vbt.h"
> diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c
> b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> index f25ee2953baf..fa6625fdf4cb 100644
> --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
> +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> @@ -38,6 +38,7 @@
>
> #include "i915_drv.h"
> #include "i915_reg.h"
> +#include "display/intel_display_regs.h"
> #include "gt/intel_engine_regs.h"
> #include "gt/intel_gpu_commands.h"
> #include "gt/intel_gt_regs.h"
> diff --git a/drivers/gpu/drm/i915/gvt/display.c
> b/drivers/gpu/drm/i915/gvt/display.c
> index 1e1af5e545a4..35e8103953a0 100644
> --- a/drivers/gpu/drm/i915/gvt/display.c
> +++ b/drivers/gpu/drm/i915/gvt/display.c
> @@ -36,6 +36,7 @@
>
> #include "i915_drv.h"
> #include "i915_reg.h"
> +#include "display/intel_display_regs.h"
> #include "gvt.h"
>
> #include "display/bxt_dpio_phy_regs.h"
> diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c
> b/drivers/gpu/drm/i915/gvt/fb_decoder.c
> index f9f7ef131371..1b009543d9a2 100644
> --- a/drivers/gpu/drm/i915/gvt/fb_decoder.c
> +++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
> @@ -39,6 +39,7 @@
> #include "i915_drv.h"
> #include "i915_pvinfo.h"
> #include "i915_reg.h"
> +#include "display/intel_display_regs.h"
>
> #include "display/i9xx_plane_regs.h"
> #include "display/intel_cursor_regs.h"
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c
> b/drivers/gpu/drm/i915/gvt/handlers.c
> index e6e9010462e3..6ef1100b5917 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -40,6 +40,7 @@
>
> #include "i915_drv.h"
> #include "i915_reg.h"
> +#include "display/intel_display_regs.h"
> #include "gvt.h"
> #include "i915_pvinfo.h"
> #include "intel_mchbar_regs.h"
> diff --git a/drivers/gpu/drm/i915/gvt/interrupt.c
> b/drivers/gpu/drm/i915/gvt/interrupt.c
> index 336d079c4207..a956da68e6bd 100644
> --- a/drivers/gpu/drm/i915/gvt/interrupt.c
> +++ b/drivers/gpu/drm/i915/gvt/interrupt.c
> @@ -33,6 +33,7 @@
>
> #include "i915_drv.h"
> #include "i915_reg.h"
> +#include "display/intel_display_regs.h"
> #include "gvt.h"
> #include "trace.h"
>
> diff --git a/drivers/gpu/drm/i915/gvt/mmio.c
> b/drivers/gpu/drm/i915/gvt/mmio.c
> index e16e0d4c9534..da1135fa7cda 100644
> --- a/drivers/gpu/drm/i915/gvt/mmio.c
> +++ b/drivers/gpu/drm/i915/gvt/mmio.c
> @@ -36,6 +36,7 @@
> #include <linux/vmalloc.h>
> #include "i915_drv.h"
> #include "i915_reg.h"
> +#include "display/intel_display_regs.h"
> #include "gvt.h"
>
> #include "display/bxt_dpio_phy_regs.h"
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 88c46a7c948f..7ae9dc2970cd 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -144,10 +144,6 @@
> #define GEN6_STOLEN_RESERVED_ENABLE (1 << 0)
> #define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL <<
> 20)
>
> -#define _GEN7_PIPEA_DE_LOAD_SL 0x70068
> -#define _GEN7_PIPEB_DE_LOAD_SL 0x71068
> -#define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe,
> _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
> -
> /*
> * Reset registers
> */
> @@ -187,46 +183,6 @@
> /* DPIO registers */
> #define DPIO_DEVFN 0
>
> -#define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110)
> -#define DPIO_MODSEL1 (1 << 3) /* if ref clk b == 27 */
> -#define DPIO_MODSEL0 (1 << 2) /* if ref clk a == 27 */
> -#define DPIO_SFR_BYPASS (1 << 1)
> -#define DPIO_CMNRST (1 << 0)
> -
> -#define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090)
> -#define MIPIO_RST_CTRL (1 << 2)
> -
> -#define _BXT_PHY_CTL_DDI_A 0x64C00
> -#define _BXT_PHY_CTL_DDI_B 0x64C10
> -#define _BXT_PHY_CTL_DDI_C 0x64C20
> -#define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10)
> -#define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9)
> -#define BXT_PHY_LANE_ENABLED (1 << 8)
> -#define BXT_PHY_CTL(port) _MMIO_PORT(port,
> _BXT_PHY_CTL_DDI_A, \
> -
> _BXT_PHY_CTL_DDI_B)
> -
> -#define _PHY_CTL_FAMILY_DDI 0x64C90
> -#define _PHY_CTL_FAMILY_EDP 0x64C80
> -#define _PHY_CTL_FAMILY_DDI_C 0x64CA0
> -#define COMMON_RESET_DIS (1 << 31)
> -#define BXT_PHY_CTL_FAMILY(phy)
> \
> - _MMIO(_PICK_EVEN_2RANGES(phy, 1,
> \
> - _PHY_CTL_FAMILY_DDI,
> _PHY_CTL_FAMILY_DDI, \
> - _PHY_CTL_FAMILY_EDP,
> _PHY_CTL_FAMILY_DDI_C))
> -
> -/* UAIMI scratch pad register 1 */
> -#define UAIMI_SPR1 _MMIO(0x4F074)
> -/* SKL VccIO mask */
> -#define SKL_VCCIO_MASK 0x1
> -/* SKL balance leg register */
> -#define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C)
> -/* I_boost values */
> -#define BALANCE_LEG_SHIFT(port) (8 + 3 * (port))
> -#define BALANCE_LEG_MASK(port) (7 << (8 + 3 * (port)))
> -/* Balance leg disable bits */
> -#define BALANCE_LEG_DISABLE_SHIFT 23
> -#define BALANCE_LEG_DISABLE(port) (1 << (23 + (port)))
> -
> /*
> * Fence registers
> * [0-7] @ 0x2000 gen2,gen3
> @@ -372,16 +328,6 @@
> #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070)
> #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074)
>
> -#define ILK_GTT_FAULT _MMIO(0x44040) /* ilk/snb */
> -#define GTT_FAULT_INVALID_GTT_PTE (1 << 7)
> -#define GTT_FAULT_INVALID_PTE_DATA (1 << 6)
> -#define GTT_FAULT_CURSOR_B_FAULT (1 << 5)
> -#define GTT_FAULT_CURSOR_A_FAULT (1 << 4)
> -#define GTT_FAULT_SPRITE_B_FAULT (1 << 3)
> -#define GTT_FAULT_SPRITE_A_FAULT (1 << 2)
> -#define GTT_FAULT_PRIMARY_B_FAULT (1 << 1)
> -#define GTT_FAULT_PRIMARY_A_FAULT (1 << 0)
> -
> #define GEN7_ERR_INT _MMIO(0x44040)
> #define ERR_INT_POISON (1 << 31)
> #define ERR_INT_INVALID_GTT_PTE (1 << 29)
> @@ -458,10 +404,6 @@
> #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)
> #define VLV_PCBR_ADDR_SHIFT 12
>
> -#define VLV_IRQ_REGS I915_IRQ_REGS(VLV_IMR, \
> - VLV_IER, \
> - VLV_IIR)
> -
> #define DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B
> only */
> #define EIR _MMIO(0x20b0)
> #define EMR _MMIO(0x20b4)
> @@ -475,16 +417,6 @@
>
> #define GEN2_ERROR_REGS I915_ERROR_REGS(EMR, EIR)
>
> -#define VLV_EIR _MMIO(VLV_DISPLAY_BASE + 0x20b0)
> -#define VLV_EMR _MMIO(VLV_DISPLAY_BASE + 0x20b4)
> -#define VLV_ESR _MMIO(VLV_DISPLAY_BASE + 0x20b8)
> -#define VLV_ERROR_GUNIT_TLB_DATA (1 << 6)
> -#define VLV_ERROR_GUNIT_TLB_PTE (1 << 5)
> -#define VLV_ERROR_PAGE_TABLE (1 << 4)
> -#define VLV_ERROR_CLAIM (1 << 0)
> -
> -#define VLV_ERROR_REGS I915_ERROR_REGS(VLV_EMR,
> VLV_EIR)
> -
> #define INSTPM _MMIO(0x20c0)
> #define INSTPM_SELF_EN (1 << 12) /* 915GM only */
> #define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending
> interrupts
> @@ -509,23 +441,6 @@
> #define LM_FIFO_WATERMARK 0x0000001F
> #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */
>
> -#define _MBUS_ABOX0_CTL 0x45038
> -#define _MBUS_ABOX1_CTL 0x45048
> -#define _MBUS_ABOX2_CTL 0x4504C
> -#define MBUS_ABOX_CTL(x)
> \
> - _MMIO(_PICK_EVEN_2RANGES(x, 2,
> \
> - _MBUS_ABOX0_CTL, _MBUS_ABOX1_CTL,
> \
> - _MBUS_ABOX2_CTL, _MBUS_ABOX2_CTL))
> -
> -#define MBUS_ABOX_BW_CREDIT_MASK (3 << 20)
> -#define MBUS_ABOX_BW_CREDIT(x) ((x) << 20)
> -#define MBUS_ABOX_B_CREDIT_MASK (0xF << 16)
> -#define MBUS_ABOX_B_CREDIT(x) ((x) << 16)
> -#define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8)
> -#define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8)
> -#define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0)
> -#define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0)
> -
> /*
> * Make render/texture TLB fetches lower priority than associated data
> * fetches. This is not turned on by default.
> @@ -700,173 +615,6 @@
> #define IVB_SPR_STRETCH_MAX_X2
> REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2)
> #define IVB_SPR_STRETCH_MAX_X1
> REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3)
>
> -#define IPS_CTL _MMIO(0x43408)
> -#define IPS_ENABLE REG_BIT(31)
> -#define IPS_FALSE_COLOR REG_BIT(4)
> -
> -/*
> - * Clock control & power management
> - */
> -#define _DPLL_A 0x6014
> -#define _DPLL_B 0x6018
> -#define _CHV_DPLL_C 0x6030
> -#define DPLL(dev_priv, pipe)
> _MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \
> - (pipe), _DPLL_A, _DPLL_B,
> _CHV_DPLL_C)
> -
> -#define VGA0 _MMIO(0x6000)
> -#define VGA1 _MMIO(0x6004)
> -#define VGA_PD _MMIO(0x6010)
> -#define VGA0_PD_P2_DIV_4 (1 << 7)
> -#define VGA0_PD_P1_DIV_2 (1 << 5)
> -#define VGA0_PD_P1_SHIFT 0
> -#define VGA0_PD_P1_MASK (0x1f << 0)
> -#define VGA1_PD_P2_DIV_4 (1 << 15)
> -#define VGA1_PD_P1_DIV_2 (1 << 13)
> -#define VGA1_PD_P1_SHIFT 8
> -#define VGA1_PD_P1_MASK (0x1f << 8)
> -#define DPLL_VCO_ENABLE (1 << 31)
> -#define DPLL_SDVO_HIGH_SPEED (1 << 30)
> -#define DPLL_DVO_2X_MODE (1 << 30)
> -#define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
> -#define DPLL_SYNCLOCK_ENABLE (1 << 29)
> -#define DPLL_REF_CLK_ENABLE_VLV (1 << 29)
> -#define DPLL_VGA_MODE_DIS (1 << 28)
> -#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
> -#define DPLLB_MODE_LVDS (2 << 26) /* i915 */
> -#define DPLL_MODE_MASK (3 << 26)
> -#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
> -#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
> -#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
> -#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
> -#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
> -#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
> -#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /*
> Pineview */
> -#define DPLL_LOCK_VLV (1 << 15)
> -#define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14)
> -#define DPLL_INTEGRATED_REF_CLK_VLV (1 << 13)
> -#define DPLL_SSC_REF_CLK_CHV (1 << 13)
> -#define DPLL_PORTC_READY_MASK (0xf << 4)
> -#define DPLL_PORTB_READY_MASK (0xf)
> -
> -#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
> -
> -/* Additional CHV pll/phy registers */
> -#define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE +
> 0x6240)
> -#define DPLL_PORTD_READY_MASK (0xf)
> -#define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
> -#define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2 * (phy) + (ch) +
> 27))
> -#define PHY_LDO_DELAY_0NS 0x0
> -#define PHY_LDO_DELAY_200NS 0x1
> -#define PHY_LDO_DELAY_600NS 0x2
> -#define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2 * (phy) +
> 23))
> -#define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 *
> (phy) + 4 * (ch) + 11))
> -#define PHY_CH_SU_PSR 0x1
> -#define PHY_CH_DEEP_PSR 0x7
> -#define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6 * (phy) +
> 3 * (ch) + 2))
> -#define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))
> -#define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
> -#define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1
> << 30))
> -#define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 *
> (ch))))
> -#define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 *
> (ch) + (spline))))
> -
> -/*
> - * The i830 generation, in LVDS mode, defines P1 as the bit number set within
> - * this field (only one bit may be set).
> - */
> -#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
> -#define DPLL_FPA01_P1_POST_DIV_SHIFT 16
> -#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
> -/* i830, required in DVO non-gang */
> -#define PLL_P2_DIVIDE_BY_4 (1 << 23)
> -#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
> -#define PLL_REF_INPUT_DREFCLK (0 << 13)
> -#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
> -#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
> -#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
> -#define PLL_REF_INPUT_MASK (3 << 13)
> -#define PLL_LOAD_PULSE_PHASE_SHIFT 9
> -/* Ironlake */
> -# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
> -# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
> -# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9)
> -# define DPLL_FPA1_P1_POST_DIV_SHIFT 0
> -# define DPLL_FPA1_P1_POST_DIV_MASK 0xff
> -
> -/*
> - * Parallel to Serial Load Pulse phase selection.
> - * Selects the phase for the 10X DPLL clock for the PCIe
> - * digital display port. The range is 4 to 13; 10 or more
> - * is just a flip delay. The default is 6
> - */
> -#define PLL_LOAD_PULSE_PHASE_MASK (0xf <<
> PLL_LOAD_PULSE_PHASE_SHIFT)
> -#define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
> -/*
> - * SDVO multiplier for 945G/GM. Not used on 965.
> - */
> -#define SDVO_MULTIPLIER_MASK 0x000000ff
> -#define SDVO_MULTIPLIER_SHIFT_HIRES 4
> -#define SDVO_MULTIPLIER_SHIFT_VGA 0
> -
> -#define _DPLL_A_MD 0x601c
> -#define _DPLL_B_MD 0x6020
> -#define _CHV_DPLL_C_MD 0x603c
> -#define DPLL_MD(dev_priv, pipe)
> _MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \
> - (pipe), _DPLL_A_MD,
> _DPLL_B_MD, _CHV_DPLL_C_MD)
> -
> -/*
> - * UDI pixel divider, controlling how many pixels are stuffed into a packet.
> - *
> - * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
> - */
> -#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
> -#define DPLL_MD_UDI_DIVIDER_SHIFT 24
> -/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
> -#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
> -#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
> -/*
> - * SDVO/UDI pixel multiplier.
> - *
> - * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
> - * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
> - * modes, the bus rate would be below the limits, so SDVO allows for stuffing
> - * dummy bytes in the datastream at an increased clock rate, with both sides
> of
> - * the link knowing how many bytes are fill.
> - *
> - * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
> - * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
> - * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
> - * through an SDVO command.
> - *
> - * This register field has values of multiplication factor minus 1, with
> - * a maximum multiplier of 5 for SDVO.
> - */
> -#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
> -#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
> -/*
> - * SDVO/UDI pixel multiplier for VGA, same as
> DPLL_MD_UDI_MULTIPLIER_MASK.
> - * This best be set to the default value (3) or the CRT won't work. No,
> - * I don't entirely understand what this does...
> - */
> -#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
> -#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
> -
> -#define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024)
> -
> -#define _FPA0 0x6040
> -#define _FPA1 0x6044
> -#define _FPB0 0x6048
> -#define _FPB1 0x604c
> -#define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0)
> -#define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1)
> -#define FP_N_DIV_MASK 0x003f0000
> -#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
> -#define FP_N_DIV_SHIFT 16
> -#define FP_M1_DIV_MASK 0x00003f00
> -#define FP_M1_DIV_SHIFT 8
> -#define FP_M2_DIV_MASK 0x0000003f
> -#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
> -#define FP_M2_DIV_SHIFT 0
> -
> #define DPLL_TEST _MMIO(0x606c)
> #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
> #define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
> @@ -1000,27 +748,6 @@
> #define RAMCLK_GATE_D _MMIO(0x6210) /* CRL
> only */
> #define DEUC _MMIO(0x6214) /* CRL only */
>
> -#define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500)
> -#define FW_CSPWRDWNEN (1 << 15)
> -
> -#define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)
> -
> -#define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508)
> -#define CDCLK_FREQ_SHIFT 4
> -#define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT)
> -#define CZCLK_FREQ_MASK 0xf
> -
> -#define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C)
> -#define PFI_CREDIT_63 (9 << 28) /* chv only */
> -#define PFI_CREDIT_31 (8 << 28) /* chv only */
> -#define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */
> -#define PFI_CREDIT_RESEND (1 << 27)
> -#define VGA_FAST_MODE_DISABLE (1 << 14)
> -
> -#define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510)
> -
> -#define PEG_BAND_GAP_DATA _MMIO(0x14d68)
> -
> #define BXT_RP_STATE_CAP _MMIO(0x138170)
> #define GEN9_RP_STATE_LIMITS _MMIO(0x138148)
>
> @@ -1050,19 +777,6 @@
> #define VLV_CLK_CTL2 _MMIO(0x101104)
> #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
>
> -/*
> - * Overlay regs
> - */
> -#define OVADD _MMIO(0x30000)
> -#define DOVSTA _MMIO(0x30008)
> -#define OC_BUF (0x3 << 20)
> -#define OGAMC5 _MMIO(0x30010)
> -#define OGAMC4 _MMIO(0x30014)
> -#define OGAMC3 _MMIO(0x30018)
> -#define OGAMC2 _MMIO(0x3001c)
> -#define OGAMC1 _MMIO(0x30020)
> -#define OGAMC0 _MMIO(0x30024)
> -
> /*
> * GEN9 clock gating regs
> */
> @@ -1077,482 +791,6 @@
> #define TGL_VRH_GATING_DIS REG_BIT(31)
> #define DPT_GATING_DIS REG_BIT(22)
>
> -#define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
> -#define BXT_GMBUS_GATING_DIS (1 << 14)
> -#define DG2_DPFC_GATING_DIS REG_BIT(31)
> -
> -#define GEN9_CLKGATE_DIS_5 _MMIO(0x46540)
> -#define DPCE_GATING_DIS REG_BIT(17)
> -
> -#define _CLKGATE_DIS_PSL_A 0x46520
> -#define _CLKGATE_DIS_PSL_B 0x46524
> -#define _CLKGATE_DIS_PSL_C 0x46528
> -#define DUPS1_GATING_DIS (1 << 15)
> -#define DUPS2_GATING_DIS (1 << 19)
> -#define DUPS3_GATING_DIS (1 << 23)
> -#define CURSOR_GATING_DIS REG_BIT(28)
> -#define DPF_GATING_DIS (1 << 10)
> -#define DPF_RAM_GATING_DIS (1 << 9)
> -#define DPFR_GATING_DIS (1 << 8)
> -
> -#define CLKGATE_DIS_PSL(pipe) \
> - _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B)
> -
> -#define _CLKGATE_DIS_PSL_EXT_A 0x4654C
> -#define _CLKGATE_DIS_PSL_EXT_B 0x46550
> -#define PIPEDMC_GATING_DIS REG_BIT(12)
> -
> -#define CLKGATE_DIS_PSL_EXT(pipe) \
> - _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_EXT_A,
> _CLKGATE_DIS_PSL_EXT_B)
> -
> -/*
> - * Display engine regs
> - */
> -/* Pipe/transcoder A timing regs */
> -#define _TRANS_HTOTAL_A 0x60000
> -#define _TRANS_HTOTAL_B 0x61000
> -#define TRANS_HTOTAL(dev_priv, trans) _MMIO_TRANS2(dev_priv,
> (trans), _TRANS_HTOTAL_A)
> -#define HTOTAL_MASK REG_GENMASK(31, 16)
> -#define HTOTAL(htotal) REG_FIELD_PREP(HTOTAL_MASK,
> (htotal))
> -#define HACTIVE_MASK REG_GENMASK(15, 0)
> -#define HACTIVE(hdisplay) REG_FIELD_PREP(HACTIVE_MASK,
> (hdisplay))
> -
> -#define _TRANS_HBLANK_A 0x60004
> -#define _TRANS_HBLANK_B 0x61004
> -#define TRANS_HBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv,
> (trans), _TRANS_HBLANK_A)
> -#define HBLANK_END_MASK REG_GENMASK(31, 16)
> -#define HBLANK_END(hblank_end)
> REG_FIELD_PREP(HBLANK_END_MASK, (hblank_end))
> -#define HBLANK_START_MASK REG_GENMASK(15, 0)
> -#define HBLANK_START(hblank_start)
> REG_FIELD_PREP(HBLANK_START_MASK, (hblank_start))
> -
> -#define _TRANS_HSYNC_A 0x60008
> -#define _TRANS_HSYNC_B 0x61008
> -#define TRANS_HSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans),
> _TRANS_HSYNC_A)
> -#define HSYNC_END_MASK REG_GENMASK(31, 16)
> -#define HSYNC_END(hsync_end)
> REG_FIELD_PREP(HSYNC_END_MASK, (hsync_end))
> -#define HSYNC_START_MASK REG_GENMASK(15, 0)
> -#define HSYNC_START(hsync_start)
> REG_FIELD_PREP(HSYNC_START_MASK, (hsync_start))
> -
> -#define _TRANS_VTOTAL_A 0x6000c
> -#define _TRANS_VTOTAL_B 0x6100c
> -#define TRANS_VTOTAL(dev_priv, trans) _MMIO_TRANS2(dev_priv,
> (trans), _TRANS_VTOTAL_A)
> -#define VTOTAL_MASK REG_GENMASK(31, 16)
> -#define VTOTAL(vtotal) REG_FIELD_PREP(VTOTAL_MASK,
> (vtotal))
> -#define VACTIVE_MASK REG_GENMASK(15, 0)
> -#define VACTIVE(vdisplay) REG_FIELD_PREP(VACTIVE_MASK,
> (vdisplay))
> -
> -#define _TRANS_VBLANK_A 0x60010
> -#define _TRANS_VBLANK_B 0x61010
> -#define TRANS_VBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv,
> (trans), _TRANS_VBLANK_A)
> -#define VBLANK_END_MASK REG_GENMASK(31, 16)
> -#define VBLANK_END(vblank_end)
> REG_FIELD_PREP(VBLANK_END_MASK, (vblank_end))
> -#define VBLANK_START_MASK REG_GENMASK(15, 0)
> -#define VBLANK_START(vblank_start)
> REG_FIELD_PREP(VBLANK_START_MASK, (vblank_start))
> -
> -#define _TRANS_VSYNC_A 0x60014
> -#define _TRANS_VSYNC_B 0x61014
> -#define TRANS_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans),
> _TRANS_VSYNC_A)
> -#define VSYNC_END_MASK REG_GENMASK(31, 16)
> -#define VSYNC_END(vsync_end)
> REG_FIELD_PREP(VSYNC_END_MASK, (vsync_end))
> -#define VSYNC_START_MASK REG_GENMASK(15, 0)
> -#define VSYNC_START(vsync_start)
> REG_FIELD_PREP(VSYNC_START_MASK, (vsync_start))
> -
> -#define _PIPEASRC 0x6001c
> -#define _PIPEBSRC 0x6101c
> -#define PIPESRC(dev_priv, pipe) _MMIO_TRANS2(dev_priv,
> (pipe), _PIPEASRC)
> -#define PIPESRC_WIDTH_MASK REG_GENMASK(31, 16)
> -#define PIPESRC_WIDTH(w) REG_FIELD_PREP(PIPESRC_WIDTH_MASK, (w))
> -#define PIPESRC_HEIGHT_MASK REG_GENMASK(15, 0)
> -#define PIPESRC_HEIGHT(h) REG_FIELD_PREP(PIPESRC_HEIGHT_MASK, (h))
> -
> -#define _BCLRPAT_A 0x60020
> -#define _BCLRPAT_B 0x61020
> -#define BCLRPAT(dev_priv, trans) _MMIO_TRANS2(dev_priv,
> (trans), _BCLRPAT_A)
> -
> -#define _TRANS_VSYNCSHIFT_A 0x60028
> -#define _TRANS_VSYNCSHIFT_B 0x61028
> -#define TRANS_VSYNCSHIFT(dev_priv, trans) _MMIO_TRANS2(dev_priv,
> (trans), _TRANS_VSYNCSHIFT_A)
> -
> -#define _TRANS_MULT_A 0x6002c
> -#define _TRANS_MULT_B 0x6102c
> -#define TRANS_MULT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans),
> _TRANS_MULT_A)
> -
> -/* Hotplug control (945+ only) */
> -#define PORT_HOTPLUG_EN(dev_priv)
> _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
> -#define PORTB_HOTPLUG_INT_EN (1 << 29)
> -#define PORTC_HOTPLUG_INT_EN (1 << 28)
> -#define PORTD_HOTPLUG_INT_EN (1 << 27)
> -#define SDVOB_HOTPLUG_INT_EN (1 << 26)
> -#define SDVOC_HOTPLUG_INT_EN (1 << 25)
> -#define TV_HOTPLUG_INT_EN (1 << 18)
> -#define CRT_HOTPLUG_INT_EN (1 << 9)
> -#define HOTPLUG_INT_EN_MASK
> (PORTB_HOTPLUG_INT_EN | \
> - PORTC_HOTPLUG_INT_EN | \
> - PORTD_HOTPLUG_INT_EN | \
> - SDVOC_HOTPLUG_INT_EN | \
> - SDVOB_HOTPLUG_INT_EN | \
> - CRT_HOTPLUG_INT_EN)
> -#define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
> -#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
> -/* must use period 64 on GM45 according to docs */
> -#define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
> -#define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
> -#define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
> -#define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
> -#define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
> -#define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
> -#define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
> -#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
> -#define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
> -#define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
> -#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
> -#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
> -
> -#define PORT_HOTPLUG_STAT(dev_priv)
> _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114)
> -/* HDMI/DP bits are g4x+ */
> -#define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27)
> -#define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28)
> -#define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29)
> -#define PORTD_HOTPLUG_INT_STATUS (3 << 21)
> -#define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21)
> -#define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21)
> -#define PORTC_HOTPLUG_INT_STATUS (3 << 19)
> -#define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19)
> -#define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19)
> -#define PORTB_HOTPLUG_INT_STATUS (3 << 17)
> -#define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17)
> -#define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17)
> -/* CRT/TV common between gen3+ */
> -#define CRT_HOTPLUG_INT_STATUS (1 << 11)
> -#define TV_HOTPLUG_INT_STATUS (1 << 10)
> -#define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
> -#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
> -#define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
> -#define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
> -#define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6)
> -#define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5)
> -#define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4)
> -#define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4)
> -
> -/* SDVO is different across gen3/4 */
> -#define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
> -#define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
> -/*
> - * Bspec seems to be seriously misleaded about the SDVO hpd bits on
> i965g/gm,
> - * since reality corrobates that they're the same as on gen3. But keep these
> - * bits here (and the comment!) to help any other lost wanderers back onto
> the
> - * right tracks.
> - */
> -#define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
> -#define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
> -#define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
> -#define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
> -#define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS |
> \
> -
> SDVOB_HOTPLUG_INT_STATUS_G4X | \
> -
> SDVOC_HOTPLUG_INT_STATUS_G4X | \
> -
> PORTB_HOTPLUG_INT_STATUS | \
> -
> PORTC_HOTPLUG_INT_STATUS | \
> -
> PORTD_HOTPLUG_INT_STATUS)
> -
> -#define HOTPLUG_INT_STATUS_I915
> (CRT_HOTPLUG_INT_STATUS | \
> -
> SDVOB_HOTPLUG_INT_STATUS_I915 | \
> -
> SDVOC_HOTPLUG_INT_STATUS_I915 | \
> -
> PORTB_HOTPLUG_INT_STATUS | \
> -
> PORTC_HOTPLUG_INT_STATUS | \
> -
> PORTD_HOTPLUG_INT_STATUS)
> -
> -/* SDVO and HDMI port control.
> - * The same register may be used for SDVO or HDMI */
> -#define _GEN3_SDVOB 0x61140
> -#define _GEN3_SDVOC 0x61160
> -#define GEN3_SDVOB _MMIO(_GEN3_SDVOB)
> -#define GEN3_SDVOC _MMIO(_GEN3_SDVOC)
> -#define GEN4_HDMIB GEN3_SDVOB
> -#define GEN4_HDMIC GEN3_SDVOC
> -#define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140)
> -#define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160)
> -#define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C)
> -#define PCH_SDVOB _MMIO(0xe1140)
> -#define PCH_HDMIB PCH_SDVOB
> -#define PCH_HDMIC _MMIO(0xe1150)
> -#define PCH_HDMID _MMIO(0xe1160)
> -
> -#define PORT_DFT_I9XX _MMIO(0x61150)
> -#define DC_BALANCE_RESET (1 << 25)
> -#define PORT_DFT2_G4X(dev_priv)
> _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154)
> -#define DC_BALANCE_RESET_VLV (1 << 31)
> -#define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0))
> -#define PIPE_C_SCRAMBLE_RESET REG_BIT(14) /* chv */
> -#define PIPE_B_SCRAMBLE_RESET REG_BIT(1)
> -#define PIPE_A_SCRAMBLE_RESET REG_BIT(0)
> -
> -/* Gen 3 SDVO bits: */
> -#define SDVO_ENABLE (1 << 31)
> -#define SDVO_PIPE_SEL_SHIFT 30
> -#define SDVO_PIPE_SEL_MASK (1 << 30)
> -#define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
> -#define SDVO_STALL_SELECT (1 << 29)
> -#define SDVO_INTERRUPT_ENABLE (1 << 26)
> -/*
> - * 915G/GM SDVO pixel multiplier.
> - * Programmed value is multiplier - 1, up to 5x.
> - * \sa DPLL_MD_UDI_MULTIPLIER_MASK
> - */
> -#define SDVO_PORT_MULTIPLY_MASK (7 << 23)
> -#define SDVO_PORT_MULTIPLY_SHIFT 23
> -#define SDVO_PHASE_SELECT_MASK (15 << 19)
> -#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
> -#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
> -#define SDVOC_GANG_MODE (1 << 16) /* Port C only */
> -#define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only
> */
> -#define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */
> -#define SDVO_DETECTED (1 << 2)
> -/* Bits to be preserved when writing */
> -#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
> - SDVO_INTERRUPT_ENABLE)
> -#define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
> -
> -/* Gen 4 SDVO/HDMI bits: */
> -#define SDVO_COLOR_FORMAT_8bpc (0 << 26)
> -#define SDVO_COLOR_FORMAT_MASK (7 << 26)
> -#define SDVO_ENCODING_SDVO (0 << 10)
> -#define SDVO_ENCODING_HDMI (2 << 10)
> -#define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only
> */
> -#define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only
> */
> -#define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only
> */
> -#define HDMI_AUDIO_ENABLE (1 << 6) /* HDMI only
> */
> -/* VSYNC/HSYNC bits new with 965, default is to be set */
> -#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
> -#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
> -
> -/* Gen 5 (IBX) SDVO/HDMI bits: */
> -#define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only
> */
> -#define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only
> */
> -
> -/* Gen 6 (CPT) SDVO/HDMI bits: */
> -#define SDVO_PIPE_SEL_SHIFT_CPT 29
> -#define SDVO_PIPE_SEL_MASK_CPT (3 << 29)
> -#define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
> -
> -/* CHV SDVO/HDMI bits: */
> -#define SDVO_PIPE_SEL_SHIFT_CHV 24
> -#define SDVO_PIPE_SEL_MASK_CHV (3 << 24)
> -#define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24)
> -
> -/* Video Data Island Packet control */
> -#define VIDEO_DIP_DATA _MMIO(0x61178)
> -/* Read the description of VIDEO_DIP_DATA (before Haswell) or
> VIDEO_DIP_ECC
> - * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to
> each byte
> - * of the infoframe structure specified by CEA-861. */
> -#define VIDEO_DIP_DATA_SIZE 32
> -#define VIDEO_DIP_ASYNC_DATA_SIZE 36
> -#define VIDEO_DIP_GMP_DATA_SIZE 36
> -#define VIDEO_DIP_VSC_DATA_SIZE 36
> -#define VIDEO_DIP_PPS_DATA_SIZE 132
> -#define VIDEO_DIP_CTL _MMIO(0x61170)
> -/* Pre HSW: */
> -#define VIDEO_DIP_ENABLE (1 << 31)
> -#define VIDEO_DIP_PORT(port) ((port) << 29)
> -#define VIDEO_DIP_PORT_MASK (3 << 29)
> -#define VIDEO_DIP_ENABLE_GCP (1 << 25) /* ilk+ */
> -#define VIDEO_DIP_ENABLE_AVI (1 << 21)
> -#define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
> -#define VIDEO_DIP_ENABLE_GAMUT (4 << 21) /* ilk+ */
> -#define VIDEO_DIP_ENABLE_SPD (8 << 21)
> -#define VIDEO_DIP_SELECT_AVI (0 << 19)
> -#define VIDEO_DIP_SELECT_VENDOR (1 << 19)
> -#define VIDEO_DIP_SELECT_GAMUT (2 << 19)
> -#define VIDEO_DIP_SELECT_SPD (3 << 19)
> -#define VIDEO_DIP_SELECT_MASK (3 << 19)
> -#define VIDEO_DIP_FREQ_ONCE (0 << 16)
> -#define VIDEO_DIP_FREQ_VSYNC (1 << 16)
> -#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
> -#define VIDEO_DIP_FREQ_MASK (3 << 16)
> -/* HSW and later: */
> -#define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28)
> -#define PSR_VSC_BIT_7_SET (1 << 27)
> -#define VSC_SELECT_MASK (0x3 << 25)
> -#define VSC_SELECT_SHIFT 25
> -#define VSC_DIP_HW_HEA_DATA (0 << 25)
> -#define VSC_DIP_HW_HEA_SW_DATA (1 << 25)
> -#define VSC_DIP_HW_DATA_SW_HEA (2 << 25)
> -#define VSC_DIP_SW_HEA_DATA (3 << 25)
> -#define VDIP_ENABLE_PPS (1 << 24)
> -#define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
> -#define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
> -#define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
> -#define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
> -#define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
> -#define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
> -/* ADL and later: */
> -#define VIDEO_DIP_ENABLE_AS_ADL REG_BIT(23)
> -
> -#define PCH_GTC_CTL _MMIO(0xe7000)
> -#define PCH_GTC_ENABLE (1 << 31)
> -
> -/* Display Port */
> -#define DP_A _MMIO(0x64000) /* eDP */
> -#define DP_B _MMIO(0x64100)
> -#define DP_C _MMIO(0x64200)
> -#define DP_D _MMIO(0x64300)
> -#define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100)
> -#define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200)
> -#define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300)
> -#define DP_PORT_EN REG_BIT(31)
> -#define DP_PIPE_SEL_MASK REG_GENMASK(30, 30)
> -#define DP_PIPE_SEL(pipe) REG_FIELD_PREP(DP_PIPE_SEL_MASK,
> (pipe))
> -#define DP_PIPE_SEL_MASK_IVB REG_GENMASK(30, 29)
> -#define DP_PIPE_SEL_IVB(pipe)
> REG_FIELD_PREP(DP_PIPE_SEL_MASK_IVB, (pipe))
> -#define DP_PIPE_SEL_SHIFT_CHV 16
> -#define DP_PIPE_SEL_MASK_CHV REG_GENMASK(17, 16)
> -#define DP_PIPE_SEL_CHV(pipe)
> REG_FIELD_PREP(DP_PIPE_SEL_MASK_CHV, (pipe))
> -#define DP_LINK_TRAIN_MASK REG_GENMASK(29, 28)
> -#define DP_LINK_TRAIN_PAT_1
> REG_FIELD_PREP(DP_LINK_TRAIN_MASK, 0)
> -#define DP_LINK_TRAIN_PAT_2
> REG_FIELD_PREP(DP_LINK_TRAIN_MASK, 1)
> -#define DP_LINK_TRAIN_PAT_IDLE
> REG_FIELD_PREP(DP_LINK_TRAIN_MASK, 2)
> -#define DP_LINK_TRAIN_OFF
> REG_FIELD_PREP(DP_LINK_TRAIN_MASK, 3)
> -#define DP_LINK_TRAIN_MASK_CPT REG_GENMASK(10, 8)
> -#define DP_LINK_TRAIN_PAT_1_CPT
> REG_FIELD_PREP(DP_LINK_TRAIN_MASK_CPT, 0)
> -#define DP_LINK_TRAIN_PAT_2_CPT
> REG_FIELD_PREP(DP_LINK_TRAIN_MASK_CPT, 1)
> -#define DP_LINK_TRAIN_PAT_IDLE_CPT
> REG_FIELD_PREP(DP_LINK_TRAIN_MASK_CPT, 2)
> -#define DP_LINK_TRAIN_OFF_CPT
> REG_FIELD_PREP(DP_LINK_TRAIN_MASK_CPT, 3)
> -#define DP_VOLTAGE_MASK REG_GENMASK(27, 25)
> -#define DP_VOLTAGE_0_4 REG_FIELD_PREP(DP_VOLTAGE_MASK,
> 0)
> -#define DP_VOLTAGE_0_6 REG_FIELD_PREP(DP_VOLTAGE_MASK,
> 1)
> -#define DP_VOLTAGE_0_8 REG_FIELD_PREP(DP_VOLTAGE_MASK,
> 2)
> -#define DP_VOLTAGE_1_2 REG_FIELD_PREP(DP_VOLTAGE_MASK,
> 3)
> -#define DP_PRE_EMPHASIS_MASK REG_GENMASK(24, 22)
> -#define DP_PRE_EMPHASIS_0
> REG_FIELD_PREP(DP_PRE_EMPHASIS_MASK, 0)
> -#define DP_PRE_EMPHASIS_3_5
> REG_FIELD_PREP(DP_PRE_EMPHASIS_MASK, 1)
> -#define DP_PRE_EMPHASIS_6
> REG_FIELD_PREP(DP_PRE_EMPHASIS_MASK, 2)
> -#define DP_PRE_EMPHASIS_9_5
> REG_FIELD_PREP(DP_PRE_EMPHASIS_MASK, 3)
> -#define DP_PORT_WIDTH_MASK REG_GENMASK(21, 19)
> -#define DP_PORT_WIDTH(width)
> REG_FIELD_PREP(DP_PORT_WIDTH_MASK, (width) - 1)
> -#define DP_ENHANCED_FRAMING REG_BIT(18)
> -#define EDP_PLL_FREQ_MASK REG_GENMASK(17, 16)
> -#define EDP_PLL_FREQ_270MHZ
> REG_FIELD_PREP(EDP_PLL_FREQ_MASK, 0)
> -#define EDP_PLL_FREQ_162MHZ
> REG_FIELD_PREP(EDP_PLL_FREQ_MASK, 1)
> -#define DP_PORT_REVERSAL REG_BIT(15)
> -#define EDP_PLL_ENABLE REG_BIT(14)
> -#define DP_CLOCK_OUTPUT_ENABLE REG_BIT(13)
> -#define DP_SCRAMBLING_DISABLE REG_BIT(12)
> -#define DP_SCRAMBLING_DISABLE_ILK REG_BIT(7)
> -#define DP_COLOR_RANGE_16_235 REG_BIT(8)
> -#define DP_AUDIO_OUTPUT_ENABLE REG_BIT(6)
> -#define DP_SYNC_VS_HIGH REG_BIT(4)
> -#define DP_SYNC_HS_HIGH REG_BIT(3)
> -#define DP_DETECTED REG_BIT(2)
> -
> -/*
> - * Computing GMCH M and N values for the Display Port link
> - *
> - * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
> - *
> - * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
> - *
> - * The GMCH value is used internally
> - *
> - * bytes_per_pixel is the number of bytes coming out of the plane,
> - * which is after the LUTs, so we want the bytes for our color format.
> - * For our current usage, this is always 3, one byte for R, G and B.
> - */
> -#define _PIPEA_DATA_M_G4X 0x70050
> -#define _PIPEB_DATA_M_G4X 0x71050
> -#define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X,
> _PIPEB_DATA_M_G4X)
> -/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
> -#define TU_SIZE_MASK REG_GENMASK(30, 25)
> -#define TU_SIZE(x) REG_FIELD_PREP(TU_SIZE_MASK, (x) - 1) /*
> default size 64 */
> -#define DATA_LINK_M_N_MASK REG_GENMASK(23, 0)
> -#define DATA_LINK_N_MAX (0x800000)
> -
> -#define _PIPEA_DATA_N_G4X 0x70054
> -#define _PIPEB_DATA_N_G4X 0x71054
> -#define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X,
> _PIPEB_DATA_N_G4X)
> -
> -/*
> - * Computing Link M and N values for the Display Port link
> - *
> - * Link M / N = pixel_clock / ls_clk
> - *
> - * (the DP spec calls pixel_clock the 'strm_clk')
> - *
> - * The Link value is transmitted in the Main Stream
> - * Attributes and VB-ID.
> - */
> -#define _PIPEA_LINK_M_G4X 0x70060
> -#define _PIPEB_LINK_M_G4X 0x71060
> -#define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X,
> _PIPEB_LINK_M_G4X)
> -
> -#define _PIPEA_LINK_N_G4X 0x70064
> -#define _PIPEB_LINK_N_G4X 0x71064
> -#define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X,
> _PIPEB_LINK_N_G4X)
> -
> -/* Pipe A */
> -#define _PIPEADSL 0x70000
> -#define PIPEDSL(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe,
> _PIPEADSL)
> -#define PIPEDSL_CURR_FIELD REG_BIT(31) /* ctg+ */
> -#define PIPEDSL_LINE_MASK REG_GENMASK(19, 0)
> -
> -#define _TRANSACONF 0x70008
> -#define TRANSCONF(dev_priv, trans) _MMIO_PIPE2(dev_priv, (trans),
> _TRANSACONF)
> -#define TRANSCONF_ENABLE REG_BIT(31)
> -#define TRANSCONF_DOUBLE_WIDE REG_BIT(30) /* pre-
> i965 */
> -#define TRANSCONF_STATE_ENABLE REG_BIT(30) /* i965+
> */
> -#define TRANSCONF_DSI_PLL_LOCKED REG_BIT(29) /* vlv &
> pipe A only */
> -#define TRANSCONF_FRAME_START_DELAY_MASK REG_GENMASK(28,
> 27) /* pre-hsw */
> -#define TRANSCONF_FRAME_START_DELAY(x)
> REG_FIELD_PREP(TRANSCONF_FRAME_START_DELAY_MASK, (x)) /*
> pre-hsw: 0-3 */
> -#define TRANSCONF_PIPE_LOCKED REG_BIT(25)
> -#define TRANSCONF_FORCE_BORDER REG_BIT(25)
> -#define TRANSCONF_GAMMA_MODE_MASK_I9XX REG_BIT(24)
> /* gmch */
> -#define TRANSCONF_GAMMA_MODE_MASK_ILK
> REG_GENMASK(25, 24) /* ilk-ivb */
> -#define TRANSCONF_GAMMA_MODE_8BIT
> REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 0)
> -#define TRANSCONF_GAMMA_MODE_10BIT
> REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 1)
> -#define TRANSCONF_GAMMA_MODE_12BIT
> REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-
> ivb */
> -#define TRANSCONF_GAMMA_MODE_SPLIT
> REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 3) /* ivb */
> -#define TRANSCONF_GAMMA_MODE(x)
> REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, (x)) /* pass
> in GAMMA_MODE_MODE_* */
> -#define TRANSCONF_INTERLACE_MASK REG_GENMASK(23,
> 21) /* gen3+ */
> -#define TRANSCONF_INTERLACE_PROGRESSIVE
> REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 0)
> -#define TRANSCONF_INTERLACE_W_SYNC_SHIFT_PANEL
> REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 4) /* gen4 only */
> -#define TRANSCONF_INTERLACE_W_SYNC_SHIFT
> REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 5) /* gen4 only */
> -#define TRANSCONF_INTERLACE_W_FIELD_INDICATION
> REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 6)
> -#define TRANSCONF_INTERLACE_FIELD_0_ONLY
> REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 7) /* gen3 only */
> -/*
> - * ilk+: PF/D=progressive fetch/display, IF/D=interlaced fetch/display,
> - * DBL=power saving pixel doubling, PF-ID* requires panel fitter
> - */
> -#define TRANSCONF_INTERLACE_MASK_ILK REG_GENMASK(23,
> 21) /* ilk+ */
> -#define TRANSCONF_INTERLACE_MASK_HSW REG_GENMASK(22,
> 21) /* hsw+ */
> -#define TRANSCONF_INTERLACE_PF_PD_ILK
> REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 0)
> -#define TRANSCONF_INTERLACE_PF_ID_ILK
> REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 1)
> -#define TRANSCONF_INTERLACE_IF_ID_ILK
> REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 3)
> -#define TRANSCONF_INTERLACE_IF_ID_DBL_ILK
> REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 4) /* ilk/snb
> only */
> -#define TRANSCONF_INTERLACE_PF_ID_DBL_ILK
> REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 5) /* ilk/snb
> only */
> -#define TRANSCONF_REFRESH_RATE_ALT_ILK REG_BIT(20)
> -#define TRANSCONF_MSA_TIMING_DELAY_MASK REG_GENMASK(19,
> 18) /* ilk/snb/ivb */
> -#define TRANSCONF_MSA_TIMING_DELAY(x)
> REG_FIELD_PREP(TRANSCONF_MSA_TIMING_DELAY_MASK, (x))
> -#define TRANSCONF_CXSR_DOWNCLOCK REG_BIT(16)
> -#define TRANSCONF_WGC_ENABLE REG_BIT(15) /* vlv/chv
> only */
> -#define TRANSCONF_REFRESH_RATE_ALT_VLV REG_BIT(14)
> -#define TRANSCONF_COLOR_RANGE_SELECT REG_BIT(13)
> -#define TRANSCONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12,
> 11) /* ilk-ivb */
> -#define TRANSCONF_OUTPUT_COLORSPACE_RGB
> REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-
> ivb */
> -#define TRANSCONF_OUTPUT_COLORSPACE_YUV601
> REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-
> ivb */
> -#define TRANSCONF_OUTPUT_COLORSPACE_YUV709
> REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-
> ivb */
> -#define TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW REG_BIT(11)
> /* hsw only */
> -#define TRANSCONF_BPC_MASK REG_GENMASK(7, 5)
> /* ctg-ivb */
> -#define TRANSCONF_BPC_8
> REG_FIELD_PREP(TRANSCONF_BPC_MASK, 0)
> -#define TRANSCONF_BPC_10
> REG_FIELD_PREP(TRANSCONF_BPC_MASK, 1)
> -#define TRANSCONF_BPC_6
> REG_FIELD_PREP(TRANSCONF_BPC_MASK, 2)
> -#define TRANSCONF_BPC_12
> REG_FIELD_PREP(TRANSCONF_BPC_MASK, 3)
> -#define TRANSCONF_DITHER_EN REG_BIT(4)
> -#define TRANSCONF_DITHER_TYPE_MASK REG_GENMASK(3, 2)
> -#define TRANSCONF_DITHER_TYPE_SP
> REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 0)
> -#define TRANSCONF_DITHER_TYPE_ST1
> REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 1)
> -#define TRANSCONF_DITHER_TYPE_ST2
> REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 2)
> -#define TRANSCONF_DITHER_TYPE_TEMP
> REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 3)
> -#define TRANSCONF_PIXEL_COUNT_SCALING_MASK REG_GENMASK(1, 0)
> -#define TRANSCONF_PIXEL_COUNT_SCALING_X4 1
> -
> #define _PIPEASTAT 0x70024
> #define PIPESTAT(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe,
> _PIPEASTAT)
> #define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31)
> @@ -1604,50 +842,6 @@
> #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000
> #define PIPESTAT_INT_STATUS_MASK 0x0000ffff
>
> -#define _PIPE_ARB_CTL_A 0x70028 /* icl+ */
> -#define PIPE_ARB_CTL(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe,
> _PIPE_ARB_CTL_A)
> -#define PIPE_ARB_USE_PROG_SLOTS REG_BIT(13)
> -
> -#define _PIPE_MISC_A 0x70030
> -#define _PIPE_MISC_B 0x71030
> -#define PIPE_MISC(pipe) _MMIO_PIPE(pipe,
> _PIPE_MISC_A, _PIPE_MISC_B)
> -#define PIPE_MISC_YUV420_ENABLE REG_BIT(27) /* glk+ */
> -#define PIPE_MISC_YUV420_MODE_FULL_BLEND REG_BIT(26) /* glk+ */
> -#define PIPE_MISC_HDR_MODE_PRECISION REG_BIT(23) /* icl+ */
> -#define PIPE_MISC_PSR_MASK_PRIMARY_FLIP REG_BIT(23) /* bdw */
> -#define PIPE_MISC_PSR_MASK_SPRITE_ENABLE REG_BIT(22) /* bdw */
> -#define PIPE_MISC_PSR_MASK_PIPE_REG_WRITE REG_BIT(21) /* skl+ */
> -#define PIPE_MISC_PSR_MASK_CURSOR_MOVE REG_BIT(21) /* bdw */
> -#define PIPE_MISC_PSR_MASK_VBLANK_VSYNC_INT REG_BIT(20)
> -#define PIPE_MISC_OUTPUT_COLORSPACE_YUV REG_BIT(11)
> -#define PIPE_MISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */
> -/*
> - * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with
> - * valid values of: 6, 8, 10 BPC.
> - * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of:
> - * 6, 8, 10, 12 BPC.
> - */
> -#define PIPE_MISC_BPC_MASK REG_GENMASK(7, 5)
> -#define PIPE_MISC_BPC_8
> REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 0)
> -#define PIPE_MISC_BPC_10
> REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 1)
> -#define PIPE_MISC_BPC_6
> REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 2)
> -#define PIPE_MISC_BPC_12_ADLP
> REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 4) /* adlp+ */
> -#define PIPE_MISC_DITHER_ENABLE REG_BIT(4)
> -#define PIPE_MISC_DITHER_TYPE_MASK REG_GENMASK(3, 2)
> -#define PIPE_MISC_DITHER_TYPE_SP
> REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 0)
> -#define PIPE_MISC_DITHER_TYPE_ST1
> REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 1)
> -#define PIPE_MISC_DITHER_TYPE_ST2
> REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 2)
> -#define PIPE_MISC_DITHER_TYPE_TEMP
> REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 3)
> -
> -#define _PIPE_MISC2_A 0x7002C
> -#define _PIPE_MISC2_B 0x7102C
> -#define PIPE_MISC2(pipe) _MMIO_PIPE(pipe, _PIPE_MISC2_A,
> _PIPE_MISC2_B)
> -#define PIPE_MISC2_BUBBLE_COUNTER_MASK REG_GENMASK(31,
> 24)
> -#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN
> REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 80)
> -#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS
> REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 20)
> -#define PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK
> REG_GENMASK(2, 0) /* tgl+ */
> -#define PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id)
> REG_FIELD_PREP(PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK,
> (plane_id))
> -
> #define VLV_DPFLIPSTAT
> _MMIO(VLV_DISPLAY_BASE + 0x70028)
> #define PIPEB_LINE_COMPARE_INT_EN REG_BIT(29)
> #define PIPEB_HLINE_INT_EN REG_BIT(28)
> @@ -1669,141 +863,8 @@
> #define SPRITEE_FLIPDONE_INT_EN REG_BIT(9)
> #define PLANEC_FLIPDONE_INT_EN REG_BIT(8)
>
> -#define DPINVGTT _MMIO(VLV_DISPLAY_BASE +
> 0x7002c) /* VLV/CHV only */
> -#define DPINVGTT_EN_MASK_CHV
> REG_GENMASK(27, 16)
> -#define DPINVGTT_EN_MASK_VLV
> REG_GENMASK(23, 16)
> -#define SPRITEF_INVALID_GTT_INT_EN REG_BIT(27)
> -#define SPRITEE_INVALID_GTT_INT_EN REG_BIT(26)
> -#define PLANEC_INVALID_GTT_INT_EN REG_BIT(25)
> -#define CURSORC_INVALID_GTT_INT_EN REG_BIT(24)
> -#define CURSORB_INVALID_GTT_INT_EN REG_BIT(23)
> -#define CURSORA_INVALID_GTT_INT_EN REG_BIT(22)
> -#define SPRITED_INVALID_GTT_INT_EN REG_BIT(21)
> -#define SPRITEC_INVALID_GTT_INT_EN REG_BIT(20)
> -#define PLANEB_INVALID_GTT_INT_EN REG_BIT(19)
> -#define SPRITEB_INVALID_GTT_INT_EN REG_BIT(18)
> -#define SPRITEA_INVALID_GTT_INT_EN REG_BIT(17)
> -#define PLANEA_INVALID_GTT_INT_EN REG_BIT(16)
> -#define DPINVGTT_STATUS_MASK_CHV
> REG_GENMASK(11, 0)
> -#define DPINVGTT_STATUS_MASK_VLV
> REG_GENMASK(7, 0)
> -#define SPRITEF_INVALID_GTT_STATUS REG_BIT(11)
> -#define SPRITEE_INVALID_GTT_STATUS REG_BIT(10)
> -#define PLANEC_INVALID_GTT_STATUS REG_BIT(9)
> -#define CURSORC_INVALID_GTT_STATUS REG_BIT(8)
> -#define CURSORB_INVALID_GTT_STATUS REG_BIT(7)
> -#define CURSORA_INVALID_GTT_STATUS REG_BIT(6)
> -#define SPRITED_INVALID_GTT_STATUS REG_BIT(5)
> -#define SPRITEC_INVALID_GTT_STATUS REG_BIT(4)
> -#define PLANEB_INVALID_GTT_STATUS REG_BIT(3)
> -#define SPRITEB_INVALID_GTT_STATUS REG_BIT(2)
> -#define SPRITEA_INVALID_GTT_STATUS REG_BIT(1)
> -#define PLANEA_INVALID_GTT_STATUS REG_BIT(0)
> -
> -#define CBR1_VLV _MMIO(VLV_DISPLAY_BASE +
> 0x70400)
> -#define CBR_PND_DEADLINE_DISABLE (1 << 31)
> -#define CBR_PWM_CLOCK_MUX_SELECT (1 << 30)
> -
> -#define CBR4_VLV _MMIO(VLV_DISPLAY_BASE +
> 0x70450)
> -#define CBR_DPLLBMD_PIPE(pipe) (1 << (7 + (pipe) * 11)) /* pipes
> B and C */
> -
> -/*
> - * The two pipe frame counter registers are not synchronized, so
> - * reading a stable value is somewhat tricky. The following code
> - * should work:
> - *
> - * do {
> - * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
> - * PIPE_FRAME_HIGH_SHIFT;
> - * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
> - * PIPE_FRAME_LOW_SHIFT);
> - * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
> - * PIPE_FRAME_HIGH_SHIFT);
> - * } while (high1 != high2);
> - * frame = (high1 << 8) | low1;
> - */
> -#define _PIPEAFRAMEHIGH 0x70040
> -#define PIPEFRAME(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe,
> _PIPEAFRAMEHIGH)
> -#define PIPE_FRAME_HIGH_MASK 0x0000ffff
> -#define PIPE_FRAME_HIGH_SHIFT 0
> -
> -#define _PIPEAFRAMEPIXEL 0x70044
> -#define PIPEFRAMEPIXEL(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe,
> _PIPEAFRAMEPIXEL)
> -#define PIPE_FRAME_LOW_MASK 0xff000000
> -#define PIPE_FRAME_LOW_SHIFT 24
> -#define PIPE_PIXEL_MASK 0x00ffffff
> -#define PIPE_PIXEL_SHIFT 0
> -
> -/* GM45+ just has to be different */
> -#define _PIPEA_FRMCOUNT_G4X 0x70040
> -#define PIPE_FRMCOUNT_G4X(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe,
> _PIPEA_FRMCOUNT_G4X)
> -
> -#define _PIPEA_FLIPCOUNT_G4X 0x70044
> -#define PIPE_FLIPCOUNT_G4X(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe,
> _PIPEA_FLIPCOUNT_G4X)
> -
> -/* CHV pipe B blender */
> -#define _CHV_BLEND_A 0x60a00
> -#define CHV_BLEND(dev_priv, pipe) _MMIO_TRANS2(dev_priv,
> pipe, _CHV_BLEND_A)
> -#define CHV_BLEND_MASK REG_GENMASK(31, 30)
> -#define CHV_BLEND_LEGACY REG_FIELD_PREP(CHV_BLEND_MASK, 0)
> -#define CHV_BLEND_ANDROID REG_FIELD_PREP(CHV_BLEND_MASK,
> 1)
> -#define CHV_BLEND_MPO REG_FIELD_PREP(CHV_BLEND_MASK,
> 2)
> -
> -#define _CHV_CANVAS_A 0x60a04
> -#define CHV_CANVAS(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe,
> _CHV_CANVAS_A)
> -#define CHV_CANVAS_RED_MASK REG_GENMASK(29, 20)
> -#define CHV_CANVAS_GREEN_MASK REG_GENMASK(19, 10)
> -#define CHV_CANVAS_BLUE_MASK REG_GENMASK(9, 0)
> -
> -/* Display/Sprite base address macros */
> -#define DISP_BASEADDR_MASK (0xfffff000)
> -#define I915_LO_DISPBASE(val) ((val) & ~DISP_BASEADDR_MASK)
> -#define I915_HI_DISPBASE(val) ((val) & DISP_BASEADDR_MASK)
> -
> -/*
> - * VBIOS flags
> - * gen2:
> - * [00:06] alm,mgm
> - * [10:16] all
> - * [30:32] alm,mgm
> - * gen3+:
> - * [00:0f] all
> - * [10:1f] all
> - * [30:32] all
> - */
> -#define SWF0(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) +
> 0x70410 + (i) * 4)
> -#define SWF1(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) +
> 0x71410 + (i) * 4)
> -#define SWF3(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) +
> 0x72414 + (i) * 4)
> -#define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)
> -
> -/* VBIOS regs */
> -#define VGACNTRL _MMIO(0x71400)
> -# define VGA_DISP_DISABLE (1 << 31)
> -# define VGA_2X_MODE (1 << 30)
> -# define VGA_PIPE_B_SELECT (1 << 29)
> -
> -#define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE +
> 0x71400)
> -
> /* Ironlake */
>
> -#define CPU_VGACNTRL _MMIO(0x41000)
> -
> -#define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030)
> -#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
> -#define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */
> -#define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */
> -#define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */
> -#define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */
> -#define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */
> -#define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0)
> -#define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0)
> -#define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0)
> -#define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0)
> -
> -/* refresh rate hardware control */
> -#define RR_HW_CTL _MMIO(0x45300)
> -#define RR_HW_LOW_POWER_FRAMES_MASK 0xff
> -#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
> -
> #define PCH_3DCGDIS0 _MMIO(0x46020)
> # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
> # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
> @@ -1811,211 +872,6 @@
> #define PCH_3DCGDIS1 _MMIO(0x46024)
> # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
>
> -#define _PIPEA_DATA_M1 0x60030
> -#define _PIPEB_DATA_M1 0x61030
> -#define PIPE_DATA_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran,
> _PIPEA_DATA_M1)
> -
> -#define _PIPEA_DATA_N1 0x60034
> -#define _PIPEB_DATA_N1 0x61034
> -#define PIPE_DATA_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran,
> _PIPEA_DATA_N1)
> -
> -#define _PIPEA_DATA_M2 0x60038
> -#define _PIPEB_DATA_M2 0x61038
> -#define PIPE_DATA_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran,
> _PIPEA_DATA_M2)
> -
> -#define _PIPEA_DATA_N2 0x6003c
> -#define _PIPEB_DATA_N2 0x6103c
> -#define PIPE_DATA_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran,
> _PIPEA_DATA_N2)
> -
> -#define _PIPEA_LINK_M1 0x60040
> -#define _PIPEB_LINK_M1 0x61040
> -#define PIPE_LINK_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran,
> _PIPEA_LINK_M1)
> -
> -#define _PIPEA_LINK_N1 0x60044
> -#define _PIPEB_LINK_N1 0x61044
> -#define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran,
> _PIPEA_LINK_N1)
> -
> -#define _PIPEA_LINK_M2 0x60048
> -#define _PIPEB_LINK_M2 0x61048
> -#define PIPE_LINK_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran,
> _PIPEA_LINK_M2)
> -
> -#define _PIPEA_LINK_N2 0x6004c
> -#define _PIPEB_LINK_N2 0x6104c
> -#define PIPE_LINK_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran,
> _PIPEA_LINK_N2)
> -
> -/*
> - * Skylake scalers
> - */
> -#define _ID(id, a, b) _PICK_EVEN(id, a, b)
> -#define _PS_1A_CTRL 0x68180
> -#define _PS_2A_CTRL 0x68280
> -#define _PS_1B_CTRL 0x68980
> -#define _PS_2B_CTRL 0x68A80
> -#define _PS_1C_CTRL 0x69180
> -#define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \
> - _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \
> - _ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
> -#define PS_SCALER_EN REG_BIT(31)
> -#define PS_SCALER_TYPE_MASK REG_BIT(30) /* icl+ */
> -#define PS_SCALER_TYPE_NON_LINEAR
> REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 0)
> -#define PS_SCALER_TYPE_LINEAR
> REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 1)
> -#define SKL_PS_SCALER_MODE_MASK REG_GENMASK(29,
> 28) /* skl/bxt */
> -#define SKL_PS_SCALER_MODE_DYN
> REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 0)
> -#define SKL_PS_SCALER_MODE_HQ
> REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 1)
> -#define SKL_PS_SCALER_MODE_NV12
> REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 2)
> -#define PS_SCALER_MODE_MASK REG_BIT(29) /* glk-tgl
> */
> -#define PS_SCALER_MODE_NORMAL
> REG_FIELD_PREP(PS_SCALER_MODE_MASK, 0)
> -#define PS_SCALER_MODE_PLANAR
> REG_FIELD_PREP(PS_SCALER_MODE_MASK, 1)
> -#define PS_ADAPTIVE_FILTERING_EN REG_BIT(28) /* icl+ */
> -#define PS_BINDING_MASK REG_GENMASK(27, 25)
> -#define PS_BINDING_PIPE
> REG_FIELD_PREP(PS_BINDING_MASK, 0)
> -#define PS_BINDING_PLANE(plane_id)
> REG_FIELD_PREP(PS_BINDING_MASK, (plane_id) + 1)
> -#define PS_FILTER_MASK REG_GENMASK(24, 23)
> -#define PS_FILTER_MEDIUM
> REG_FIELD_PREP(PS_FILTER_MASK, 0)
> -#define PS_FILTER_PROGRAMMED
> REG_FIELD_PREP(PS_FILTER_MASK, 1)
> -#define PS_FILTER_EDGE_ENHANCE
> REG_FIELD_PREP(PS_FILTER_MASK, 2)
> -#define PS_FILTER_BILINEAR
> REG_FIELD_PREP(PS_FILTER_MASK, 3)
> -#define PS_ADAPTIVE_FILTER_MASK REG_BIT(22) /* icl+ */
> -#define PS_ADAPTIVE_FILTER_MEDIUM
> REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 0)
> -#define PS_ADAPTIVE_FILTER_EDGE_ENHANCE
> REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 1)
> -#define PS_PIPE_SCALER_LOC_MASK REG_BIT(21) /* icl+ */
> -#define PS_PIPE_SCALER_LOC_AFTER_OUTPUT_CSC
> REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 0) /* non-linear */
> -#define PS_PIPE_SCALER_LOC_AFTER_CSC
> REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 1) /* linear */
> -#define PS_VERT3TAP REG_BIT(21) /* skl/bxt */
> -#define PS_VERT_INT_INVERT_FIELD REG_BIT(20)
> -#define PS_PROG_SCALE_FACTOR REG_BIT(19) /* tgl+ */
> -#define PS_PWRUP_PROGRESS REG_BIT(17)
> -#define PS_V_FILTER_BYPASS REG_BIT(8)
> -#define PS_VADAPT_EN REG_BIT(7) /* skl/bxt
> */
> -#define PS_VADAPT_MODE_MASK REG_GENMASK(6, 5)
> /* skl/bxt */
> -#define PS_VADAPT_MODE_LEAST_ADAPT
> REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 0)
> -#define PS_VADAPT_MODE_MOD_ADAPT
> REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 1)
> -#define PS_VADAPT_MODE_MOST_ADAPT
> REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 3)
> -#define PS_BINDING_Y_MASK REG_GENMASK(7, 5) /* icl-tgl
> */
> -#define PS_BINDING_Y_PLANE(plane_id)
> REG_FIELD_PREP(PS_BINDING_Y_MASK, (plane_id) + 1)
> -#define PS_Y_VERT_FILTER_SELECT_MASK REG_BIT(4) /* glk+ */
> -#define PS_Y_VERT_FILTER_SELECT(set)
> REG_FIELD_PREP(PS_Y_VERT_FILTER_SELECT_MASK, (set))
> -#define PS_Y_HORZ_FILTER_SELECT_MASK REG_BIT(3) /* glk+ */
> -#define PS_Y_HORZ_FILTER_SELECT(set)
> REG_FIELD_PREP(PS_Y_HORZ_FILTER_SELECT_MASK, (set))
> -#define PS_UV_VERT_FILTER_SELECT_MASK REG_BIT(2) /* glk+ */
> -#define PS_UV_VERT_FILTER_SELECT(set)
> REG_FIELD_PREP(PS_UV_VERT_FILTER_SELECT_MASK, (set))
> -#define PS_UV_HORZ_FILTER_SELECT_MASK REG_BIT(1) /* glk+ */
> -#define PS_UV_HORZ_FILTER_SELECT(set)
> REG_FIELD_PREP(PS_UV_HORZ_FILTER_SELECT_MASK, (set))
> -
> -#define _PS_PWR_GATE_1A 0x68160
> -#define _PS_PWR_GATE_2A 0x68260
> -#define _PS_PWR_GATE_1B 0x68960
> -#define _PS_PWR_GATE_2B 0x68A60
> -#define _PS_PWR_GATE_1C 0x69160
> -#define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \
> - _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \
> - _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))
> -#define PS_PWR_GATE_DIS_OVERRIDE REG_BIT(31)
> -#define PS_PWR_GATE_SETTLING_TIME_MASK REG_GENMASK(4, 3)
> -#define PS_PWR_GATE_SETTLING_TIME_32
> REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 0)
> -#define PS_PWR_GATE_SETTLING_TIME_64
> REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 1)
> -#define PS_PWR_GATE_SETTLING_TIME_96
> REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 2)
> -#define PS_PWR_GATE_SETTLING_TIME_128
> REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 3)
> -#define PS_PWR_GATE_SLPEN_MASK REG_GENMASK(1, 0)
> -#define PS_PWR_GATE_SLPEN_8
> REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 0)
> -#define PS_PWR_GATE_SLPEN_16
> REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 1)
> -#define PS_PWR_GATE_SLPEN_24
> REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 2)
> -#define PS_PWR_GATE_SLPEN_32
> REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 3)
> -
> -#define _PS_WIN_POS_1A 0x68170
> -#define _PS_WIN_POS_2A 0x68270
> -#define _PS_WIN_POS_1B 0x68970
> -#define _PS_WIN_POS_2B 0x68A70
> -#define _PS_WIN_POS_1C 0x69170
> -#define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \
> - _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \
> - _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))
> -#define PS_WIN_XPOS_MASK REG_GENMASK(31, 16)
> -#define PS_WIN_XPOS(x)
> REG_FIELD_PREP(PS_WIN_XPOS_MASK, (x))
> -#define PS_WIN_YPOS_MASK REG_GENMASK(15, 0)
> -#define PS_WIN_YPOS(y)
> REG_FIELD_PREP(PS_WIN_YPOS_MASK, (y))
> -
> -#define _PS_WIN_SZ_1A 0x68174
> -#define _PS_WIN_SZ_2A 0x68274
> -#define _PS_WIN_SZ_1B 0x68974
> -#define _PS_WIN_SZ_2B 0x68A74
> -#define _PS_WIN_SZ_1C 0x69174
> -#define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \
> - _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \
> - _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))
> -#define PS_WIN_XSIZE_MASK REG_GENMASK(31, 16)
> -#define PS_WIN_XSIZE(w)
> REG_FIELD_PREP(PS_WIN_XSIZE_MASK, (w))
> -#define PS_WIN_YSIZE_MASK REG_GENMASK(15, 0)
> -#define PS_WIN_YSIZE(h)
> REG_FIELD_PREP(PS_WIN_YSIZE_MASK, (h))
> -
> -#define _PS_VSCALE_1A 0x68184
> -#define _PS_VSCALE_2A 0x68284
> -#define _PS_VSCALE_1B 0x68984
> -#define _PS_VSCALE_2B 0x68A84
> -#define _PS_VSCALE_1C 0x69184
> -#define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \
> - _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \
> - _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))
> -
> -#define _PS_HSCALE_1A 0x68190
> -#define _PS_HSCALE_2A 0x68290
> -#define _PS_HSCALE_1B 0x68990
> -#define _PS_HSCALE_2B 0x68A90
> -#define _PS_HSCALE_1C 0x69190
> -#define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \
> - _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \
> - _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))
> -
> -#define _PS_VPHASE_1A 0x68188
> -#define _PS_VPHASE_2A 0x68288
> -#define _PS_VPHASE_1B 0x68988
> -#define _PS_VPHASE_2B 0x68A88
> -#define _PS_VPHASE_1C 0x69188
> -#define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \
> - _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \
> - _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))
> -#define PS_Y_PHASE_MASK REG_GENMASK(31, 16)
> -#define PS_Y_PHASE(x)
> REG_FIELD_PREP(PS_Y_PHASE_MASK, (x))
> -#define PS_UV_RGB_PHASE_MASK REG_GENMASK(15, 0)
> -#define PS_UV_RGB_PHASE(x)
> REG_FIELD_PREP(PS_UV_RGB_PHASE_MASK, (x))
> -#define PS_PHASE_MASK (0x7fff << 1) /* u2.13
> */
> -#define PS_PHASE_TRIP (1 << 0)
> -
> -#define _PS_HPHASE_1A 0x68194
> -#define _PS_HPHASE_2A 0x68294
> -#define _PS_HPHASE_1B 0x68994
> -#define _PS_HPHASE_2B 0x68A94
> -#define _PS_HPHASE_1C 0x69194
> -#define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \
> - _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \
> - _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))
> -
> -#define _PS_ECC_STAT_1A 0x681D0
> -#define _PS_ECC_STAT_2A 0x682D0
> -#define _PS_ECC_STAT_1B 0x689D0
> -#define _PS_ECC_STAT_2B 0x68AD0
> -#define _PS_ECC_STAT_1C 0x691D0
> -#define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \
> - _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
> - _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
> -
> -#define _PS_COEF_SET0_INDEX_1A 0x68198
> -#define _PS_COEF_SET0_INDEX_2A 0x68298
> -#define _PS_COEF_SET0_INDEX_1B 0x68998
> -#define _PS_COEF_SET0_INDEX_2B 0x68A98
> -#define GLK_PS_COEF_INDEX_SET(pipe, id, set) _MMIO_PIPE(pipe, \
> - _ID(id, _PS_COEF_SET0_INDEX_1A,
> _PS_COEF_SET0_INDEX_2A) + (set) * 8, \
> - _ID(id, _PS_COEF_SET0_INDEX_1B,
> _PS_COEF_SET0_INDEX_2B) + (set) * 8)
> -#define PS_COEF_INDEX_AUTO_INC REG_BIT(10)
> -
> -#define _PS_COEF_SET0_DATA_1A 0x6819C
> -#define _PS_COEF_SET0_DATA_2A 0x6829C
> -#define _PS_COEF_SET0_DATA_1B 0x6899C
> -#define _PS_COEF_SET0_DATA_2B 0x68A9C
> -#define GLK_PS_COEF_DATA_SET(pipe, id, set) _MMIO_PIPE(pipe, \
> - _ID(id, _PS_COEF_SET0_DATA_1A,
> _PS_COEF_SET0_DATA_2A) + (set) * 8, \
> - _ID(id, _PS_COEF_SET0_DATA_1B,
> _PS_COEF_SET0_DATA_2B) + (set) * 8)
> -
> /* Display Internal Timeout Register */
> #define RM_TIMEOUT _MMIO(0x42060)
> #define RM_TIMEOUT_REG_CAPTURE _MMIO(0x420E0)
> @@ -2054,25 +910,6 @@
> #define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
> #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe)))
>
> -/* More Ivybridge lolz */
> -#define DE_ERR_INT_IVB (1 << 30)
> -#define DE_GSE_IVB (1 << 29)
> -#define DE_PCH_EVENT_IVB (1 << 28)
> -#define DE_DP_A_HOTPLUG_IVB (1 << 27)
> -#define DE_AUX_CHANNEL_A_IVB (1 << 26)
> -#define DE_EDP_PSR_INT_HSW (1 << 19)
> -#define DE_SPRITEC_FLIP_DONE_IVB (1 << 14)
> -#define DE_PLANEC_FLIP_DONE_IVB (1 << 13)
> -#define DE_PIPEC_VBLANK_IVB (1 << 10)
> -#define DE_SPRITEB_FLIP_DONE_IVB (1 << 9)
> -#define DE_PLANEB_FLIP_DONE_IVB (1 << 8)
> -#define DE_PIPEB_VBLANK_IVB (1 << 5)
> -#define DE_SPRITEA_FLIP_DONE_IVB (1 << 4)
> -#define DE_PLANEA_FLIP_DONE_IVB (1 << 3)
> -#define DE_PLANE_FLIP_DONE_IVB(plane) (1 << (3 + 5 * (plane)))
> -#define DE_PIPEA_VBLANK_IVB (1 << 0)
> -#define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5))
> -
> #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit
> master IER */
> #define MASTER_INTERRUPT_ENABLE (1 << 31)
>
> @@ -2112,8 +949,6 @@
> #define GEN8_GT_BCS_IRQ (1 << 1)
> #define GEN8_GT_RCS_IRQ (1 << 0)
>
> -#define XELPD_DISPLAY_ERR_FATAL_MASK _MMIO(0x4421c)
> -
> #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
> #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
> #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
> @@ -2130,91 +965,6 @@
> #define GEN8_VECS_IRQ_SHIFT 0
> #define GEN8_WD_IRQ_SHIFT 16
>
> -#define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))
> -#define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))
> -#define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))
> -#define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))
> -#define GEN8_PIPE_FIFO_UNDERRUN REG_BIT(31)
> -#define GEN8_PIPE_CDCLK_CRC_ERROR REG_BIT(29)
> -#define GEN8_PIPE_CDCLK_CRC_DONE REG_BIT(28)
> -#define GEN12_PIPEDMC_INTERRUPT REG_BIT(26) /* tgl+ */
> -#define GEN12_PIPEDMC_FAULT REG_BIT(25) /* tgl+ */
> -#define MTL_PIPEDMC_ATS_FAULT REG_BIT(24) /* mtl+ */
> -#define GEN11_PIPE_PLANE7_FAULT REG_BIT(22) /* icl/tgl */
> -#define GEN11_PIPE_PLANE6_FAULT REG_BIT(21) /* icl/tgl */
> -#define GEN11_PIPE_PLANE5_FAULT REG_BIT(20) /* icl+ */
> -#define GEN12_PIPE_VBLANK_UNMOD REG_BIT(19) /* tgl+ */
> -#define MTL_PLANE_ATS_FAULT REG_BIT(18) /* mtl+ */
> -#define GEN11_PIPE_PLANE7_FLIP_DONE REG_BIT(18) /* icl/tgl */
> -#define GEN11_PIPE_PLANE6_FLIP_DONE REG_BIT(17) /* icl/tgl */
> -#define GEN11_PIPE_PLANE5_FLIP_DONE REG_BIT(16) /* icl+ */
> -#define GEN12_DSB_2_INT REG_BIT(15) /* tgl+ */
> -#define GEN12_DSB_1_INT REG_BIT(14) /* tgl+ */
> -#define GEN12_DSB_0_INT REG_BIT(13) /* tgl+ */
> -#define GEN12_DSB_INT(dsb_id) REG_BIT(13 + (dsb_id))
> -#define GEN9_PIPE_CURSOR_FAULT REG_BIT(11) /* skl+ */
> -#define GEN9_PIPE_PLANE4_FAULT REG_BIT(10) /* skl+ */
> -#define GEN8_PIPE_CURSOR_FAULT REG_BIT(10) /* bdw */
> -#define GEN9_PIPE_PLANE3_FAULT REG_BIT(9) /* skl+ */
> -#define GEN8_PIPE_SPRITE_FAULT REG_BIT(9) /* bdw */
> -#define GEN9_PIPE_PLANE2_FAULT REG_BIT(8) /* skl+ */
> -#define GEN8_PIPE_PRIMARY_FAULT REG_BIT(8) /* bdw */
> -#define GEN9_PIPE_PLANE1_FAULT REG_BIT(7) /* skl+ */
> -#define GEN9_PIPE_PLANE4_FLIP_DONE REG_BIT(6) /* skl+ */
> -#define GEN9_PIPE_PLANE3_FLIP_DONE REG_BIT(5) /* skl+ */
> -#define GEN8_PIPE_SPRITE_FLIP_DONE REG_BIT(5) /* bdw */
> -#define GEN9_PIPE_PLANE2_FLIP_DONE REG_BIT(4) /* skl+ */
> -#define GEN8_PIPE_PRIMARY_FLIP_DONE REG_BIT(4) /* bdw */
> -#define GEN9_PIPE_PLANE1_FLIP_DONE REG_BIT(3) /* skl+ */
> -#define GEN9_PIPE_PLANE_FLIP_DONE(plane_id) \
> - REG_BIT(((plane_id) >= PLANE_5 ? 16 - PLANE_5 : 3 - PLANE_1) +
> (plane_id)) /* skl+ */
> -#define GEN8_PIPE_SCAN_LINE_EVENT REG_BIT(2)
> -#define GEN8_PIPE_VSYNC REG_BIT(1)
> -#define GEN8_PIPE_VBLANK REG_BIT(0)
> -
> -#define GEN8_DE_PIPE_IRQ_REGS(pipe)
> I915_IRQ_REGS(GEN8_DE_PIPE_IMR(pipe), \
> - GEN8_DE_PIPE_IER(pipe), \
> - GEN8_DE_PIPE_IIR(pipe))
> -
> -#define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A)
> -#define _HPD_PIN_TC(hpd_pin) ((hpd_pin) - HPD_PORT_TC1)
> -
> -#define GEN8_DE_PORT_ISR _MMIO(0x44440)
> -#define GEN8_DE_PORT_IMR _MMIO(0x44444)
> -#define GEN8_DE_PORT_IIR _MMIO(0x44448)
> -#define GEN8_DE_PORT_IER _MMIO(0x4444c)
> -#define DSI1_NON_TE (1 << 31)
> -#define DSI0_NON_TE (1 << 30)
> -#define ICL_AUX_CHANNEL_E (1 << 29)
> -#define ICL_AUX_CHANNEL_F (1 << 28)
> -#define GEN9_AUX_CHANNEL_D (1 << 27)
> -#define GEN9_AUX_CHANNEL_C (1 << 26)
> -#define GEN9_AUX_CHANNEL_B (1 << 25)
> -#define DSI1_TE (1 << 24)
> -#define DSI0_TE (1 << 23)
> -#define GEN8_DE_PORT_HOTPLUG(hpd_pin) REG_BIT(3 +
> _HPD_PIN_DDI(hpd_pin))
> -#define BXT_DE_PORT_HOTPLUG_MASK
> (GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \
> -
> GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \
> -
> GEN8_DE_PORT_HOTPLUG(HPD_PORT_C))
> -#define BDW_DE_PORT_HOTPLUG_MASK
> GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)
> -#define BXT_DE_PORT_GMBUS (1 << 1)
> -#define GEN8_AUX_CHANNEL_A (1 << 0)
> -#define TGL_DE_PORT_AUX_USBC6 REG_BIT(13)
> -#define XELPD_DE_PORT_AUX_DDIE REG_BIT(13)
> -#define TGL_DE_PORT_AUX_USBC5 REG_BIT(12)
> -#define XELPD_DE_PORT_AUX_DDID REG_BIT(12)
> -#define TGL_DE_PORT_AUX_USBC4 REG_BIT(11)
> -#define TGL_DE_PORT_AUX_USBC3 REG_BIT(10)
> -#define TGL_DE_PORT_AUX_USBC2 REG_BIT(9)
> -#define TGL_DE_PORT_AUX_USBC1 REG_BIT(8)
> -#define TGL_DE_PORT_AUX_DDIC REG_BIT(2)
> -#define TGL_DE_PORT_AUX_DDIB REG_BIT(1)
> -#define TGL_DE_PORT_AUX_DDIA REG_BIT(0)
> -
> -#define GEN8_DE_PORT_IRQ_REGS
> I915_IRQ_REGS(GEN8_DE_PORT_IMR, \
> - GEN8_DE_PORT_IER, \
> - GEN8_DE_PORT_IIR)
> -
> #define GEN8_DE_MISC_ISR _MMIO(0x44460)
> #define GEN8_DE_MISC_IMR _MMIO(0x44464)
> #define GEN8_DE_MISC_IIR _MMIO(0x44468)
> @@ -2226,10 +976,6 @@
> #define XELPDP_PMDEMAND_RSP REG_BIT(3)
> #define XE2LPD_DBUF_OVERLAP_DETECTED REG_BIT(1)
>
> -#define GEN8_DE_MISC_IRQ_REGS
> I915_IRQ_REGS(GEN8_DE_MISC_IMR, \
> - GEN8_DE_MISC_IER, \
> - GEN8_DE_MISC_IIR)
> -
> #define GEN8_PCU_ISR _MMIO(0x444e0)
> #define GEN8_PCU_IMR _MMIO(0x444e4)
> #define GEN8_PCU_IIR _MMIO(0x444e8)
> @@ -2262,110 +1008,12 @@
> #define DG1_MSTR_IRQ REG_BIT(31)
> #define DG1_MSTR_TILE(t) REG_BIT(t)
>
> -#define GEN11_DISPLAY_INT_CTL _MMIO(0x44200)
> -#define GEN11_DISPLAY_IRQ_ENABLE (1 << 31)
> -#define GEN11_AUDIO_CODEC_IRQ (1 << 24)
> -#define GEN11_DE_PCH_IRQ (1 << 23)
> -#define GEN11_DE_MISC_IRQ (1 << 22)
> -#define GEN11_DE_HPD_IRQ (1 << 21)
> -#define GEN11_DE_PORT_IRQ (1 << 20)
> -#define GEN11_DE_PIPE_C (1 << 18)
> -#define GEN11_DE_PIPE_B (1 << 17)
> -#define GEN11_DE_PIPE_A (1 << 16)
> -
> -#define GEN11_DE_HPD_ISR _MMIO(0x44470)
> -#define GEN11_DE_HPD_IMR _MMIO(0x44474)
> -#define GEN11_DE_HPD_IIR _MMIO(0x44478)
> -#define GEN11_DE_HPD_IER _MMIO(0x4447c)
> -#define GEN11_TC_HOTPLUG(hpd_pin) REG_BIT(16 +
> _HPD_PIN_TC(hpd_pin))
> -#define GEN11_DE_TC_HOTPLUG_MASK
> (GEN11_TC_HOTPLUG(HPD_PORT_TC6) | \
> -
> GEN11_TC_HOTPLUG(HPD_PORT_TC5) | \
> -
> GEN11_TC_HOTPLUG(HPD_PORT_TC4) | \
> -
> GEN11_TC_HOTPLUG(HPD_PORT_TC3) | \
> -
> GEN11_TC_HOTPLUG(HPD_PORT_TC2) | \
> -
> GEN11_TC_HOTPLUG(HPD_PORT_TC1))
> -#define GEN11_TBT_HOTPLUG(hpd_pin)
> REG_BIT(_HPD_PIN_TC(hpd_pin))
> -#define GEN11_DE_TBT_HOTPLUG_MASK
> (GEN11_TBT_HOTPLUG(HPD_PORT_TC6) | \
> -
> GEN11_TBT_HOTPLUG(HPD_PORT_TC5) | \
> -
> GEN11_TBT_HOTPLUG(HPD_PORT_TC4) | \
> -
> GEN11_TBT_HOTPLUG(HPD_PORT_TC3) | \
> -
> GEN11_TBT_HOTPLUG(HPD_PORT_TC2) | \
> -
> GEN11_TBT_HOTPLUG(HPD_PORT_TC1))
> -
> -#define GEN11_DE_HPD_IRQ_REGS
> I915_IRQ_REGS(GEN11_DE_HPD_IMR, \
> - GEN11_DE_HPD_IER, \
> - GEN11_DE_HPD_IIR)
> -
> -#define GEN11_TBT_HOTPLUG_CTL
> _MMIO(0x44030)
> -#define GEN11_TC_HOTPLUG_CTL
> _MMIO(0x44038)
> -#define GEN11_HOTPLUG_CTL_ENABLE(hpd_pin) (8 <<
> (_HPD_PIN_TC(hpd_pin) * 4))
> -#define GEN11_HOTPLUG_CTL_LONG_DETECT(hpd_pin) (2 <<
> (_HPD_PIN_TC(hpd_pin) * 4))
> -#define GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin) (1 <<
> (_HPD_PIN_TC(hpd_pin) * 4))
> -#define GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin) (0 <<
> (_HPD_PIN_TC(hpd_pin) * 4))
> -
> -#define PICAINTERRUPT_ISR _MMIO(0x16FE50)
> -#define PICAINTERRUPT_IMR _MMIO(0x16FE54)
> -#define PICAINTERRUPT_IIR _MMIO(0x16FE58)
> -#define PICAINTERRUPT_IER _MMIO(0x16FE5C)
> -#define XELPDP_DP_ALT_HOTPLUG(hpd_pin) REG_BIT(16 +
> _HPD_PIN_TC(hpd_pin))
> -#define XELPDP_DP_ALT_HOTPLUG_MASK REG_GENMASK(19,
> 16)
> -#define XELPDP_AUX_TC(hpd_pin) REG_BIT(8 +
> _HPD_PIN_TC(hpd_pin))
> -#define XELPDP_AUX_TC_MASK REG_GENMASK(11, 8)
> -#define XE2LPD_AUX_DDI(hpd_pin) REG_BIT(6 +
> _HPD_PIN_DDI(hpd_pin))
> -#define XE2LPD_AUX_DDI_MASK REG_GENMASK(7, 6)
> -#define XELPDP_TBT_HOTPLUG(hpd_pin)
> REG_BIT(_HPD_PIN_TC(hpd_pin))
> -#define XELPDP_TBT_HOTPLUG_MASK REG_GENMASK(3, 0)
> -
> -#define PICAINTERRUPT_IRQ_REGS
> I915_IRQ_REGS(PICAINTERRUPT_IMR, \
> -
> PICAINTERRUPT_IER, \
> -
> PICAINTERRUPT_IIR)
> -
> -#define XELPDP_PORT_HOTPLUG_CTL(hpd_pin) _MMIO(0x16F270 +
> (_HPD_PIN_TC(hpd_pin) * 0x200))
> -#define XELPDP_TBT_HOTPLUG_ENABLE REG_BIT(6)
> -#define XELPDP_TBT_HPD_LONG_DETECT REG_BIT(5)
> -#define XELPDP_TBT_HPD_SHORT_DETECT REG_BIT(4)
> -#define XELPDP_DP_ALT_HOTPLUG_ENABLE REG_BIT(2)
> -#define XELPDP_DP_ALT_HPD_LONG_DETECT REG_BIT(1)
> -#define XELPDP_DP_ALT_HPD_SHORT_DETECT REG_BIT(0)
> -
> -#define XELPDP_INITIATE_PMDEMAND_REQUEST(dword)
> _MMIO(0x45230 + 4 * (dword))
> -#define XELPDP_PMDEMAND_QCLK_GV_BW_MASK
> REG_GENMASK(31, 16)
> -#define XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK
> REG_GENMASK(14, 12)
> -#define XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK
> REG_GENMASK(11, 8)
> -#define XE3_PMDEMAND_PIPES_MASK
> REG_GENMASK(7, 4)
> -#define XELPDP_PMDEMAND_PIPES_MASK
> REG_GENMASK(7, 6)
> -#define XELPDP_PMDEMAND_DBUFS_MASK
> REG_GENMASK(5, 4)
> -#define XELPDP_PMDEMAND_PHYS_MASK
> REG_GENMASK(2, 0)
> -
> -#define XELPDP_PMDEMAND_REQ_ENABLE REG_BIT(31)
> -#define XELPDP_PMDEMAND_CDCLK_FREQ_MASK
> REG_GENMASK(30, 20)
> -#define XELPDP_PMDEMAND_DDICLK_FREQ_MASK
> REG_GENMASK(18, 8)
> -#define XELPDP_PMDEMAND_SCALERS_MASK
> REG_GENMASK(6, 4)
> -#define XELPDP_PMDEMAND_PLLS_MASK
> REG_GENMASK(2, 0)
> -
> -#define GEN12_DCPR_STATUS_1
> _MMIO(0x46440)
> -#define XELPDP_PMDEMAND_INFLIGHT_STATUS REG_BIT(26)
> -
> #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004)
> /* Required on all Ironlake and Sandybridge according to the B-Spec. */
> #define ILK_ELPIN_409_SELECT REG_BIT(25)
> #define ILK_DPARB_GATE REG_BIT(22)
> #define ILK_VSDPFD_FULL REG_BIT(21)
>
> -#define FUSE_STRAP _MMIO(0x42014)
> -#define ILK_INTERNAL_GRAPHICS_DISABLE REG_BIT(31)
> -#define ILK_INTERNAL_DISPLAY_DISABLE REG_BIT(30)
> -#define ILK_DISPLAY_DEBUG_DISABLE REG_BIT(29)
> -#define IVB_PIPE_C_DISABLE REG_BIT(28)
> -#define ILK_HDCP_DISABLE REG_BIT(25)
> -#define ILK_eDP_A_DISABLE REG_BIT(24)
> -#define HSW_CDCLK_LIMIT REG_BIT(24)
> -#define ILK_DESKTOP REG_BIT(23)
> -#define HSW_CPU_SSC_ENABLE REG_BIT(21)
> -
> -#define FUSE_STRAP3 _MMIO(0x42020)
> -#define HSW_REF_CLK_SELECT REG_BIT(1)
> -
> #define ILK_DSPCLK_GATE_D _MMIO(0x42020)
> #define ILK_VRHUNIT_CLOCK_GATE_DISABLE REG_BIT(28)
> #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE REG_BIT(9)
> @@ -2390,25 +1038,6 @@
> #define CHICKEN_PAR2_1 _MMIO(0x42090)
> #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT REG_BIT(14)
>
> -#define CHICKEN_MISC_2 _MMIO(0x42084)
> -#define CHICKEN_MISC_DISABLE_DPT REG_BIT(30) /* adl,dg2 */
> -#define BMG_DARB_HALF_BLK_END_BURST REG_BIT(27)
> -#define KBL_ARB_FILL_SPARE_14 REG_BIT(14)
> -#define KBL_ARB_FILL_SPARE_13 REG_BIT(13)
> -#define GLK_CL2_PWR_DOWN REG_BIT(12)
> -#define GLK_CL1_PWR_DOWN REG_BIT(11)
> -#define GLK_CL0_PWR_DOWN REG_BIT(10)
> -
> -#define CHICKEN_MISC_3 _MMIO(0x42088)
> -#define DP_MST_DPT_DPTP_ALIGN_WA(trans) REG_BIT(9 + (trans) -
> TRANSCODER_A)
> -#define DP_MST_SHORT_HBLANK_WA(trans) REG_BIT(5 + (trans) -
> TRANSCODER_A)
> -#define DP_MST_FEC_BS_JITTER_WA(trans) REG_BIT(0 + (trans) -
> TRANSCODER_A)
> -
> -#define CHICKEN_MISC_4 _MMIO(0x4208c)
> -#define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13)
> -#define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0)
> -#define CHICKEN_FBC_STRIDE(x)
> REG_FIELD_PREP(CHICKEN_FBC_STRIDE_MASK, (x))
> -
> #define _CHICKEN_PIPESL_1_A 0x420b0
> #define _CHICKEN_PIPESL_1_B 0x420b4
> #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe,
> _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
> @@ -2432,72 +1061,11 @@
> #define SKL_PLANE1_STRETCH_MAX_X1
> REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3)
> #define BDW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(0) /* bdw */
>
> -#define _CHICKEN_TRANS_A 0x420c0
> -#define _CHICKEN_TRANS_B 0x420c4
> -#define _CHICKEN_TRANS_C 0x420c8
> -#define _CHICKEN_TRANS_EDP 0x420cc
> -#define _CHICKEN_TRANS_D 0x420d8
> -#define _CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \
> - [TRANSCODER_EDP] =
> _CHICKEN_TRANS_EDP, \
> - [TRANSCODER_A] =
> _CHICKEN_TRANS_A, \
> - [TRANSCODER_B] =
> _CHICKEN_TRANS_B, \
> - [TRANSCODER_C] =
> _CHICKEN_TRANS_C, \
> - [TRANSCODER_D] =
> _CHICKEN_TRANS_D))
> -#define _MTL_CHICKEN_TRANS_A 0x604e0
> -#define _MTL_CHICKEN_TRANS_B 0x614e0
> -#define _MTL_CHICKEN_TRANS(trans) _MMIO_TRANS((trans), \
> - _MTL_CHICKEN_TRANS_A, \
> - _MTL_CHICKEN_TRANS_B)
> -#define CHICKEN_TRANS(display, trans) (DISPLAY_VER(display) >= 14 ?
> _MTL_CHICKEN_TRANS(trans) : _CHICKEN_TRANS(trans))
> -#define PIPE_VBLANK_WITH_DELAY REG_BIT(31) /* tgl+ */
> -#define SKL_UNMASK_VBL_TO_PIPE_IN_SRD REG_BIT(30) /* skl+ */
> -#define HSW_FRAME_START_DELAY_MASK REG_GENMASK(28, 27)
> -#define HSW_FRAME_START_DELAY(x)
> REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x)
> -#define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */
> -#define FECSTALL_DIS_DPTSTREAM_DPTTG REG_BIT(23)
> -#define DDI_TRAINING_OVERRIDE_ENABLE REG_BIT(19)
> -#define ADLP_1_BASED_X_GRANULARITY REG_BIT(18)
> -#define DDI_TRAINING_OVERRIDE_VALUE REG_BIT(18)
> -#define DDIE_TRAINING_OVERRIDE_ENABLE REG_BIT(17) /*
> CHICKEN_TRANS_A only */
> -#define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /*
> CHICKEN_TRANS_A only */
> -#define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15)
> -#define DP_FEC_BS_JITTER_WA REG_BIT(15)
> -#define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12)
> -#define DP_DSC_INSERT_SF_AT_EOL_WA REG_BIT(4)
> -#define HDCP_LINE_REKEY_DISABLE REG_BIT(0)
> -
> #define DISP_ARB_CTL _MMIO(0x45000)
> #define DISP_FBC_MEMORY_WAKE REG_BIT(31)
> #define DISP_TILE_SURFACE_SWIZZLING REG_BIT(13)
> #define DISP_FBC_WM_DIS REG_BIT(15)
>
> -#define DISP_ARB_CTL2 _MMIO(0x45004)
> -#define DISP_DATA_PARTITION_5_6 REG_BIT(6)
> -#define DISP_IPC_ENABLE REG_BIT(3)
> -
> -#define GEN7_MSG_CTL _MMIO(0x45010)
> -#define WAIT_FOR_PCH_RESET_ACK (1 << 1)
> -#define WAIT_FOR_PCH_FLR_ACK (1 << 0)
> -
> -#define _BW_BUDDY0_CTL 0x45130
> -#define _BW_BUDDY1_CTL 0x45140
> -#define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \
> - _BW_BUDDY0_CTL, \
> - _BW_BUDDY1_CTL))
> -#define BW_BUDDY_DISABLE REG_BIT(31)
> -#define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16)
> -#define BW_BUDDY_TLB_REQ_TIMER(x)
> REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, x)
> -
> -#define _BW_BUDDY0_PAGE_MASK 0x45134
> -#define _BW_BUDDY1_PAGE_MASK 0x45144
> -#define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \
> -
> _BW_BUDDY0_PAGE_MASK, \
> -
> _BW_BUDDY1_PAGE_MASK))
> -
> -#define HSW_NDE_RSTWRN_OPT _MMIO(0x46408)
> -#define MTL_RESET_PICA_HANDSHAKE_EN REG_BIT(6)
> -#define RESET_PCH_HANDSHAKE_ENABLE REG_BIT(4)
> -
> #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
> #define _LATENCY_REPORTING_REMOVED_PIPE_D REG_BIT(31)
> #define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30)
> @@ -2514,171 +1082,13 @@
> #define MASK_WAKEMEM REG_BIT(13)
> #define DDI_CLOCK_REG_ACCESS REG_BIT(7)
>
> -#define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434)
> -#define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27)
> -#define DCPR_MASK_LPMODE REG_BIT(26)
> -#define DCPR_SEND_RESP_IMM REG_BIT(25)
> -#define DCPR_CLEAR_MEMSTAT_DIS REG_BIT(24)
> -
> -#define XELPD_CHICKEN_DCPR_3 _MMIO(0x46438)
> -#define DMD_RSP_TIMEOUT_DISABLE REG_BIT(19)
> -
> -#define SKL_DFSM _MMIO(0x51000)
> -#define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27)
> -#define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25)
> -#define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
> -#define ICL_DFSM_DMC_DISABLE (1 << 23)
> -#define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
> -#define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
> -#define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
> -#define TGL_DFSM_PIPE_D_DISABLE (1 << 22)
> -#define GLK_DFSM_DISPLAY_DSC_DISABLE (1 << 7)
> -#define XE2LPD_DFSM_DBUF_OVERLAP_DISABLE (1 << 3)
> -
> -#define XE2LPD_DE_CAP _MMIO(0x41100)
> -#define XE2LPD_DE_CAP_3DLUT_MASK REG_GENMASK(31, 30)
> -#define XE2LPD_DE_CAP_DSC_MASK REG_GENMASK(29, 28)
> -#define XE2LPD_DE_CAP_DSC_REMOVED 1
> -#define XE2LPD_DE_CAP_SCALER_MASK REG_GENMASK(27, 26)
> -#define XE2LPD_DE_CAP_SCALER_SINGLE 1
> -
> -#define SKL_DSSM _MMIO(0x51004)
> -#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29)
> -#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29)
> -#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29)
> -#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29)
> -
> #define GMD_ID_DISPLAY _MMIO(0x510a0)
> #define GMD_ID_ARCH_MASK REG_GENMASK(31,
> 22)
> #define GMD_ID_RELEASE_MASK REG_GENMASK(21,
> 14)
> #define GMD_ID_STEP REG_GENMASK(5, 0)
>
> -/*GEN11 chicken */
> -#define _PIPEA_CHICKEN 0x70038
> -#define _PIPEB_CHICKEN 0x71038
> -#define _PIPEC_CHICKEN 0x72038
> -#define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe,
> _PIPEA_CHICKEN,\
> - _PIPEB_CHICKEN)
> -#define UNDERRUN_RECOVERY_DISABLE_ADLP REG_BIT(30)
> -#define UNDERRUN_RECOVERY_ENABLE_DG2 REG_BIT(30)
> -#define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU REG_BIT(15)
> -#define DG2_RENDER_CCSTAG_4_3_EN REG_BIT(12)
> -#define PER_PIXEL_ALPHA_BYPASS_EN REG_BIT(7)
> -
> /* PCH */
>
> -#define PCH_DISPLAY_BASE 0xc0000u
> -
> -/* south display engine interrupt: IBX */
> -#define SDE_AUDIO_POWER_D (1 << 27)
> -#define SDE_AUDIO_POWER_C (1 << 26)
> -#define SDE_AUDIO_POWER_B (1 << 25)
> -#define SDE_AUDIO_POWER_SHIFT (25)
> -#define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
> -#define SDE_GMBUS (1 << 24)
> -#define SDE_AUDIO_HDCP_TRANSB (1 << 23)
> -#define SDE_AUDIO_HDCP_TRANSA (1 << 22)
> -#define SDE_AUDIO_HDCP_MASK (3 << 22)
> -#define SDE_AUDIO_TRANSB (1 << 21)
> -#define SDE_AUDIO_TRANSA (1 << 20)
> -#define SDE_AUDIO_TRANS_MASK (3 << 20)
> -#define SDE_POISON (1 << 19)
> -/* 18 reserved */
> -#define SDE_FDI_RXB (1 << 17)
> -#define SDE_FDI_RXA (1 << 16)
> -#define SDE_FDI_MASK (3 << 16)
> -#define SDE_AUXD (1 << 15)
> -#define SDE_AUXC (1 << 14)
> -#define SDE_AUXB (1 << 13)
> -#define SDE_AUX_MASK (7 << 13)
> -/* 12 reserved */
> -#define SDE_CRT_HOTPLUG (1 << 11)
> -#define SDE_PORTD_HOTPLUG (1 << 10)
> -#define SDE_PORTC_HOTPLUG (1 << 9)
> -#define SDE_PORTB_HOTPLUG (1 << 8)
> -#define SDE_SDVOB_HOTPLUG (1 << 6)
> -#define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \
> - SDE_SDVOB_HOTPLUG | \
> - SDE_PORTB_HOTPLUG | \
> - SDE_PORTC_HOTPLUG | \
> - SDE_PORTD_HOTPLUG)
> -#define SDE_TRANSB_CRC_DONE (1 << 5)
> -#define SDE_TRANSB_CRC_ERR (1 << 4)
> -#define SDE_TRANSB_FIFO_UNDER (1 << 3)
> -#define SDE_TRANSA_CRC_DONE (1 << 2)
> -#define SDE_TRANSA_CRC_ERR (1 << 1)
> -#define SDE_TRANSA_FIFO_UNDER (1 << 0)
> -#define SDE_TRANS_MASK (0x3f)
> -
> -/* south display engine interrupt: CPT - CNP */
> -#define SDE_AUDIO_POWER_D_CPT (1 << 31)
> -#define SDE_AUDIO_POWER_C_CPT (1 << 30)
> -#define SDE_AUDIO_POWER_B_CPT (1 << 29)
> -#define SDE_AUDIO_POWER_SHIFT_CPT 29
> -#define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
> -#define SDE_AUXD_CPT (1 << 27)
> -#define SDE_AUXC_CPT (1 << 26)
> -#define SDE_AUXB_CPT (1 << 25)
> -#define SDE_AUX_MASK_CPT (7 << 25)
> -#define SDE_PORTE_HOTPLUG_SPT (1 << 25)
> -#define SDE_PORTA_HOTPLUG_SPT (1 << 24)
> -#define SDE_PORTD_HOTPLUG_CPT (1 << 23)
> -#define SDE_PORTC_HOTPLUG_CPT (1 << 22)
> -#define SDE_PORTB_HOTPLUG_CPT (1 << 21)
> -#define SDE_CRT_HOTPLUG_CPT (1 << 19)
> -#define SDE_SDVOB_HOTPLUG_CPT (1 << 18)
> -#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT |
> \
> - SDE_SDVOB_HOTPLUG_CPT | \
> - SDE_PORTD_HOTPLUG_CPT | \
> - SDE_PORTC_HOTPLUG_CPT | \
> - SDE_PORTB_HOTPLUG_CPT)
> -#define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \
> - SDE_PORTD_HOTPLUG_CPT | \
> - SDE_PORTC_HOTPLUG_CPT | \
> - SDE_PORTB_HOTPLUG_CPT | \
> - SDE_PORTA_HOTPLUG_SPT)
> -#define SDE_GMBUS_CPT (1 << 17)
> -#define SDE_ERROR_CPT (1 << 16)
> -#define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
> -#define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
> -#define SDE_FDI_RXC_CPT (1 << 8)
> -#define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
> -#define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
> -#define SDE_FDI_RXB_CPT (1 << 4)
> -#define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
> -#define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
> -#define SDE_FDI_RXA_CPT (1 << 0)
> -#define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
> - SDE_AUDIO_CP_REQ_B_CPT | \
> - SDE_AUDIO_CP_REQ_A_CPT)
> -#define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
> - SDE_AUDIO_CP_CHG_B_CPT | \
> - SDE_AUDIO_CP_CHG_A_CPT)
> -#define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
> - SDE_FDI_RXB_CPT | \
> - SDE_FDI_RXA_CPT)
> -
> -/* south display engine interrupt: ICP/TGP/MTP */
> -#define SDE_PICAINTERRUPT REG_BIT(31)
> -#define SDE_GMBUS_ICP (1 << 23)
> -#define SDE_TC_HOTPLUG_ICP(hpd_pin) REG_BIT(24 +
> _HPD_PIN_TC(hpd_pin))
> -#define SDE_TC_HOTPLUG_DG2(hpd_pin) REG_BIT(25 +
> _HPD_PIN_TC(hpd_pin)) /* sigh */
> -#define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 +
> _HPD_PIN_DDI(hpd_pin))
> -#define SDE_DDI_HOTPLUG_MASK_ICP
> (SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \
> -
> SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
> -
> SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
> -
> SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
> -#define SDE_TC_HOTPLUG_MASK_ICP
> (SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \
> -
> SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \
> -
> SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \
> -
> SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \
> -
> SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \
> -
> SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))
> -
> #define SDEISR _MMIO(0xc4000)
> #define SDEIMR _MMIO(0xc4004)
> #define SDEIIR _MMIO(0xc4008)
> @@ -2692,340 +1102,12 @@
> #define SERR_INT_POISON (1 << 31)
> #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
>
> -/* digital port hotplug */
> -#define PCH_PORT_HOTPLUG _MMIO(0xc4030) /*
> SHOTPLUG_CTL */
> -#define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */
> -#define BXT_DDIA_HPD_INVERT (1 << 27)
> -#define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */
> -#define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */
> -#define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */
> -#define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */
> -#define PORTD_HOTPLUG_ENABLE (1 << 20)
> -#define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */
> -#define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */
> -#define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */
> -#define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */
> -#define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */
> -#define PORTD_HOTPLUG_STATUS_MASK (3 << 16)
> -#define PORTD_HOTPLUG_NO_DETECT (0 << 16)
> -#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
> -#define PORTD_HOTPLUG_LONG_DETECT (2 << 16)
> -#define PORTC_HOTPLUG_ENABLE (1 << 12)
> -#define BXT_DDIC_HPD_INVERT (1 << 11)
> -#define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */
> -#define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */
> -#define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */
> -#define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */
> -#define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */
> -#define PORTC_HOTPLUG_STATUS_MASK (3 << 8)
> -#define PORTC_HOTPLUG_NO_DETECT (0 << 8)
> -#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
> -#define PORTC_HOTPLUG_LONG_DETECT (2 << 8)
> -#define PORTB_HOTPLUG_ENABLE (1 << 4)
> -#define BXT_DDIB_HPD_INVERT (1 << 3)
> -#define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */
> -#define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */
> -#define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */
> -#define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */
> -#define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */
> -#define PORTB_HOTPLUG_STATUS_MASK (3 << 0)
> -#define PORTB_HOTPLUG_NO_DETECT (0 << 0)
> -#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
> -#define PORTB_HOTPLUG_LONG_DETECT (2 << 0)
> -#define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \
> - BXT_DDIB_HPD_INVERT | \
> - BXT_DDIC_HPD_INVERT)
> -
> -#define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /*
> SHOTPLUG_CTL2 SPT+ */
> -#define PORTE_HOTPLUG_ENABLE (1 << 4)
> -#define PORTE_HOTPLUG_STATUS_MASK (3 << 0)
> -#define PORTE_HOTPLUG_NO_DETECT (0 << 0)
> -#define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)
> -#define PORTE_HOTPLUG_LONG_DETECT (2 << 0)
> -
> -/* This register is a reuse of PCH_PORT_HOTPLUG register. The
> - * functionality covered in PCH_PORT_HOTPLUG is split into
> - * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
> - */
> -#define SHOTPLUG_CTL_DDI _MMIO(0xc4030)
> -#define SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin) (0x8
> << (_HPD_PIN_DDI(hpd_pin) * 4))
> -#define SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(hpd_pin) (0x4
> << (_HPD_PIN_DDI(hpd_pin) * 4))
> -#define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin) (0x3
> << (_HPD_PIN_DDI(hpd_pin) * 4))
> -#define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin) (0x0
> << (_HPD_PIN_DDI(hpd_pin) * 4))
> -#define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin) (0x1
> << (_HPD_PIN_DDI(hpd_pin) * 4))
> -#define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(hpd_pin) (0x2
> << (_HPD_PIN_DDI(hpd_pin) * 4))
> -#define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin) (0x3
> << (_HPD_PIN_DDI(hpd_pin) * 4))
> -
> -#define SHOTPLUG_CTL_TC _MMIO(0xc4034)
> -#define ICP_TC_HPD_ENABLE(hpd_pin) (8 <<
> (_HPD_PIN_TC(hpd_pin) * 4))
> -#define ICP_TC_HPD_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin)
> * 4))
> -#define ICP_TC_HPD_SHORT_DETECT(hpd_pin) (1 <<
> (_HPD_PIN_TC(hpd_pin) * 4))
> -
> -#define SHPD_FILTER_CNT _MMIO(0xc4038)
> -#define SHPD_FILTER_CNT_500_ADJ 0x001D9
> -#define SHPD_FILTER_CNT_250 0x000F8
> -
> -#define _PCH_DPLL_A 0xc6014
> -#define _PCH_DPLL_B 0xc6018
> -#define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
> -
> -#define _PCH_FPA0 0xc6040
> -#define _PCH_FPB0 0xc6048
> -#define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0)
> -#define FP_CB_TUNE (0x3 << 22)
> -
> -#define _PCH_FPA1 0xc6044
> -#define _PCH_FPB1 0xc604c
> -#define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1)
> -
> -#define PCH_DPLL_TEST _MMIO(0xc606c)
> -
> -#define PCH_DREF_CONTROL _MMIO(0xC6200)
> -#define DREF_CONTROL_MASK 0x7fc3
> -#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13)
> -#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13)
> -#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13)
> -#define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13)
> -#define DREF_SSC_SOURCE_DISABLE (0 << 11)
> -#define DREF_SSC_SOURCE_ENABLE (2 << 11)
> -#define DREF_SSC_SOURCE_MASK (3 << 11)
> -#define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9)
> -#define DREF_NONSPREAD_CK505_ENABLE (1 << 9)
> -#define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9)
> -#define DREF_NONSPREAD_SOURCE_MASK (3 << 9)
> -#define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7)
> -#define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7)
> -#define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7)
> -#define DREF_SSC4_DOWNSPREAD (0 << 6)
> -#define DREF_SSC4_CENTERSPREAD (1 << 6)
> -#define DREF_SSC1_DISABLE (0 << 1)
> -#define DREF_SSC1_ENABLE (1 << 1)
> -#define DREF_SSC4_DISABLE (0)
> -#define DREF_SSC4_ENABLE (1)
> -
> -#define PCH_RAWCLK_FREQ _MMIO(0xc6204)
> -#define FDL_TP1_TIMER_SHIFT 12
> -#define FDL_TP1_TIMER_MASK (3 << 12)
> -#define FDL_TP2_TIMER_SHIFT 10
> -#define FDL_TP2_TIMER_MASK (3 << 10)
> -#define RAWCLK_FREQ_MASK 0x3ff
> -#define CNP_RAWCLK_DIV_MASK (0x3ff << 16)
> -#define CNP_RAWCLK_DIV(div) ((div) << 16)
> -#define CNP_RAWCLK_FRAC_MASK (0xf << 26)
> -#define CNP_RAWCLK_DEN(den) ((den) << 26)
> -#define ICP_RAWCLK_NUM(num) ((num) << 11)
> -
> -#define PCH_DPLL_TMR_CFG _MMIO(0xc6208)
> -
> -#define PCH_SSC4_PARMS _MMIO(0xc6210)
> -#define PCH_SSC4_AUX_PARMS _MMIO(0xc6214)
> -
> -#define PCH_DPLL_SEL _MMIO(0xc7000)
> -#define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4))
> -#define TRANS_DPLLA_SEL(pipe) 0
> -#define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3))
> -
> -/* transcoder */
> -#define _PCH_TRANS_HTOTAL_A 0xe0000
> -#define _PCH_TRANS_HTOTAL_B 0xe1000
> -#define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe,
> _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
> -#define TRANS_HTOTAL_SHIFT 16
> -#define TRANS_HACTIVE_SHIFT 0
> -
> -#define _PCH_TRANS_HBLANK_A 0xe0004
> -#define _PCH_TRANS_HBLANK_B 0xe1004
> -#define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe,
> _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
> -#define TRANS_HBLANK_END_SHIFT 16
> -#define TRANS_HBLANK_START_SHIFT 0
> -
> -#define _PCH_TRANS_HSYNC_A 0xe0008
> -#define _PCH_TRANS_HSYNC_B 0xe1008
> -#define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe,
> _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
> -#define TRANS_HSYNC_END_SHIFT 16
> -#define TRANS_HSYNC_START_SHIFT 0
> -
> -#define _PCH_TRANS_VTOTAL_A 0xe000c
> -#define _PCH_TRANS_VTOTAL_B 0xe100c
> -#define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe,
> _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
> -#define TRANS_VTOTAL_SHIFT 16
> -#define TRANS_VACTIVE_SHIFT 0
> -
> -#define _PCH_TRANS_VBLANK_A 0xe0010
> -#define _PCH_TRANS_VBLANK_B 0xe1010
> -#define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe,
> _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
> -#define TRANS_VBLANK_END_SHIFT 16
> -#define TRANS_VBLANK_START_SHIFT 0
> -
> -#define _PCH_TRANS_VSYNC_A 0xe0014
> -#define _PCH_TRANS_VSYNC_B 0xe1014
> -#define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe,
> _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
> -#define TRANS_VSYNC_END_SHIFT 16
> -#define TRANS_VSYNC_START_SHIFT 0
> -
> -#define _PCH_TRANS_VSYNCSHIFT_A 0xe0028
> -#define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
> -#define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe,
> _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)
> -
> -#define _PCH_TRANSA_DATA_M1 0xe0030
> -#define _PCH_TRANSB_DATA_M1 0xe1030
> -#define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe,
> _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
> -
> -#define _PCH_TRANSA_DATA_N1 0xe0034
> -#define _PCH_TRANSB_DATA_N1 0xe1034
> -#define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe,
> _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
> -
> -#define _PCH_TRANSA_DATA_M2 0xe0038
> -#define _PCH_TRANSB_DATA_M2 0xe1038
> -#define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe,
> _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
> -
> -#define _PCH_TRANSA_DATA_N2 0xe003c
> -#define _PCH_TRANSB_DATA_N2 0xe103c
> -#define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe,
> _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
> -
> -#define _PCH_TRANSA_LINK_M1 0xe0040
> -#define _PCH_TRANSB_LINK_M1 0xe1040
> -#define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe,
> _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
> -
> -#define _PCH_TRANSA_LINK_N1 0xe0044
> -#define _PCH_TRANSB_LINK_N1 0xe1044
> -#define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe,
> _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
> -
> -#define _PCH_TRANSA_LINK_M2 0xe0048
> -#define _PCH_TRANSB_LINK_M2 0xe1048
> -#define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe,
> _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
> -
> -#define _PCH_TRANSA_LINK_N2 0xe004c
> -#define _PCH_TRANSB_LINK_N2 0xe104c
> -#define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe,
> _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
> -
> -/* Per-transcoder DIP controls (PCH) */
> -#define _VIDEO_DIP_CTL_A 0xe0200
> -#define _VIDEO_DIP_CTL_B 0xe1200
> -#define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A,
> _VIDEO_DIP_CTL_B)
> -
> -#define _VIDEO_DIP_DATA_A 0xe0208
> -#define _VIDEO_DIP_DATA_B 0xe1208
> -#define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A,
> _VIDEO_DIP_DATA_B)
> -
> -#define _VIDEO_DIP_GCP_A 0xe0210
> -#define _VIDEO_DIP_GCP_B 0xe1210
> -#define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A,
> _VIDEO_DIP_GCP_B)
> -#define GCP_COLOR_INDICATION (1 << 2)
> -#define GCP_DEFAULT_PHASE_ENABLE (1 << 1)
> -#define GCP_AV_MUTE (1 << 0)
> -
> -/* Per-transcoder DIP controls (VLV) */
> -#define _VLV_VIDEO_DIP_CTL_A 0x60200
> -#define _VLV_VIDEO_DIP_CTL_B 0x61170
> -#define _CHV_VIDEO_DIP_CTL_C 0x611f0
> -#define VLV_TVIDEO_DIP_CTL(pipe)
> _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \
> -
> _VLV_VIDEO_DIP_CTL_A, \
> -
> _VLV_VIDEO_DIP_CTL_B, \
> -
> _CHV_VIDEO_DIP_CTL_C)
> -
> -#define _VLV_VIDEO_DIP_DATA_A 0x60208
> -#define _VLV_VIDEO_DIP_DATA_B 0x61174
> -#define _CHV_VIDEO_DIP_DATA_C 0x611f4
> -#define VLV_TVIDEO_DIP_DATA(pipe)
> _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \
> -
> _VLV_VIDEO_DIP_DATA_A, \
> -
> _VLV_VIDEO_DIP_DATA_B, \
> -
> _CHV_VIDEO_DIP_DATA_C)
> -
> -#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A 0x60210
> -#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B 0x61178
> -#define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C 0x611f8
> -#define VLV_TVIDEO_DIP_GCP(pipe)
> _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \
> -
> _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
> -
> _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, \
> -
> _CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
> -
> -/* Haswell DIP controls */
> -#define _HSW_VIDEO_DIP_CTL_A 0x60200
> -#define _HSW_VIDEO_DIP_CTL_B 0x61200
> -#define HSW_TVIDEO_DIP_CTL(dev_priv, trans)
> _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_CTL_A)
> -
> -#define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220
> -#define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220
> -#define HSW_TVIDEO_DIP_AVI_DATA(dev_priv, trans, i)
> _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i)
> * 4)
> -
> -#define _HSW_VIDEO_DIP_VS_DATA_A 0x60260
> -#define _HSW_VIDEO_DIP_VS_DATA_B 0x61260
> -#define HSW_TVIDEO_DIP_VS_DATA(dev_priv, trans, i)
> _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) *
> 4)
> -
> -#define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
> -#define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
> -#define HSW_TVIDEO_DIP_SPD_DATA(dev_priv, trans, i)
> _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i)
> * 4)
> -
> -#define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
> -#define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
> -#define HSW_TVIDEO_DIP_GMP_DATA(dev_priv, trans, i)
> _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i)
> * 4)
> -
> -#define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320
> -#define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320
> -#define HSW_TVIDEO_DIP_VSC_DATA(dev_priv, trans, i)
> _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i)
> * 4)
> -
> -/*ADLP and later: */
> -#define _ADL_VIDEO_DIP_AS_DATA_A 0x60484
> -#define _ADL_VIDEO_DIP_AS_DATA_B 0x61484
> -#define ADL_TVIDEO_DIP_AS_SDP_DATA(dev_priv, trans, i)
> _MMIO_TRANS2(dev_priv, trans,\
> -
> _ADL_VIDEO_DIP_AS_DATA_A + (i) * 4)
> -
> -#define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440
> -#define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440
> -#define GLK_TVIDEO_DIP_DRM_DATA(dev_priv, trans, i)
> _MMIO_TRANS2(dev_priv, trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i)
> * 4)
> -
> -#define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240
> -#define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240
> -#define _HSW_VIDEO_DIP_VS_ECC_A 0x60280
> -#define _HSW_VIDEO_DIP_VS_ECC_B 0x61280
> -#define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
> -#define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
> -#define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300
> -#define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300
> -#define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344
> -#define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344
> -
> -#define _HSW_VIDEO_DIP_GCP_A 0x60210
> -#define _HSW_VIDEO_DIP_GCP_B 0x61210
> -#define HSW_TVIDEO_DIP_GCP(dev_priv, trans)
> _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GCP_A)
> -
> /* Icelake PPS_DATA and _ECC DIP Registers.
> * These are available for transcoders B,C and eDP.
> * Adding the _A so as to reuse the _MMIO_TRANS2
> * definition, with which it offsets to the right location.
> */
>
> -#define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350
> -#define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350
> -#define ICL_VIDEO_DIP_PPS_DATA(dev_priv, trans, i)
> _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) *
> 4)
> -
> -#define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4
> -#define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4
> -#define ICL_VIDEO_DIP_PPS_ECC(dev_priv, trans, i)
> _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
> -
> -#define _HSW_STEREO_3D_CTL_A 0x70020
> -#define _HSW_STEREO_3D_CTL_B 0x71020
> -#define HSW_STEREO_3D_CTL(dev_priv, trans) _MMIO_PIPE2(dev_priv, trans,
> _HSW_STEREO_3D_CTL_A)
> -#define S3D_ENABLE (1 << 31)
> -
> -#define _PCH_TRANSACONF 0xf0008
> -#define _PCH_TRANSBCONF 0xf1008
> -#define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe,
> _PCH_TRANSACONF, _PCH_TRANSBCONF)
> -#define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has
> only one transcoder */
> -#define TRANS_ENABLE REG_BIT(31)
> -#define TRANS_STATE_ENABLE REG_BIT(30)
> -#define TRANS_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* ibx
> */
> -#define TRANS_FRAME_START_DELAY(x)
> REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3
> */
> -#define TRANS_INTERLACE_MASK REG_GENMASK(23, 21)
> -#define TRANS_INTERLACE_PROGRESSIVE
> REG_FIELD_PREP(TRANS_INTERLACE_MASK, 0)
> -#define TRANS_INTERLACE_LEGACY_VSYNC_IBX
> REG_FIELD_PREP(TRANS_INTERLACE_MASK, 2) /* ibx */
> -#define TRANS_INTERLACE_INTERLACED
> REG_FIELD_PREP(TRANS_INTERLACE_MASK, 3)
> -#define TRANS_BPC_MASK REG_GENMASK(7, 5) /* ibx */
> -#define TRANS_BPC_8 REG_FIELD_PREP(TRANS_BPC_MASK,
> 0)
> -#define TRANS_BPC_10
> REG_FIELD_PREP(TRANS_BPC_MASK, 1)
> -#define TRANS_BPC_6 REG_FIELD_PREP(TRANS_BPC_MASK,
> 2)
> -#define TRANS_BPC_12
> REG_FIELD_PREP(TRANS_BPC_MASK, 3)
> -
> #define _TRANSA_CHICKEN1 0xf0060
> #define _TRANSB_CHICKEN1 0xf1060
> #define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe,
> _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
> @@ -3078,88 +1160,6 @@
> #define CNP_PWM_CGE_GATING_DISABLE (1 << 13)
> #define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12)
>
> -#define PCH_DP_B _MMIO(0xe4100)
> -#define PCH_DP_C _MMIO(0xe4200)
> -#define PCH_DP_D _MMIO(0xe4300)
> -
> -/* CPT */
> -#define _TRANS_DP_CTL_A 0xe0300
> -#define _TRANS_DP_CTL_B 0xe1300
> -#define _TRANS_DP_CTL_C 0xe2300
> -#define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A,
> _TRANS_DP_CTL_B)
> -#define TRANS_DP_OUTPUT_ENABLE REG_BIT(31)
> -#define TRANS_DP_PORT_SEL_MASK REG_GENMASK(30, 29)
> -#define TRANS_DP_PORT_SEL_NONE
> REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, 3)
> -#define TRANS_DP_PORT_SEL(port)
> REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, (port) - PORT_B)
> -#define TRANS_DP_AUDIO_ONLY REG_BIT(26)
> -#define TRANS_DP_ENH_FRAMING REG_BIT(18)
> -#define TRANS_DP_BPC_MASK REG_GENMASK(10, 9)
> -#define TRANS_DP_BPC_8
> REG_FIELD_PREP(TRANS_DP_BPC_MASK, 0)
> -#define TRANS_DP_BPC_10
> REG_FIELD_PREP(TRANS_DP_BPC_MASK, 1)
> -#define TRANS_DP_BPC_6
> REG_FIELD_PREP(TRANS_DP_BPC_MASK, 2)
> -#define TRANS_DP_BPC_12
> REG_FIELD_PREP(TRANS_DP_BPC_MASK, 3)
> -#define TRANS_DP_VSYNC_ACTIVE_HIGH REG_BIT(4)
> -#define TRANS_DP_HSYNC_ACTIVE_HIGH REG_BIT(3)
> -
> -#define _TRANS_DP2_CTL_A 0x600a0
> -#define _TRANS_DP2_CTL_B 0x610a0
> -#define _TRANS_DP2_CTL_C 0x620a0
> -#define _TRANS_DP2_CTL_D 0x630a0
> -#define TRANS_DP2_CTL(trans) _MMIO_TRANS(trans,
> _TRANS_DP2_CTL_A, _TRANS_DP2_CTL_B)
> -#define TRANS_DP2_128B132B_CHANNEL_CODING REG_BIT(31)
> -#define TRANS_DP2_PANEL_REPLAY_ENABLE REG_BIT(30)
> -#define TRANS_DP2_DEBUG_ENABLE REG_BIT(23)
> -
> -#define _TRANS_DP2_VFREQHIGH_A 0x600a4
> -#define _TRANS_DP2_VFREQHIGH_B 0x610a4
> -#define _TRANS_DP2_VFREQHIGH_C 0x620a4
> -#define _TRANS_DP2_VFREQHIGH_D 0x630a4
> -#define TRANS_DP2_VFREQHIGH(trans) _MMIO_TRANS(trans,
> _TRANS_DP2_VFREQHIGH_A, _TRANS_DP2_VFREQHIGH_B)
> -#define TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK REG_GENMASK(31, 8)
> -#define TRANS_DP2_VFREQ_PIXEL_CLOCK(clk_hz)
> REG_FIELD_PREP(TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK, (clk_hz))
> -
> -#define _TRANS_DP2_VFREQLOW_A 0x600a8
> -#define _TRANS_DP2_VFREQLOW_B 0x610a8
> -#define _TRANS_DP2_VFREQLOW_C 0x620a8
> -#define _TRANS_DP2_VFREQLOW_D 0x630a8
> -#define TRANS_DP2_VFREQLOW(trans) _MMIO_TRANS(trans,
> _TRANS_DP2_VFREQLOW_A, _TRANS_DP2_VFREQLOW_B)
> -
> -#define _DP_MIN_HBLANK_CTL_A 0x600ac
> -#define _DP_MIN_HBLANK_CTL_B 0x610ac
> -#define DP_MIN_HBLANK_CTL(trans) _MMIO_TRANS(trans,
> _DP_MIN_HBLANK_CTL_A, _DP_MIN_HBLANK_CTL_B)
> -
> -/* SNB eDP training params */
> -/* SNB A-stepping */
> -#define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22)
> -#define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22)
> -#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22)
> -#define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22)
> -/* SNB B-stepping */
> -#define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0 << 22)
> -#define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1 << 22)
> -#define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a << 22)
> -#define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39 << 22)
> -#define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38 << 22)
> -#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f << 22)
> -
> -/* IVB */
> -#define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 << 22)
> -#define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a << 22)
> -#define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f << 22)
> -#define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 << 22)
> -#define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 << 22)
> -#define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 << 22)
> -#define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e << 22)
> -
> -/* legacy values */
> -#define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 << 22)
> -#define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 << 22)
> -#define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 << 22)
> -#define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 << 22)
> -#define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 << 22)
> -
> -#define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f << 22)
> -
> #define VLV_PMWGICZ _MMIO(0x1300a4)
>
> #define HSW_EDRAM_CAP _MMIO(0x120010)
> @@ -3168,10 +1168,6 @@
> #define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7)
> #define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3)
>
> -#define VLV_CHICKEN_3
> _MMIO(VLV_DISPLAY_BASE + 0x7040C)
> -#define PIXEL_OVERLAP_CNT_MASK (3 << 30)
> -#define PIXEL_OVERLAP_CNT_SHIFT 30
> -
> #define GEN6_PCODE_MAILBOX _MMIO(0x138124)
> #define GEN6_PCODE_READY (1 << 31)
> #define GEN6_PCODE_MB_PARAM2 REG_GENMASK(23,
> 16)
> @@ -3300,110 +1296,6 @@
> */
> #define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4)
>
> -/*
> - * HSW - ICL power wells
> - *
> - * Platforms have up to 3 power well control register sets, each set
> - * controlling up to 16 power wells via a request/status HW flag tuple:
> - * - main (HSW_PWR_WELL_CTL[1-4])
> - * - AUX (ICL_PWR_WELL_CTL_AUX[1-4])
> - * - DDI (ICL_PWR_WELL_CTL_DDI[1-4])
> - * Each control register set consists of up to 4 registers used by different
> - * sources that can request a power well to be enabled:
> - * - BIOS
> (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI
> 1)
> - * - DRIVER
> (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI
> 2)
> - * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set)
> - * - DEBUG
> (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI
> 4)
> - */
> -#define HSW_PWR_WELL_CTL1 _MMIO(0x45400)
> -#define HSW_PWR_WELL_CTL2 _MMIO(0x45404)
> -#define HSW_PWR_WELL_CTL3 _MMIO(0x45408)
> -#define HSW_PWR_WELL_CTL4 _MMIO(0x4540C)
> -#define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2))
> -#define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2))
> -
> -/* HSW/BDW power well */
> -#define HSW_PW_CTL_IDX_GLOBAL 15
> -
> -/* SKL/BXT/GLK power wells */
> -#define SKL_PW_CTL_IDX_PW_2 15
> -#define SKL_PW_CTL_IDX_PW_1 14
> -#define GLK_PW_CTL_IDX_AUX_C 10
> -#define GLK_PW_CTL_IDX_AUX_B 9
> -#define GLK_PW_CTL_IDX_AUX_A 8
> -#define SKL_PW_CTL_IDX_DDI_D 4
> -#define SKL_PW_CTL_IDX_DDI_C 3
> -#define SKL_PW_CTL_IDX_DDI_B 2
> -#define SKL_PW_CTL_IDX_DDI_A_E 1
> -#define GLK_PW_CTL_IDX_DDI_A 1
> -#define SKL_PW_CTL_IDX_MISC_IO 0
> -
> -/* ICL/TGL - power wells */
> -#define TGL_PW_CTL_IDX_PW_5 4
> -#define ICL_PW_CTL_IDX_PW_4 3
> -#define ICL_PW_CTL_IDX_PW_3 2
> -#define ICL_PW_CTL_IDX_PW_2 1
> -#define ICL_PW_CTL_IDX_PW_1 0
> -
> -/* XE_LPD - power wells */
> -#define XELPD_PW_CTL_IDX_PW_D 8
> -#define XELPD_PW_CTL_IDX_PW_C 7
> -#define XELPD_PW_CTL_IDX_PW_B 6
> -#define XELPD_PW_CTL_IDX_PW_A 5
> -
> -#define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440)
> -#define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444)
> -#define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C)
> -#define TGL_PW_CTL_IDX_AUX_TBT6 14
> -#define TGL_PW_CTL_IDX_AUX_TBT5 13
> -#define TGL_PW_CTL_IDX_AUX_TBT4 12
> -#define ICL_PW_CTL_IDX_AUX_TBT4 11
> -#define TGL_PW_CTL_IDX_AUX_TBT3 11
> -#define ICL_PW_CTL_IDX_AUX_TBT3 10
> -#define TGL_PW_CTL_IDX_AUX_TBT2 10
> -#define ICL_PW_CTL_IDX_AUX_TBT2 9
> -#define TGL_PW_CTL_IDX_AUX_TBT1 9
> -#define ICL_PW_CTL_IDX_AUX_TBT1 8
> -#define TGL_PW_CTL_IDX_AUX_TC6 8
> -#define XELPD_PW_CTL_IDX_AUX_E 8
> -#define TGL_PW_CTL_IDX_AUX_TC5 7
> -#define XELPD_PW_CTL_IDX_AUX_D 7
> -#define TGL_PW_CTL_IDX_AUX_TC4 6
> -#define ICL_PW_CTL_IDX_AUX_F 5
> -#define TGL_PW_CTL_IDX_AUX_TC3 5
> -#define ICL_PW_CTL_IDX_AUX_E 4
> -#define TGL_PW_CTL_IDX_AUX_TC2 4
> -#define ICL_PW_CTL_IDX_AUX_D 3
> -#define TGL_PW_CTL_IDX_AUX_TC1 3
> -#define ICL_PW_CTL_IDX_AUX_C 2
> -#define ICL_PW_CTL_IDX_AUX_B 1
> -#define ICL_PW_CTL_IDX_AUX_A 0
> -
> -#define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450)
> -#define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454)
> -#define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C)
> -#define XELPD_PW_CTL_IDX_DDI_E 8
> -#define TGL_PW_CTL_IDX_DDI_TC6 8
> -#define XELPD_PW_CTL_IDX_DDI_D 7
> -#define TGL_PW_CTL_IDX_DDI_TC5 7
> -#define TGL_PW_CTL_IDX_DDI_TC4 6
> -#define ICL_PW_CTL_IDX_DDI_F 5
> -#define TGL_PW_CTL_IDX_DDI_TC3 5
> -#define ICL_PW_CTL_IDX_DDI_E 4
> -#define TGL_PW_CTL_IDX_DDI_TC2 4
> -#define ICL_PW_CTL_IDX_DDI_D 3
> -#define TGL_PW_CTL_IDX_DDI_TC1 3
> -#define ICL_PW_CTL_IDX_DDI_C 2
> -#define ICL_PW_CTL_IDX_DDI_B 1
> -#define ICL_PW_CTL_IDX_DDI_A 0
> -
> -/* HSW - power well misc debug registers */
> -#define HSW_PWR_WELL_CTL5 _MMIO(0x45410)
> -#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31)
> -#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20)
> -#define HSW_PWR_WELL_FORCE_ON (1 << 19)
> -#define HSW_PWR_WELL_CTL6 _MMIO(0x45414)
> -
> /* SKL Fuse Status */
> enum skl_power_gate {
> SKL_PG0,
> @@ -3413,193 +1305,6 @@ enum skl_power_gate {
> ICL_PG4,
> };
>
> -#define SKL_FUSE_STATUS _MMIO(0x42000)
> -#define SKL_FUSE_DOWNLOAD_STATUS (1 << 31)
> -/*
> - * PG0 is HW controlled, so doesn't have a corresponding power well control
> knob
> - * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2
> - */
> -#define SKL_PW_CTL_IDX_TO_PG(pw_idx) \
> - ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1)
> -/*
> - * PG0 is HW controlled, so doesn't have a corresponding power well control
> knob
> - * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4
> - */
> -#define ICL_PW_CTL_IDX_TO_PG(pw_idx) \
> - ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1)
> -#define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
> -
> -/* Per-pipe DDI Function Control */
> -#define _TRANS_DDI_FUNC_CTL_A 0x60400
> -#define _TRANS_DDI_FUNC_CTL_B 0x61400
> -#define _TRANS_DDI_FUNC_CTL_C 0x62400
> -#define _TRANS_DDI_FUNC_CTL_D 0x63400
> -#define _TRANS_DDI_FUNC_CTL_EDP 0x6F400
> -#define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400
> -#define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00
> -#define TRANS_DDI_FUNC_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv,
> tran, _TRANS_DDI_FUNC_CTL_A)
> -
> -#define TRANS_DDI_FUNC_ENABLE (1 << 31)
> -/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
> -#define TRANS_DDI_PORT_SHIFT 28
> -#define TGL_TRANS_DDI_PORT_SHIFT 27
> -#define TRANS_DDI_PORT_MASK (7 <<
> TRANS_DDI_PORT_SHIFT)
> -#define TGL_TRANS_DDI_PORT_MASK (0xf << TGL_TRANS_DDI_PORT_SHIFT)
> -#define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT)
> -#define TGL_TRANS_DDI_SELECT_PORT(x) (((x) + 1) <<
> TGL_TRANS_DDI_PORT_SHIFT)
> -#define TRANS_DDI_MODE_SELECT_MASK (7 << 24)
> -#define TRANS_DDI_MODE_SELECT_HDMI (0 << 24)
> -#define TRANS_DDI_MODE_SELECT_DVI (1 << 24)
> -#define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24)
> -#define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24)
> -#define TRANS_DDI_MODE_SELECT_FDI_OR_128B132B (4 << 24)
> -#define TRANS_DDI_BPC_MASK (7 << 20)
> -#define TRANS_DDI_BPC_8 (0 << 20)
> -#define TRANS_DDI_BPC_10 (1 << 20)
> -#define TRANS_DDI_BPC_6 (2 << 20)
> -#define TRANS_DDI_BPC_12 (3 << 20)
> -#define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK
> REG_GENMASK(19, 18)
> -#define TRANS_DDI_PORT_SYNC_MASTER_SELECT(x)
> REG_FIELD_PREP(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK,
> (x))
> -#define TRANS_DDI_PVSYNC (1 << 17)
> -#define TRANS_DDI_PHSYNC (1 << 16)
> -#define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15)
> -#define XE3_TRANS_DDI_HDCP_LINE_REKEY_DISABLE REG_BIT(15)
> -#define TRANS_DDI_EDP_INPUT_MASK (7 << 12)
> -#define TRANS_DDI_EDP_INPUT_A_ON (0 << 12)
> -#define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12)
> -#define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12)
> -#define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12)
> -#define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12)
> -#define TRANS_DDI_HDCP_LINE_REKEY_DISABLE REG_BIT(12)
> -#define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11,
> 10)
> -#define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \
> - REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans)
> -#define TRANS_DDI_HDCP_SIGNALLING (1 << 9)
> -#define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8)
> -#define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7)
> -#define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6)
> -#define TRANS_DDI_HDCP_SELECT REG_BIT(5)
> -#define TRANS_DDI_BFI_ENABLE (1 << 4)
> -#define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4)
> -#define TRANS_DDI_PORT_WIDTH_MASK REG_GENMASK(3, 1)
> -#define TRANS_DDI_PORT_WIDTH(width)
> REG_FIELD_PREP(TRANS_DDI_PORT_WIDTH_MASK, (width) - 1)
> -#define TRANS_DDI_HDMI_SCRAMBLING (1 << 0)
> -#define TRANS_DDI_HDMI_SCRAMBLING_MASK
> (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \
> - |
> TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \
> - | TRANS_DDI_HDMI_SCRAMBLING)
> -
> -#define _TRANS_DDI_FUNC_CTL2_A 0x60404
> -#define _TRANS_DDI_FUNC_CTL2_B 0x61404
> -#define _TRANS_DDI_FUNC_CTL2_C 0x62404
> -#define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404
> -#define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404
> -#define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04
> -#define TRANS_DDI_FUNC_CTL2(dev_priv, tran)
> _MMIO_TRANS2(dev_priv, tran, _TRANS_DDI_FUNC_CTL2_A)
> -#define PORT_SYNC_MODE_ENABLE REG_BIT(4)
> -#define CMTG_SECONDARY_MODE REG_BIT(3)
> -#define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0)
> -#define PORT_SYNC_MODE_MASTER_SELECT(x)
> REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x))
> -
> -#define TRANS_CMTG_CHICKEN _MMIO(0x6fa90)
> -#define DISABLE_DPT_CLK_GATING REG_BIT(1)
> -
> -/* DisplayPort Transport Control */
> -#define _DP_TP_CTL_A 0x64040
> -#define _DP_TP_CTL_B 0x64140
> -#define _TGL_DP_TP_CTL_A 0x60540
> -#define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
> -#define TGL_DP_TP_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, (tran),
> _TGL_DP_TP_CTL_A)
> -#define DP_TP_CTL_ENABLE REG_BIT(31)
> -#define DP_TP_CTL_FEC_ENABLE REG_BIT(30)
> -#define DP_TP_CTL_MODE_MASK REG_BIT(27)
> -#define DP_TP_CTL_MODE_SST
> REG_FIELD_PREP(DP_TP_CTL_MODE_MASK, 0)
> -#define DP_TP_CTL_MODE_MST
> REG_FIELD_PREP(DP_TP_CTL_MODE_MASK, 1)
> -#define DP_TP_CTL_FORCE_ACT REG_BIT(25)
> -#define DP_TP_CTL_TRAIN_PAT4_SEL_MASK REG_GENMASK(20,
> 19)
> -#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4A
> REG_FIELD_PREP(DP_TP_CTL_TRAIN_PAT4_SEL_MASK, 0)
> -#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4B
> REG_FIELD_PREP(DP_TP_CTL_TRAIN_PAT4_SEL_MASK, 1)
> -#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4C
> REG_FIELD_PREP(DP_TP_CTL_TRAIN_PAT4_SEL_MASK, 2)
> -#define DP_TP_CTL_ENHANCED_FRAME_ENABLE REG_BIT(18)
> -#define DP_TP_CTL_FDI_AUTOTRAIN REG_BIT(15)
> -#define DP_TP_CTL_LINK_TRAIN_MASK REG_GENMASK(10, 8)
> -#define DP_TP_CTL_LINK_TRAIN_PAT1
> REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 0)
> -#define DP_TP_CTL_LINK_TRAIN_PAT2
> REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 1)
> -#define DP_TP_CTL_LINK_TRAIN_PAT3
> REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 4)
> -#define DP_TP_CTL_LINK_TRAIN_PAT4
> REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 5)
> -#define DP_TP_CTL_LINK_TRAIN_IDLE
> REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 2)
> -#define DP_TP_CTL_LINK_TRAIN_NORMAL
> REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 3)
> -#define DP_TP_CTL_SCRAMBLE_DISABLE REG_BIT(7)
> -
> -/* DisplayPort Transport Status */
> -#define _DP_TP_STATUS_A 0x64044
> -#define _DP_TP_STATUS_B 0x64144
> -#define _TGL_DP_TP_STATUS_A 0x60544
> -#define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A,
> _DP_TP_STATUS_B)
> -#define TGL_DP_TP_STATUS(dev_priv, tran) _MMIO_TRANS2(dev_priv, (tran),
> _TGL_DP_TP_STATUS_A)
> -#define DP_TP_STATUS_FEC_ENABLE_LIVE REG_BIT(28)
> -#define DP_TP_STATUS_IDLE_DONE REG_BIT(25)
> -#define DP_TP_STATUS_ACT_SENT REG_BIT(24)
> -#define DP_TP_STATUS_MODE_STATUS_MST REG_BIT(23)
> -#define DP_TP_STATUS_STREAMS_ENABLED_MASK REG_GENMASK(18,
> 16) /* 17:16 on hsw but bit 18 mbz */
> -#define DP_TP_STATUS_AUTOTRAIN_DONE REG_BIT(12)
> -#define DP_TP_STATUS_PAYLOAD_MAPPING_VC2_MASK REG_GENMASK(9,
> 8)
> -#define DP_TP_STATUS_PAYLOAD_MAPPING_VC1_MASK
> REG_GENMASK(5, 4)
> -#define DP_TP_STATUS_PAYLOAD_MAPPING_VC0_MASK
> REG_GENMASK(1, 0)
> -
> -/* DDI Buffer Control */
> -#define _DDI_BUF_CTL_A 0x64000
> -#define _DDI_BUF_CTL_B 0x64100
> -/* Known as DDI_CTL_DE in MTL+ */
> -#define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A,
> _DDI_BUF_CTL_B)
> -#define DDI_BUF_CTL_ENABLE REG_BIT(31)
> -#define XE2LPD_DDI_BUF_D2D_LINK_ENABLE REG_BIT(29)
> -#define XE2LPD_DDI_BUF_D2D_LINK_STATE REG_BIT(28)
> -#define DDI_BUF_EMP_MASK REG_GENMASK(27, 24)
> -#define DDI_BUF_TRANS_SELECT(n)
> REG_FIELD_PREP(DDI_BUF_EMP_MASK, (n))
> -#define DDI_BUF_PHY_LINK_RATE_MASK REG_GENMASK(23,
> 20)
> -#define DDI_BUF_PHY_LINK_RATE(r)
> REG_FIELD_PREP(DDI_BUF_PHY_LINK_RATE_MASK, (r))
> -#define DDI_BUF_PORT_DATA_MASK REG_GENMASK(19,
> 18)
> -#define DDI_BUF_PORT_DATA_10BIT
> REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 0)
> -#define DDI_BUF_PORT_DATA_20BIT
> REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 1)
> -#define DDI_BUF_PORT_DATA_40BIT
> REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 2)
> -#define DDI_BUF_PORT_REVERSAL REG_BIT(16)
> -#define DDI_BUF_LANE_STAGGER_DELAY_MASK REG_GENMASK(15, 8)
> -#define DDI_BUF_LANE_STAGGER_DELAY(symbols)
> REG_FIELD_PREP(DDI_BUF_LANE_STAGGER_DELAY_MASK, \
> - (symbols))
> -#define DDI_BUF_IS_IDLE REG_BIT(7)
> -#define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6)
> -#define DDI_A_4_LANES REG_BIT(4)
> -#define DDI_PORT_WIDTH_MASK REG_GENMASK(3, 1)
> -#define DDI_PORT_WIDTH(width)
> REG_FIELD_PREP(DDI_PORT_WIDTH_MASK, \
> - ((width) == 3 ? 4 :
> (width) - 1))
> -#define DDI_PORT_WIDTH_SHIFT 1
> -#define DDI_INIT_DISPLAY_DETECTED REG_BIT(0)
> -
> -/* DDI Buffer Translations */
> -#define _DDI_BUF_TRANS_A 0x64E00
> -#define _DDI_BUF_TRANS_B 0x64E60
> -#define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port,
> _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)
> -#define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
> -#define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port,
> _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
> -
> -/* DDI DP Compliance Control */
> -#define _DDI_DP_COMP_CTL_A 0x605F0
> -#define _DDI_DP_COMP_CTL_B 0x615F0
> -#define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe,
> _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B)
> -#define DDI_DP_COMP_CTL_ENABLE (1 << 31)
> -#define DDI_DP_COMP_CTL_D10_2 (0 << 28)
> -#define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28)
> -#define DDI_DP_COMP_CTL_PRBS7 (2 << 28)
> -#define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28)
> -#define DDI_DP_COMP_CTL_HBR2 (4 << 28)
> -#define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28)
> -#define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0)
> -
> -/* DDI DP Compliance Pattern */
> -#define _DDI_DP_COMP_PAT_A 0x605F4
> -#define _DDI_DP_COMP_PAT_B 0x615F4
> -#define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe,
> _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4)
> -
> /* Sideband Interface (SBI) is programmed indirectly, via
> * SBI_ADDR, which contains the register offset; and SBI_DATA,
> * which contains the payload */
> @@ -3617,489 +1322,6 @@ enum skl_power_gate {
> #define SBI_BUSY (0x1 << 0)
> #define SBI_READY (0x0 << 0)
>
> -/* SBI offsets */
> -#define SBI_SSCDIVINTPHASE 0x0200
> -#define SBI_SSCDIVINTPHASE6 0x0600
> -#define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1
> -#define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1)
> -#define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1)
> -#define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8
> -#define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8)
> -#define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8)
> -#define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15)
> -#define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0)
> -#define SBI_SSCDITHPHASE 0x0204
> -#define SBI_SSCCTL 0x020c
> -#define SBI_SSCCTL6 0x060C
> -#define SBI_SSCCTL_PATHALT (1 << 3)
> -#define SBI_SSCCTL_DISABLE (1 << 0)
> -#define SBI_SSCAUXDIV6 0x0610
> -#define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4
> -#define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4)
> -#define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4)
> -#define SBI_DBUFF0 0x2a00
> -#define SBI_GEN0 0x1f00
> -#define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0)
> -
> -/* LPT PIXCLK_GATE */
> -#define PIXCLK_GATE _MMIO(0xC6020)
> -#define PIXCLK_GATE_UNGATE (1 << 0)
> -#define PIXCLK_GATE_GATE (0 << 0)
> -
> -/* SPLL */
> -#define SPLL_CTL _MMIO(0x46020)
> -#define SPLL_PLL_ENABLE (1 << 31)
> -#define SPLL_REF_BCLK (0 << 28)
> -#define SPLL_REF_MUXED_SSC (1 << 28) /* CPU SSC if fused
> enabled, PCH SSC otherwise */
> -#define SPLL_REF_NON_SSC_HSW (2 << 28)
> -#define SPLL_REF_PCH_SSC_BDW (2 << 28)
> -#define SPLL_REF_LCPLL (3 << 28)
> -#define SPLL_REF_MASK (3 << 28)
> -#define SPLL_FREQ_810MHz (0 << 26)
> -#define SPLL_FREQ_1350MHz (1 << 26)
> -#define SPLL_FREQ_2700MHz (2 << 26)
> -#define SPLL_FREQ_MASK (3 << 26)
> -
> -/* WRPLL */
> -#define _WRPLL_CTL1 0x46040
> -#define _WRPLL_CTL2 0x46060
> -#define WRPLL_CTL(pll) _MMIO_PIPE(pll,
> _WRPLL_CTL1, _WRPLL_CTL2)
> -#define WRPLL_PLL_ENABLE (1 << 31)
> -#define WRPLL_REF_BCLK (0 << 28)
> -#define WRPLL_REF_PCH_SSC (1 << 28)
> -#define WRPLL_REF_MUXED_SSC_BDW (2 << 28) /* CPU SSC if fused
> enabled, PCH SSC otherwise */
> -#define WRPLL_REF_SPECIAL_HSW (2 << 28) /* muxed SSC (ULT),
> non-SSC (non-ULT) */
> -#define WRPLL_REF_LCPLL (3 << 28)
> -#define WRPLL_REF_MASK (3 << 28)
> -/* WRPLL divider programming */
> -#define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0)
> -#define WRPLL_DIVIDER_REF_MASK (0xff)
> -#define WRPLL_DIVIDER_POST(x) ((x) << 8)
> -#define WRPLL_DIVIDER_POST_MASK (0x3f << 8)
> -#define WRPLL_DIVIDER_POST_SHIFT 8
> -#define WRPLL_DIVIDER_FEEDBACK(x) ((x) << 16)
> -#define WRPLL_DIVIDER_FB_SHIFT 16
> -#define WRPLL_DIVIDER_FB_MASK (0xff << 16)
> -
> -/* Port clock selection */
> -#define _PORT_CLK_SEL_A 0x46100
> -#define _PORT_CLK_SEL_B 0x46104
> -#define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A,
> _PORT_CLK_SEL_B)
> -#define PORT_CLK_SEL_MASK REG_GENMASK(31, 29)
> -#define PORT_CLK_SEL_LCPLL_2700
> REG_FIELD_PREP(PORT_CLK_SEL_MASK, 0)
> -#define PORT_CLK_SEL_LCPLL_1350
> REG_FIELD_PREP(PORT_CLK_SEL_MASK, 1)
> -#define PORT_CLK_SEL_LCPLL_810
> REG_FIELD_PREP(PORT_CLK_SEL_MASK, 2)
> -#define PORT_CLK_SEL_SPLL
> REG_FIELD_PREP(PORT_CLK_SEL_MASK, 3)
> -#define PORT_CLK_SEL_WRPLL(pll)
> REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4 + (pll))
> -#define PORT_CLK_SEL_WRPLL1
> REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4)
> -#define PORT_CLK_SEL_WRPLL2
> REG_FIELD_PREP(PORT_CLK_SEL_MASK, 5)
> -#define PORT_CLK_SEL_NONE
> REG_FIELD_PREP(PORT_CLK_SEL_MASK, 7)
> -
> -/* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */
> -#define DDI_CLK_SEL(port) PORT_CLK_SEL(port)
> -#define DDI_CLK_SEL_MASK REG_GENMASK(31, 28)
> -#define DDI_CLK_SEL_NONE REG_FIELD_PREP(DDI_CLK_SEL_MASK,
> 0x0)
> -#define DDI_CLK_SEL_MG
> REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x8)
> -#define DDI_CLK_SEL_TBT_162
> REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xC)
> -#define DDI_CLK_SEL_TBT_270
> REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xD)
> -#define DDI_CLK_SEL_TBT_540
> REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xE)
> -#define DDI_CLK_SEL_TBT_810
> REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xF)
> -
> -/* Transcoder clock selection */
> -#define _TRANS_CLK_SEL_A 0x46140
> -#define _TRANS_CLK_SEL_B 0x46144
> -#define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A,
> _TRANS_CLK_SEL_B)
> -/* For each transcoder, we need to select the corresponding port clock */
> -#define TRANS_CLK_SEL_DISABLED (0x0 << 29)
> -#define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29)
> -#define TGL_TRANS_CLK_SEL_DISABLED (0x0 << 28)
> -#define TGL_TRANS_CLK_SEL_PORT(x) (((x) + 1) << 28)
> -
> -
> -#define CDCLK_FREQ _MMIO(0x46200)
> -
> -#define _TRANSA_MSA_MISC 0x60410
> -#define _TRANSB_MSA_MISC 0x61410
> -#define _TRANSC_MSA_MISC 0x62410
> -#define _TRANS_EDP_MSA_MISC 0x6f410
> -#define TRANS_MSA_MISC(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran,
> _TRANSA_MSA_MISC)
> -/* See DP_MSA_MISC_* for the bit definitions */
> -
> -#define _TRANS_A_SET_CONTEXT_LATENCY 0x6007C
> -#define _TRANS_B_SET_CONTEXT_LATENCY 0x6107C
> -#define _TRANS_C_SET_CONTEXT_LATENCY 0x6207C
> -#define _TRANS_D_SET_CONTEXT_LATENCY 0x6307C
> -#define TRANS_SET_CONTEXT_LATENCY(dev_priv, tran)
> _MMIO_TRANS2(dev_priv, tran, _TRANS_A_SET_CONTEXT_LATENCY)
> -#define TRANS_SET_CONTEXT_LATENCY_MASK
> REG_GENMASK(15, 0)
> -#define TRANS_SET_CONTEXT_LATENCY_VALUE(x)
> REG_FIELD_PREP(TRANS_SET_CONTEXT_LATENCY_MASK, (x))
> -
> -/* LCPLL Control */
> -#define LCPLL_CTL _MMIO(0x130040)
> -#define LCPLL_PLL_DISABLE (1 << 31)
> -#define LCPLL_PLL_LOCK (1 << 30)
> -#define LCPLL_REF_NON_SSC (0 << 28)
> -#define LCPLL_REF_BCLK (2 << 28)
> -#define LCPLL_REF_PCH_SSC (3 << 28)
> -#define LCPLL_REF_MASK (3 << 28)
> -#define LCPLL_CLK_FREQ_MASK (3 << 26)
> -#define LCPLL_CLK_FREQ_450 (0 << 26)
> -#define LCPLL_CLK_FREQ_54O_BDW (1 << 26)
> -#define LCPLL_CLK_FREQ_337_5_BDW (2 << 26)
> -#define LCPLL_CLK_FREQ_675_BDW (3 << 26)
> -#define LCPLL_CD_CLOCK_DISABLE (1 << 25)
> -#define LCPLL_ROOT_CD_CLOCK_DISABLE (1 << 24)
> -#define LCPLL_CD2X_CLOCK_DISABLE (1 << 23)
> -#define LCPLL_POWER_DOWN_ALLOW (1 << 22)
> -#define LCPLL_CD_SOURCE_FCLK (1 << 21)
> -#define LCPLL_CD_SOURCE_FCLK_DONE (1 << 19)
> -
> -/*
> - * SKL Clocks
> - */
> -/* CDCLK_CTL */
> -#define CDCLK_CTL _MMIO(0x46000)
> -#define CDCLK_FREQ_SEL_MASK REG_GENMASK(27, 26)
> -#define CDCLK_FREQ_450_432
> REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 0)
> -#define CDCLK_FREQ_540
> REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1)
> -#define CDCLK_FREQ_337_308
> REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2)
> -#define CDCLK_FREQ_675_617
> REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3)
> -#define MDCLK_SOURCE_SEL_MASK REG_GENMASK(25, 25)
> -#define MDCLK_SOURCE_SEL_CD2XCLK
> REG_FIELD_PREP(MDCLK_SOURCE_SEL_MASK, 0)
> -#define MDCLK_SOURCE_SEL_CDCLK_PLL
> REG_FIELD_PREP(MDCLK_SOURCE_SEL_MASK, 1)
> -#define BXT_CDCLK_CD2X_DIV_SEL_MASK REG_GENMASK(23, 22)
> -#define BXT_CDCLK_CD2X_DIV_SEL_1
> REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0)
> -#define BXT_CDCLK_CD2X_DIV_SEL_1_5
> REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1)
> -#define BXT_CDCLK_CD2X_DIV_SEL_2
> REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 2)
> -#define BXT_CDCLK_CD2X_DIV_SEL_4
> REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 3)
> -#define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20)
> -#define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19)
> -#define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
> -#define ICL_CDCLK_CD2X_PIPE(pipe) (_PICK(pipe, 0, 2, 6) << 19)
> -#define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19)
> -#define TGL_CDCLK_CD2X_PIPE(pipe) BXT_CDCLK_CD2X_PIPE(pipe)
> -#define TGL_CDCLK_CD2X_PIPE_NONE ICL_CDCLK_CD2X_PIPE_NONE
> -#define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16)
> -#define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
> -
> -/* CDCLK_SQUASH_CTL */
> -#define CDCLK_SQUASH_CTL _MMIO(0x46008)
> -#define CDCLK_SQUASH_ENABLE REG_BIT(31)
> -#define CDCLK_SQUASH_WINDOW_SIZE_MASK REG_GENMASK(27,
> 24)
> -#define CDCLK_SQUASH_WINDOW_SIZE(x)
> REG_FIELD_PREP(CDCLK_SQUASH_WINDOW_SIZE_MASK, (x))
> -#define CDCLK_SQUASH_WAVEFORM_MASK REG_GENMASK(15, 0)
> -#define CDCLK_SQUASH_WAVEFORM(x)
> REG_FIELD_PREP(CDCLK_SQUASH_WAVEFORM_MASK, (x))
> -
> -/* LCPLL_CTL */
> -#define LCPLL1_CTL _MMIO(0x46010)
> -#define LCPLL2_CTL _MMIO(0x46014)
> -#define LCPLL_PLL_ENABLE (1 << 31)
> -
> -/* DPLL control1 */
> -#define DPLL_CTRL1 _MMIO(0x6C058)
> -#define DPLL_CTRL1_HDMI_MODE(id) (1 << ((id) * 6 + 5))
> -#define DPLL_CTRL1_SSC(id) (1 << ((id) * 6 + 4))
> -#define DPLL_CTRL1_LINK_RATE_MASK(id) (7 << ((id) * 6 + 1))
> -#define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id) * 6 + 1)
> -#define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate) << ((id) * 6 + 1))
> -#define DPLL_CTRL1_OVERRIDE(id) (1 << ((id) * 6))
> -#define DPLL_CTRL1_LINK_RATE_2700 0
> -#define DPLL_CTRL1_LINK_RATE_1350 1
> -#define DPLL_CTRL1_LINK_RATE_810 2
> -#define DPLL_CTRL1_LINK_RATE_1620 3
> -#define DPLL_CTRL1_LINK_RATE_1080 4
> -#define DPLL_CTRL1_LINK_RATE_2160 5
> -
> -/* DPLL control2 */
> -#define DPLL_CTRL2 _MMIO(0x6C05C)
> -#define DPLL_CTRL2_DDI_CLK_OFF(port) (1 << ((port) + 15))
> -#define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3 << ((port) * 3 + 1))
> -#define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port) * 3 + 1)
> -#define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk) << ((port) * 3 + 1))
> -#define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1 << ((port) * 3))
> -
> -/* DPLL Status */
> -#define DPLL_STATUS _MMIO(0x6C060)
> -#define DPLL_LOCK(id) (1 << ((id) * 8))
> -
> -/* DPLL cfg */
> -#define _DPLL1_CFGCR1 0x6C040
> -#define _DPLL2_CFGCR1 0x6C048
> -#define _DPLL3_CFGCR1 0x6C050
> -#define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1,
> _DPLL1_CFGCR1, _DPLL2_CFGCR1)
> -#define DPLL_CFGCR1_FREQ_ENABLE (1 << 31)
> -#define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff << 9)
> -#define DPLL_CFGCR1_DCO_FRACTION(x) ((x) << 9)
> -#define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff)
> -
> -#define _DPLL1_CFGCR2 0x6C044
> -#define _DPLL2_CFGCR2 0x6C04C
> -#define _DPLL3_CFGCR2 0x6C054
> -#define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1,
> _DPLL1_CFGCR2, _DPLL2_CFGCR2)
> -#define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff << 8)
> -#define DPLL_CFGCR2_QDIV_RATIO(x) ((x) << 8)
> -#define DPLL_CFGCR2_QDIV_MODE(x) ((x) << 7)
> -#define DPLL_CFGCR2_KDIV_MASK (3 << 5)
> -#define DPLL_CFGCR2_KDIV(x) ((x) << 5)
> -#define DPLL_CFGCR2_KDIV_5 (0 << 5)
> -#define DPLL_CFGCR2_KDIV_2 (1 << 5)
> -#define DPLL_CFGCR2_KDIV_3 (2 << 5)
> -#define DPLL_CFGCR2_KDIV_1 (3 << 5)
> -#define DPLL_CFGCR2_PDIV_MASK (7 << 2)
> -#define DPLL_CFGCR2_PDIV(x) ((x) << 2)
> -#define DPLL_CFGCR2_PDIV_1 (0 << 2)
> -#define DPLL_CFGCR2_PDIV_2 (1 << 2)
> -#define DPLL_CFGCR2_PDIV_3 (2 << 2)
> -#define DPLL_CFGCR2_PDIV_7 (4 << 2)
> -#define DPLL_CFGCR2_PDIV_7_INVALID (5 << 2)
> -#define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
> -
> -/* ICL Clocks */
> -#define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
> -#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10,
> 11, 24, 4, 5))
> -#define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10)
> -#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) <
> TC_PORT_4 ? \
> - (tc_port) + 12 : \
> - (tc_port) - TC_PORT_4 +
> 21))
> -#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2)
> -#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 <<
> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
> -#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) <<
> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
> -#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0,
> 2, 4, 27)
> -#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \
> - (3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
> -#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \
> - ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
> -
> -/*
> - * DG1 Clocks
> - * First registers controls the first A and B, while the second register
> - * controls the phy C and D. The bits on these registers are the
> - * same, but refer to different phys
> - */
> -#define _DG1_DPCLKA_CFGCR0 0x164280
> -#define _DG1_DPCLKA1_CFGCR0 0x16C280
> -#define _DG1_DPCLKA_PHY_IDX(phy) ((phy) % 2)
> -#define _DG1_DPCLKA_PLL_IDX(pll) ((pll) % 2)
> -#define DG1_DPCLKA_CFGCR0(phy)
> _MMIO_PHY((phy) / 2, \
> -
> _DG1_DPCLKA_CFGCR0, \
> -
> _DG1_DPCLKA1_CFGCR0)
> -#define DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)
> REG_BIT(_DG1_DPCLKA_PHY_IDX(phy) + 10)
> -#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)
> (_DG1_DPCLKA_PHY_IDX(phy) * 2)
> -#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy)
> (_DG1_DPCLKA_PLL_IDX(pll) <<
> DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
> -#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (0x3 <<
> DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
> -
> -/* ADLS Clocks */
> -#define _ADLS_DPCLKA_CFGCR0 0x164280
> -#define _ADLS_DPCLKA_CFGCR1 0x1642BC
> -#define ADLS_DPCLKA_CFGCR(phy) _MMIO_PHY((phy) / 3,
> \
> -
> _ADLS_DPCLKA_CFGCR0, \
> -
> _ADLS_DPCLKA_CFGCR1)
> -#define ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy) (((phy) % 3) * 2)
> -/* ADLS DPCLKA_CFGCR0 DDI mask */
> -#define ADLS_DPCLKA_DDII_SEL_MASK
> REG_GENMASK(5, 4)
> -#define ADLS_DPCLKA_DDIB_SEL_MASK
> REG_GENMASK(3, 2)
> -#define ADLS_DPCLKA_DDIA_SEL_MASK
> REG_GENMASK(1, 0)
> -/* ADLS DPCLKA_CFGCR1 DDI mask */
> -#define ADLS_DPCLKA_DDIK_SEL_MASK
> REG_GENMASK(3, 2)
> -#define ADLS_DPCLKA_DDIJ_SEL_MASK
> REG_GENMASK(1, 0)
> -#define ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy) _PICK((phy), \
> -
> ADLS_DPCLKA_DDIA_SEL_MASK, \
> -
> ADLS_DPCLKA_DDIB_SEL_MASK, \
> -
> ADLS_DPCLKA_DDII_SEL_MASK, \
> -
> ADLS_DPCLKA_DDIJ_SEL_MASK, \
> -
> ADLS_DPCLKA_DDIK_SEL_MASK)
> -
> -/* ICL PLL */
> -#define _DPLL0_ENABLE 0x46010
> -#define _DPLL1_ENABLE 0x46014
> -#define _ADLS_DPLL2_ENABLE 0x46018
> -#define _ADLS_DPLL3_ENABLE 0x46030
> -#define PLL_ENABLE REG_BIT(31)
> -#define PLL_LOCK REG_BIT(30)
> -#define PLL_POWER_ENABLE REG_BIT(27)
> -#define PLL_POWER_STATE REG_BIT(26)
> -#define ICL_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3,
> \
> - _DPLL0_ENABLE,
> _DPLL1_ENABLE, \
> -
> _ADLS_DPLL3_ENABLE, _ADLS_DPLL3_ENABLE))
> -
> -#define _DG2_PLL3_ENABLE 0x4601C
> -
> -#define DG2_PLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3,
> \
> - _DPLL0_ENABLE,
> _DPLL1_ENABLE, \
> - _DG2_PLL3_ENABLE,
> _DG2_PLL3_ENABLE))
> -
> -#define TBT_PLL_ENABLE _MMIO(0x46020)
> -
> -#define _MG_PLL1_ENABLE 0x46030
> -#define _MG_PLL2_ENABLE 0x46034
> -#define _MG_PLL3_ENABLE 0x46038
> -#define _MG_PLL4_ENABLE 0x4603C
> -/* Bits are the same as _DPLL0_ENABLE */
> -#define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port),
> _MG_PLL1_ENABLE, \
> - _MG_PLL2_ENABLE)
> -
> -/* DG1 PLL */
> -#define DG1_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2,
> \
> - _DPLL0_ENABLE,
> _DPLL1_ENABLE, \
> - _MG_PLL1_ENABLE,
> _MG_PLL2_ENABLE))
> -
> -/* ADL-P Type C PLL */
> -#define PORTTC1_PLL_ENABLE 0x46038
> -#define PORTTC2_PLL_ENABLE 0x46040
> -#define ADLP_PORTTC_PLL_ENABLE(tc_port)
> _MMIO_PORT((tc_port), \
> -
> PORTTC1_PLL_ENABLE, \
> -
> PORTTC2_PLL_ENABLE)
> -
> -#define _ICL_DPLL0_CFGCR0 0x164000
> -#define _ICL_DPLL1_CFGCR0 0x164080
> -#define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0,
> \
> - _ICL_DPLL1_CFGCR0)
> -#define DPLL_CFGCR0_HDMI_MODE (1 << 30)
> -#define DPLL_CFGCR0_SSC_ENABLE (1 << 29)
> -#define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25)
> -#define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25)
> -#define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25)
> -#define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25)
> -#define DPLL_CFGCR0_LINK_RATE_810 (2 << 25)
> -#define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25)
> -#define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25)
> -#define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25)
> -#define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25)
> -#define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25)
> -#define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10)
> -#define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10)
> -#define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10)
> -#define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff)
> -
> -#define _ICL_DPLL0_CFGCR1 0x164004
> -#define _ICL_DPLL1_CFGCR1 0x164084
> -#define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1,
> \
> - _ICL_DPLL1_CFGCR1)
> -#define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10)
> -#define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10)
> -#define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10)
> -#define DPLL_CFGCR1_QDIV_MODE_SHIFT (9)
> -#define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9)
> -#define DPLL_CFGCR1_KDIV_MASK (7 << 6)
> -#define DPLL_CFGCR1_KDIV_SHIFT (6)
> -#define DPLL_CFGCR1_KDIV(x) ((x) << 6)
> -#define DPLL_CFGCR1_KDIV_1 (1 << 6)
> -#define DPLL_CFGCR1_KDIV_2 (2 << 6)
> -#define DPLL_CFGCR1_KDIV_3 (4 << 6)
> -#define DPLL_CFGCR1_PDIV_MASK (0xf << 2)
> -#define DPLL_CFGCR1_PDIV_SHIFT (2)
> -#define DPLL_CFGCR1_PDIV(x) ((x) << 2)
> -#define DPLL_CFGCR1_PDIV_2 (1 << 2)
> -#define DPLL_CFGCR1_PDIV_3 (2 << 2)
> -#define DPLL_CFGCR1_PDIV_5 (4 << 2)
> -#define DPLL_CFGCR1_PDIV_7 (8 << 2)
> -#define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0)
> -#define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0)
> -#define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0)
> -
> -#define _TGL_DPLL0_CFGCR0 0x164284
> -#define _TGL_DPLL1_CFGCR0 0x16428C
> -#define _TGL_TBTPLL_CFGCR0 0x16429C
> -#define TGL_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2,
> \
> - _TGL_DPLL0_CFGCR0,
> _TGL_DPLL1_CFGCR0, \
> - _TGL_TBTPLL_CFGCR0,
> _TGL_TBTPLL_CFGCR0))
> -#define RKL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0,
> \
> - _TGL_DPLL1_CFGCR0)
> -
> -#define _TGL_DPLL0_DIV0 0x164B00
> -#define _TGL_DPLL1_DIV0 0x164C00
> -#define TGL_DPLL0_DIV0(pll) _MMIO_PLL(pll,
> _TGL_DPLL0_DIV0, _TGL_DPLL1_DIV0)
> -#define TGL_DPLL0_DIV0_AFC_STARTUP_MASK
> REG_GENMASK(27, 25)
> -#define TGL_DPLL0_DIV0_AFC_STARTUP(val)
> REG_FIELD_PREP(TGL_DPLL0_DIV0_AFC_STARTUP_MASK, (val))
> -
> -#define _TGL_DPLL0_CFGCR1 0x164288
> -#define _TGL_DPLL1_CFGCR1 0x164290
> -#define _TGL_TBTPLL_CFGCR1 0x1642A0
> -#define TGL_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2,
> \
> - _TGL_DPLL0_CFGCR1,
> _TGL_DPLL1_CFGCR1, \
> - _TGL_TBTPLL_CFGCR1,
> _TGL_TBTPLL_CFGCR1))
> -#define RKL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1,
> \
> - _TGL_DPLL1_CFGCR1)
> -
> -#define _DG1_DPLL2_CFGCR0 0x16C284
> -#define _DG1_DPLL3_CFGCR0 0x16C28C
> -#define DG1_DPLL_CFGCR0(pll)
> _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
> - _TGL_DPLL0_CFGCR0,
> _TGL_DPLL1_CFGCR0, \
> - _DG1_DPLL2_CFGCR0,
> _DG1_DPLL3_CFGCR0))
> -
> -#define _DG1_DPLL2_CFGCR1 0x16C288
> -#define _DG1_DPLL3_CFGCR1 0x16C290
> -#define DG1_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2,
> \
> - _TGL_DPLL0_CFGCR1,
> _TGL_DPLL1_CFGCR1, \
> - _DG1_DPLL2_CFGCR1,
> _DG1_DPLL3_CFGCR1))
> -
> -/* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */
> -#define _ADLS_DPLL4_CFGCR0 0x164294
> -#define _ADLS_DPLL3_CFGCR0 0x1642C0
> -#define ADLS_DPLL_CFGCR0(pll)
> _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
> - _TGL_DPLL0_CFGCR0,
> _TGL_DPLL1_CFGCR0, \
> - _ADLS_DPLL4_CFGCR0,
> _ADLS_DPLL3_CFGCR0))
> -
> -#define _ADLS_DPLL4_CFGCR1 0x164298
> -#define _ADLS_DPLL3_CFGCR1 0x1642C4
> -#define ADLS_DPLL_CFGCR1(pll)
> _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
> - _TGL_DPLL0_CFGCR1,
> _TGL_DPLL1_CFGCR1, \
> - _ADLS_DPLL4_CFGCR1,
> _ADLS_DPLL3_CFGCR1))
> -
> -/* BXT display engine PLL */
> -#define BXT_DE_PLL_CTL _MMIO(0x6d000)
> -#define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */
> -#define BXT_DE_PLL_RATIO_MASK 0xff
> -
> -#define BXT_DE_PLL_ENABLE _MMIO(0x46070)
> -#define BXT_DE_PLL_PLL_ENABLE (1 << 31)
> -#define BXT_DE_PLL_LOCK (1 << 30)
> -#define BXT_DE_PLL_FREQ_REQ (1 << 23)
> -#define BXT_DE_PLL_FREQ_REQ_ACK (1 << 22)
> -#define ICL_CDCLK_PLL_RATIO(x) (x)
> -#define ICL_CDCLK_PLL_RATIO_MASK 0xff
> -
> -/* GEN9 DC */
> -#define DC_STATE_EN _MMIO(0x45504)
> -#define DC_STATE_DISABLE 0
> -#define DC_STATE_EN_DC3CO REG_BIT(30)
> -#define DC_STATE_DC3CO_STATUS REG_BIT(29)
> -#define HOLD_PHY_CLKREQ_PG1_LATCH REG_BIT(21)
> -#define HOLD_PHY_PG1_LATCH REG_BIT(20)
> -#define DC_STATE_EN_UPTO_DC5 (1 << 0)
> -#define DC_STATE_EN_DC9 (1 << 3)
> -#define DC_STATE_EN_UPTO_DC6 (2 << 0)
> -#define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3
> -
> -#define DC_STATE_DEBUG _MMIO(0x45520)
> -#define DC_STATE_DEBUG_MASK_CORES (1 << 0)
> -#define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1)
> -
> -#define D_COMP_BDW _MMIO(0x138144)
> -
> -/* Pipe WM_LINETIME - watermark line time */
> -#define _WM_LINETIME_A 0x45270
> -#define _WM_LINETIME_B 0x45274
> -#define WM_LINETIME(pipe) _MMIO_PIPE(pipe, _WM_LINETIME_A,
> _WM_LINETIME_B)
> -#define HSW_LINETIME_MASK REG_GENMASK(8, 0)
> -#define HSW_LINETIME(x) REG_FIELD_PREP(HSW_LINETIME_MASK, (x))
> -#define HSW_IPS_LINETIME_MASK REG_GENMASK(24, 16)
> -#define HSW_IPS_LINETIME(x) REG_FIELD_PREP(HSW_IPS_LINETIME_MASK,
> (x))
> -
> -/* SFUSE_STRAP */
> -#define SFUSE_STRAP _MMIO(0xc2014)
> -#define SFUSE_STRAP_FUSE_LOCK (1 << 13)
> -#define SFUSE_STRAP_RAW_FREQUENCY (1 << 8)
> -#define SFUSE_STRAP_DISPLAY_DISABLED (1 << 7)
> -#define SFUSE_STRAP_CRT_DISABLED (1 << 6)
> -#define SFUSE_STRAP_DDIF_DETECTED (1 << 3)
> -#define SFUSE_STRAP_DDIB_DETECTED (1 << 2)
> -#define SFUSE_STRAP_DDIC_DETECTED (1 << 1)
> -#define SFUSE_STRAP_DDID_DETECTED (1 << 0)
> -
> -/* Gen4+ Timestamp and Pipe Frame time stamp registers */
> -#define GEN4_TIMESTAMP _MMIO(0x2358)
> -#define ILK_TIMESTAMP_HI _MMIO(0x70070)
> -#define IVB_TIMESTAMP_CTR _MMIO(0x44070)
>
> #define GEN9_TIMESTAMP_OVERRIDE
> _MMIO(0x44074)
> #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0
> @@ -4107,30 +1329,6 @@ enum skl_power_gate {
> #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT
> 12
> #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK
> (0xf << 12)
>
> -/* g4x+, except vlv/chv! */
> -#define _PIPE_FRMTMSTMP_A 0x70048
> -#define _PIPE_FRMTMSTMP_B 0x71048
> -#define PIPE_FRMTMSTMP(pipe) \
> - _MMIO_PIPE(pipe, _PIPE_FRMTMSTMP_A, _PIPE_FRMTMSTMP_B)
> -
> -/* g4x+, except vlv/chv! */
> -#define _PIPE_FLIPTMSTMP_A 0x7004C
> -#define _PIPE_FLIPTMSTMP_B 0x7104C
> -#define PIPE_FLIPTMSTMP(pipe) \
> - _MMIO_PIPE(pipe, _PIPE_FLIPTMSTMP_A, _PIPE_FLIPTMSTMP_B)
> -
> -/* tgl+ */
> -#define _PIPE_FLIPDONETMSTMP_A 0x70054
> -#define _PIPE_FLIPDONETMSTMP_B 0x71054
> -#define PIPE_FLIPDONETIMSTMP(pipe) \
> - _MMIO_PIPE(pipe, _PIPE_FLIPDONETMSTMP_A,
> _PIPE_FLIPDONETMSTMP_B)
> -
> -#define _VLV_PIPE_MSA_MISC_A 0x70048
> -#define VLV_PIPE_MSA_MISC(__display, pipe) \
> - _MMIO_PIPE2(__display, pipe, _VLV_PIPE_MSA_MISC_A)
> -#define VLV_MSA_MISC1_HW_ENABLE REG_BIT(31)
> -#define VLV_MSA_MISC1_SW_S3D_MASK
> REG_GENMASK(2, 0) /* MSA MISC1 3:1 */
> -
> #define GGC _MMIO(0x108040)
> #define GMS_MASK REG_GENMASK(15, 8)
> #define GGMS_MASK REG_GENMASK(7, 6)
> @@ -4145,45 +1343,6 @@ enum skl_power_gate {
> #define SGGI_DIS REG_BIT(15)
> #define SGR_DIS REG_BIT(13)
>
> -#define _ICL_PHY_MISC_A 0x64C00
> -#define _ICL_PHY_MISC_B 0x64C04
> -#define _DG2_PHY_MISC_TC1 0x64C14 /* TC1="PHY E" but offset as if "PHY
> F" */
> -#define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A,
> _ICL_PHY_MISC_B)
> -#define DG2_PHY_MISC(port) ((port) == PHY_E ?
> _MMIO(_DG2_PHY_MISC_TC1) : \
> - ICL_PHY_MISC(port))
> -#define ICL_PHY_MISC_MUX_DDID (1 << 28)
> -#define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
> -#define DG2_PHY_DP_TX_ACK_MASK REG_GENMASK(23,
> 20)
> -
> -#define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia),
> 0x008A0)
> -#define MODULAR_FIA_MASK (1 << 4)
> -#define TC_LIVE_STATE_TBT(idx) (1 << ((idx) * 8 + 6))
> -#define TC_LIVE_STATE_TC(idx) (1 << ((idx) * 8 + 5))
> -#define DP_LANE_ASSIGNMENT_SHIFT(idx) ((idx) * 8)
> -#define DP_LANE_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 8))
> -#define DP_LANE_ASSIGNMENT(idx, x) ((x) << ((idx) * 8))
> -
> -#define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia),
> 0x00890)
> -#define DP_PHY_MODE_STATUS_COMPLETED(idx) (1 << (idx))
> -
> -#define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894)
> -#define DP_PHY_MODE_STATUS_NOT_SAFE(idx) (1 << (idx))
> -
> -#define PORT_TX_DFLEXPA1(fia) _MMIO_FIA((fia),
> 0x00880)
> -#define DP_PIN_ASSIGNMENT_SHIFT(idx) ((idx) * 4)
> -#define DP_PIN_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 4))
> -#define DP_PIN_ASSIGNMENT(idx, x) ((x) << ((idx) * 4))
> -
> -#define _TCSS_DDI_STATUS_1 0x161500
> -#define _TCSS_DDI_STATUS_2 0x161504
> -#define TCSS_DDI_STATUS(tc) _MMIO(_PICK_EVEN(tc, \
> -
> _TCSS_DDI_STATUS_1, \
> -
> _TCSS_DDI_STATUS_2))
> -#define TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK REG_GENMASK(28,
> 25)
> -#define TCSS_DDI_STATUS_READY REG_BIT(2)
> -#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1)
> -#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0)
> -
> #define PRIMARY_SPI_TRIGGER _MMIO(0x102040)
> #define PRIMARY_SPI_ADDRESS _MMIO(0x102080)
> #define PRIMARY_SPI_REGIONID _MMIO(0x102084)
> @@ -4192,37 +1351,11 @@ enum skl_power_gate {
> #define OROM_OFFSET _MMIO(0x1020c0)
> #define OROM_OFFSET_MASK REG_GENMASK(20,
> 16)
>
> -#define CLKREQ_POLICY _MMIO(0x101038)
> -#define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1)
> -
> -#define CLKGATE_DIS_MISC _MMIO(0x46534)
> -#define CLKGATE_DIS_MISC_DMASC_GATING_DIS REG_BIT(21)
> -
> -#define _MTL_CLKGATE_DIS_TRANS_A 0x604E8
> -#define _MTL_CLKGATE_DIS_TRANS_B 0x614E8
> -#define MTL_CLKGATE_DIS_TRANS(dev_priv, trans)
> _MMIO_TRANS2(dev_priv, trans, _MTL_CLKGATE_DIS_TRANS_A)
> -#define MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS
> REG_BIT(7)
> -
> -#define _MTL_PIPE_CLKGATE_DIS2_A 0x60114
> -#define _MTL_PIPE_CLKGATE_DIS2_B 0x61114
> -#define MTL_PIPE_CLKGATE_DIS2(pipe) _MMIO_PIPE(pipe,
> _MTL_PIPE_CLKGATE_DIS2_A, _MTL_PIPE_CLKGATE_DIS2_B)
> -#define MTL_DPFC_GATING_DIS REG_BIT(6)
> -
> #define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700)
> #define MTL_N_OF_ENABLED_QGV_POINTS_MASK REG_GENMASK(11, 8)
> #define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4)
> #define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0)
>
> -#define MTL_MEM_SS_INFO_QGV_POINT_OFFSET 0x45710
> -#define MTL_MEM_SS_INFO_QGV_POINT_LOW(point)
> _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8)
> -#define MTL_TRCD_MASK REG_GENMASK(31, 24)
> -#define MTL_TRP_MASK REG_GENMASK(23, 16)
> -#define MTL_DCLK_MASK REG_GENMASK(15, 0)
> -
> -#define MTL_MEM_SS_INFO_QGV_POINT_HIGH(point)
> _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8 + 4)
> -#define MTL_TRAS_MASK REG_GENMASK(16, 8)
> -#define MTL_TRDPRE_MASK REG_GENMASK(7, 0)
> -
> #define MTL_MEDIA_GSI_BASE 0x380000
>
> #endif /* _I915_REG_H_ */
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index 76d84cbb8361..de48dbc11740 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -31,6 +31,7 @@
> #include "i915_drv.h"
> #include "i915_pvinfo.h"
> #include "i915_reg.h"
> +#include "display/intel_display_regs.h"
> #include "intel_gvt.h"
> #include "intel_mchbar_regs.h"
>
> diff --git a/drivers/gpu/drm/xe/display/xe_plane_initial.c
> b/drivers/gpu/drm/xe/display/xe_plane_initial.c
> index 6502b8274173..d7a7ccab9e2e 100644
> --- a/drivers/gpu/drm/xe/display/xe_plane_initial.c
> +++ b/drivers/gpu/drm/xe/display/xe_plane_initial.c
> @@ -14,6 +14,7 @@
> #include "intel_atomic_plane.h"
> #include "intel_crtc.h"
> #include "intel_display.h"
> +#include "intel_display_regs.h"
> #include "intel_display_types.h"
> #include "intel_fb.h"
> #include "intel_fb_pin.h"
> --
> 2.39.5
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2025-04-17 8:34 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-04-15 10:51 [PATCH v2 0/3] drm/i915: i915_reg.h display split Jani Nikula
2025-04-15 10:51 ` [PATCH v2 1/3] drm/i915/reg: use REG_BIT and friends to define DP registers Jani Nikula
2025-04-15 10:51 ` [PATCH v2 2/3] drm/i915/reg: Add/remove some extra blank lines Jani Nikula
2025-04-15 10:51 ` [PATCH v2 3/3] drm/i915: split out display register macros to a separate file Jani Nikula
2025-04-17 8:33 ` Kandpal, Suraj
2025-04-15 11:42 ` ✓ CI.Patch_applied: success for drm/i915: i915_reg.h display split (rev2) Patchwork
2025-04-15 11:43 ` ✗ CI.checkpatch: warning " Patchwork
2025-04-15 11:44 ` ✓ CI.KUnit: success " Patchwork
2025-04-15 11:52 ` ✓ CI.Build: " Patchwork
2025-04-15 11:55 ` ✓ CI.Hooks: " Patchwork
2025-04-15 11:56 ` ✓ CI.checksparse: " Patchwork
2025-04-15 12:52 ` ✓ Xe.CI.BAT: " Patchwork
2025-04-15 17:29 ` ✗ Xe.CI.Full: failure " Patchwork
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