[CI v2 00/16] drm/i915/display: make all global state opaque

[CI v2 00/16] drm/i915/display: make all global state opaque

[Jani Nikula]

v2 of [1], primarily for CI.

[1] https://lore.kernel.org/r/cover.1749730224.git.jani.nikula@intel.com

Jani Nikula (16):
  drm/i915/wm: abstract intel_dbuf_pmdemand_needs_update()
  drm/i915/wm: add more accessors to dbuf state
  drm/i915/wm: make struct intel_dbuf_state opaque type
  drm/i915/bw: abstract intel_bw_pmdemand_needs_update()
  drm/i915/bw: relocate intel_can_enable_sagv() and rename to
    intel_bw_can_enable_sagv()
  drm/i915: move icl_sagv_{pre,post}_plane_update() to intel_bw.c
  drm/i915/bw: abstract intel_bw_qgv_point_peakbw()
  drm/i915/bw: make struct intel_bw_state opaque
  drm/i915/cdclk: abstract intel_cdclk_logical()
  drm/i915/cdclk: abstract intel_cdclk_min_cdclk()
  drm/i915/cdclk: abstract intel_cdclk_bw_min_cdclk()
  drm/i915/cdclk: abstract intel_cdclk_pmdemand_needs_update()
  drm/i915/cdclk: abstract intel_cdclk_force_min_cdclk()
  drm/i915/cdclk: abstract intel_cdclk_read_hw()
  drm/i915/cdclk: abstract intel_cdclk_actual() and
    intel_cdclk_actual_voltage_level()
  drm/i915/cdclk: make struct intel_cdclk_state opaque

 drivers/gpu/drm/i915/display/hsw_ips.c        |   2 +-
 drivers/gpu/drm/i915/display/intel_audio.c    |   2 +-
 drivers/gpu/drm/i915/display/intel_bw.c       | 153 ++++++++++++++++--
 drivers/gpu/drm/i915/display/intel_bw.h       |  53 ++----
 drivers/gpu/drm/i915/display/intel_cdclk.c    |  93 +++++++++++
 drivers/gpu/drm/i915/display/intel_cdclk.h    |  50 ++----
 drivers/gpu/drm/i915/display/intel_display.c  |   2 +-
 .../drm/i915/display/intel_display_driver.c   |   8 +-
 drivers/gpu/drm/i915/display/intel_fbc.c      |   2 +-
 drivers/gpu/drm/i915/display/intel_plane.c    |   4 +-
 drivers/gpu/drm/i915/display/intel_pmdemand.c |  41 ++---
 drivers/gpu/drm/i915/display/skl_watermark.c  | 134 +++++++--------
 drivers/gpu/drm/i915/display/skl_watermark.h  |  33 +---
 13 files changed, 336 insertions(+), 241 deletions(-)

-- 
2.39.5

[CI v2 01/16] drm/i915/wm: abstract intel_dbuf_pmdemand_needs_update()

[Jani Nikula]

Add intel_dbuf_pmdemand_needs_update() helper to avoid looking at struct
intel_dbuf_state internals outside of skl_watermark.c.

With this, we can also move to_intel_dbuf_state(),
intel_atomic_get_old_dbuf_state(), and intel_atomic_get_new_dbuf_state()
inside skl_watermark.c.

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_pmdemand.c | 14 +--------
 drivers/gpu/drm/i915/display/skl_watermark.c  | 30 +++++++++++++++++++
 drivers/gpu/drm/i915/display/skl_watermark.h  | 10 ++-----
 3 files changed, 33 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
index 93d5ee36fff1..0f1501c456df 100644
--- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
@@ -294,11 +294,9 @@ intel_pmdemand_connector_needs_update(struct intel_atomic_state *state)
 
 static bool intel_pmdemand_needs_update(struct intel_atomic_state *state)
 {
-	struct intel_display *display = to_intel_display(state);
 	const struct intel_bw_state *new_bw_state, *old_bw_state;
 	const struct intel_cdclk_state *new_cdclk_state, *old_cdclk_state;
 	const struct intel_crtc_state *new_crtc_state, *old_crtc_state;
-	const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;
 	struct intel_crtc *crtc;
 	int i;
 
@@ -308,19 +306,9 @@ static bool intel_pmdemand_needs_update(struct intel_atomic_state *state)
 	    old_bw_state->qgv_point_peakbw)
 		return true;
 
-	new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
-	old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
-	if (new_dbuf_state &&
-	    new_dbuf_state->active_pipes != old_dbuf_state->active_pipes)
+	if (intel_dbuf_pmdemand_needs_update(state))
 		return true;
 
-	if (DISPLAY_VER(display) < 30) {
-		if (new_dbuf_state &&
-		    new_dbuf_state->enabled_slices !=
-		    old_dbuf_state->enabled_slices)
-			return true;
-	}
-
 	new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
 	old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
 	if (new_cdclk_state &&
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index d39fabd09938..9ae9f02b11ca 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -39,6 +39,14 @@
  */
 #define DSB_EXE_TIME 100
 
+#define to_intel_dbuf_state(global_state) \
+	container_of_const((global_state), struct intel_dbuf_state, base)
+
+#define intel_atomic_get_old_dbuf_state(state) \
+	to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state, &to_intel_display(state)->dbuf.obj))
+#define intel_atomic_get_new_dbuf_state(state) \
+	to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_intel_display(state)->dbuf.obj))
+
 static void skl_sagv_disable(struct intel_display *display);
 
 /* Stores plane specific WM parameters */
@@ -3696,6 +3704,28 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
 	gen9_dbuf_slices_update(display, new_slices);
 }
 
+bool intel_dbuf_pmdemand_needs_update(struct intel_atomic_state *state)
+{
+	struct intel_display *display = to_intel_display(state);
+	const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;
+
+	new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
+	old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
+
+	if (new_dbuf_state &&
+	    new_dbuf_state->active_pipes != old_dbuf_state->active_pipes)
+		return true;
+
+	if (DISPLAY_VER(display) < 30) {
+		if (new_dbuf_state &&
+		    new_dbuf_state->enabled_slices !=
+		    old_dbuf_state->enabled_slices)
+			return true;
+	}
+
+	return false;
+}
+
 static void skl_mbus_sanitize(struct intel_display *display)
 {
 	struct intel_dbuf_state *dbuf_state =
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h
index 95b0b599d5c3..3b9a0b254cff 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.h
+++ b/drivers/gpu/drm/i915/display/skl_watermark.h
@@ -78,14 +78,6 @@ struct intel_dbuf_state {
 struct intel_dbuf_state *
 intel_atomic_get_dbuf_state(struct intel_atomic_state *state);
 
-#define to_intel_dbuf_state(global_state) \
-	container_of_const((global_state), struct intel_dbuf_state, base)
-
-#define intel_atomic_get_old_dbuf_state(state) \
-	to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state, &to_intel_display(state)->dbuf.obj))
-#define intel_atomic_get_new_dbuf_state(state) \
-	to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_intel_display(state)->dbuf.obj))
-
 int intel_dbuf_init(struct intel_display *display);
 int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state,
 					   int ratio);
@@ -98,5 +90,7 @@ void intel_dbuf_mbus_pre_ddb_update(struct intel_atomic_state *state);
 void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state);
 void intel_program_dpkgc_latency(struct intel_atomic_state *state);
 
+bool intel_dbuf_pmdemand_needs_update(struct intel_atomic_state *state);
+
 #endif /* __SKL_WATERMARK_H__ */
 
-- 
2.39.5

[CI v2 02/16] drm/i915/wm: add more accessors to dbuf state

[Jani Nikula]

Add intel_dbuf_num_enabled_slices() and intel_dbuf_num_active_pipes()
helpers to avoid looking at struct intel_dbuf_state internals outside of
skl_watermark.c.

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_pmdemand.c |  6 +++---
 drivers/gpu/drm/i915/display/skl_watermark.c  | 10 ++++++++++
 drivers/gpu/drm/i915/display/skl_watermark.h  |  3 +++
 3 files changed, 16 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
index 0f1501c456df..eeb88f9fc92d 100644
--- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
@@ -358,12 +358,12 @@ int intel_pmdemand_atomic_check(struct intel_atomic_state *state)
 
 	if (DISPLAY_VER(display) < 30) {
 		new_pmdemand_state->params.active_dbufs =
-			min_t(u8, hweight8(new_dbuf_state->enabled_slices), 3);
+			min_t(u8, intel_dbuf_num_enabled_slices(new_dbuf_state), 3);
 		new_pmdemand_state->params.active_pipes =
-			min_t(u8, hweight8(new_dbuf_state->active_pipes), 3);
+			min_t(u8, intel_dbuf_num_active_pipes(new_dbuf_state), 3);
 	} else {
 		new_pmdemand_state->params.active_pipes =
-			min_t(u8, hweight8(new_dbuf_state->active_pipes), INTEL_NUM_PIPES(display));
+			min_t(u8, intel_dbuf_num_active_pipes(new_dbuf_state), INTEL_NUM_PIPES(display));
 	}
 
 	new_cdclk_state = intel_atomic_get_cdclk_state(state);
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 9ae9f02b11ca..3574df9b1df7 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3704,6 +3704,16 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
 	gen9_dbuf_slices_update(display, new_slices);
 }
 
+int intel_dbuf_num_enabled_slices(const struct intel_dbuf_state *dbuf_state)
+{
+	return hweight8(dbuf_state->enabled_slices);
+}
+
+int intel_dbuf_num_active_pipes(const struct intel_dbuf_state *dbuf_state)
+{
+	return hweight8(dbuf_state->active_pipes);
+}
+
 bool intel_dbuf_pmdemand_needs_update(struct intel_atomic_state *state)
 {
 	struct intel_display *display = to_intel_display(state);
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h
index 3b9a0b254cff..a1993ded034a 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.h
+++ b/drivers/gpu/drm/i915/display/skl_watermark.h
@@ -78,6 +78,9 @@ struct intel_dbuf_state {
 struct intel_dbuf_state *
 intel_atomic_get_dbuf_state(struct intel_atomic_state *state);
 
+int intel_dbuf_num_enabled_slices(const struct intel_dbuf_state *dbuf_state);
+int intel_dbuf_num_active_pipes(const struct intel_dbuf_state *dbuf_state);
+
 int intel_dbuf_init(struct intel_display *display);
 int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state,
 					   int ratio);
-- 
2.39.5

[CI v2 03/16] drm/i915/wm: make struct intel_dbuf_state opaque type

[Jani Nikula]

With all the code touching struct intel_dbuf_state moved inside
skl_watermark.c, we move the struct definition there too, and make the
type opaque. This nicely reduces includes from skl_watermark.h.

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 12 ++++++++++++
 drivers/gpu/drm/i915/display/skl_watermark.h | 19 +++----------------
 2 files changed, 15 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 3574df9b1df7..8b8cf74e64a7 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -39,6 +39,18 @@
  */
 #define DSB_EXE_TIME 100
 
+struct intel_dbuf_state {
+	struct intel_global_state base;
+
+	struct skl_ddb_entry ddb[I915_MAX_PIPES];
+	unsigned int weight[I915_MAX_PIPES];
+	u8 slices[I915_MAX_PIPES];
+	u8 enabled_slices;
+	u8 active_pipes;
+	u8 mdclk_cdclk_ratio;
+	bool joined_mbus;
+};
+
 #define to_intel_dbuf_state(global_state) \
 	container_of_const((global_state), struct intel_dbuf_state, base)
 
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h
index a1993ded034a..87d052b640b3 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.h
+++ b/drivers/gpu/drm/i915/display/skl_watermark.h
@@ -8,17 +8,16 @@
 
 #include <linux/types.h>
 
-#include "intel_display_limits.h"
-#include "intel_global_state.h"
-#include "intel_wm_types.h"
-
+enum plane_id;
 struct intel_atomic_state;
 struct intel_bw_state;
 struct intel_crtc;
 struct intel_crtc_state;
+struct intel_dbuf_state;
 struct intel_display;
 struct intel_plane;
 struct intel_plane_state;
+struct skl_ddb_entry;
 struct skl_pipe_wm;
 struct skl_wm_level;
 
@@ -63,18 +62,6 @@ unsigned int skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_st
 					  struct intel_plane *plane, int width,
 					  int height, int cpp);
 
-struct intel_dbuf_state {
-	struct intel_global_state base;
-
-	struct skl_ddb_entry ddb[I915_MAX_PIPES];
-	unsigned int weight[I915_MAX_PIPES];
-	u8 slices[I915_MAX_PIPES];
-	u8 enabled_slices;
-	u8 active_pipes;
-	u8 mdclk_cdclk_ratio;
-	bool joined_mbus;
-};
-
 struct intel_dbuf_state *
 intel_atomic_get_dbuf_state(struct intel_atomic_state *state);
 
-- 
2.39.5

[CI v2 04/16] drm/i915/bw: abstract intel_bw_pmdemand_needs_update()

[Jani Nikula]

Add intel_bw_pmdemand_needs_update() helper to avoid looking at struct
intel_bw_state internals outside of intel_bw.c.

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c       | 14 ++++++++++++++
 drivers/gpu/drm/i915/display/intel_bw.h       |  2 ++
 drivers/gpu/drm/i915/display/intel_pmdemand.c |  6 +-----
 3 files changed, 17 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 8f5bc6872eda..7a014b28312a 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -1651,3 +1651,17 @@ int intel_bw_init(struct intel_display *display)
 
 	return 0;
 }
+
+bool intel_bw_pmdemand_needs_update(struct intel_atomic_state *state)
+{
+	const struct intel_bw_state *new_bw_state, *old_bw_state;
+
+	new_bw_state = intel_atomic_get_new_bw_state(state);
+	old_bw_state = intel_atomic_get_old_bw_state(state);
+
+	if (new_bw_state &&
+	    new_bw_state->qgv_point_peakbw != old_bw_state->qgv_point_peakbw)
+		return true;
+
+	return false;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index eb2cc883e9c1..0acc6f19c981 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -76,4 +76,6 @@ int intel_bw_min_cdclk(struct intel_display *display,
 void intel_bw_update_hw_state(struct intel_display *display);
 void intel_bw_crtc_disable_noatomic(struct intel_crtc *crtc);
 
+bool intel_bw_pmdemand_needs_update(struct intel_atomic_state *state);
+
 #endif /* __INTEL_BW_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
index eeb88f9fc92d..8334744a2e23 100644
--- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
@@ -294,16 +294,12 @@ intel_pmdemand_connector_needs_update(struct intel_atomic_state *state)
 
 static bool intel_pmdemand_needs_update(struct intel_atomic_state *state)
 {
-	const struct intel_bw_state *new_bw_state, *old_bw_state;
 	const struct intel_cdclk_state *new_cdclk_state, *old_cdclk_state;
 	const struct intel_crtc_state *new_crtc_state, *old_crtc_state;
 	struct intel_crtc *crtc;
 	int i;
 
-	new_bw_state = intel_atomic_get_new_bw_state(state);
-	old_bw_state = intel_atomic_get_old_bw_state(state);
-	if (new_bw_state && new_bw_state->qgv_point_peakbw !=
-	    old_bw_state->qgv_point_peakbw)
+	if (intel_bw_pmdemand_needs_update(state))
 		return true;
 
 	if (intel_dbuf_pmdemand_needs_update(state))
-- 
2.39.5

[CI v2 05/16] drm/i915/bw: relocate intel_can_enable_sagv() and rename to intel_bw_can_enable_sagv()

[Jani Nikula]

Prefer only looking at struct intel_bw_state internals inside
intel_bw.c. To that effect, move intel_can_enable_sagv() there, and
rename to intel_bw_can_enable_sagv() to have consistent naming.

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c      | 22 ++++++++++++++------
 drivers/gpu/drm/i915/display/intel_bw.h      |  2 ++
 drivers/gpu/drm/i915/display/skl_watermark.c | 16 +++-----------
 drivers/gpu/drm/i915/display/skl_watermark.h |  3 ---
 4 files changed, 21 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 7a014b28312a..32e38eeb8128 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -1001,7 +1001,7 @@ static int mtl_find_qgv_points(struct intel_display *display,
 	 * for qgv peak bw in PM Demand request. So assign UINT_MAX if SAGV is
 	 * not enabled. PM Demand code will clamp the value for the register
 	 */
-	if (!intel_can_enable_sagv(display, new_bw_state)) {
+	if (!intel_bw_can_enable_sagv(display, new_bw_state)) {
 		new_bw_state->qgv_point_peakbw = U16_MAX;
 		drm_dbg_kms(display->drm, "No SAGV, use UINT_MAX as peak bw.");
 		return 0;
@@ -1114,7 +1114,7 @@ static int icl_find_qgv_points(struct intel_display *display,
 	 * we can't enable SAGV due to the increased memory latency it may
 	 * cause.
 	 */
-	if (!intel_can_enable_sagv(display, new_bw_state)) {
+	if (!intel_bw_can_enable_sagv(display, new_bw_state)) {
 		qgv_points = icl_max_bw_qgv_point_mask(display, num_active_planes);
 		drm_dbg_kms(display->drm, "No SAGV, using single QGV point mask 0x%x\n",
 			    qgv_points);
@@ -1481,8 +1481,8 @@ static int intel_bw_check_sagv_mask(struct intel_atomic_state *state)
 	if (!new_bw_state)
 		return 0;
 
-	if (intel_can_enable_sagv(display, new_bw_state) !=
-	    intel_can_enable_sagv(display, old_bw_state)) {
+	if (intel_bw_can_enable_sagv(display, new_bw_state) !=
+	    intel_bw_can_enable_sagv(display, old_bw_state)) {
 		ret = intel_atomic_serialize_global_state(&new_bw_state->base);
 		if (ret)
 			return ret;
@@ -1528,8 +1528,8 @@ int intel_bw_atomic_check(struct intel_atomic_state *state, bool any_ms)
 	new_bw_state = intel_atomic_get_new_bw_state(state);
 
 	if (new_bw_state &&
-	    intel_can_enable_sagv(display, old_bw_state) !=
-	    intel_can_enable_sagv(display, new_bw_state))
+	    intel_bw_can_enable_sagv(display, old_bw_state) !=
+	    intel_bw_can_enable_sagv(display, new_bw_state))
 		changed = true;
 
 	/*
@@ -1665,3 +1665,13 @@ bool intel_bw_pmdemand_needs_update(struct intel_atomic_state *state)
 
 	return false;
 }
+
+bool intel_bw_can_enable_sagv(struct intel_display *display,
+			      const struct intel_bw_state *bw_state)
+{
+	if (DISPLAY_VER(display) < 11 &&
+	    bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
+		return false;
+
+	return bw_state->pipe_sagv_reject == 0;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index 0acc6f19c981..ee6e4a7ac89d 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -77,5 +77,7 @@ void intel_bw_update_hw_state(struct intel_display *display);
 void intel_bw_crtc_disable_noatomic(struct intel_crtc *crtc);
 
 bool intel_bw_pmdemand_needs_update(struct intel_atomic_state *state);
+bool intel_bw_can_enable_sagv(struct intel_display *display,
+			      const struct intel_bw_state *bw_state);
 
 #endif /* __INTEL_BW_H__ */
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 8b8cf74e64a7..514d9cd45d69 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -248,7 +248,7 @@ static void skl_sagv_pre_plane_update(struct intel_atomic_state *state)
 	if (!new_bw_state)
 		return;
 
-	if (!intel_can_enable_sagv(display, new_bw_state))
+	if (!intel_bw_can_enable_sagv(display, new_bw_state))
 		skl_sagv_disable(display);
 }
 
@@ -261,7 +261,7 @@ static void skl_sagv_post_plane_update(struct intel_atomic_state *state)
 	if (!new_bw_state)
 		return;
 
-	if (intel_can_enable_sagv(display, new_bw_state))
+	if (intel_bw_can_enable_sagv(display, new_bw_state))
 		skl_sagv_enable(display);
 }
 
@@ -462,16 +462,6 @@ bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
 		return skl_crtc_can_enable_sagv(crtc_state);
 }
 
-bool intel_can_enable_sagv(struct intel_display *display,
-			   const struct intel_bw_state *bw_state)
-{
-	if (DISPLAY_VER(display) < 11 &&
-	    bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
-		return false;
-
-	return bw_state->pipe_sagv_reject == 0;
-}
-
 static u16 skl_ddb_entry_init(struct skl_ddb_entry *entry,
 			      u16 start, u16 end)
 {
@@ -3035,7 +3025,7 @@ skl_compute_wm(struct intel_atomic_state *state)
 		 * drm_atomic_check_only() gets upset if we pull more crtcs
 		 * into the state, so we have to calculate this based on the
 		 * individual intel_crtc_can_enable_sagv() rather than
-		 * the overall intel_can_enable_sagv(). Otherwise the
+		 * the overall intel_bw_can_enable_sagv(). Otherwise the
 		 * crtcs not included in the commit would not switch to the
 		 * SAGV watermarks when we are about to enable SAGV, and that
 		 * would lead to underruns. This does mean extra power draw
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h
index 87d052b640b3..62790816f030 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.h
+++ b/drivers/gpu/drm/i915/display/skl_watermark.h
@@ -10,7 +10,6 @@
 
 enum plane_id;
 struct intel_atomic_state;
-struct intel_bw_state;
 struct intel_crtc;
 struct intel_crtc_state;
 struct intel_dbuf_state;
@@ -26,8 +25,6 @@ u8 intel_enabled_dbuf_slices_mask(struct intel_display *display);
 void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
 void intel_sagv_post_plane_update(struct intel_atomic_state *state);
 bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state);
-bool intel_can_enable_sagv(struct intel_display *display,
-			   const struct intel_bw_state *bw_state);
 bool intel_has_sagv(struct intel_display *display);
 
 u32 skl_ddb_dbuf_slice_mask(struct intel_display *display,
-- 
2.39.5

[CI v2 06/16] drm/i915: move icl_sagv_{pre, post}_plane_update() to intel_bw.c

[Jani Nikula]

Prefer only looking at struct intel_bw_state internals inside
intel_bw.c. To that effect, move icl_sagv_{pre,post}_plane_update()
there.

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c      | 68 +++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_bw.h      |  4 +-
 drivers/gpu/drm/i915/display/skl_watermark.c | 64 ------------------
 3 files changed, 68 insertions(+), 68 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 32e38eeb8128..3c3b4dd71ec3 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -153,8 +153,8 @@ static bool is_sagv_enabled(struct intel_display *display, u16 points_mask)
 			      ICL_PCODE_REQ_QGV_PT_MASK);
 }
 
-int icl_pcode_restrict_qgv_points(struct intel_display *display,
-				  u32 points_mask)
+static int icl_pcode_restrict_qgv_points(struct intel_display *display,
+					 u32 points_mask)
 {
 	int ret;
 
@@ -981,6 +981,70 @@ static void icl_force_disable_sagv(struct intel_display *display,
 	icl_pcode_restrict_qgv_points(display, bw_state->qgv_points_mask);
 }
 
+void icl_sagv_pre_plane_update(struct intel_atomic_state *state)
+{
+	struct intel_display *display = to_intel_display(state);
+	const struct intel_bw_state *old_bw_state =
+		intel_atomic_get_old_bw_state(state);
+	const struct intel_bw_state *new_bw_state =
+		intel_atomic_get_new_bw_state(state);
+	u16 old_mask, new_mask;
+
+	if (!new_bw_state)
+		return;
+
+	old_mask = old_bw_state->qgv_points_mask;
+	new_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask;
+
+	if (old_mask == new_mask)
+		return;
+
+	WARN_ON(!new_bw_state->base.changed);
+
+	drm_dbg_kms(display->drm, "Restricting QGV points: 0x%x -> 0x%x\n",
+		    old_mask, new_mask);
+
+	/*
+	 * Restrict required qgv points before updating the configuration.
+	 * According to BSpec we can't mask and unmask qgv points at the same
+	 * time. Also masking should be done before updating the configuration
+	 * and unmasking afterwards.
+	 */
+	icl_pcode_restrict_qgv_points(display, new_mask);
+}
+
+void icl_sagv_post_plane_update(struct intel_atomic_state *state)
+{
+	struct intel_display *display = to_intel_display(state);
+	const struct intel_bw_state *old_bw_state =
+		intel_atomic_get_old_bw_state(state);
+	const struct intel_bw_state *new_bw_state =
+		intel_atomic_get_new_bw_state(state);
+	u16 old_mask, new_mask;
+
+	if (!new_bw_state)
+		return;
+
+	old_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask;
+	new_mask = new_bw_state->qgv_points_mask;
+
+	if (old_mask == new_mask)
+		return;
+
+	WARN_ON(!new_bw_state->base.changed);
+
+	drm_dbg_kms(display->drm, "Relaxing QGV points: 0x%x -> 0x%x\n",
+		    old_mask, new_mask);
+
+	/*
+	 * Allow required qgv points after updating the configuration.
+	 * According to BSpec we can't mask and unmask qgv points at the same
+	 * time. Also masking should be done before updating the configuration
+	 * and unmasking afterwards.
+	 */
+	icl_pcode_restrict_qgv_points(display, new_mask);
+}
+
 static int mtl_find_qgv_points(struct intel_display *display,
 			       unsigned int data_rate,
 			       unsigned int num_active_planes,
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index ee6e4a7ac89d..68b95c2a0cb9 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -67,8 +67,6 @@ intel_atomic_get_bw_state(struct intel_atomic_state *state);
 void intel_bw_init_hw(struct intel_display *display);
 int intel_bw_init(struct intel_display *display);
 int intel_bw_atomic_check(struct intel_atomic_state *state, bool any_ms);
-int icl_pcode_restrict_qgv_points(struct intel_display *display,
-				  u32 points_mask);
 int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
 			    bool *need_cdclk_calc);
 int intel_bw_min_cdclk(struct intel_display *display,
@@ -79,5 +77,7 @@ void intel_bw_crtc_disable_noatomic(struct intel_crtc *crtc);
 bool intel_bw_pmdemand_needs_update(struct intel_atomic_state *state);
 bool intel_bw_can_enable_sagv(struct intel_display *display,
 			      const struct intel_bw_state *bw_state);
+void icl_sagv_pre_plane_update(struct intel_atomic_state *state);
+void icl_sagv_post_plane_update(struct intel_atomic_state *state);
 
 #endif /* __INTEL_BW_H__ */
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 514d9cd45d69..f98c4a0fc7a9 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -265,70 +265,6 @@ static void skl_sagv_post_plane_update(struct intel_atomic_state *state)
 		skl_sagv_enable(display);
 }
 
-static void icl_sagv_pre_plane_update(struct intel_atomic_state *state)
-{
-	struct intel_display *display = to_intel_display(state);
-	const struct intel_bw_state *old_bw_state =
-		intel_atomic_get_old_bw_state(state);
-	const struct intel_bw_state *new_bw_state =
-		intel_atomic_get_new_bw_state(state);
-	u16 old_mask, new_mask;
-
-	if (!new_bw_state)
-		return;
-
-	old_mask = old_bw_state->qgv_points_mask;
-	new_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask;
-
-	if (old_mask == new_mask)
-		return;
-
-	WARN_ON(!new_bw_state->base.changed);
-
-	drm_dbg_kms(display->drm, "Restricting QGV points: 0x%x -> 0x%x\n",
-		    old_mask, new_mask);
-
-	/*
-	 * Restrict required qgv points before updating the configuration.
-	 * According to BSpec we can't mask and unmask qgv points at the same
-	 * time. Also masking should be done before updating the configuration
-	 * and unmasking afterwards.
-	 */
-	icl_pcode_restrict_qgv_points(display, new_mask);
-}
-
-static void icl_sagv_post_plane_update(struct intel_atomic_state *state)
-{
-	struct intel_display *display = to_intel_display(state);
-	const struct intel_bw_state *old_bw_state =
-		intel_atomic_get_old_bw_state(state);
-	const struct intel_bw_state *new_bw_state =
-		intel_atomic_get_new_bw_state(state);
-	u16 old_mask, new_mask;
-
-	if (!new_bw_state)
-		return;
-
-	old_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask;
-	new_mask = new_bw_state->qgv_points_mask;
-
-	if (old_mask == new_mask)
-		return;
-
-	WARN_ON(!new_bw_state->base.changed);
-
-	drm_dbg_kms(display->drm, "Relaxing QGV points: 0x%x -> 0x%x\n",
-		    old_mask, new_mask);
-
-	/*
-	 * Allow required qgv points after updating the configuration.
-	 * According to BSpec we can't mask and unmask qgv points at the same
-	 * time. Also masking should be done before updating the configuration
-	 * and unmasking afterwards.
-	 */
-	icl_pcode_restrict_qgv_points(display, new_mask);
-}
-
 void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
 {
 	struct intel_display *display = to_intel_display(state);
-- 
2.39.5

[CI v2 07/16] drm/i915/bw: abstract intel_bw_qgv_point_peakbw()

[Jani Nikula]

Add intel_bw_qgv_point_peakbw() helper to avoid looking at struct
intel_bw_state internals outside of intel_bw.c.

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c       | 5 +++++
 drivers/gpu/drm/i915/display/intel_bw.h       | 1 +
 drivers/gpu/drm/i915/display/intel_pmdemand.c | 2 +-
 3 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 3c3b4dd71ec3..1f86f3cb9cae 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -1739,3 +1739,8 @@ bool intel_bw_can_enable_sagv(struct intel_display *display,
 
 	return bw_state->pipe_sagv_reject == 0;
 }
+
+int intel_bw_qgv_point_peakbw(const struct intel_bw_state *bw_state)
+{
+	return bw_state->qgv_point_peakbw;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index 68b95c2a0cb9..7728dc86a31a 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -79,5 +79,6 @@ bool intel_bw_can_enable_sagv(struct intel_display *display,
 			      const struct intel_bw_state *bw_state);
 void icl_sagv_pre_plane_update(struct intel_atomic_state *state);
 void icl_sagv_post_plane_update(struct intel_atomic_state *state);
+int intel_bw_qgv_point_peakbw(const struct intel_bw_state *bw_state);
 
 #endif /* __INTEL_BW_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
index 8334744a2e23..a4d53fd94489 100644
--- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
@@ -346,7 +346,7 @@ int intel_pmdemand_atomic_check(struct intel_atomic_state *state)
 
 	/* firmware will calculate the qclk_gv_index, requirement is set to 0 */
 	new_pmdemand_state->params.qclk_gv_index = 0;
-	new_pmdemand_state->params.qclk_gv_bw = new_bw_state->qgv_point_peakbw;
+	new_pmdemand_state->params.qclk_gv_bw = intel_bw_qgv_point_peakbw(new_bw_state);
 
 	new_dbuf_state = intel_atomic_get_dbuf_state(state);
 	if (IS_ERR(new_dbuf_state))
-- 
2.39.5

[CI v2 08/16] drm/i915/bw: make struct intel_bw_state opaque

[Jani Nikula]

With all the code touching struct intel_bw_state moved inside
intel_bw.c, we move the struct definition there too, and make the type
opaque. to_intel_bw_state() needs to be turned into a proper
function. All of this nicely reduces includes from intel_bw.h.

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 40 ++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_bw.h | 44 ++-----------------------
 2 files changed, 43 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 1f86f3cb9cae..5942a3bae32c 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -21,6 +21,41 @@
 #include "intel_uncore.h"
 #include "skl_watermark.h"
 
+struct intel_dbuf_bw {
+	unsigned int max_bw[I915_MAX_DBUF_SLICES];
+	u8 active_planes[I915_MAX_DBUF_SLICES];
+};
+
+struct intel_bw_state {
+	struct intel_global_state base;
+	struct intel_dbuf_bw dbuf_bw[I915_MAX_PIPES];
+
+	/*
+	 * Contains a bit mask, used to determine, whether correspondent
+	 * pipe allows SAGV or not.
+	 */
+	u8 pipe_sagv_reject;
+
+	/* bitmask of active pipes */
+	u8 active_pipes;
+
+	/*
+	 * From MTL onwards, to lock a QGV point, punit expects the peak BW of
+	 * the selected QGV point as the parameter in multiples of 100MB/s
+	 */
+	u16 qgv_point_peakbw;
+
+	/*
+	 * Current QGV points mask, which restricts
+	 * some particular SAGV states, not to confuse
+	 * with pipe_sagv_mask.
+	 */
+	u16 qgv_points_mask;
+
+	unsigned int data_rate[I915_MAX_PIPES];
+	u8 num_active_planes[I915_MAX_PIPES];
+};
+
 /* Parameters for Qclk Geyserville (QGV) */
 struct intel_qgv_point {
 	u16 dclk, t_rp, t_rdpre, t_rc, t_ras, t_rcd;
@@ -872,6 +907,11 @@ static unsigned int intel_bw_data_rate(struct intel_display *display,
 	return data_rate;
 }
 
+struct intel_bw_state *to_intel_bw_state(struct intel_global_state *obj_state)
+{
+	return container_of(obj_state, struct intel_bw_state, base);
+}
+
 struct intel_bw_state *
 intel_atomic_get_old_bw_state(struct intel_atomic_state *state)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index 7728dc86a31a..d51f50c9d302 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -8,52 +8,14 @@
 
 #include <drm/drm_atomic.h>
 
-#include "intel_display_limits.h"
-#include "intel_display_power.h"
-#include "intel_global_state.h"
-
 struct intel_atomic_state;
+struct intel_bw_state;
 struct intel_crtc;
 struct intel_crtc_state;
 struct intel_display;
+struct intel_global_state;
 
-struct intel_dbuf_bw {
-	unsigned int max_bw[I915_MAX_DBUF_SLICES];
-	u8 active_planes[I915_MAX_DBUF_SLICES];
-};
-
-struct intel_bw_state {
-	struct intel_global_state base;
-	struct intel_dbuf_bw dbuf_bw[I915_MAX_PIPES];
-
-	/*
-	 * Contains a bit mask, used to determine, whether correspondent
-	 * pipe allows SAGV or not.
-	 */
-	u8 pipe_sagv_reject;
-
-	/* bitmask of active pipes */
-	u8 active_pipes;
-
-	/*
-	 * From MTL onwards, to lock a QGV point, punit expects the peak BW of
-	 * the selected QGV point as the parameter in multiples of 100MB/s
-	 */
-	u16 qgv_point_peakbw;
-
-	/*
-	 * Current QGV points mask, which restricts
-	 * some particular SAGV states, not to confuse
-	 * with pipe_sagv_mask.
-	 */
-	u16 qgv_points_mask;
-
-	unsigned int data_rate[I915_MAX_PIPES];
-	u8 num_active_planes[I915_MAX_PIPES];
-};
-
-#define to_intel_bw_state(global_state) \
-	container_of_const((global_state), struct intel_bw_state, base)
+struct intel_bw_state *to_intel_bw_state(struct intel_global_state *obj_state);
 
 struct intel_bw_state *
 intel_atomic_get_old_bw_state(struct intel_atomic_state *state);
-- 
2.39.5

[CI v2 09/16] drm/i915/cdclk: abstract intel_cdclk_logical()

[Jani Nikula]

Add intel_cdclk_logical() helper to avoid looking at struct
intel_cdclk_state internals outside of intel_cdclk.c.

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/hsw_ips.c       | 2 +-
 drivers/gpu/drm/i915/display/intel_cdclk.c   | 5 +++++
 drivers/gpu/drm/i915/display/intel_cdclk.h   | 2 ++
 drivers/gpu/drm/i915/display/intel_display.c | 2 +-
 drivers/gpu/drm/i915/display/intel_fbc.c     | 2 +-
 drivers/gpu/drm/i915/display/skl_watermark.c | 2 +-
 6 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c b/drivers/gpu/drm/i915/display/hsw_ips.c
index 989a9171b07f..927fe56aec77 100644
--- a/drivers/gpu/drm/i915/display/hsw_ips.c
+++ b/drivers/gpu/drm/i915/display/hsw_ips.c
@@ -265,7 +265,7 @@ int hsw_ips_compute_config(struct intel_atomic_state *state,
 			return PTR_ERR(cdclk_state);
 
 		/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
-		if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)
+		if (crtc_state->pixel_rate > intel_cdclk_logical(cdclk_state) * 95 / 100)
 			return 0;
 	}
 
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 95fab2ee3d94..51485c777b62 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3834,3 +3834,8 @@ void intel_init_cdclk_hooks(struct intel_display *display)
 		     "Unknown platform. Assuming i830\n"))
 		display->funcs.cdclk = &i830_cdclk_funcs;
 }
+
+int intel_cdclk_logical(const struct intel_cdclk_state *cdclk_state)
+{
+	return cdclk_state->logical.cdclk;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index a1cefd455d92..20a66f613072 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -97,4 +97,6 @@ void intel_cdclk_crtc_disable_noatomic(struct intel_crtc *crtc);
 int intel_cdclk_init(struct intel_display *display);
 void intel_cdclk_debugfs_register(struct intel_display *display);
 
+int intel_cdclk_logical(const struct intel_cdclk_state *cdclk_state);
+
 #endif /* __INTEL_CDCLK_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index de8bf292897c..cd6fa1669074 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4168,7 +4168,7 @@ static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
 		return 0;
 
 	linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
-					cdclk_state->logical.cdclk);
+					intel_cdclk_logical(cdclk_state));
 
 	return min(linetime_wm, 0x1ff);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index ec1ef8694c35..5d28a6062db1 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1576,7 +1576,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state,
 		if (IS_ERR(cdclk_state))
 			return PTR_ERR(cdclk_state);
 
-		if (crtc_state->pixel_rate >= cdclk_state->logical.cdclk * 95 / 100) {
+		if (crtc_state->pixel_rate >= intel_cdclk_logical(cdclk_state) * 95 / 100) {
 			plane_state->no_fbc_reason = "pixel rate too high";
 			return 0;
 		}
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index f98c4a0fc7a9..f234a3aa3d15 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -2178,7 +2178,7 @@ cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state)
 	}
 
 	return min(1, DIV_ROUND_UP(crtc_state->pixel_rate,
-				   2 * cdclk_state->logical.cdclk));
+				   2 * intel_cdclk_logical(cdclk_state)));
 }
 
 static int
-- 
2.39.5

[CI v2 10/16] drm/i915/cdclk: abstract intel_cdclk_min_cdclk()

[Jani Nikula]

Add intel_cdclk_min_cdclk() helper to avoid looking at struct
intel_cdclk_state internals outside of intel_cdclk.c.

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 5 +++++
 drivers/gpu/drm/i915/display/intel_cdclk.h | 1 +
 drivers/gpu/drm/i915/display/intel_plane.c | 4 ++--
 3 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 51485c777b62..1fc82844458b 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3839,3 +3839,8 @@ int intel_cdclk_logical(const struct intel_cdclk_state *cdclk_state)
 {
 	return cdclk_state->logical.cdclk;
 }
+
+int intel_cdclk_min_cdclk(const struct intel_cdclk_state *cdclk_state, enum pipe pipe)
+{
+	return cdclk_state->min_cdclk[pipe];
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index 20a66f613072..ef6ad9d04c20 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -98,5 +98,6 @@ int intel_cdclk_init(struct intel_display *display);
 void intel_cdclk_debugfs_register(struct intel_display *display);
 
 int intel_cdclk_logical(const struct intel_cdclk_state *cdclk_state);
+int intel_cdclk_min_cdclk(const struct intel_cdclk_state *cdclk_state, enum pipe pipe);
 
 #endif /* __INTEL_CDCLK_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_plane.c b/drivers/gpu/drm/i915/display/intel_plane.c
index eae926d998ff..7c28ef677107 100644
--- a/drivers/gpu/drm/i915/display/intel_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_plane.c
@@ -333,7 +333,7 @@ int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
 	 * display blinking due to constant cdclk changes.
 	 */
 	if (new_crtc_state->min_cdclk[plane->id] <=
-	    cdclk_state->min_cdclk[crtc->pipe])
+	    intel_cdclk_min_cdclk(cdclk_state, crtc->pipe))
 		return 0;
 
 	drm_dbg_kms(display->drm,
@@ -341,7 +341,7 @@ int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
 		    plane->base.base.id, plane->base.name,
 		    new_crtc_state->min_cdclk[plane->id],
 		    crtc->base.base.id, crtc->base.name,
-		    cdclk_state->min_cdclk[crtc->pipe]);
+		    intel_cdclk_min_cdclk(cdclk_state, crtc->pipe));
 	*need_cdclk_calc = true;
 
 	return 0;
-- 
2.39.5

[CI v2 11/16] drm/i915/cdclk: abstract intel_cdclk_bw_min_cdclk()

[Jani Nikula]

Add intel_cdclk_bw_min_cdclk() helper to avoid looking at struct
intel_cdclk_state internals outside of intel_cdclk.c.

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c    | 4 ++--
 drivers/gpu/drm/i915/display/intel_cdclk.c | 5 +++++
 drivers/gpu/drm/i915/display/intel_cdclk.h | 1 +
 3 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 5942a3bae32c..d29a755612de 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -1468,12 +1468,12 @@ int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
 	 * requirements. This can reduce back and forth
 	 * display blinking due to constant cdclk changes.
 	 */
-	if (new_min_cdclk <= cdclk_state->bw_min_cdclk)
+	if (new_min_cdclk <= intel_cdclk_bw_min_cdclk(cdclk_state))
 		return 0;
 
 	drm_dbg_kms(display->drm,
 		    "new bandwidth min cdclk (%d kHz) > old min cdclk (%d kHz)\n",
-		    new_min_cdclk, cdclk_state->bw_min_cdclk);
+		    new_min_cdclk, intel_cdclk_bw_min_cdclk(cdclk_state));
 	*need_cdclk_calc = true;
 
 	return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 1fc82844458b..baec4042e4b6 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3844,3 +3844,8 @@ int intel_cdclk_min_cdclk(const struct intel_cdclk_state *cdclk_state, enum pipe
 {
 	return cdclk_state->min_cdclk[pipe];
 }
+
+int intel_cdclk_bw_min_cdclk(const struct intel_cdclk_state *cdclk_state)
+{
+	return cdclk_state->bw_min_cdclk;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index ef6ad9d04c20..fe1a1f1c1900 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -99,5 +99,6 @@ void intel_cdclk_debugfs_register(struct intel_display *display);
 
 int intel_cdclk_logical(const struct intel_cdclk_state *cdclk_state);
 int intel_cdclk_min_cdclk(const struct intel_cdclk_state *cdclk_state, enum pipe pipe);
+int intel_cdclk_bw_min_cdclk(const struct intel_cdclk_state *cdclk_state);
 
 #endif /* __INTEL_CDCLK_H__ */
-- 
2.39.5

[CI v2 12/16] drm/i915/cdclk: abstract intel_cdclk_pmdemand_needs_update()

[Jani Nikula]

Add intel_cdclk_pmdemand_needs_update() helper to avoid looking at
struct intel_cdclk_state internals outside of intel_cdclk.c.

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c    | 15 +++++++++++++++
 drivers/gpu/drm/i915/display/intel_cdclk.h    |  1 +
 drivers/gpu/drm/i915/display/intel_pmdemand.c |  9 +--------
 3 files changed, 17 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index baec4042e4b6..a0c254f942fd 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3849,3 +3849,18 @@ int intel_cdclk_bw_min_cdclk(const struct intel_cdclk_state *cdclk_state)
 {
 	return cdclk_state->bw_min_cdclk;
 }
+
+bool intel_cdclk_pmdemand_needs_update(struct intel_atomic_state *state)
+{
+	const struct intel_cdclk_state *new_cdclk_state, *old_cdclk_state;
+
+	new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
+	old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
+
+	if (new_cdclk_state &&
+	    (new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk ||
+	     new_cdclk_state->actual.voltage_level != old_cdclk_state->actual.voltage_level))
+		return true;
+
+	return false;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index fe1a1f1c1900..8527a6e44ee5 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -100,5 +100,6 @@ void intel_cdclk_debugfs_register(struct intel_display *display);
 int intel_cdclk_logical(const struct intel_cdclk_state *cdclk_state);
 int intel_cdclk_min_cdclk(const struct intel_cdclk_state *cdclk_state, enum pipe pipe);
 int intel_cdclk_bw_min_cdclk(const struct intel_cdclk_state *cdclk_state);
+bool intel_cdclk_pmdemand_needs_update(struct intel_atomic_state *state);
 
 #endif /* __INTEL_CDCLK_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
index a4d53fd94489..16ef68ef4041 100644
--- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
@@ -294,7 +294,6 @@ intel_pmdemand_connector_needs_update(struct intel_atomic_state *state)
 
 static bool intel_pmdemand_needs_update(struct intel_atomic_state *state)
 {
-	const struct intel_cdclk_state *new_cdclk_state, *old_cdclk_state;
 	const struct intel_crtc_state *new_crtc_state, *old_crtc_state;
 	struct intel_crtc *crtc;
 	int i;
@@ -305,13 +304,7 @@ static bool intel_pmdemand_needs_update(struct intel_atomic_state *state)
 	if (intel_dbuf_pmdemand_needs_update(state))
 		return true;
 
-	new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
-	old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
-	if (new_cdclk_state &&
-	    (new_cdclk_state->actual.cdclk !=
-	     old_cdclk_state->actual.cdclk ||
-	     new_cdclk_state->actual.voltage_level !=
-	     old_cdclk_state->actual.voltage_level))
+	if (intel_cdclk_pmdemand_needs_update(state))
 		return true;
 
 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
-- 
2.39.5

[CI v2 13/16] drm/i915/cdclk: abstract intel_cdclk_force_min_cdclk()

[Jani Nikula]

Add intel_cdclk_force_min_cdclk() helper to avoid modifying struct
intel_cdclk_state internals outside of intel_cdclk.c.

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_audio.c | 2 +-
 drivers/gpu/drm/i915/display/intel_cdclk.c | 5 +++++
 drivers/gpu/drm/i915/display/intel_cdclk.h | 1 +
 3 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index 55af3a553c58..5bdaef38f13d 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -951,7 +951,7 @@ static int glk_force_audio_cdclk_commit(struct intel_atomic_state *state,
 	if (IS_ERR(cdclk_state))
 		return PTR_ERR(cdclk_state);
 
-	cdclk_state->force_min_cdclk = enable ? 2 * 96000 : 0;
+	intel_cdclk_force_min_cdclk(cdclk_state, enable ? 2 * 96000 : 0);
 
 	return drm_atomic_commit(&state->base);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index a0c254f942fd..0c2d0195a2d9 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3864,3 +3864,8 @@ bool intel_cdclk_pmdemand_needs_update(struct intel_atomic_state *state)
 
 	return false;
 }
+
+void intel_cdclk_force_min_cdclk(struct intel_cdclk_state *cdclk_state, int force_min_cdclk)
+{
+	cdclk_state->force_min_cdclk = force_min_cdclk;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index 8527a6e44ee5..ff10ed526bd4 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -101,5 +101,6 @@ int intel_cdclk_logical(const struct intel_cdclk_state *cdclk_state);
 int intel_cdclk_min_cdclk(const struct intel_cdclk_state *cdclk_state, enum pipe pipe);
 int intel_cdclk_bw_min_cdclk(const struct intel_cdclk_state *cdclk_state);
 bool intel_cdclk_pmdemand_needs_update(struct intel_atomic_state *state);
+void intel_cdclk_force_min_cdclk(struct intel_cdclk_state *cdclk_state, int force_min_cdclk);
 
 #endif /* __INTEL_CDCLK_H__ */
-- 
2.39.5

[CI v2 14/16] drm/i915/cdclk: abstract intel_cdclk_read_hw()

[Jani Nikula]

Add intel_cdclk_read_hw() function to avoid looking at struct
intel_cdclk_state internals outside of intel_cdclk.c.

intel_cdclk_init_hw() would be a better name, but we already have that.

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c          | 12 ++++++++++++
 drivers/gpu/drm/i915/display/intel_cdclk.h          |  1 +
 drivers/gpu/drm/i915/display/intel_display_driver.c |  8 +-------
 3 files changed, 14 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 0c2d0195a2d9..156b5b5190cc 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3869,3 +3869,15 @@ void intel_cdclk_force_min_cdclk(struct intel_cdclk_state *cdclk_state, int forc
 {
 	cdclk_state->force_min_cdclk = force_min_cdclk;
 }
+
+void intel_cdclk_read_hw(struct intel_display *display)
+{
+	struct intel_cdclk_state *cdclk_state;
+
+	cdclk_state = to_intel_cdclk_state(display->cdclk.obj.state);
+
+	intel_update_cdclk(display);
+	intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK");
+	cdclk_state->actual = display->cdclk.hw;
+	cdclk_state->logical = display->cdclk.hw;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index ff10ed526bd4..0d5ee1826168 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -102,5 +102,6 @@ int intel_cdclk_min_cdclk(const struct intel_cdclk_state *cdclk_state, enum pipe
 int intel_cdclk_bw_min_cdclk(const struct intel_cdclk_state *cdclk_state);
 bool intel_cdclk_pmdemand_needs_update(struct intel_atomic_state *state);
 void intel_cdclk_force_min_cdclk(struct intel_cdclk_state *cdclk_state, int force_min_cdclk);
+void intel_cdclk_read_hw(struct intel_display *display);
 
 #endif /* __INTEL_CDCLK_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
index ec799a1773e4..9058c23dd487 100644
--- a/drivers/gpu/drm/i915/display/intel_display_driver.c
+++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
@@ -84,16 +84,10 @@ bool intel_display_driver_probe_defer(struct pci_dev *pdev)
 
 void intel_display_driver_init_hw(struct intel_display *display)
 {
-	struct intel_cdclk_state *cdclk_state;
-
 	if (!HAS_DISPLAY(display))
 		return;
 
-	cdclk_state = to_intel_cdclk_state(display->cdclk.obj.state);
-
-	intel_update_cdclk(display);
-	intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK");
-	cdclk_state->logical = cdclk_state->actual = display->cdclk.hw;
+	intel_cdclk_read_hw(display);
 
 	intel_display_wa_apply(display);
 }
-- 
2.39.5

[CI v2 15/16] drm/i915/cdclk: abstract intel_cdclk_actual() and intel_cdclk_actual_voltage_level()

[Jani Nikula]

Add intel_cdclk_actual() and intel_cdclk_actual_voltage_level() helpers
to avoid looking at struct intel_cdclk_state internals outside of
intel_cdclk.c.

v2: Better location (Imre)

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c    | 10 ++++++++++
 drivers/gpu/drm/i915/display/intel_cdclk.h    |  2 ++
 drivers/gpu/drm/i915/display/intel_pmdemand.c |  4 ++--
 3 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 156b5b5190cc..588d776e8624 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3840,6 +3840,16 @@ int intel_cdclk_logical(const struct intel_cdclk_state *cdclk_state)
 	return cdclk_state->logical.cdclk;
 }
 
+int intel_cdclk_actual(const struct intel_cdclk_state *cdclk_state)
+{
+	return cdclk_state->actual.cdclk;
+}
+
+int intel_cdclk_actual_voltage_level(const struct intel_cdclk_state *cdclk_state)
+{
+	return cdclk_state->actual.voltage_level;
+}
+
 int intel_cdclk_min_cdclk(const struct intel_cdclk_state *cdclk_state, enum pipe pipe)
 {
 	return cdclk_state->min_cdclk[pipe];
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index 0d5ee1826168..07f8b184b5fe 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -98,6 +98,8 @@ int intel_cdclk_init(struct intel_display *display);
 void intel_cdclk_debugfs_register(struct intel_display *display);
 
 int intel_cdclk_logical(const struct intel_cdclk_state *cdclk_state);
+int intel_cdclk_actual(const struct intel_cdclk_state *cdclk_state);
+int intel_cdclk_actual_voltage_level(const struct intel_cdclk_state *cdclk_state);
 int intel_cdclk_min_cdclk(const struct intel_cdclk_state *cdclk_state, enum pipe pipe);
 int intel_cdclk_bw_min_cdclk(const struct intel_cdclk_state *cdclk_state);
 bool intel_cdclk_pmdemand_needs_update(struct intel_atomic_state *state);
diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
index 16ef68ef4041..d806c15db7ce 100644
--- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
@@ -360,9 +360,9 @@ int intel_pmdemand_atomic_check(struct intel_atomic_state *state)
 		return PTR_ERR(new_cdclk_state);
 
 	new_pmdemand_state->params.voltage_index =
-		new_cdclk_state->actual.voltage_level;
+		intel_cdclk_actual_voltage_level(new_cdclk_state);
 	new_pmdemand_state->params.cdclk_freq_mhz =
-		DIV_ROUND_UP(new_cdclk_state->actual.cdclk, 1000);
+		DIV_ROUND_UP(intel_cdclk_actual(new_cdclk_state), 1000);
 
 	intel_pmdemand_update_max_ddiclk(display, state, new_pmdemand_state);
 
-- 
2.39.5

[CI v2 16/16] drm/i915/cdclk: make struct intel_cdclk_state opaque

[Jani Nikula]

With all the code touching struct intel_cdclk_state moved inside
intel_cdclk.c, we move the struct definition there too, and make the
type opaque. This nicely reduces includes from intel_cdclk.h.

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 36 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_cdclk.h | 41 ++--------------------
 2 files changed, 38 insertions(+), 39 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 588d776e8624..228aa64c1349 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -114,6 +114,42 @@
  * dividers can be programmed correctly.
  */
 
+struct intel_cdclk_state {
+	struct intel_global_state base;
+
+	/*
+	 * Logical configuration of cdclk (used for all scaling,
+	 * watermark, etc. calculations and checks). This is
+	 * computed as if all enabled crtcs were active.
+	 */
+	struct intel_cdclk_config logical;
+
+	/*
+	 * Actual configuration of cdclk, can be different from the
+	 * logical configuration only when all crtc's are DPMS off.
+	 */
+	struct intel_cdclk_config actual;
+
+	/* minimum acceptable cdclk to satisfy bandwidth requirements */
+	int bw_min_cdclk;
+	/* minimum acceptable cdclk for each pipe */
+	int min_cdclk[I915_MAX_PIPES];
+	/* minimum acceptable voltage level for each pipe */
+	u8 min_voltage_level[I915_MAX_PIPES];
+
+	/* pipe to which cd2x update is synchronized */
+	enum pipe pipe;
+
+	/* forced minimum cdclk for glk+ audio w/a */
+	int force_min_cdclk;
+
+	/* bitmask of active pipes */
+	u8 active_pipes;
+
+	/* update cdclk with pipes disabled */
+	bool disable_pipes;
+};
+
 struct intel_cdclk_funcs {
 	void (*get_cdclk)(struct intel_display *display,
 			  struct intel_cdclk_config *cdclk_config);
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index 07f8b184b5fe..cacee598af0e 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -8,10 +8,9 @@
 
 #include <linux/types.h>
 
-#include "intel_display_limits.h"
-#include "intel_global_state.h"
-
+enum pipe;
 struct intel_atomic_state;
+struct intel_cdclk_state;
 struct intel_crtc;
 struct intel_crtc_state;
 struct intel_display;
@@ -23,42 +22,6 @@ struct intel_cdclk_config {
 	bool joined_mbus;
 };
 
-struct intel_cdclk_state {
-	struct intel_global_state base;
-
-	/*
-	 * Logical configuration of cdclk (used for all scaling,
-	 * watermark, etc. calculations and checks). This is
-	 * computed as if all enabled crtcs were active.
-	 */
-	struct intel_cdclk_config logical;
-
-	/*
-	 * Actual configuration of cdclk, can be different from the
-	 * logical configuration only when all crtc's are DPMS off.
-	 */
-	struct intel_cdclk_config actual;
-
-	/* minimum acceptable cdclk to satisfy bandwidth requirements */
-	int bw_min_cdclk;
-	/* minimum acceptable cdclk for each pipe */
-	int min_cdclk[I915_MAX_PIPES];
-	/* minimum acceptable voltage level for each pipe */
-	u8 min_voltage_level[I915_MAX_PIPES];
-
-	/* pipe to which cd2x update is synchronized */
-	enum pipe pipe;
-
-	/* forced minimum cdclk for glk+ audio w/a */
-	int force_min_cdclk;
-
-	/* bitmask of active pipes */
-	u8 active_pipes;
-
-	/* update cdclk with pipes disabled */
-	bool disable_pipes;
-};
-
 void intel_cdclk_init_hw(struct intel_display *display);
 void intel_cdclk_uninit_hw(struct intel_display *display);
 void intel_init_cdclk_hooks(struct intel_display *display);
-- 
2.39.5

✗ CI.checkpatch: warning for drm/i915/display: make all global state opaque (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/display: make all global state opaque (rev2)
URL   : https://patchwork.freedesktop.org/series/150157/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
f8ff75ae1d2127635239b134695774ed4045d05b
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 03470e8c7ece10eeaeec77d95bf2529d4d878040
Author: Jani Nikula <jani.nikula@intel.com>
Date:   Wed Jun 25 13:32:34 2025 +0300

    drm/i915/cdclk: make struct intel_cdclk_state opaque
    
    With all the code touching struct intel_cdclk_state moved inside
    intel_cdclk.c, we move the struct definition there too, and make the
    type opaque. This nicely reduces includes from intel_cdclk.h.
    
    Reviewed-by: Imre Deak <imre.deak@intel.com>
    Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+ /mt/dim checkpatch e4196e8184ee5a9c70c136f659dccef786c263b3 drm-intel
0039319189b4 drm/i915/wm: abstract intel_dbuf_pmdemand_needs_update()
-:64: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'state' - possible side-effects?
#64: FILE: drivers/gpu/drm/i915/display/skl_watermark.c:45:
+#define intel_atomic_get_old_dbuf_state(state) \
+	to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state, &to_intel_display(state)->dbuf.obj))

-:65: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#65: FILE: drivers/gpu/drm/i915/display/skl_watermark.c:46:
+	to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state, &to_intel_display(state)->dbuf.obj))

-:66: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'state' - possible side-effects?
#66: FILE: drivers/gpu/drm/i915/display/skl_watermark.c:47:
+#define intel_atomic_get_new_dbuf_state(state) \
+	to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_intel_display(state)->dbuf.obj))

-:67: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#67: FILE: drivers/gpu/drm/i915/display/skl_watermark.c:48:
+	to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_intel_display(state)->dbuf.obj))

total: 0 errors, 2 warnings, 2 checks, 94 lines checked
cf99f9955488 drm/i915/wm: add more accessors to dbuf state
-:29: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#29: FILE: drivers/gpu/drm/i915/display/intel_pmdemand.c:366:
+			min_t(u8, intel_dbuf_num_active_pipes(new_dbuf_state), INTEL_NUM_PIPES(display));

total: 0 errors, 1 warnings, 0 checks, 40 lines checked
7c151bf53e16 drm/i915/wm: make struct intel_dbuf_state opaque type
ce8b5d2c32f8 drm/i915/bw: abstract intel_bw_pmdemand_needs_update()
eae7144cbf1d drm/i915/bw: relocate intel_can_enable_sagv() and rename to intel_bw_can_enable_sagv()
4d9c2f4c5934 drm/i915: move icl_sagv_{pre, post}_plane_update() to intel_bw.c
3d0e5a83bb3b drm/i915/bw: abstract intel_bw_qgv_point_peakbw()
e32ed708fb64 drm/i915/bw: make struct intel_bw_state opaque
f81cfbc4a25b drm/i915/cdclk: abstract intel_cdclk_logical()
ae21fbc18dd6 drm/i915/cdclk: abstract intel_cdclk_min_cdclk()
41eee6fbfe50 drm/i915/cdclk: abstract intel_cdclk_bw_min_cdclk()
f409597f69ba drm/i915/cdclk: abstract intel_cdclk_pmdemand_needs_update()
efec290d819f drm/i915/cdclk: abstract intel_cdclk_force_min_cdclk()
216c5784b41d drm/i915/cdclk: abstract intel_cdclk_read_hw()
5aa60c5a12aa drm/i915/cdclk: abstract intel_cdclk_actual() and intel_cdclk_actual_voltage_level()
03470e8c7ece drm/i915/cdclk: make struct intel_cdclk_state opaque

✓ CI.KUnit: success for drm/i915/display: make all global state opaque (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/display: make all global state opaque (rev2)
URL   : https://patchwork.freedesktop.org/series/150157/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[10:42:21] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:42:26] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[10:42:52] Starting KUnit Kernel (1/1)...
[10:42:52] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:42:53] ================== guc_buf (11 subtests) ===================
[10:42:53] [PASSED] test_smallest
[10:42:53] [PASSED] test_largest
[10:42:53] [PASSED] test_granular
[10:42:53] [PASSED] test_unique
[10:42:53] [PASSED] test_overlap
[10:42:53] [PASSED] test_reusable
[10:42:53] [PASSED] test_too_big
[10:42:53] [PASSED] test_flush
[10:42:53] [PASSED] test_lookup
[10:42:53] [PASSED] test_data
[10:42:53] [PASSED] test_class
[10:42:53] ===================== [PASSED] guc_buf =====================
[10:42:53] =================== guc_dbm (7 subtests) ===================
[10:42:53] [PASSED] test_empty
[10:42:53] [PASSED] test_default
[10:42:53] ======================== test_size  ========================
[10:42:53] [PASSED] 4
[10:42:53] [PASSED] 8
[10:42:53] [PASSED] 32
[10:42:53] [PASSED] 256
[10:42:53] ==================== [PASSED] test_size ====================
[10:42:53] ======================= test_reuse  ========================
[10:42:53] [PASSED] 4
[10:42:53] [PASSED] 8
[10:42:53] [PASSED] 32
[10:42:53] [PASSED] 256
[10:42:53] =================== [PASSED] test_reuse ====================
[10:42:53] =================== test_range_overlap  ====================
[10:42:53] [PASSED] 4
[10:42:53] [PASSED] 8
[10:42:53] [PASSED] 32
[10:42:53] [PASSED] 256
[10:42:53] =============== [PASSED] test_range_overlap ================
[10:42:53] =================== test_range_compact  ====================
[10:42:53] [PASSED] 4
[10:42:53] [PASSED] 8
[10:42:53] [PASSED] 32
[10:42:53] [PASSED] 256
[10:42:53] =============== [PASSED] test_range_compact ================
[10:42:53] ==================== test_range_spare  =====================
[10:42:53] [PASSED] 4
[10:42:53] [PASSED] 8
[10:42:53] [PASSED] 32
[10:42:53] [PASSED] 256
[10:42:53] ================ [PASSED] test_range_spare =================
[10:42:53] ===================== [PASSED] guc_dbm =====================
[10:42:53] =================== guc_idm (6 subtests) ===================
[10:42:53] [PASSED] bad_init
[10:42:53] [PASSED] no_init
[10:42:53] [PASSED] init_fini
[10:42:53] [PASSED] check_used
[10:42:53] [PASSED] check_quota
[10:42:53] [PASSED] check_all
[10:42:53] ===================== [PASSED] guc_idm =====================
[10:42:53] ================== no_relay (3 subtests) ===================
[10:42:53] [PASSED] xe_drops_guc2pf_if_not_ready
[10:42:53] [PASSED] xe_drops_guc2vf_if_not_ready
[10:42:53] [PASSED] xe_rejects_send_if_not_ready
[10:42:53] ==================== [PASSED] no_relay =====================
[10:42:53] ================== pf_relay (14 subtests) ==================
[10:42:53] [PASSED] pf_rejects_guc2pf_too_short
[10:42:53] [PASSED] pf_rejects_guc2pf_too_long
[10:42:53] [PASSED] pf_rejects_guc2pf_no_payload
[10:42:53] [PASSED] pf_fails_no_payload
[10:42:53] [PASSED] pf_fails_bad_origin
[10:42:53] [PASSED] pf_fails_bad_type
[10:42:53] [PASSED] pf_txn_reports_error
[10:42:53] [PASSED] pf_txn_sends_pf2guc
[10:42:53] [PASSED] pf_sends_pf2guc
[10:42:53] [SKIPPED] pf_loopback_nop
[10:42:53] [SKIPPED] pf_loopback_echo
[10:42:53] [SKIPPED] pf_loopback_fail
[10:42:53] [SKIPPED] pf_loopback_busy
[10:42:53] [SKIPPED] pf_loopback_retry
[10:42:53] ==================== [PASSED] pf_relay =====================
[10:42:53] ================== vf_relay (3 subtests) ===================
[10:42:53] [PASSED] vf_rejects_guc2vf_too_short
[10:42:53] [PASSED] vf_rejects_guc2vf_too_long
[10:42:53] [PASSED] vf_rejects_guc2vf_no_payload
[10:42:53] ==================== [PASSED] vf_relay =====================
[10:42:53] ================= pf_service (11 subtests) =================
[10:42:53] [PASSED] pf_negotiate_any
[10:42:53] [PASSED] pf_negotiate_base_match
[10:42:53] [PASSED] pf_negotiate_base_newer
[10:42:53] [PASSED] pf_negotiate_base_next
[10:42:53] [SKIPPED] pf_negotiate_base_older
[10:42:53] [PASSED] pf_negotiate_base_prev
[10:42:53] [PASSED] pf_negotiate_latest_match
[10:42:53] [PASSED] pf_negotiate_latest_newer
[10:42:53] [PASSED] pf_negotiate_latest_next
[10:42:53] [SKIPPED] pf_negotiate_latest_older
[10:42:53] [SKIPPED] pf_negotiate_latest_prev
[10:42:53] =================== [PASSED] pf_service ====================
[10:42:53] ===================== lmtt (1 subtest) =====================
[10:42:53] ======================== test_ops  =========================
[10:42:53] [PASSED] 2-level
[10:42:53] [PASSED] multi-level
[10:42:53] ==================== [PASSED] test_ops =====================
[10:42:53] ====================== [PASSED] lmtt =======================
[10:42:53] =================== xe_mocs (2 subtests) ===================
[10:42:53] ================ xe_live_mocs_kernel_kunit  ================
[10:42:53] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[10:42:53] ================ xe_live_mocs_reset_kunit  =================
[10:42:53] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[10:42:53] ==================== [SKIPPED] xe_mocs =====================
[10:42:53] ================= xe_migrate (2 subtests) ==================
[10:42:53] ================= xe_migrate_sanity_kunit  =================
[10:42:53] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[10:42:53] ================== xe_validate_ccs_kunit  ==================
[10:42:53] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[10:42:53] =================== [SKIPPED] xe_migrate ===================
[10:42:53] ================== xe_dma_buf (1 subtest) ==================
[10:42:53] ==================== xe_dma_buf_kunit  =====================
[10:42:53] ================ [SKIPPED] xe_dma_buf_kunit ================
[10:42:53] =================== [SKIPPED] xe_dma_buf ===================
[10:42:53] ================= xe_bo_shrink (1 subtest) =================
[10:42:53] =================== xe_bo_shrink_kunit  ====================
[10:42:53] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[10:42:53] ================== [SKIPPED] xe_bo_shrink ==================
[10:42:53] ==================== xe_bo (2 subtests) ====================
[10:42:53] ================== xe_ccs_migrate_kunit  ===================
[10:42:53] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[10:42:53] ==================== xe_bo_evict_kunit  ====================
[10:42:53] =============== [SKIPPED] xe_bo_evict_kunit ================
[10:42:53] ===================== [SKIPPED] xe_bo ======================
[10:42:53] ==================== args (11 subtests) ====================
[10:42:53] [PASSED] count_args_test
[10:42:53] [PASSED] call_args_example
[10:42:53] [PASSED] call_args_test
[10:42:53] [PASSED] drop_first_arg_example
[10:42:53] [PASSED] drop_first_arg_test
[10:42:53] [PASSED] first_arg_example
[10:42:53] [PASSED] first_arg_test
[10:42:53] [PASSED] last_arg_example
[10:42:53] [PASSED] last_arg_test
[10:42:53] [PASSED] pick_arg_example
[10:42:53] [PASSED] sep_comma_example
[10:42:53] ====================== [PASSED] args =======================
[10:42:53] =================== xe_pci (2 subtests) ====================
[10:42:53] ==================== check_graphics_ip  ====================
[10:42:53] [PASSED] 12.70 Xe_LPG
[10:42:53] [PASSED] 12.71 Xe_LPG
[10:42:53] [PASSED] 12.74 Xe_LPG+
[10:42:53] [PASSED] 20.01 Xe2_HPG
[10:42:53] [PASSED] 20.02 Xe2_HPG
[10:42:53] [PASSED] 20.04 Xe2_LPG
[10:42:53] [PASSED] 30.00 Xe3_LPG
[10:42:53] [PASSED] 30.01 Xe3_LPG
[10:42:53] [PASSED] 30.03 Xe3_LPG
[10:42:53] ================ [PASSED] check_graphics_ip ================
[10:42:53] ===================== check_media_ip  ======================
[10:42:53] [PASSED] 13.00 Xe_LPM+
[10:42:53] [PASSED] 13.01 Xe2_HPM
[10:42:53] [PASSED] 20.00 Xe2_LPM
[10:42:53] [PASSED] 30.00 Xe3_LPM
[10:42:53] [PASSED] 30.02 Xe3_LPM
stty: 'standard input': Inappropriate ioctl for device
[10:42:53] ================= [PASSED] check_media_ip ==================
[10:42:53] ===================== [PASSED] xe_pci ======================
[10:42:53] =================== xe_rtp (2 subtests) ====================
[10:42:53] =============== xe_rtp_process_to_sr_tests  ================
[10:42:53] [PASSED] coalesce-same-reg
[10:42:53] [PASSED] no-match-no-add
[10:42:53] [PASSED] match-or
[10:42:53] [PASSED] match-or-xfail
[10:42:53] [PASSED] no-match-no-add-multiple-rules
[10:42:53] [PASSED] two-regs-two-entries
[10:42:53] [PASSED] clr-one-set-other
[10:42:53] [PASSED] set-field
[10:42:53] [PASSED] conflict-duplicate
[10:42:53] [PASSED] conflict-not-disjoint
[10:42:53] [PASSED] conflict-reg-type
[10:42:53] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[10:42:53] ================== xe_rtp_process_tests  ===================
[10:42:53] [PASSED] active1
[10:42:53] [PASSED] active2
[10:42:53] [PASSED] active-inactive
[10:42:53] [PASSED] inactive-active
[10:42:53] [PASSED] inactive-1st_or_active-inactive
[10:42:53] [PASSED] inactive-2nd_or_active-inactive
[10:42:53] [PASSED] inactive-last_or_active-inactive
[10:42:53] [PASSED] inactive-no_or_active-inactive
[10:42:53] ============== [PASSED] xe_rtp_process_tests ===============
[10:42:53] ===================== [PASSED] xe_rtp ======================
[10:42:53] ==================== xe_wa (1 subtest) =====================
[10:42:53] ======================== xe_wa_gt  =========================
[10:42:53] [PASSED] TIGERLAKE (B0)
[10:42:53] [PASSED] DG1 (A0)
[10:42:53] [PASSED] DG1 (B0)
[10:42:53] [PASSED] ALDERLAKE_S (A0)
[10:42:53] [PASSED] ALDERLAKE_S (B0)
[10:42:53] [PASSED] ALDERLAKE_S (C0)
[10:42:53] [PASSED] ALDERLAKE_S (D0)
[10:42:53] [PASSED] ALDERLAKE_P (A0)
[10:42:53] [PASSED] ALDERLAKE_P (B0)
[10:42:53] [PASSED] ALDERLAKE_P (C0)
[10:42:53] [PASSED] ALDERLAKE_S_RPLS (D0)
[10:42:53] [PASSED] ALDERLAKE_P_RPLU (E0)
[10:42:53] [PASSED] DG2_G10 (C0)
[10:42:53] [PASSED] DG2_G11 (B1)
[10:42:53] [PASSED] DG2_G12 (A1)
[10:42:53] [PASSED] METEORLAKE (g:A0, m:A0)
[10:42:53] [PASSED] METEORLAKE (g:A0, m:A0)
[10:42:53] [PASSED] METEORLAKE (g:A0, m:A0)
[10:42:53] [PASSED] LUNARLAKE (g:A0, m:A0)
[10:42:53] [PASSED] LUNARLAKE (g:B0, m:A0)
[10:42:53] [PASSED] BATTLEMAGE (g:A0, m:A1)
[10:42:53] ==================== [PASSED] xe_wa_gt =====================
[10:42:53] ====================== [PASSED] xe_wa ======================
[10:42:53] ============================================================
[10:42:53] Testing complete. Ran 145 tests: passed: 129, skipped: 16
[10:42:53] Elapsed time: 31.185s total, 4.138s configuring, 26.730s building, 0.307s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[10:42:53] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:42:54] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[10:43:16] Starting KUnit Kernel (1/1)...
[10:43:16] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:43:16] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[10:43:16] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[10:43:16] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[10:43:16] =========== drm_validate_clone_mode (2 subtests) ===========
[10:43:16] ============== drm_test_check_in_clone_mode  ===============
[10:43:16] [PASSED] in_clone_mode
[10:43:16] [PASSED] not_in_clone_mode
[10:43:16] ========== [PASSED] drm_test_check_in_clone_mode ===========
[10:43:16] =============== drm_test_check_valid_clones  ===============
[10:43:16] [PASSED] not_in_clone_mode
[10:43:16] [PASSED] valid_clone
[10:43:16] [PASSED] invalid_clone
[10:43:16] =========== [PASSED] drm_test_check_valid_clones ===========
[10:43:16] ============= [PASSED] drm_validate_clone_mode =============
[10:43:16] ============= drm_validate_modeset (1 subtest) =============
[10:43:16] [PASSED] drm_test_check_connector_changed_modeset
[10:43:16] ============== [PASSED] drm_validate_modeset ===============
[10:43:16] ====== drm_test_bridge_get_current_state (2 subtests) ======
[10:43:16] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[10:43:16] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[10:43:16] ======== [PASSED] drm_test_bridge_get_current_state ========
[10:43:16] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[10:43:16] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[10:43:16] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[10:43:16] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[10:43:16] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[10:43:16] ============== drm_bridge_alloc (2 subtests) ===============
[10:43:16] [PASSED] drm_test_drm_bridge_alloc_basic
[10:43:16] [PASSED] drm_test_drm_bridge_alloc_get_put
[10:43:16] ================ [PASSED] drm_bridge_alloc =================
[10:43:16] ================== drm_buddy (7 subtests) ==================
[10:43:16] [PASSED] drm_test_buddy_alloc_limit
[10:43:16] [PASSED] drm_test_buddy_alloc_optimistic
[10:43:16] [PASSED] drm_test_buddy_alloc_pessimistic
[10:43:16] [PASSED] drm_test_buddy_alloc_pathological
[10:43:16] [PASSED] drm_test_buddy_alloc_contiguous
[10:43:16] [PASSED] drm_test_buddy_alloc_clear
[10:43:16] [PASSED] drm_test_buddy_alloc_range_bias
[10:43:16] ==================== [PASSED] drm_buddy ====================
[10:43:16] ============= drm_cmdline_parser (40 subtests) =============
[10:43:16] [PASSED] drm_test_cmdline_force_d_only
[10:43:16] [PASSED] drm_test_cmdline_force_D_only_dvi
[10:43:16] [PASSED] drm_test_cmdline_force_D_only_hdmi
[10:43:16] [PASSED] drm_test_cmdline_force_D_only_not_digital
[10:43:16] [PASSED] drm_test_cmdline_force_e_only
[10:43:16] [PASSED] drm_test_cmdline_res
[10:43:16] [PASSED] drm_test_cmdline_res_vesa
[10:43:16] [PASSED] drm_test_cmdline_res_vesa_rblank
[10:43:16] [PASSED] drm_test_cmdline_res_rblank
[10:43:16] [PASSED] drm_test_cmdline_res_bpp
[10:43:16] [PASSED] drm_test_cmdline_res_refresh
[10:43:16] [PASSED] drm_test_cmdline_res_bpp_refresh
[10:43:16] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[10:43:16] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[10:43:16] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[10:43:16] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[10:43:16] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[10:43:16] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[10:43:16] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[10:43:16] [PASSED] drm_test_cmdline_res_margins_force_on
[10:43:16] [PASSED] drm_test_cmdline_res_vesa_margins
[10:43:16] [PASSED] drm_test_cmdline_name
[10:43:16] [PASSED] drm_test_cmdline_name_bpp
[10:43:16] [PASSED] drm_test_cmdline_name_option
[10:43:16] [PASSED] drm_test_cmdline_name_bpp_option
[10:43:16] [PASSED] drm_test_cmdline_rotate_0
[10:43:16] [PASSED] drm_test_cmdline_rotate_90
[10:43:16] [PASSED] drm_test_cmdline_rotate_180
[10:43:16] [PASSED] drm_test_cmdline_rotate_270
[10:43:16] [PASSED] drm_test_cmdline_hmirror
[10:43:16] [PASSED] drm_test_cmdline_vmirror
[10:43:16] [PASSED] drm_test_cmdline_margin_options
[10:43:16] [PASSED] drm_test_cmdline_multiple_options
[10:43:16] [PASSED] drm_test_cmdline_bpp_extra_and_option
[10:43:16] [PASSED] drm_test_cmdline_extra_and_option
[10:43:16] [PASSED] drm_test_cmdline_freestanding_options
[10:43:16] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[10:43:16] [PASSED] drm_test_cmdline_panel_orientation
[10:43:16] ================ drm_test_cmdline_invalid  =================
[10:43:16] [PASSED] margin_only
[10:43:16] [PASSED] interlace_only
[10:43:16] [PASSED] res_missing_x
[10:43:16] [PASSED] res_missing_y
[10:43:16] [PASSED] res_bad_y
[10:43:16] [PASSED] res_missing_y_bpp
[10:43:16] [PASSED] res_bad_bpp
[10:43:16] [PASSED] res_bad_refresh
[10:43:16] [PASSED] res_bpp_refresh_force_on_off
[10:43:16] [PASSED] res_invalid_mode
[10:43:16] [PASSED] res_bpp_wrong_place_mode
[10:43:16] [PASSED] name_bpp_refresh
[10:43:16] [PASSED] name_refresh
[10:43:16] [PASSED] name_refresh_wrong_mode
[10:43:16] [PASSED] name_refresh_invalid_mode
[10:43:16] [PASSED] rotate_multiple
[10:43:16] [PASSED] rotate_invalid_val
[10:43:16] [PASSED] rotate_truncated
[10:43:16] [PASSED] invalid_option
[10:43:16] [PASSED] invalid_tv_option
[10:43:16] [PASSED] truncated_tv_option
[10:43:16] ============ [PASSED] drm_test_cmdline_invalid =============
[10:43:16] =============== drm_test_cmdline_tv_options  ===============
[10:43:16] [PASSED] NTSC
[10:43:16] [PASSED] NTSC_443
[10:43:16] [PASSED] NTSC_J
[10:43:16] [PASSED] PAL
[10:43:16] [PASSED] PAL_M
[10:43:16] [PASSED] PAL_N
[10:43:16] [PASSED] SECAM
[10:43:16] [PASSED] MONO_525
[10:43:16] [PASSED] MONO_625
[10:43:16] =========== [PASSED] drm_test_cmdline_tv_options ===========
[10:43:16] =============== [PASSED] drm_cmdline_parser ================
[10:43:16] ========== drmm_connector_hdmi_init (20 subtests) ==========
[10:43:16] [PASSED] drm_test_connector_hdmi_init_valid
[10:43:16] [PASSED] drm_test_connector_hdmi_init_bpc_8
[10:43:16] [PASSED] drm_test_connector_hdmi_init_bpc_10
[10:43:16] [PASSED] drm_test_connector_hdmi_init_bpc_12
[10:43:16] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[10:43:16] [PASSED] drm_test_connector_hdmi_init_bpc_null
[10:43:16] [PASSED] drm_test_connector_hdmi_init_formats_empty
[10:43:16] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[10:43:16] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[10:43:16] [PASSED] supported_formats=0x9 yuv420_allowed=1
[10:43:16] [PASSED] supported_formats=0x9 yuv420_allowed=0
[10:43:16] [PASSED] supported_formats=0x3 yuv420_allowed=1
[10:43:16] [PASSED] supported_formats=0x3 yuv420_allowed=0
[10:43:16] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[10:43:16] [PASSED] drm_test_connector_hdmi_init_null_ddc
[10:43:16] [PASSED] drm_test_connector_hdmi_init_null_product
[10:43:16] [PASSED] drm_test_connector_hdmi_init_null_vendor
[10:43:16] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[10:43:16] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[10:43:16] [PASSED] drm_test_connector_hdmi_init_product_valid
[10:43:16] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[10:43:16] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[10:43:16] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[10:43:16] ========= drm_test_connector_hdmi_init_type_valid  =========
[10:43:16] [PASSED] HDMI-A
[10:43:16] [PASSED] HDMI-B
[10:43:16] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[10:43:16] ======== drm_test_connector_hdmi_init_type_invalid  ========
[10:43:16] [PASSED] Unknown
[10:43:16] [PASSED] VGA
[10:43:16] [PASSED] DVI-I
[10:43:16] [PASSED] DVI-D
[10:43:16] [PASSED] DVI-A
[10:43:16] [PASSED] Composite
[10:43:16] [PASSED] SVIDEO
[10:43:16] [PASSED] LVDS
[10:43:16] [PASSED] Component
[10:43:16] [PASSED] DIN
[10:43:16] [PASSED] DP
[10:43:16] [PASSED] TV
[10:43:16] [PASSED] eDP
[10:43:16] [PASSED] Virtual
[10:43:16] [PASSED] DSI
[10:43:16] [PASSED] DPI
[10:43:16] [PASSED] Writeback
[10:43:16] [PASSED] SPI
[10:43:16] [PASSED] USB
[10:43:16] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[10:43:16] ============ [PASSED] drmm_connector_hdmi_init =============
[10:43:16] ============= drmm_connector_init (3 subtests) =============
[10:43:16] [PASSED] drm_test_drmm_connector_init
[10:43:16] [PASSED] drm_test_drmm_connector_init_null_ddc
[10:43:16] ========= drm_test_drmm_connector_init_type_valid  =========
[10:43:16] [PASSED] Unknown
[10:43:16] [PASSED] VGA
[10:43:16] [PASSED] DVI-I
[10:43:16] [PASSED] DVI-D
[10:43:16] [PASSED] DVI-A
[10:43:16] [PASSED] Composite
[10:43:16] [PASSED] SVIDEO
[10:43:16] [PASSED] LVDS
[10:43:16] [PASSED] Component
[10:43:16] [PASSED] DIN
[10:43:16] [PASSED] DP
[10:43:16] [PASSED] HDMI-A
[10:43:16] [PASSED] HDMI-B
[10:43:16] [PASSED] TV
[10:43:16] [PASSED] eDP
[10:43:16] [PASSED] Virtual
[10:43:16] [PASSED] DSI
[10:43:16] [PASSED] DPI
[10:43:16] [PASSED] Writeback
[10:43:16] [PASSED] SPI
[10:43:16] [PASSED] USB
[10:43:16] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[10:43:16] =============== [PASSED] drmm_connector_init ===============
[10:43:16] ========= drm_connector_dynamic_init (6 subtests) ==========
[10:43:16] [PASSED] drm_test_drm_connector_dynamic_init
[10:43:16] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[10:43:16] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[10:43:16] [PASSED] drm_test_drm_connector_dynamic_init_properties
[10:43:16] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[10:43:16] [PASSED] Unknown
[10:43:16] [PASSED] VGA
[10:43:16] [PASSED] DVI-I
[10:43:16] [PASSED] DVI-D
[10:43:16] [PASSED] DVI-A
[10:43:16] [PASSED] Composite
[10:43:16] [PASSED] SVIDEO
[10:43:16] [PASSED] LVDS
[10:43:16] [PASSED] Component
[10:43:16] [PASSED] DIN
[10:43:16] [PASSED] DP
[10:43:16] [PASSED] HDMI-A
[10:43:16] [PASSED] HDMI-B
[10:43:16] [PASSED] TV
[10:43:16] [PASSED] eDP
[10:43:16] [PASSED] Virtual
[10:43:16] [PASSED] DSI
[10:43:16] [PASSED] DPI
[10:43:16] [PASSED] Writeback
[10:43:16] [PASSED] SPI
[10:43:16] [PASSED] USB
[10:43:16] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[10:43:16] ======== drm_test_drm_connector_dynamic_init_name  =========
[10:43:16] [PASSED] Unknown
[10:43:16] [PASSED] VGA
[10:43:16] [PASSED] DVI-I
[10:43:16] [PASSED] DVI-D
[10:43:16] [PASSED] DVI-A
[10:43:16] [PASSED] Composite
[10:43:16] [PASSED] SVIDEO
[10:43:16] [PASSED] LVDS
[10:43:16] [PASSED] Component
[10:43:16] [PASSED] DIN
[10:43:16] [PASSED] DP
[10:43:16] [PASSED] HDMI-A
[10:43:16] [PASSED] HDMI-B
[10:43:16] [PASSED] TV
[10:43:16] [PASSED] eDP
[10:43:16] [PASSED] Virtual
[10:43:16] [PASSED] DSI
[10:43:16] [PASSED] DPI
[10:43:16] [PASSED] Writeback
[10:43:16] [PASSED] SPI
[10:43:16] [PASSED] USB
[10:43:16] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[10:43:16] =========== [PASSED] drm_connector_dynamic_init ============
[10:43:16] ==== drm_connector_dynamic_register_early (4 subtests) =====
[10:43:16] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[10:43:16] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[10:43:16] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[10:43:16] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[10:43:16] ====== [PASSED] drm_connector_dynamic_register_early =======
[10:43:16] ======= drm_connector_dynamic_register (7 subtests) ========
[10:43:16] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[10:43:16] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[10:43:16] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[10:43:16] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[10:43:16] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[10:43:16] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[10:43:16] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[10:43:16] ========= [PASSED] drm_connector_dynamic_register ==========
[10:43:16] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[10:43:16] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[10:43:16] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[10:43:16] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[10:43:16] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[10:43:16] ========== drm_test_get_tv_mode_from_name_valid  ===========
[10:43:16] [PASSED] NTSC
[10:43:16] [PASSED] NTSC-443
[10:43:16] [PASSED] NTSC-J
[10:43:16] [PASSED] PAL
[10:43:16] [PASSED] PAL-M
[10:43:16] [PASSED] PAL-N
[10:43:16] [PASSED] SECAM
[10:43:16] [PASSED] Mono
[10:43:16] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[10:43:16] [PASSED] drm_test_get_tv_mode_from_name_truncated
[10:43:16] ============ [PASSED] drm_get_tv_mode_from_name ============
[10:43:16] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[10:43:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[10:43:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[10:43:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[10:43:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[10:43:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[10:43:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[10:43:16] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[10:43:16] [PASSED] VIC 96
[10:43:16] [PASSED] VIC 97
[10:43:16] [PASSED] VIC 101
[10:43:16] [PASSED] VIC 102
[10:43:16] [PASSED] VIC 106
[10:43:16] [PASSED] VIC 107
[10:43:16] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[10:43:16] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[10:43:16] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[10:43:16] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[10:43:16] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[10:43:16] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[10:43:16] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[10:43:16] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[10:43:16] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[10:43:16] [PASSED] Automatic
[10:43:16] [PASSED] Full
[10:43:16] [PASSED] Limited 16:235
[10:43:16] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[10:43:16] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[10:43:16] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[10:43:16] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[10:43:16] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[10:43:16] [PASSED] RGB
[10:43:16] [PASSED] YUV 4:2:0
[10:43:16] [PASSED] YUV 4:2:2
[10:43:16] [PASSED] YUV 4:4:4
[10:43:16] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[10:43:16] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[10:43:16] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[10:43:16] ============= drm_damage_helper (21 subtests) ==============
[10:43:16] [PASSED] drm_test_damage_iter_no_damage
[10:43:16] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[10:43:16] [PASSED] drm_test_damage_iter_no_damage_src_moved
[10:43:16] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[10:43:16] [PASSED] drm_test_damage_iter_no_damage_not_visible
[10:43:16] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[10:43:16] [PASSED] drm_test_damage_iter_no_damage_no_fb
[10:43:16] [PASSED] drm_test_damage_iter_simple_damage
[10:43:16] [PASSED] drm_test_damage_iter_single_damage
[10:43:16] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[10:43:16] [PASSED] drm_test_damage_iter_single_damage_outside_src
[10:43:16] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[10:43:16] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[10:43:16] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[10:43:16] [PASSED] drm_test_damage_iter_single_damage_src_moved
[10:43:16] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[10:43:16] [PASSED] drm_test_damage_iter_damage
[10:43:16] [PASSED] drm_test_damage_iter_damage_one_intersect
[10:43:16] [PASSED] drm_test_damage_iter_damage_one_outside
[10:43:16] [PASSED] drm_test_damage_iter_damage_src_moved
[10:43:16] [PASSED] drm_test_damage_iter_damage_not_visible
[10:43:16] ================ [PASSED] drm_damage_helper ================
[10:43:16] ============== drm_dp_mst_helper (3 subtests) ==============
[10:43:16] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[10:43:16] [PASSED] Clock 154000 BPP 30 DSC disabled
[10:43:16] [PASSED] Clock 234000 BPP 30 DSC disabled
[10:43:16] [PASSED] Clock 297000 BPP 24 DSC disabled
[10:43:16] [PASSED] Clock 332880 BPP 24 DSC enabled
[10:43:16] [PASSED] Clock 324540 BPP 24 DSC enabled
[10:43:16] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[10:43:16] ============== drm_test_dp_mst_calc_pbn_div  ===============
[10:43:16] [PASSED] Link rate 2000000 lane count 4
[10:43:16] [PASSED] Link rate 2000000 lane count 2
[10:43:16] [PASSED] Link rate 2000000 lane count 1
[10:43:16] [PASSED] Link rate 1350000 lane count 4
[10:43:16] [PASSED] Link rate 1350000 lane count 2
[10:43:16] [PASSED] Link rate 1350000 lane count 1
[10:43:16] [PASSED] Link rate 1000000 lane count 4
[10:43:16] [PASSED] Link rate 1000000 lane count 2
[10:43:16] [PASSED] Link rate 1000000 lane count 1
[10:43:16] [PASSED] Link rate 810000 lane count 4
[10:43:16] [PASSED] Link rate 810000 lane count 2
[10:43:16] [PASSED] Link rate 810000 lane count 1
[10:43:16] [PASSED] Link rate 540000 lane count 4
[10:43:16] [PASSED] Link rate 540000 lane count 2
[10:43:16] [PASSED] Link rate 540000 lane count 1
[10:43:16] [PASSED] Link rate 270000 lane count 4
[10:43:16] [PASSED] Link rate 270000 lane count 2
[10:43:16] [PASSED] Link rate 270000 lane count 1
[10:43:16] [PASSED] Link rate 162000 lane count 4
[10:43:16] [PASSED] Link rate 162000 lane count 2
[10:43:16] [PASSED] Link rate 162000 lane count 1
[10:43:16] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[10:43:16] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[10:43:16] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[10:43:16] [PASSED] DP_POWER_UP_PHY with port number
[10:43:16] [PASSED] DP_POWER_DOWN_PHY with port number
[10:43:16] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[10:43:16] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[10:43:16] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[10:43:16] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[10:43:16] [PASSED] DP_QUERY_PAYLOAD with port number
[10:43:16] [PASSED] DP_QUERY_PAYLOAD with VCPI
[10:43:16] [PASSED] DP_REMOTE_DPCD_READ with port number
[10:43:16] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[10:43:16] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[10:43:16] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[10:43:16] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[10:43:16] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[10:43:16] [PASSED] DP_REMOTE_I2C_READ with port number
[10:43:16] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[10:43:16] [PASSED] DP_REMOTE_I2C_READ with transactions array
[10:43:16] [PASSED] DP_REMOTE_I2C_WRITE with port number
[10:43:16] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[10:43:16] [PASSED] DP_REMOTE_I2C_WRITE with data array
[10:43:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[10:43:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[10:43:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[10:43:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[10:43:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[10:43:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[10:43:16] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[10:43:16] ================ [PASSED] drm_dp_mst_helper ================
[10:43:16] ================== drm_exec (7 subtests) ===================
[10:43:16] [PASSED] sanitycheck
[10:43:16] [PASSED] test_lock
[10:43:16] [PASSED] test_lock_unlock
[10:43:16] [PASSED] test_duplicates
[10:43:16] [PASSED] test_prepare
[10:43:16] [PASSED] test_prepare_array
[10:43:16] [PASSED] test_multiple_loops
[10:43:16] ==================== [PASSED] drm_exec =====================
[10:43:16] =========== drm_format_helper_test (17 subtests) ===========
[10:43:16] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[10:43:16] [PASSED] single_pixel_source_buffer
[10:43:16] [PASSED] single_pixel_clip_rectangle
[10:43:16] [PASSED] well_known_colors
[10:43:16] [PASSED] destination_pitch
[10:43:16] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[10:43:16] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[10:43:16] [PASSED] single_pixel_source_buffer
[10:43:16] [PASSED] single_pixel_clip_rectangle
[10:43:16] [PASSED] well_known_colors
[10:43:16] [PASSED] destination_pitch
[10:43:16] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[10:43:16] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[10:43:16] [PASSED] single_pixel_source_buffer
[10:43:16] [PASSED] single_pixel_clip_rectangle
[10:43:16] [PASSED] well_known_colors
[10:43:16] [PASSED] destination_pitch
[10:43:16] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[10:43:16] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[10:43:16] [PASSED] single_pixel_source_buffer
[10:43:16] [PASSED] single_pixel_clip_rectangle
[10:43:16] [PASSED] well_known_colors
[10:43:16] [PASSED] destination_pitch
[10:43:16] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[10:43:16] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[10:43:16] [PASSED] single_pixel_source_buffer
[10:43:16] [PASSED] single_pixel_clip_rectangle
[10:43:16] [PASSED] well_known_colors
[10:43:16] [PASSED] destination_pitch
[10:43:16] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[10:43:16] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[10:43:16] [PASSED] single_pixel_source_buffer
[10:43:16] [PASSED] single_pixel_clip_rectangle
[10:43:16] [PASSED] well_known_colors
[10:43:16] [PASSED] destination_pitch
[10:43:16] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[10:43:16] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[10:43:16] [PASSED] single_pixel_source_buffer
[10:43:16] [PASSED] single_pixel_clip_rectangle
[10:43:16] [PASSED] well_known_colors
[10:43:16] [PASSED] destination_pitch
[10:43:16] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[10:43:16] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[10:43:16] [PASSED] single_pixel_source_buffer
[10:43:16] [PASSED] single_pixel_clip_rectangle
[10:43:16] [PASSED] well_known_colors
[10:43:16] [PASSED] destination_pitch
[10:43:16] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[10:43:16] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[10:43:16] [PASSED] single_pixel_source_buffer
[10:43:16] [PASSED] single_pixel_clip_rectangle
[10:43:16] [PASSED] well_known_colors
[10:43:16] [PASSED] destination_pitch
[10:43:16] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[10:43:16] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[10:43:16] [PASSED] single_pixel_source_buffer
[10:43:16] [PASSED] single_pixel_clip_rectangle
[10:43:16] [PASSED] well_known_colors
[10:43:16] [PASSED] destination_pitch
[10:43:16] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[10:43:16] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[10:43:16] [PASSED] single_pixel_source_buffer
[10:43:16] [PASSED] single_pixel_clip_rectangle
[10:43:16] [PASSED] well_known_colors
[10:43:16] [PASSED] destination_pitch
[10:43:16] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[10:43:16] ============== drm_test_fb_xrgb8888_to_mono  ===============
[10:43:16] [PASSED] single_pixel_source_buffer
[10:43:16] [PASSED] single_pixel_clip_rectangle
[10:43:16] [PASSED] well_known_colors
[10:43:16] [PASSED] destination_pitch
[10:43:16] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[10:43:16] ==================== drm_test_fb_swab  =====================
[10:43:16] [PASSED] single_pixel_source_buffer
[10:43:16] [PASSED] single_pixel_clip_rectangle
[10:43:16] [PASSED] well_known_colors
[10:43:16] [PASSED] destination_pitch
[10:43:16] ================ [PASSED] drm_test_fb_swab =================
[10:43:16] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[10:43:16] [PASSED] single_pixel_source_buffer
[10:43:16] [PASSED] single_pixel_clip_rectangle
[10:43:16] [PASSED] well_known_colors
[10:43:16] [PASSED] destination_pitch
[10:43:16] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[10:43:16] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[10:43:16] [PASSED] single_pixel_source_buffer
[10:43:16] [PASSED] single_pixel_clip_rectangle
[10:43:16] [PASSED] well_known_colors
[10:43:16] [PASSED] destination_pitch
[10:43:16] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[10:43:16] ================= drm_test_fb_clip_offset  =================
[10:43:16] [PASSED] pass through
[10:43:16] [PASSED] horizontal offset
[10:43:16] [PASSED] vertical offset
[10:43:16] [PASSED] horizontal and vertical offset
[10:43:16] [PASSED] horizontal offset (custom pitch)
[10:43:16] [PASSED] vertical offset (custom pitch)
[10:43:16] [PASSED] horizontal and vertical offset (custom pitch)
[10:43:16] ============= [PASSED] drm_test_fb_clip_offset =============
[10:43:16] =================== drm_test_fb_memcpy  ====================
[10:43:16] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[10:43:16] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[10:43:16] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[10:43:16] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[10:43:16] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[10:43:16] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[10:43:16] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[10:43:16] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[10:43:16] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[10:43:16] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[10:43:16] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[10:43:16] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[10:43:16] =============== [PASSED] drm_test_fb_memcpy ================
[10:43:16] ============= [PASSED] drm_format_helper_test ==============
[10:43:16] ================= drm_format (18 subtests) =================
[10:43:16] [PASSED] drm_test_format_block_width_invalid
[10:43:16] [PASSED] drm_test_format_block_width_one_plane
[10:43:16] [PASSED] drm_test_format_block_width_two_plane
[10:43:16] [PASSED] drm_test_format_block_width_three_plane
[10:43:16] [PASSED] drm_test_format_block_width_tiled
[10:43:16] [PASSED] drm_test_format_block_height_invalid
[10:43:16] [PASSED] drm_test_format_block_height_one_plane
[10:43:16] [PASSED] drm_test_format_block_height_two_plane
[10:43:16] [PASSED] drm_test_format_block_height_three_plane
[10:43:16] [PASSED] drm_test_format_block_height_tiled
[10:43:16] [PASSED] drm_test_format_min_pitch_invalid
[10:43:16] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[10:43:16] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[10:43:16] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[10:43:16] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[10:43:16] [PASSED] drm_test_format_min_pitch_two_plane
[10:43:16] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[10:43:16] [PASSED] drm_test_format_min_pitch_tiled
[10:43:16] =================== [PASSED] drm_format ====================
[10:43:16] ============== drm_framebuffer (10 subtests) ===============
[10:43:16] ========== drm_test_framebuffer_check_src_coords  ==========
[10:43:16] [PASSED] Success: source fits into fb
[10:43:16] [PASSED] Fail: overflowing fb with x-axis coordinate
[10:43:16] [PASSED] Fail: overflowing fb with y-axis coordinate
[10:43:16] [PASSED] Fail: overflowing fb with source width
[10:43:16] [PASSED] Fail: overflowing fb with source height
[10:43:16] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[10:43:16] [PASSED] drm_test_framebuffer_cleanup
[10:43:16] =============== drm_test_framebuffer_create  ===============
[10:43:16] [PASSED] ABGR8888 normal sizes
[10:43:16] [PASSED] ABGR8888 max sizes
[10:43:16] [PASSED] ABGR8888 pitch greater than min required
[10:43:16] [PASSED] ABGR8888 pitch less than min required
[10:43:16] [PASSED] ABGR8888 Invalid width
[10:43:16] [PASSED] ABGR8888 Invalid buffer handle
[10:43:16] [PASSED] No pixel format
[10:43:16] [PASSED] ABGR8888 Width 0
[10:43:16] [PASSED] ABGR8888 Height 0
[10:43:16] [PASSED] ABGR8888 Out of bound height * pitch combination
[10:43:16] [PASSED] ABGR8888 Large buffer offset
[10:43:16] [PASSED] ABGR8888 Buffer offset for inexistent plane
[10:43:16] [PASSED] ABGR8888 Invalid flag
[10:43:16] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[10:43:16] [PASSED] ABGR8888 Valid buffer modifier
[10:43:16] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[10:43:16] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[10:43:16] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[10:43:16] [PASSED] NV12 Normal sizes
[10:43:16] [PASSED] NV12 Max sizes
[10:43:16] [PASSED] NV12 Invalid pitch
[10:43:16] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[10:43:16] [PASSED] NV12 different  modifier per-plane
[10:43:16] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[10:43:16] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[10:43:16] [PASSED] NV12 Modifier for inexistent plane
[10:43:16] [PASSED] NV12 Handle for inexistent plane
[10:43:16] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[10:43:16] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[10:43:16] [PASSED] YVU420 Normal sizes
[10:43:16] [PASSED] YVU420 Max sizes
[10:43:16] [PASSED] YVU420 Invalid pitch
[10:43:16] [PASSED] YVU420 Different pitches
[10:43:16] [PASSED] YVU420 Different buffer offsets/pitches
[10:43:16] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[10:43:16] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[10:43:16] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[10:43:16] [PASSED] YVU420 Valid modifier
[10:43:16] [PASSED] YVU420 Different modifiers per plane
[10:43:16] [PASSED] YVU420 Modifier for inexistent plane
[10:43:16] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[10:43:16] [PASSED] X0L2 Normal sizes
[10:43:16] [PASSED] X0L2 Max sizes
[10:43:16] [PASSED] X0L2 Invalid pitch
[10:43:16] [PASSED] X0L2 Pitch greater than minimum required
[10:43:16] [PASSED] X0L2 Handle for inexistent plane
[10:43:16] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[10:43:16] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[10:43:16] [PASSED] X0L2 Valid modifier
[10:43:16] [PASSED] X0L2 Modifier for inexistent plane
[10:43:16] =========== [PASSED] drm_test_framebuffer_create ===========
[10:43:16] [PASSED] drm_test_framebuffer_free
[10:43:16] [PASSED] drm_test_framebuffer_init
[10:43:16] [PASSED] drm_test_framebuffer_init_bad_format
[10:43:16] [PASSED] drm_test_framebuffer_init_dev_mismatch
[10:43:16] [PASSED] drm_test_framebuffer_lookup
[10:43:16] [PASSED] drm_test_framebuffer_lookup_inexistent
[10:43:16] [PASSED] drm_test_framebuffer_modifiers_not_supported
[10:43:16] ================= [PASSED] drm_framebuffer =================
[10:43:16] ================ drm_gem_shmem (8 subtests) ================
[10:43:16] [PASSED] drm_gem_shmem_test_obj_create
[10:43:16] [PASSED] drm_gem_shmem_test_obj_create_private
[10:43:16] [PASSED] drm_gem_shmem_test_pin_pages
[10:43:16] [PASSED] drm_gem_shmem_test_vmap
[10:43:16] [PASSED] drm_gem_shmem_test_get_pages_sgt
[10:43:16] [PASSED] drm_gem_shmem_test_get_sg_table
[10:43:16] [PASSED] drm_gem_shmem_test_madvise
[10:43:16] [PASSED] drm_gem_shmem_test_purge
[10:43:16] ================== [PASSED] drm_gem_shmem ==================
[10:43:16] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[10:43:16] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[10:43:16] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[10:43:16] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[10:43:16] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[10:43:16] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[10:43:16] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[10:43:16] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[10:43:16] [PASSED] Automatic
[10:43:16] [PASSED] Full
[10:43:16] [PASSED] Limited 16:235
[10:43:16] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[10:43:16] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[10:43:16] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[10:43:16] [PASSED] drm_test_check_disable_connector
[10:43:16] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[10:43:16] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[10:43:16] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[10:43:16] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[10:43:16] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[10:43:16] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[10:43:16] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[10:43:16] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[10:43:16] [PASSED] drm_test_check_output_bpc_dvi
[10:43:16] [PASSED] drm_test_check_output_bpc_format_vic_1
[10:43:16] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[10:43:16] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[10:43:16] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[10:43:16] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[10:43:16] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[10:43:16] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[10:43:16] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[10:43:16] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[10:43:16] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[10:43:16] [PASSED] drm_test_check_broadcast_rgb_value
[10:43:16] [PASSED] drm_test_check_bpc_8_value
[10:43:16] [PASSED] drm_test_check_bpc_10_value
[10:43:16] [PASSED] drm_test_check_bpc_12_value
[10:43:16] [PASSED] drm_test_check_format_value
[10:43:16] [PASSED] drm_test_check_tmds_char_value
[10:43:16] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[10:43:16] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[10:43:16] [PASSED] drm_test_check_mode_valid
[10:43:16] [PASSED] drm_test_check_mode_valid_reject
[10:43:16] [PASSED] drm_test_check_mode_valid_reject_rate
[10:43:16] [PASSED] drm_test_check_mode_valid_reject_max_clock
[10:43:16] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[10:43:16] ================= drm_managed (2 subtests) =================
[10:43:16] [PASSED] drm_test_managed_release_action
[10:43:16] [PASSED] drm_test_managed_run_action
[10:43:16] =================== [PASSED] drm_managed ===================
[10:43:16] =================== drm_mm (6 subtests) ====================
[10:43:16] [PASSED] drm_test_mm_init
[10:43:16] [PASSED] drm_test_mm_debug
[10:43:16] [PASSED] drm_test_mm_align32
[10:43:16] [PASSED] drm_test_mm_align64
[10:43:16] [PASSED] drm_test_mm_lowest
[10:43:16] [PASSED] drm_test_mm_highest
[10:43:16] ===================== [PASSED] drm_mm ======================
[10:43:16] ============= drm_modes_analog_tv (5 subtests) =============
[10:43:16] [PASSED] drm_test_modes_analog_tv_mono_576i
[10:43:16] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[10:43:16] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[10:43:16] [PASSED] drm_test_modes_analog_tv_pal_576i
[10:43:16] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[10:43:16] =============== [PASSED] drm_modes_analog_tv ===============
[10:43:16] ============== drm_plane_helper (2 subtests) ===============
[10:43:16] =============== drm_test_check_plane_state  ================
[10:43:16] [PASSED] clipping_simple
[10:43:16] [PASSED] clipping_rotate_reflect
[10:43:16] [PASSED] positioning_simple
[10:43:16] [PASSED] upscaling
[10:43:16] [PASSED] downscaling
[10:43:16] [PASSED] rounding1
[10:43:16] [PASSED] rounding2
[10:43:16] [PASSED] rounding3
[10:43:16] [PASSED] rounding4
[10:43:16] =========== [PASSED] drm_test_check_plane_state ============
[10:43:16] =========== drm_test_check_invalid_plane_state  ============
[10:43:16] [PASSED] positioning_invalid
[10:43:16] [PASSED] upscaling_invalid
[10:43:16] [PASSED] downscaling_invalid
[10:43:16] ======= [PASSED] drm_test_check_invalid_plane_state ========
[10:43:16] ================ [PASSED] drm_plane_helper =================
[10:43:16] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[10:43:16] ====== drm_test_connector_helper_tv_get_modes_check  =======
[10:43:16] [PASSED] None
[10:43:16] [PASSED] PAL
[10:43:16] [PASSED] NTSC
[10:43:16] [PASSED] Both, NTSC Default
[10:43:16] [PASSED] Both, PAL Default
[10:43:16] [PASSED] Both, NTSC Default, with PAL on command-line
[10:43:16] [PASSED] Both, PAL Default, with NTSC on command-line
[10:43:16] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[10:43:16] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[10:43:16] ================== drm_rect (9 subtests) ===================
[10:43:16] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[10:43:16] [PASSED] drm_test_rect_clip_scaled_not_clipped
[10:43:16] [PASSED] drm_test_rect_clip_scaled_clipped
[10:43:16] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[10:43:16] ================= drm_test_rect_intersect  =================
[10:43:16] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[10:43:16] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[10:43:16] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[10:43:16] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[10:43:16] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[10:43:16] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[10:43:16] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[10:43:16] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[10:43:16] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[10:43:16] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[10:43:16] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[10:43:16] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[10:43:16] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[10:43:16] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[10:43:16] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[10:43:16] ============= [PASSED] drm_test_rect_intersect =============
[10:43:16] ================ drm_test_rect_calc_hscale  ================
[10:43:16] [PASSED] normal use
[10:43:16] [PASSED] out of max range
[10:43:16] [PASSED] out of min range
[10:43:16] [PASSED] zero dst
[10:43:16] [PASSED] negative src
[10:43:16] [PASSED] negative dst
[10:43:16] ============ [PASSED] drm_test_rect_calc_hscale ============
[10:43:16] ================ drm_test_rect_calc_vscale  ================
[10:43:16] [PASSED] normal use
[10:43:16] [PASSED] out of max range
[10:43:16] [PASSED] out of min range
[10:43:16] [PASSED] zero dst
[10:43:16] [PASSED] negative src
[10:43:16] [PASSED] negative dst
[10:43:16] ============ [PASSED] drm_test_rect_calc_vscale ============
[10:43:16] ================== drm_test_rect_rotate  ===================
[10:43:16] [PASSED] reflect-x
[10:43:16] [PASSED] reflect-y
[10:43:16] [PASSED] rotate-0
[10:43:16] [PASSED] rotate-90
[10:43:16] [PASSED] rotate-180
[10:43:16] [PASSED] rotate-270
stty: 'standard input': Inappropriate ioctl for device
[10:43:16] ============== [PASSED] drm_test_rect_rotate ===============
[10:43:16] ================ drm_test_rect_rotate_inv  =================
[10:43:16] [PASSED] reflect-x
[10:43:16] [PASSED] reflect-y
[10:43:16] [PASSED] rotate-0
[10:43:16] [PASSED] rotate-90
[10:43:16] [PASSED] rotate-180
[10:43:16] [PASSED] rotate-270
[10:43:16] ============ [PASSED] drm_test_rect_rotate_inv =============
[10:43:16] ==================== [PASSED] drm_rect =====================
[10:43:16] ============ drm_sysfb_modeset_test (1 subtest) ============
[10:43:16] ============ drm_test_sysfb_build_fourcc_list  =============
[10:43:16] [PASSED] no native formats
[10:43:16] [PASSED] XRGB8888 as native format
[10:43:16] [PASSED] remove duplicates
[10:43:16] [PASSED] convert alpha formats
[10:43:16] [PASSED] random formats
[10:43:16] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[10:43:16] ============= [PASSED] drm_sysfb_modeset_test ==============
[10:43:16] ============================================================
[10:43:16] Testing complete. Ran 616 tests: passed: 616
[10:43:16] Elapsed time: 23.529s total, 1.681s configuring, 21.678s building, 0.147s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[10:43:16] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:43:18] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[10:43:26] Starting KUnit Kernel (1/1)...
[10:43:26] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:43:26] ================= ttm_device (5 subtests) ==================
[10:43:26] [PASSED] ttm_device_init_basic
[10:43:26] [PASSED] ttm_device_init_multiple
[10:43:26] [PASSED] ttm_device_fini_basic
[10:43:26] [PASSED] ttm_device_init_no_vma_man
[10:43:26] ================== ttm_device_init_pools  ==================
[10:43:26] [PASSED] No DMA allocations, no DMA32 required
[10:43:26] [PASSED] DMA allocations, DMA32 required
[10:43:26] [PASSED] No DMA allocations, DMA32 required
[10:43:26] [PASSED] DMA allocations, no DMA32 required
[10:43:26] ============== [PASSED] ttm_device_init_pools ==============
[10:43:26] =================== [PASSED] ttm_device ====================
[10:43:26] ================== ttm_pool (8 subtests) ===================
[10:43:26] ================== ttm_pool_alloc_basic  ===================
[10:43:26] [PASSED] One page
[10:43:26] [PASSED] More than one page
[10:43:26] [PASSED] Above the allocation limit
[10:43:26] [PASSED] One page, with coherent DMA mappings enabled
[10:43:26] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[10:43:26] ============== [PASSED] ttm_pool_alloc_basic ===============
[10:43:26] ============== ttm_pool_alloc_basic_dma_addr  ==============
[10:43:26] [PASSED] One page
[10:43:26] [PASSED] More than one page
[10:43:26] [PASSED] Above the allocation limit
[10:43:26] [PASSED] One page, with coherent DMA mappings enabled
[10:43:26] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[10:43:26] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[10:43:26] [PASSED] ttm_pool_alloc_order_caching_match
[10:43:26] [PASSED] ttm_pool_alloc_caching_mismatch
[10:43:26] [PASSED] ttm_pool_alloc_order_mismatch
[10:43:26] [PASSED] ttm_pool_free_dma_alloc
[10:43:26] [PASSED] ttm_pool_free_no_dma_alloc
[10:43:26] [PASSED] ttm_pool_fini_basic
[10:43:26] ==================== [PASSED] ttm_pool =====================
[10:43:26] ================ ttm_resource (8 subtests) =================
[10:43:26] ================= ttm_resource_init_basic  =================
[10:43:26] [PASSED] Init resource in TTM_PL_SYSTEM
[10:43:26] [PASSED] Init resource in TTM_PL_VRAM
[10:43:26] [PASSED] Init resource in a private placement
[10:43:26] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[10:43:26] ============= [PASSED] ttm_resource_init_basic =============
[10:43:26] [PASSED] ttm_resource_init_pinned
[10:43:26] [PASSED] ttm_resource_fini_basic
[10:43:26] [PASSED] ttm_resource_manager_init_basic
[10:43:26] [PASSED] ttm_resource_manager_usage_basic
[10:43:26] [PASSED] ttm_resource_manager_set_used_basic
[10:43:26] [PASSED] ttm_sys_man_alloc_basic
[10:43:26] [PASSED] ttm_sys_man_free_basic
[10:43:26] ================== [PASSED] ttm_resource ===================
[10:43:26] =================== ttm_tt (15 subtests) ===================
[10:43:26] ==================== ttm_tt_init_basic  ====================
[10:43:26] [PASSED] Page-aligned size
[10:43:26] [PASSED] Extra pages requested
[10:43:26] ================ [PASSED] ttm_tt_init_basic ================
[10:43:26] [PASSED] ttm_tt_init_misaligned
[10:43:26] [PASSED] ttm_tt_fini_basic
[10:43:26] [PASSED] ttm_tt_fini_sg
[10:43:26] [PASSED] ttm_tt_fini_shmem
[10:43:26] [PASSED] ttm_tt_create_basic
[10:43:26] [PASSED] ttm_tt_create_invalid_bo_type
[10:43:26] [PASSED] ttm_tt_create_ttm_exists
[10:43:26] [PASSED] ttm_tt_create_failed
[10:43:26] [PASSED] ttm_tt_destroy_basic
[10:43:26] [PASSED] ttm_tt_populate_null_ttm
[10:43:26] [PASSED] ttm_tt_populate_populated_ttm
[10:43:26] [PASSED] ttm_tt_unpopulate_basic
[10:43:26] [PASSED] ttm_tt_unpopulate_empty_ttm
[10:43:26] [PASSED] ttm_tt_swapin_basic
[10:43:26] ===================== [PASSED] ttm_tt ======================
[10:43:26] =================== ttm_bo (14 subtests) ===================
[10:43:26] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[10:43:26] [PASSED] Cannot be interrupted and sleeps
[10:43:26] [PASSED] Cannot be interrupted, locks straight away
[10:43:26] [PASSED] Can be interrupted, sleeps
[10:43:26] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[10:43:26] [PASSED] ttm_bo_reserve_locked_no_sleep
[10:43:26] [PASSED] ttm_bo_reserve_no_wait_ticket
[10:43:26] [PASSED] ttm_bo_reserve_double_resv
[10:43:26] [PASSED] ttm_bo_reserve_interrupted
[10:43:26] [PASSED] ttm_bo_reserve_deadlock
[10:43:26] [PASSED] ttm_bo_unreserve_basic
[10:43:26] [PASSED] ttm_bo_unreserve_pinned
[10:43:26] [PASSED] ttm_bo_unreserve_bulk
[10:43:26] [PASSED] ttm_bo_put_basic
[10:43:26] [PASSED] ttm_bo_put_shared_resv
[10:43:26] [PASSED] ttm_bo_pin_basic
[10:43:26] [PASSED] ttm_bo_pin_unpin_resource
[10:43:26] [PASSED] ttm_bo_multiple_pin_one_unpin
[10:43:26] ===================== [PASSED] ttm_bo ======================
[10:43:26] ============== ttm_bo_validate (22 subtests) ===============
[10:43:26] ============== ttm_bo_init_reserved_sys_man  ===============
[10:43:26] [PASSED] Buffer object for userspace
[10:43:26] [PASSED] Kernel buffer object
[10:43:26] [PASSED] Shared buffer object
[10:43:26] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[10:43:26] ============== ttm_bo_init_reserved_mock_man  ==============
[10:43:26] [PASSED] Buffer object for userspace
[10:43:26] [PASSED] Kernel buffer object
[10:43:26] [PASSED] Shared buffer object
[10:43:26] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[10:43:26] [PASSED] ttm_bo_init_reserved_resv
[10:43:26] ================== ttm_bo_validate_basic  ==================
[10:43:26] [PASSED] Buffer object for userspace
[10:43:26] [PASSED] Kernel buffer object
[10:43:26] [PASSED] Shared buffer object
[10:43:26] ============== [PASSED] ttm_bo_validate_basic ==============
[10:43:26] [PASSED] ttm_bo_validate_invalid_placement
[10:43:26] ============= ttm_bo_validate_same_placement  ==============
[10:43:26] [PASSED] System manager
[10:43:26] [PASSED] VRAM manager
[10:43:26] ========= [PASSED] ttm_bo_validate_same_placement ==========
[10:43:26] [PASSED] ttm_bo_validate_failed_alloc
[10:43:26] [PASSED] ttm_bo_validate_pinned
[10:43:26] [PASSED] ttm_bo_validate_busy_placement
[10:43:26] ================ ttm_bo_validate_multihop  =================
[10:43:26] [PASSED] Buffer object for userspace
[10:43:26] [PASSED] Kernel buffer object
[10:43:26] [PASSED] Shared buffer object
[10:43:26] ============ [PASSED] ttm_bo_validate_multihop =============
[10:43:26] ========== ttm_bo_validate_no_placement_signaled  ==========
[10:43:26] [PASSED] Buffer object in system domain, no page vector
[10:43:26] [PASSED] Buffer object in system domain with an existing page vector
[10:43:26] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[10:43:26] ======== ttm_bo_validate_no_placement_not_signaled  ========
[10:43:26] [PASSED] Buffer object for userspace
[10:43:26] [PASSED] Kernel buffer object
[10:43:26] [PASSED] Shared buffer object
[10:43:26] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[10:43:26] [PASSED] ttm_bo_validate_move_fence_signaled
[10:43:26] ========= ttm_bo_validate_move_fence_not_signaled  =========
[10:43:26] [PASSED] Waits for GPU
[10:43:26] [PASSED] Tries to lock straight away
[10:43:26] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[10:43:26] [PASSED] ttm_bo_validate_swapout
[10:43:26] [PASSED] ttm_bo_validate_happy_evict
[10:43:26] [PASSED] ttm_bo_validate_all_pinned_evict
[10:43:26] [PASSED] ttm_bo_validate_allowed_only_evict
[10:43:26] [PASSED] ttm_bo_validate_deleted_evict
[10:43:26] [PASSED] ttm_bo_validate_busy_domain_evict
[10:43:26] [PASSED] ttm_bo_validate_evict_gutting
[10:43:26] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[10:43:26] ================= [PASSED] ttm_bo_validate =================
[10:43:26] ============================================================
[10:43:26] Testing complete. Ran 102 tests: passed: 102
[10:43:26] Elapsed time: 9.976s total, 1.665s configuring, 7.693s building, 0.531s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for drm/i915/display: make all global state opaque (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 960 bytes --]

== Series Details ==

Series: drm/i915/display: make all global state opaque (rev2)
URL   : https://patchwork.freedesktop.org/series/150157/
State : success

== Summary ==

CI Bug Log - changes from xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19_BAT -> xe-pw-150157v2_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (9 -> 8)
------------------------------

  Missing    (1): bat-adlp-vm 


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19 -> xe-pw-150157v2

  IGT_8424: 68588b3c89a1bbe08c54d21c4d3d2e509957c795 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19: bd57aee20daefb7b0dfe9017663668c92115ff19
  xe-pw-150157v2: 150157v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/index.html

[-- Attachment #2: Type: text/html, Size: 1508 bytes --]

✓ Xe.CI.Full: success for drm/i915/display: make all global state opaque (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 66035 bytes --]

== Series Details ==

Series: drm/i915/display: make all global state opaque (rev2)
URL   : https://patchwork.freedesktop.org/series/150157/
State : success

== Summary ==

CI Bug Log - changes from xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19_FULL -> xe-pw-150157v2_FULL
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

New tests
---------

  New tests have been introduced between xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19_FULL and xe-pw-150157v2_FULL:

### New IGT tests (3) ###

  * igt@kms_pipe_crc_basic@disable-crc-after-crtc@pipe-b-dp-2:
    - Statuses : 1 pass(s)
    - Exec time: [0.51] s

  * igt@kms_pipe_crc_basic@disable-crc-after-crtc@pipe-d-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [0.46] s

  * igt@kms_properties@plane-properties-legacy@pipe-d-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [0.44] s

  

Known issues
------------

  Here are the changes found in xe-pw-150157v2_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@fbdev@read:
    - shard-dg2-set2:     [PASS][1] -> [SKIP][2] ([Intel XE#2134])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-436/igt@fbdev@read.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-464/igt@fbdev@read.html

  * igt@kms_async_flips@async-flip-with-page-flip-events-tiled-atomic@pipe-a-hdmi-a-6-4-rc-ccs-cc:
    - shard-dg2-set2:     NOTRUN -> [SKIP][3] ([Intel XE#3767]) +15 other tests skip
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-434/igt@kms_async_flips@async-flip-with-page-flip-events-tiled-atomic@pipe-a-hdmi-a-6-4-rc-ccs-cc.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-270:
    - shard-bmg:          NOTRUN -> [SKIP][4] ([Intel XE#2327]) +1 other test skip
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-3/igt@kms_big_fb@4-tiled-64bpp-rotate-270.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180:
    - shard-dg2-set2:     [PASS][5] -> [SKIP][6] ([Intel XE#2351] / [Intel XE#4208]) +1 other test skip
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-436/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-464/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180.html

  * igt@kms_big_fb@y-tiled-16bpp-rotate-0:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#1124]) +5 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-3/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html

  * igt@kms_big_fb@y-tiled-16bpp-rotate-180:
    - shard-adlp:         [PASS][8] -> [DMESG-WARN][9] ([Intel XE#2953] / [Intel XE#4173]) +6 other tests dmesg-warn
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-adlp-1/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-adlp-8/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html

  * igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
    - shard-dg2-set2:     NOTRUN -> [SKIP][10] ([Intel XE#607])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-434/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0:
    - shard-dg2-set2:     NOTRUN -> [SKIP][11] ([Intel XE#1124]) +2 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-435/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
    - shard-adlp:         [PASS][12] -> [DMESG-FAIL][13] ([Intel XE#4543]) +1 other test dmesg-fail
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-adlp-1/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-adlp-1/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html

  * igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p:
    - shard-bmg:          [PASS][14] -> [SKIP][15] ([Intel XE#2314] / [Intel XE#2894])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-bmg-7/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-6/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html

  * igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p:
    - shard-bmg:          NOTRUN -> [SKIP][16] ([Intel XE#2314] / [Intel XE#2894])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-7/igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p.html

  * igt@kms_bw@linear-tiling-1-displays-2160x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#367])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-4/igt@kms_bw@linear-tiling-1-displays-2160x1440p.html

  * igt@kms_bw@linear-tiling-4-displays-2160x1440p:
    - shard-dg2-set2:     NOTRUN -> [SKIP][18] ([Intel XE#367])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-434/igt@kms_bw@linear-tiling-4-displays-2160x1440p.html

  * igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [SKIP][19] ([Intel XE#787]) +181 other tests skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-434/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-6.html

  * igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc:
    - shard-bmg:          NOTRUN -> [SKIP][20] ([Intel XE#2887]) +7 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-4/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][21] ([Intel XE#2907])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-435/igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc:
    - shard-bmg:          NOTRUN -> [SKIP][22] ([Intel XE#3432]) +1 other test skip
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-7/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-b-dp-2:
    - shard-dg2-set2:     NOTRUN -> [INCOMPLETE][23] ([Intel XE#1727] / [Intel XE#3113])
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-b-dp-2.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-hdmi-a-6:
    - shard-dg2-set2:     [PASS][24] -> [DMESG-WARN][25] ([Intel XE#1727] / [Intel XE#3113])
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-hdmi-a-6.html
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-hdmi-a-6.html

  * igt@kms_ccs@random-ccs-data-y-tiled-ccs@pipe-d-dp-2:
    - shard-dg2-set2:     NOTRUN -> [SKIP][26] ([Intel XE#455] / [Intel XE#787]) +27 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-432/igt@kms_ccs@random-ccs-data-y-tiled-ccs@pipe-d-dp-2.html

  * igt@kms_cdclk@plane-scaling@pipe-b-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][27] ([Intel XE#4416]) +3 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-436/igt@kms_cdclk@plane-scaling@pipe-b-dp-4.html

  * igt@kms_chamelium_color@ctm-0-75:
    - shard-dg2-set2:     NOTRUN -> [SKIP][28] ([Intel XE#306])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-435/igt@kms_chamelium_color@ctm-0-75.html

  * igt@kms_chamelium_color@ctm-max:
    - shard-bmg:          NOTRUN -> [SKIP][29] ([Intel XE#2325])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-7/igt@kms_chamelium_color@ctm-max.html

  * igt@kms_chamelium_edid@vga-edid-read:
    - shard-dg2-set2:     NOTRUN -> [SKIP][30] ([Intel XE#373]) +1 other test skip
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-434/igt@kms_chamelium_edid@vga-edid-read.html

  * igt@kms_chamelium_frames@hdmi-aspect-ratio:
    - shard-bmg:          NOTRUN -> [SKIP][31] ([Intel XE#2252]) +5 other tests skip
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-4/igt@kms_chamelium_frames@hdmi-aspect-ratio.html

  * igt@kms_content_protection@atomic@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][32] ([Intel XE#1178]) +1 other test fail
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-1/igt@kms_content_protection@atomic@pipe-a-dp-2.html

  * igt@kms_content_protection@lic-type-0:
    - shard-dg2-set2:     NOTRUN -> [FAIL][33] ([Intel XE#1178]) +1 other test fail
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-436/igt@kms_content_protection@lic-type-0.html

  * igt@kms_content_protection@lic-type-0@pipe-a-dp-4:
    - shard-dg2-set2:     NOTRUN -> [FAIL][34] ([Intel XE#3304])
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-436/igt@kms_content_protection@lic-type-0@pipe-a-dp-4.html

  * igt@kms_content_protection@uevent@pipe-a-dp-2:
    - shard-dg2-set2:     NOTRUN -> [FAIL][35] ([Intel XE#1188])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-432/igt@kms_content_protection@uevent@pipe-a-dp-2.html

  * igt@kms_cursor_crc@cursor-offscreen-256x85:
    - shard-bmg:          NOTRUN -> [SKIP][36] ([Intel XE#2320]) +3 other tests skip
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-4/igt@kms_cursor_crc@cursor-offscreen-256x85.html

  * igt@kms_cursor_crc@cursor-offscreen-512x512:
    - shard-dg2-set2:     NOTRUN -> [SKIP][37] ([Intel XE#4208] / [i915#2575]) +3 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-464/igt@kms_cursor_crc@cursor-offscreen-512x512.html

  * igt@kms_cursor_crc@cursor-rapid-movement-64x64:
    - shard-dg2-set2:     [PASS][38] -> [SKIP][39] ([Intel XE#4208] / [i915#2575]) +6 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-436/igt@kms_cursor_crc@cursor-rapid-movement-64x64.html
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-464/igt@kms_cursor_crc@cursor-rapid-movement-64x64.html

  * igt@kms_cursor_crc@cursor-sliding-512x170:
    - shard-bmg:          NOTRUN -> [SKIP][40] ([Intel XE#2321])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-7/igt@kms_cursor_crc@cursor-sliding-512x170.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
    - shard-bmg:          [PASS][41] -> [SKIP][42] ([Intel XE#2291]) +8 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-bmg-3/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-5/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic:
    - shard-bmg:          [PASS][43] -> [FAIL][44] ([Intel XE#4633])
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-bmg-2/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-3/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html

  * igt@kms_dp_link_training@uhbr-mst:
    - shard-bmg:          NOTRUN -> [SKIP][45] ([Intel XE#4354])
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-3/igt@kms_dp_link_training@uhbr-mst.html

  * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests:
    - shard-bmg:          NOTRUN -> [SKIP][46] ([Intel XE#4422])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-7/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests.html

  * igt@kms_fbcon_fbt@fbc:
    - shard-bmg:          NOTRUN -> [SKIP][47] ([Intel XE#4156])
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-3/igt@kms_fbcon_fbt@fbc.html

  * igt@kms_feature_discovery@psr2:
    - shard-bmg:          NOTRUN -> [SKIP][48] ([Intel XE#2374])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-4/igt@kms_feature_discovery@psr2.html

  * igt@kms_flip@2x-flip-vs-dpms-on-nop:
    - shard-bmg:          [PASS][49] -> [SKIP][50] ([Intel XE#2316]) +6 other tests skip
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-bmg-7/igt@kms_flip@2x-flip-vs-dpms-on-nop.html
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-6/igt@kms_flip@2x-flip-vs-dpms-on-nop.html

  * igt@kms_flip@flip-vs-expired-vblank@a-dp4:
    - shard-dg2-set2:     [PASS][51] -> [FAIL][52] ([Intel XE#301] / [Intel XE#3321]) +2 other tests fail
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-435/igt@kms_flip@flip-vs-expired-vblank@a-dp4.html
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-464/igt@kms_flip@flip-vs-expired-vblank@a-dp4.html

  * igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a6:
    - shard-dg2-set2:     [PASS][53] -> [FAIL][54] ([Intel XE#301]) +2 other tests fail
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-435/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a6.html
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-464/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a6.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling:
    - shard-bmg:          NOTRUN -> [SKIP][55] ([Intel XE#2293] / [Intel XE#2380])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-7/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
    - shard-bmg:          NOTRUN -> [SKIP][56] ([Intel XE#2293])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-7/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling:
    - shard-dg2-set2:     NOTRUN -> [SKIP][57] ([Intel XE#455]) +6 other tests skip
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-434/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-onoff:
    - shard-dg2-set2:     NOTRUN -> [SKIP][58] ([Intel XE#651]) +3 other tests skip
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-436/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][59] ([Intel XE#4141]) +8 other tests skip
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][60] ([Intel XE#2311]) +17 other tests skip
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][61] ([Intel XE#653]) +2 other tests skip
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-436/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary:
    - shard-bmg:          NOTRUN -> [SKIP][62] ([Intel XE#2313]) +18 other tests skip
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-bmg:          NOTRUN -> [SKIP][63] ([Intel XE#3374] / [Intel XE#3544])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-7/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_hdr@static-swap:
    - shard-bmg:          [PASS][64] -> [SKIP][65] ([Intel XE#1503])
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-bmg-7/igt@kms_hdr@static-swap.html
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-6/igt@kms_hdr@static-swap.html

  * igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][66] ([Intel XE#4090])
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-4/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html

  * igt@kms_pm_backlight@brightness-with-dpms:
    - shard-bmg:          NOTRUN -> [SKIP][67] ([Intel XE#2938])
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-7/igt@kms_pm_backlight@brightness-with-dpms.html

  * igt@kms_pm_dc@dc3co-vpb-simulation:
    - shard-bmg:          NOTRUN -> [SKIP][68] ([Intel XE#2391])
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-4/igt@kms_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_pm_dc@dc5-psr:
    - shard-dg2-set2:     NOTRUN -> [SKIP][69] ([Intel XE#1129])
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-436/igt@kms_pm_dc@dc5-psr.html

  * igt@kms_pm_dc@dc6-psr:
    - shard-bmg:          NOTRUN -> [SKIP][70] ([Intel XE#2392])
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-3/igt@kms_pm_dc@dc6-psr.html

  * igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-sf:
    - shard-bmg:          NOTRUN -> [SKIP][71] ([Intel XE#1489]) +3 other tests skip
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-7/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf:
    - shard-dg2-set2:     NOTRUN -> [SKIP][72] ([Intel XE#1489])
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-436/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr@fbc-psr2-sprite-plane-onoff:
    - shard-dg2-set2:     NOTRUN -> [SKIP][73] ([Intel XE#2850] / [Intel XE#929]) +2 other tests skip
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-436/igt@kms_psr@fbc-psr2-sprite-plane-onoff.html

  * igt@kms_psr@psr2-sprite-blt:
    - shard-bmg:          NOTRUN -> [SKIP][74] ([Intel XE#2234] / [Intel XE#2850]) +10 other tests skip
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-3/igt@kms_psr@psr2-sprite-blt.html

  * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
    - shard-bmg:          NOTRUN -> [SKIP][75] ([Intel XE#2414])
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-4/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-0:
    - shard-dg2-set2:     NOTRUN -> [SKIP][76] ([Intel XE#1127])
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-436/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html

  * igt@kms_tv_load_detect@load-detect:
    - shard-bmg:          NOTRUN -> [SKIP][77] ([Intel XE#2450])
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-3/igt@kms_tv_load_detect@load-detect.html

  * igt@kms_vrr@seamless-rr-switch-drrs:
    - shard-bmg:          NOTRUN -> [SKIP][78] ([Intel XE#1499])
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-4/igt@kms_vrr@seamless-rr-switch-drrs.html

  * igt@xe_copy_basic@mem-set-linear-0xfd:
    - shard-dg2-set2:     NOTRUN -> [SKIP][79] ([Intel XE#1126])
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-435/igt@xe_copy_basic@mem-set-linear-0xfd.html

  * igt@xe_eudebug@basic-exec-queues:
    - shard-bmg:          NOTRUN -> [SKIP][80] ([Intel XE#4837]) +6 other tests skip
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-3/igt@xe_eudebug@basic-exec-queues.html

  * igt@xe_eudebug@basic-vm-access-userptr-faultable:
    - shard-dg2-set2:     NOTRUN -> [SKIP][81] ([Intel XE#4837]) +3 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-436/igt@xe_eudebug@basic-vm-access-userptr-faultable.html

  * igt@xe_exec_basic@many-null-rebind:
    - shard-dg2-set2:     [PASS][82] -> [SKIP][83] ([Intel XE#4208]) +28 other tests skip
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-436/igt@xe_exec_basic@many-null-rebind.html
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-464/igt@xe_exec_basic@many-null-rebind.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-invalidate-race:
    - shard-bmg:          NOTRUN -> [SKIP][84] ([Intel XE#2322]) +3 other tests skip
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-7/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-invalidate-race.html

  * igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-rebind:
    - shard-dg2-set2:     [PASS][85] -> [SKIP][86] ([Intel XE#1392]) +10 other tests skip
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-435/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-rebind.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-432/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-rebind.html

  * igt@xe_exec_fault_mode@many-execqueues-userptr-invalidate-prefetch:
    - shard-dg2-set2:     NOTRUN -> [SKIP][87] ([Intel XE#288]) +6 other tests skip
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-434/igt@xe_exec_fault_mode@many-execqueues-userptr-invalidate-prefetch.html

  * igt@xe_exec_reset@parallel-gt-reset:
    - shard-dg2-set2:     [PASS][88] -> [DMESG-WARN][89] ([Intel XE#3876])
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-436/igt@xe_exec_reset@parallel-gt-reset.html
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-433/igt@xe_exec_reset@parallel-gt-reset.html

  * igt@xe_exec_system_allocator@many-new-race:
    - shard-dg2-set2:     NOTRUN -> [SKIP][90] ([Intel XE#4208]) +23 other tests skip
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-464/igt@xe_exec_system_allocator@many-new-race.html

  * igt@xe_exec_system_allocator@threads-many-malloc-mlock-nomemset:
    - shard-dg2-set2:     NOTRUN -> [SKIP][91] ([Intel XE#4915]) +65 other tests skip
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-436/igt@xe_exec_system_allocator@threads-many-malloc-mlock-nomemset.html

  * igt@xe_exec_system_allocator@threads-many-mmap-new-huge-nomemset:
    - shard-bmg:          NOTRUN -> [SKIP][92] ([Intel XE#4943]) +17 other tests skip
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-4/igt@xe_exec_system_allocator@threads-many-mmap-new-huge-nomemset.html

  * igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv:
    - shard-dg2-set2:     NOTRUN -> [ABORT][93] ([Intel XE#4917])
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-435/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html

  * igt@xe_live_ktest@xe_bo@xe_ccs_migrate_kunit:
    - shard-bmg:          NOTRUN -> [SKIP][94] ([Intel XE#2229])
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-4/igt@xe_live_ktest@xe_bo@xe_ccs_migrate_kunit.html

  * igt@xe_oa@oa-unit-exclusive-stream-sample-oa:
    - shard-dg2-set2:     NOTRUN -> [SKIP][95] ([Intel XE#2541] / [Intel XE#3573]) +1 other test skip
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-435/igt@xe_oa@oa-unit-exclusive-stream-sample-oa.html

  * igt@xe_pat@pat-index-xelpg:
    - shard-bmg:          NOTRUN -> [SKIP][96] ([Intel XE#2236])
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-7/igt@xe_pat@pat-index-xelpg.html

  * igt@xe_peer2peer@read@read-gpua-vram01-gpub-system-p2p:
    - shard-dg2-set2:     NOTRUN -> [FAIL][97] ([Intel XE#1173])
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-435/igt@xe_peer2peer@read@read-gpua-vram01-gpub-system-p2p.html

  * igt@xe_pm@d3cold-mmap-vram:
    - shard-bmg:          NOTRUN -> [SKIP][98] ([Intel XE#2284])
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-4/igt@xe_pm@d3cold-mmap-vram.html

  * igt@xe_pm@d3cold-mocs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][99] ([Intel XE#2284])
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-434/igt@xe_pm@d3cold-mocs.html

  * igt@xe_pxp@display-black-pxp-fb:
    - shard-dg2-set2:     NOTRUN -> [SKIP][100] ([Intel XE#4733])
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-436/igt@xe_pxp@display-black-pxp-fb.html

  * igt@xe_pxp@pxp-stale-bo-exec-post-rpm:
    - shard-bmg:          NOTRUN -> [SKIP][101] ([Intel XE#4733])
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-7/igt@xe_pxp@pxp-stale-bo-exec-post-rpm.html

  * igt@xe_query@multigpu-query-invalid-cs-cycles:
    - shard-dg2-set2:     NOTRUN -> [SKIP][102] ([Intel XE#944]) +1 other test skip
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-435/igt@xe_query@multigpu-query-invalid-cs-cycles.html

  * igt@xe_query@multigpu-query-invalid-size:
    - shard-bmg:          NOTRUN -> [SKIP][103] ([Intel XE#944]) +1 other test skip
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-7/igt@xe_query@multigpu-query-invalid-size.html

  * igt@xe_sriov_auto_provisioning@resources-released-on-vfs-disabling:
    - shard-bmg:          NOTRUN -> [SKIP][104] ([Intel XE#4130]) +1 other test skip
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-3/igt@xe_sriov_auto_provisioning@resources-released-on-vfs-disabling.html

  * igt@xe_sriov_auto_provisioning@selfconfig-reprovision-reduce-numvfs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][105] ([Intel XE#4130])
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-435/igt@xe_sriov_auto_provisioning@selfconfig-reprovision-reduce-numvfs.html

  
#### Possible fixes ####

  * igt@kms_async_flips@async-flip-suspend-resume:
    - shard-dg2-set2:     [FAIL][106] ([Intel XE#4427]) -> [PASS][107]
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-435/igt@kms_async_flips@async-flip-suspend-resume.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-432/igt@kms_async_flips@async-flip-suspend-resume.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
    - shard-adlp:         [FAIL][108] ([Intel XE#3908]) -> [PASS][109] +1 other test pass
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-adlp-2/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-adlp-8/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
    - shard-adlp:         [DMESG-FAIL][110] ([Intel XE#4543]) -> [PASS][111] +2 other tests pass
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-adlp-9/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-adlp-4/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html

  * igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p:
    - shard-bmg:          [SKIP][112] ([Intel XE#2314] / [Intel XE#2894]) -> [PASS][113]
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-bmg-5/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-1/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-bmg:          [INCOMPLETE][114] ([Intel XE#3862]) -> [PASS][115] +1 other test pass
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-bmg-2/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-4/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
    - shard-dg2-set2:     [INCOMPLETE][116] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#3124]) -> [PASS][117]
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-dp-4:
    - shard-dg2-set2:     [INCOMPLETE][118] ([Intel XE#3124]) -> [PASS][119]
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-dp-4.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-dp-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     [DMESG-WARN][120] ([Intel XE#1727] / [Intel XE#3113]) -> [PASS][121]
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-6.html
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-6.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
    - shard-bmg:          [SKIP][122] ([Intel XE#2291]) -> [PASS][123] +3 other tests pass
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-bmg-5/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-1/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@cd-hdmi-a6-dp4:
    - shard-dg2-set2:     [FAIL][124] ([Intel XE#301]) -> [PASS][125] +6 other tests pass
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-464/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@cd-hdmi-a6-dp4.html
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-435/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@cd-hdmi-a6-dp4.html

  * igt@kms_flip@2x-plain-flip-ts-check-interruptible:
    - shard-bmg:          [SKIP][126] ([Intel XE#2316]) -> [PASS][127] +5 other tests pass
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-bmg-5/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-2/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html

  * igt@kms_flip@blocking-absolute-wf_vblank-interruptible:
    - shard-dg2-set2:     [FAIL][128] ([Intel XE#3149]) -> [PASS][129]
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-435/igt@kms_flip@blocking-absolute-wf_vblank-interruptible.html
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-432/igt@kms_flip@blocking-absolute-wf_vblank-interruptible.html

  * igt@kms_flip@dpms-vs-vblank-race-interruptible@a-hdmi-a6:
    - shard-dg2-set2:     [FAIL][130] ([Intel XE#3098]) -> [PASS][131] +1 other test pass
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-433/igt@kms_flip@dpms-vs-vblank-race-interruptible@a-hdmi-a6.html
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-464/igt@kms_flip@dpms-vs-vblank-race-interruptible@a-hdmi-a6.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank:
    - shard-lnl:          [FAIL][132] ([Intel XE#886]) -> [PASS][133] +1 other test pass
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-lnl-2/igt@kms_flip@flip-vs-absolute-wf_vblank.html
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-lnl-8/igt@kms_flip@flip-vs-absolute-wf_vblank.html

  * igt@kms_flip@flip-vs-dpms-on-nop-interruptible:
    - shard-adlp:         [DMESG-WARN][134] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][135] +1 other test pass
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-adlp-4/igt@kms_flip@flip-vs-dpms-on-nop-interruptible.html
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-adlp-9/igt@kms_flip@flip-vs-dpms-on-nop-interruptible.html

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-to-y:
    - shard-adlp:         [FAIL][136] ([Intel XE#1874]) -> [PASS][137] +1 other test pass
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-adlp-6/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-to-y.html
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-adlp-6/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-to-y.html

  * igt@kms_joiner@basic-force-big-joiner:
    - shard-bmg:          [SKIP][138] ([Intel XE#3012]) -> [PASS][139]
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-bmg-5/igt@kms_joiner@basic-force-big-joiner.html
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-1/igt@kms_joiner@basic-force-big-joiner.html

  * igt@xe_exec_basic@multigpu-once-basic-defer-mmap:
    - shard-dg2-set2:     [SKIP][140] ([Intel XE#1392]) -> [PASS][141] +7 other tests pass
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-432/igt@xe_exec_basic@multigpu-once-basic-defer-mmap.html
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-464/igt@xe_exec_basic@multigpu-once-basic-defer-mmap.html

  * igt@xe_exec_reset@gt-reset-stress:
    - shard-adlp:         [DMESG-WARN][142] ([Intel XE#4812]) -> [PASS][143]
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-adlp-4/igt@xe_exec_reset@gt-reset-stress.html
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-adlp-9/igt@xe_exec_reset@gt-reset-stress.html

  * igt@xe_exec_reset@parallel-gt-reset:
    - shard-bmg:          [DMESG-WARN][144] ([Intel XE#3876]) -> [PASS][145]
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-bmg-7/igt@xe_exec_reset@parallel-gt-reset.html
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-6/igt@xe_exec_reset@parallel-gt-reset.html

  
#### Warnings ####

  * igt@kms_async_flips@async-flip-suspend-resume:
    - shard-adlp:         [DMESG-WARN][146] ([Intel XE#4543]) -> [DMESG-WARN][147] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#4543])
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-adlp-8/igt@kms_async_flips@async-flip-suspend-resume.html
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-adlp-2/igt@kms_async_flips@async-flip-suspend-resume.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
    - shard-dg2-set2:     [SKIP][148] ([Intel XE#1124]) -> [SKIP][149] ([Intel XE#4208]) +2 other tests skip
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-436/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-464/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html

  * igt@kms_bw@connected-linear-tiling-3-displays-2160x1440p:
    - shard-dg2-set2:     [SKIP][150] ([Intel XE#2191]) -> [SKIP][151] ([Intel XE#4208] / [i915#2575])
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-436/igt@kms_bw@connected-linear-tiling-3-displays-2160x1440p.html
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-464/igt@kms_bw@connected-linear-tiling-3-displays-2160x1440p.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
    - shard-dg2-set2:     [INCOMPLETE][152] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#3124] / [Intel XE#4345]) -> [INCOMPLETE][153] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345])
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
    - shard-dg2-set2:     [INCOMPLETE][154] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345] / [Intel XE#4522]) -> [INCOMPLETE][155] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#3124] / [Intel XE#4345])
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-dp-4:
    - shard-dg2-set2:     [INCOMPLETE][156] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4522]) -> [INCOMPLETE][157] ([Intel XE#3124])
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-dp-4.html
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-dp-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs:
    - shard-dg2-set2:     [SKIP][158] ([Intel XE#2907]) -> [SKIP][159] ([Intel XE#4208])
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html

  * igt@kms_cdclk@mode-transition-all-outputs:
    - shard-dg2-set2:     [SKIP][160] ([Intel XE#4418]) -> [SKIP][161] ([Intel XE#2351] / [Intel XE#4208])
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-436/igt@kms_cdclk@mode-transition-all-outputs.html
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-464/igt@kms_cdclk@mode-transition-all-outputs.html

  * igt@kms_chamelium_frames@hdmi-crc-single:
    - shard-dg2-set2:     [SKIP][162] ([Intel XE#373]) -> [SKIP][163] ([Intel XE#4208] / [i915#2575]) +2 other tests skip
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-436/igt@kms_chamelium_frames@hdmi-crc-single.html
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-464/igt@kms_chamelium_frames@hdmi-crc-single.html

  * igt@kms_content_protection@atomic:
    - shard-bmg:          [SKIP][164] ([Intel XE#2341]) -> [FAIL][165] ([Intel XE#1178]) +1 other test fail
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-bmg-5/igt@kms_content_protection@atomic.html
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-1/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@legacy:
    - shard-bmg:          [FAIL][166] ([Intel XE#1178]) -> [SKIP][167] ([Intel XE#2341])
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-bmg-2/igt@kms_content_protection@legacy.html
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-5/igt@kms_content_protection@legacy.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
    - shard-dg2-set2:     [SKIP][168] ([Intel XE#323]) -> [SKIP][169] ([Intel XE#4208] / [i915#2575])
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-436/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-464/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html

  * igt@kms_dsc@dsc-fractional-bpp:
    - shard-dg2-set2:     [SKIP][170] ([Intel XE#455]) -> [SKIP][171] ([Intel XE#4208])
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-436/igt@kms_dsc@dsc-fractional-bpp.html
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-464/igt@kms_dsc@dsc-fractional-bpp.html

  * igt@kms_feature_discovery@dp-mst:
    - shard-dg2-set2:     [SKIP][172] ([Intel XE#1137]) -> [SKIP][173] ([Intel XE#4208] / [i915#2575])
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-436/igt@kms_feature_discovery@dp-mst.html
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-464/igt@kms_feature_discovery@dp-mst.html

  * igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible:
    - shard-bmg:          [FAIL][174] ([Intel XE#2882] / [Intel XE#5338]) -> [SKIP][175] ([Intel XE#2316])
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-bmg-7/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-5/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html

  * igt@kms_flip@2x-flip-vs-expired-vblank:
    - shard-dg2-set2:     [FAIL][176] ([Intel XE#301]) -> [SKIP][177] ([Intel XE#4208] / [i915#2575])
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-436/igt@kms_flip@2x-flip-vs-expired-vblank.html
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-464/igt@kms_flip@2x-flip-vs-expired-vblank.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling:
    - shard-dg2-set2:     [SKIP][178] ([Intel XE#455]) -> [SKIP][179] ([Intel XE#2351] / [Intel XE#4208])
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-436/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-464/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-msflip-blt:
    - shard-bmg:          [SKIP][180] ([Intel XE#2311]) -> [SKIP][181] ([Intel XE#2312]) +19 other tests skip
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-bmg-7/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-msflip-blt.html
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-render:
    - shard-dg2-set2:     [SKIP][182] ([Intel XE#651]) -> [SKIP][183] ([Intel XE#4208]) +4 other tests skip
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-436/igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-render.html
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-464/igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-render:
    - shard-bmg:          [SKIP][184] ([Intel XE#2312]) -> [SKIP][185] ([Intel XE#4141]) +5 other tests skip
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-render.html
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt:
    - shard-bmg:          [SKIP][186] ([Intel XE#4141]) -> [SKIP][187] ([Intel XE#2312]) +9 other tests skip
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt.html
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-render:
    - shard-bmg:          [SKIP][188] ([Intel XE#2312]) -> [SKIP][189] ([Intel XE#2311]) +15 other tests skip
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-render.html
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-draw-blt:
    - shard-dg2-set2:     [SKIP][190] ([Intel XE#651]) -> [SKIP][191] ([Intel XE#2351] / [Intel XE#4208])
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-436/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-draw-blt.html
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-render:
    - shard-dg2-set2:     [SKIP][192] ([Intel XE#653]) -> [SKIP][193] ([Intel XE#4208])
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-436/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-render.html
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt:
    - shard-bmg:          [SKIP][194] ([Intel XE#2312]) -> [SKIP][195] ([Intel XE#2313]) +15 other tests skip
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt.html
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-plflip-blt:
    - shard-bmg:          [SKIP][196] ([Intel XE#2313]) -> [SKIP][197] ([Intel XE#2312]) +22 other tests skip
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-plflip-blt.html
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-render:
    - shard-dg2-set2:     [SKIP][198] ([Intel XE#653]) -> [SKIP][199] ([Intel XE#2351] / [Intel XE#4208]) +1 other test skip
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-436/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-render.html
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-464/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-render.html

  * igt@kms_joiner@basic-big-joiner:
    - shard-dg2-set2:     [SKIP][200] ([Intel XE#346]) -> [SKIP][201] ([Intel XE#4208])
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-436/igt@kms_joiner@basic-big-joiner.html
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-464/igt@kms_joiner@basic-big-joiner.html

  * igt@kms_plane_lowres@tiling-y:
    - shard-dg2-set2:     [SKIP][202] ([Intel XE#455]) -> [SKIP][203] ([Intel XE#4208] / [i915#2575]) +1 other test skip
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-436/igt@kms_plane_lowres@tiling-y.html
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-464/igt@kms_plane_lowres@tiling-y.html

  * igt@kms_plane_multiple@2x-tiling-yf:
    - shard-bmg:          [SKIP][204] ([Intel XE#4596]) -> [SKIP][205] ([Intel XE#5021])
   [204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-bmg-5/igt@kms_plane_multiple@2x-tiling-yf.html
   [205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-1/igt@kms_plane_multiple@2x-tiling-yf.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-dg2-set2:     [SKIP][206] ([Intel XE#1489]) -> [SKIP][207] ([Intel XE#4208]) +1 other test skip
   [206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-436/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-fully-sf.html
   [207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-464/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr@fbc-psr-cursor-blt:
    - shard-dg2-set2:     [SKIP][208] ([Intel XE#2850] / [Intel XE#929]) -> [SKIP][209] ([Intel XE#4208]) +1 other test skip
   [208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-436/igt@kms_psr@fbc-psr-cursor-blt.html
   [209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-464/igt@kms_psr@fbc-psr-cursor-blt.html

  * igt@kms_psr@fbc-psr2-cursor-blt:
    - shard-dg2-set2:     [SKIP][210] ([Intel XE#2850] / [Intel XE#929]) -> [SKIP][211] ([Intel XE#2351] / [Intel XE#4208])
   [210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-436/igt@kms_psr@fbc-psr2-cursor-blt.html
   [211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-464/igt@kms_psr@fbc-psr2-cursor-blt.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
    - shard-dg2-set2:     [SKIP][212] ([Intel XE#1127]) -> [SKIP][213] ([Intel XE#4208] / [i915#2575])
   [212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-436/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
   [213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-464/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          [SKIP][214] ([Intel XE#2509]) -> [SKIP][215] ([Intel XE#2426])
   [214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-bmg-1/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-bmg-3/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_vrr@lobf:
    - shard-dg2-set2:     [SKIP][216] ([Intel XE#2168]) -> [SKIP][217] ([Intel XE#4208] / [i915#2575])
   [216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-436/igt@kms_vrr@lobf.html
   [217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-464/igt@kms_vrr@lobf.html

  * igt@xe_configfs@survivability-mode:
    - shard-dg2-set2:     [SKIP][218] ([Intel XE#5249]) -> [SKIP][219] ([Intel XE#4208])
   [218]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-436/igt@xe_configfs@survivability-mode.html
   [219]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-464/igt@xe_configfs@survivability-mode.html

  * igt@xe_eudebug@basic-vm-bind-extended:
    - shard-dg2-set2:     [SKIP][220] ([Intel XE#4837]) -> [SKIP][221] ([Intel XE#4208]) +1 other test skip
   [220]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-436/igt@xe_eudebug@basic-vm-bind-extended.html
   [221]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-464/igt@xe_eudebug@basic-vm-bind-extended.html

  * igt@xe_exec_fault_mode@many-userptr:
    - shard-dg2-set2:     [SKIP][222] ([Intel XE#288]) -> [SKIP][223] ([Intel XE#4208]) +2 other tests skip
   [222]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-436/igt@xe_exec_fault_mode@many-userptr.html
   [223]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-464/igt@xe_exec_fault_mode@many-userptr.html

  * igt@xe_exec_system_allocator@many-large-mmap-free-race-nomemset:
    - shard-dg2-set2:     [SKIP][224] ([Intel XE#4915]) -> [SKIP][225] ([Intel XE#4208]) +36 other tests skip
   [224]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-436/igt@xe_exec_system_allocator@many-large-mmap-free-race-nomemset.html
   [225]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-464/igt@xe_exec_system_allocator@many-large-mmap-free-race-nomemset.html

  * igt@xe_oa@blocking:
    - shard-dg2-set2:     [SKIP][226] ([Intel XE#2541] / [Intel XE#3573]) -> [SKIP][227] ([Intel XE#4208]) +1 other test skip
   [226]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-436/igt@xe_oa@blocking.html
   [227]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-464/igt@xe_oa@blocking.html

  * igt@xe_pat@display-vs-wb-transient:
    - shard-dg2-set2:     [SKIP][228] ([Intel XE#1337]) -> [SKIP][229] ([Intel XE#4208])
   [228]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-436/igt@xe_pat@display-vs-wb-transient.html
   [229]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-464/igt@xe_pat@display-vs-wb-transient.html

  * igt@xe_peer2peer@read:
    - shard-dg2-set2:     [SKIP][230] ([Intel XE#1061]) -> [FAIL][231] ([Intel XE#1173])
   [230]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-432/igt@xe_peer2peer@read.html
   [231]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-435/igt@xe_peer2peer@read.html

  * igt@xe_query@multigpu-query-engines:
    - shard-dg2-set2:     [SKIP][232] ([Intel XE#944]) -> [SKIP][233] ([Intel XE#4208])
   [232]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19/shard-dg2-436/igt@xe_query@multigpu-query-engines.html
   [233]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/shard-dg2-464/igt@xe_query@multigpu-query-engines.html

  
  [Intel XE#1061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1061
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1126
  [Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
  [Intel XE#1129]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1129
  [Intel XE#1137]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1137
  [Intel XE#1173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1173
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1188]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1188
  [Intel XE#1337]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1337
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1874
  [Intel XE#2134]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2134
  [Intel XE#2168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2168
  [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
  [Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2236]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2236
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2351
  [Intel XE#2374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2374
  [Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
  [Intel XE#2391]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2391
  [Intel XE#2392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2392
  [Intel XE#2414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2414
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2450]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2450
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2541
  [Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2882]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2882
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
  [Intel XE#2907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2907
  [Intel XE#2938]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2938
  [Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3012]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3012
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#3098]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3098
  [Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
  [Intel XE#3124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3124
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#3321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3321
  [Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#346]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/346
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#3767]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3767
  [Intel XE#3862]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3862
  [Intel XE#3876]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3876
  [Intel XE#3908]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3908
  [Intel XE#4090]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4090
  [Intel XE#4130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4130
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4156]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4156
  [Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
  [Intel XE#4208]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4208
  [Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
  [Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
  [Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
  [Intel XE#4416]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4416
  [Intel XE#4418]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4418
  [Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
  [Intel XE#4427]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4427
  [Intel XE#4522]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4522
  [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#4633]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4633
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4812]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4812
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
  [Intel XE#4917]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4917
  [Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
  [Intel XE#5021]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5021
  [Intel XE#5249]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5249
  [Intel XE#5338]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5338
  [Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/886
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
  [i915#2575]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2575


Build changes
-------------

  * Linux: xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19 -> xe-pw-150157v2

  IGT_8424: 68588b3c89a1bbe08c54d21c4d3d2e509957c795 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-3302-bd57aee20daefb7b0dfe9017663668c92115ff19: bd57aee20daefb7b0dfe9017663668c92115ff19
  xe-pw-150157v2: 150157v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v2/index.html

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