* [PATCH 01/15] drm/i915/display: pass display to HAS_PCH_*() macros
2025-08-06 16:55 [PATCH 00/15] drm/i915: drop __to_intel_display() transitional macro Jani Nikula
@ 2025-08-06 16:55 ` Jani Nikula
2025-08-06 16:55 ` [PATCH 02/15] drm/i915/fb: pass display to HAS_GMCH() and DISPLAY_VER() Jani Nikula
` (18 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Jani Nikula @ 2025-08-06 16:55 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Convert some leftover i915 usages to struct intel_display.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_irq.c | 9 +++------
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index fb25ec8adae3..cbf6ed62825c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -1986,20 +1986,17 @@ void vlv_display_irq_postinstall(struct intel_display *display)
void ibx_display_irq_reset(struct intel_display *display)
{
- struct drm_i915_private *i915 = to_i915(display->drm);
-
- if (HAS_PCH_NOP(i915))
+ if (HAS_PCH_NOP(display))
return;
gen2_irq_reset(to_intel_uncore(display->drm), SDE_IRQ_REGS);
- if (HAS_PCH_CPT(i915) || HAS_PCH_LPT(i915))
+ if (HAS_PCH_CPT(display) || HAS_PCH_LPT(display))
intel_de_write(display, SERR_INT, 0xffffffff);
}
void gen8_display_irq_reset(struct intel_display *display)
{
- struct drm_i915_private *i915 = to_i915(display->drm);
enum pipe pipe;
if (!HAS_DISPLAY(display))
@@ -2016,7 +2013,7 @@ void gen8_display_irq_reset(struct intel_display *display)
intel_display_irq_regs_reset(display, GEN8_DE_PORT_IRQ_REGS);
intel_display_irq_regs_reset(display, GEN8_DE_MISC_IRQ_REGS);
- if (HAS_PCH_SPLIT(i915))
+ if (HAS_PCH_SPLIT(display))
ibx_display_irq_reset(display);
}
--
2.39.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 02/15] drm/i915/fb: pass display to HAS_GMCH() and DISPLAY_VER()
2025-08-06 16:55 [PATCH 00/15] drm/i915: drop __to_intel_display() transitional macro Jani Nikula
2025-08-06 16:55 ` [PATCH 01/15] drm/i915/display: pass display to HAS_PCH_*() macros Jani Nikula
@ 2025-08-06 16:55 ` Jani Nikula
2025-08-06 16:55 ` [PATCH 03/15] drm/i915/clockgating: pass display to for_each_pipe() Jani Nikula
` (17 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Jani Nikula @ 2025-08-06 16:55 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Convert some leftover i915 usages to struct intel_display.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_fb_pin.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c b/drivers/gpu/drm/i915/display/intel_fb_pin.c
index d598a005f847..45af04cb0fb2 100644
--- a/drivers/gpu/drm/i915/display/intel_fb_pin.c
+++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c
@@ -152,7 +152,7 @@ intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb,
* happy to scanout from anywhere within its global aperture.
*/
pinctl = 0;
- if (HAS_GMCH(dev_priv))
+ if (HAS_GMCH(display))
pinctl |= PIN_MAPPABLE;
i915_gem_ww_ctx_init(&ww, true);
@@ -193,7 +193,7 @@ intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb,
* mode that matches the user configuration.
*/
ret = i915_vma_pin_fence(vma);
- if (ret != 0 && DISPLAY_VER(dev_priv) < 4) {
+ if (ret != 0 && DISPLAY_VER(display) < 4) {
i915_vma_unpin(vma);
goto err_unpin;
}
--
2.39.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 03/15] drm/i915/clockgating: pass display to for_each_pipe()
2025-08-06 16:55 [PATCH 00/15] drm/i915: drop __to_intel_display() transitional macro Jani Nikula
2025-08-06 16:55 ` [PATCH 01/15] drm/i915/display: pass display to HAS_PCH_*() macros Jani Nikula
2025-08-06 16:55 ` [PATCH 02/15] drm/i915/fb: pass display to HAS_GMCH() and DISPLAY_VER() Jani Nikula
@ 2025-08-06 16:55 ` Jani Nikula
2025-08-06 16:55 ` [PATCH 04/15] drm/i915/clockgating: pass display to HAS_PCH_*() macros Jani Nikula
` (16 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Jani Nikula @ 2025-08-06 16:55 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Underneath, for_each_pipe() really expects struct intel_display. Switch
to it in preparation for removing the transitional __to_intel_display()
macro.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_clock_gating.c | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index f86a3629ae9e..b4dddd03eaf3 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -132,9 +132,10 @@ static void ibx_init_clock_gating(struct drm_i915_private *i915)
static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
{
+ struct intel_display *display = dev_priv->display;
enum pipe pipe;
- for_each_pipe(dev_priv, pipe) {
+ for_each_pipe(display, pipe) {
intel_uncore_rmw(&dev_priv->uncore, DSPCNTR(dev_priv, pipe),
0, DISP_TRICKLE_FEED_DISABLE);
@@ -218,7 +219,7 @@ static void cpt_init_clock_gating(struct drm_i915_private *i915)
/* The below fixes the weird display corruption, a few pixels shifted
* downward, on (only) LVDS of some HP laptops with IVY.
*/
- for_each_pipe(i915, pipe) {
+ for_each_pipe(display, pipe) {
val = intel_uncore_read(&i915->uncore, TRANS_CHICKEN2(pipe));
val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
@@ -229,7 +230,7 @@ static void cpt_init_clock_gating(struct drm_i915_private *i915)
intel_uncore_write(&i915->uncore, TRANS_CHICKEN2(pipe), val);
}
/* WADP0ClockGatingDisable */
- for_each_pipe(i915, pipe) {
+ for_each_pipe(display, pipe) {
intel_uncore_write(&i915->uncore, TRANS_CHICKEN1(pipe),
TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
}
@@ -421,6 +422,7 @@ static void skl_init_clock_gating(struct drm_i915_private *i915)
static void bdw_init_clock_gating(struct drm_i915_private *i915)
{
+ struct intel_display *display = i915->display;
enum pipe pipe;
/* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
@@ -432,7 +434,7 @@ static void bdw_init_clock_gating(struct drm_i915_private *i915)
/* WaPsrDPAMaskVBlankInSRD:bdw */
intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD);
- for_each_pipe(i915, pipe) {
+ for_each_pipe(display, pipe) {
/* WaPsrDPRSUnmaskVBlankInSRD:bdw */
intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(pipe),
0, BDW_UNMASK_VBL_TO_REGS_IN_SRD);
@@ -468,6 +470,7 @@ static void bdw_init_clock_gating(struct drm_i915_private *i915)
static void hsw_init_clock_gating(struct drm_i915_private *i915)
{
+ struct intel_display *display = i915->display;
enum pipe pipe;
/* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
@@ -476,7 +479,7 @@ static void hsw_init_clock_gating(struct drm_i915_private *i915)
/* WaPsrDPAMaskVBlankInSRD:hsw */
intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD);
- for_each_pipe(i915, pipe) {
+ for_each_pipe(display, pipe) {
/* WaPsrDPRSUnmaskVBlankInSRD:hsw */
intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(pipe),
0, HSW_UNMASK_VBL_TO_REGS_IN_SRD);
--
2.39.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 04/15] drm/i915/clockgating: pass display to HAS_PCH_*() macros
2025-08-06 16:55 [PATCH 00/15] drm/i915: drop __to_intel_display() transitional macro Jani Nikula
` (2 preceding siblings ...)
2025-08-06 16:55 ` [PATCH 03/15] drm/i915/clockgating: pass display to for_each_pipe() Jani Nikula
@ 2025-08-06 16:55 ` Jani Nikula
2025-08-06 16:55 ` [PATCH 05/15] drm/i915/clockgating: pass display to DSPCNTR and DSPSURF register macros Jani Nikula
` (15 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Jani Nikula @ 2025-08-06 16:55 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Underneath, the HAS_PCH_*() macros expect struct intel_display. Switch
to it in preparation for removing the transitional __to_intel_display()
macro.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_clock_gating.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index b4dddd03eaf3..bd919fa3bee5 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -308,11 +308,13 @@ static void gen6_init_clock_gating(struct drm_i915_private *i915)
static void lpt_init_clock_gating(struct drm_i915_private *i915)
{
+ struct intel_display *display = i915->display;
+
/*
* TODO: this bit should only be enabled when really needed, then
* disabled when not needed anymore in order to save power.
*/
- if (HAS_PCH_LPT_LP(i915))
+ if (HAS_PCH_LPT_LP(display))
intel_uncore_rmw(&i915->uncore, SOUTH_DSPCLK_GATE_D,
0, PCH_LP_PARTITION_LEVEL_DISABLE);
@@ -356,7 +358,9 @@ static void dg2_init_clock_gating(struct drm_i915_private *i915)
static void cnp_init_clock_gating(struct drm_i915_private *i915)
{
- if (!HAS_PCH_CNP(i915))
+ struct intel_display *display = i915->display;
+
+ if (!HAS_PCH_CNP(display))
return;
/* Display WA #1181 WaSouthDisplayDisablePWMCGEGating: cnp */
@@ -497,6 +501,8 @@ static void hsw_init_clock_gating(struct drm_i915_private *i915)
static void ivb_init_clock_gating(struct drm_i915_private *i915)
{
+ struct intel_display *display = i915->display;
+
intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
/* WaFbcAsynchFlipDisableFbcQueue:ivb */
@@ -534,7 +540,7 @@ static void ivb_init_clock_gating(struct drm_i915_private *i915)
intel_uncore_rmw(&i915->uncore, GEN6_MBCUNIT_SNPCR, GEN6_MBC_SNPCR_MASK,
GEN6_MBC_SNPCR_MED);
- if (!HAS_PCH_NOP(i915))
+ if (!HAS_PCH_NOP(display))
cpt_init_clock_gating(i915);
gen6_check_mch_setup(i915);
--
2.39.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 05/15] drm/i915/clockgating: pass display to DSPCNTR and DSPSURF register macros
2025-08-06 16:55 [PATCH 00/15] drm/i915: drop __to_intel_display() transitional macro Jani Nikula
` (3 preceding siblings ...)
2025-08-06 16:55 ` [PATCH 04/15] drm/i915/clockgating: pass display to HAS_PCH_*() macros Jani Nikula
@ 2025-08-06 16:55 ` Jani Nikula
2025-08-06 16:55 ` [PATCH 06/15] drm/i915/irq: pass display to macros that expect display Jani Nikula
` (14 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Jani Nikula @ 2025-08-06 16:55 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Underneath, the macros expect struct intel_display. Switch to it in
preparation for removing the transitional __to_intel_display() macro.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_clock_gating.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index bd919fa3bee5..e501f4937510 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -136,13 +136,13 @@ static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
enum pipe pipe;
for_each_pipe(display, pipe) {
- intel_uncore_rmw(&dev_priv->uncore, DSPCNTR(dev_priv, pipe),
+ intel_uncore_rmw(&dev_priv->uncore, DSPCNTR(display, pipe),
0, DISP_TRICKLE_FEED_DISABLE);
- intel_uncore_rmw(&dev_priv->uncore, DSPSURF(dev_priv, pipe),
+ intel_uncore_rmw(&dev_priv->uncore, DSPSURF(display, pipe),
0, 0);
intel_uncore_posting_read(&dev_priv->uncore,
- DSPSURF(dev_priv, pipe));
+ DSPSURF(display, pipe));
}
}
--
2.39.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 06/15] drm/i915/irq: pass display to macros that expect display
2025-08-06 16:55 [PATCH 00/15] drm/i915: drop __to_intel_display() transitional macro Jani Nikula
` (4 preceding siblings ...)
2025-08-06 16:55 ` [PATCH 05/15] drm/i915/clockgating: pass display to DSPCNTR and DSPSURF register macros Jani Nikula
@ 2025-08-06 16:55 ` Jani Nikula
2025-08-06 16:55 ` [PATCH 07/15] drm/i915/dram: " Jani Nikula
` (13 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Jani Nikula @ 2025-08-06 16:55 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Underneath, the HAS_PCH_NOP(), DISPLAY_VER(), HAS_FBC(), and
HAS_HOTPLUG() macros really expect a struct intel_display. Switch to it
in preparation for removing the transitional __to_intel_display() macro.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 191ed8bb1d9c..a5fa40ab5de2 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -439,7 +439,7 @@ static irqreturn_t ilk_irq_handler(int irq, void *arg)
* able to process them after we restore SDEIER (as soon as we restore
* it, we'll get an interrupt if SDEIIR still has something to process
* due to its back queue). */
- if (!HAS_PCH_NOP(i915)) {
+ if (!HAS_PCH_NOP(display)) {
sde_ier = raw_reg_read(regs, SDEIER);
raw_reg_write(regs, SDEIER, 0);
}
@@ -459,7 +459,7 @@ static irqreturn_t ilk_irq_handler(int irq, void *arg)
de_iir = raw_reg_read(regs, DEIIR);
if (de_iir) {
raw_reg_write(regs, DEIIR, de_iir);
- if (DISPLAY_VER(i915) >= 7)
+ if (DISPLAY_VER(display) >= 7)
ivb_display_irq_handler(display, de_iir);
else
ilk_display_irq_handler(display, de_iir);
@@ -834,6 +834,7 @@ static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
static u32 i9xx_error_mask(struct drm_i915_private *i915)
{
+ struct intel_display *display = i915->display;
/*
* On gen2/3 FBC generates (seemingly spurious)
* display INVALID_GTT/INVALID_GTT_PTE table errors.
@@ -846,7 +847,7 @@ static u32 i9xx_error_mask(struct drm_i915_private *i915)
* Unfortunately we can't mask off individual PGTBL_ER bits,
* so we just have to mask off all page table errors via EMR.
*/
- if (HAS_FBC(i915))
+ if (HAS_FBC(display))
return I915_ERROR_MEMORY_REFRESH;
else
return I915_ERROR_PAGE_TABLE |
@@ -924,12 +925,12 @@ static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
I915_MASTER_ERROR_INTERRUPT |
I915_USER_INTERRUPT;
- if (DISPLAY_VER(dev_priv) >= 3) {
+ if (DISPLAY_VER(display) >= 3) {
dev_priv->irq_mask &= ~I915_ASLE_INTERRUPT;
enable_mask |= I915_ASLE_INTERRUPT;
}
- if (HAS_HOTPLUG(dev_priv)) {
+ if (HAS_HOTPLUG(display)) {
dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
}
@@ -963,7 +964,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
ret = IRQ_HANDLED;
- if (HAS_HOTPLUG(dev_priv) &&
+ if (HAS_HOTPLUG(display) &&
iir & I915_DISPLAY_PORT_INTERRUPT)
hotplug_status = i9xx_hpd_irq_ack(display);
--
2.39.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 07/15] drm/i915/dram: pass display to macros that expect display
2025-08-06 16:55 [PATCH 00/15] drm/i915: drop __to_intel_display() transitional macro Jani Nikula
` (5 preceding siblings ...)
2025-08-06 16:55 ` [PATCH 06/15] drm/i915/irq: pass display to macros that expect display Jani Nikula
@ 2025-08-06 16:55 ` Jani Nikula
2025-08-06 16:55 ` [PATCH 08/15] drm/i915/gmch: pass display to DISPLAY_VER() Jani Nikula
` (12 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Jani Nikula @ 2025-08-06 16:55 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Underneath, the HAS_DISPLAY() and DISPLAY_VER() macros really expect
struct intel_display. Switch to it in preparation for removing the
transitional __to_intel_display() macro.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/soc/intel_dram.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c
index 3eeaabdf59e8..b3c407cc200f 100644
--- a/drivers/gpu/drm/i915/soc/intel_dram.c
+++ b/drivers/gpu/drm/i915/soc/intel_dram.c
@@ -710,13 +710,14 @@ static int xelpdp_get_dram_info(struct drm_i915_private *i915, struct dram_info
int intel_dram_detect(struct drm_i915_private *i915)
{
+ struct intel_display *display = i915->display;
struct dram_info *dram_info;
int ret;
detect_fsb_freq(i915);
detect_mem_freq(i915);
- if (GRAPHICS_VER(i915) < 9 || IS_DG2(i915) || !HAS_DISPLAY(i915))
+ if (GRAPHICS_VER(i915) < 9 || IS_DG2(i915) || !HAS_DISPLAY(display))
return 0;
dram_info = drmm_kzalloc(&i915->drm, sizeof(*dram_info), GFP_KERNEL);
@@ -731,7 +732,7 @@ int intel_dram_detect(struct drm_i915_private *i915)
*/
dram_info->wm_lv_0_adjust_needed = !IS_BROXTON(i915) && !IS_GEMINILAKE(i915);
- if (DISPLAY_VER(i915) >= 14)
+ if (DISPLAY_VER(display) >= 14)
ret = xelpdp_get_dram_info(i915, dram_info);
else if (GRAPHICS_VER(i915) >= 12)
ret = gen12_get_dram_info(i915, dram_info);
--
2.39.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 08/15] drm/i915/gmch: pass display to DISPLAY_VER()
2025-08-06 16:55 [PATCH 00/15] drm/i915: drop __to_intel_display() transitional macro Jani Nikula
` (6 preceding siblings ...)
2025-08-06 16:55 ` [PATCH 07/15] drm/i915/dram: " Jani Nikula
@ 2025-08-06 16:55 ` Jani Nikula
2025-08-06 16:55 ` [PATCH 09/15] drm/i915/gem: pass display to HAS_DISPLAY() Jani Nikula
` (11 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Jani Nikula @ 2025-08-06 16:55 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Underneath, DISPLAY_VER() really expects struct intel_display. Switch to
it in preparation for removing the transitional __to_intel_display()
macro.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/soc/intel_gmch.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/soc/intel_gmch.c b/drivers/gpu/drm/i915/soc/intel_gmch.c
index 5346b8dda79a..f210c9655b53 100644
--- a/drivers/gpu/drm/i915/soc/intel_gmch.c
+++ b/drivers/gpu/drm/i915/soc/intel_gmch.c
@@ -148,7 +148,8 @@ void intel_gmch_bar_teardown(struct drm_i915_private *i915)
int intel_gmch_vga_set_state(struct drm_i915_private *i915, bool enable_decode)
{
- unsigned int reg = DISPLAY_VER(i915) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
+ struct intel_display *display = i915->display;
+ unsigned int reg = DISPLAY_VER(display) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
u16 gmch_ctrl;
if (pci_read_config_word(i915->gmch.pdev, reg, &gmch_ctrl)) {
--
2.39.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 09/15] drm/i915/gem: pass display to HAS_DISPLAY()
2025-08-06 16:55 [PATCH 00/15] drm/i915: drop __to_intel_display() transitional macro Jani Nikula
` (7 preceding siblings ...)
2025-08-06 16:55 ` [PATCH 08/15] drm/i915/gmch: pass display to DISPLAY_VER() Jani Nikula
@ 2025-08-06 16:55 ` Jani Nikula
2025-08-06 16:55 ` [PATCH 10/15] drm/i915/switcheroo: " Jani Nikula
` (10 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Jani Nikula @ 2025-08-06 16:55 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Underneath, HAS_DISPLAY() really expects a struct intel_display. Switch
to it in preparation for removing the transitional __to_intel_display()
macro.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
index 86d9d2fcb6a6..e747f5ed195e 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
@@ -110,6 +110,7 @@ struct tiled_blits {
static bool fastblit_supports_x_tiling(const struct drm_i915_private *i915)
{
+ struct intel_display *display = i915->display;
int gen = GRAPHICS_VER(i915);
/* XY_FAST_COPY_BLT does not exist on pre-gen9 platforms */
@@ -121,7 +122,7 @@ static bool fastblit_supports_x_tiling(const struct drm_i915_private *i915)
if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 55))
return false;
- return HAS_DISPLAY(i915);
+ return HAS_DISPLAY(display);
}
static bool fast_blit_ok(const struct blit_buffer *buf)
--
2.39.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 10/15] drm/i915/switcheroo: pass display to HAS_DISPLAY()
2025-08-06 16:55 [PATCH 00/15] drm/i915: drop __to_intel_display() transitional macro Jani Nikula
` (8 preceding siblings ...)
2025-08-06 16:55 ` [PATCH 09/15] drm/i915/gem: pass display to HAS_DISPLAY() Jani Nikula
@ 2025-08-06 16:55 ` Jani Nikula
2025-08-06 16:55 ` [PATCH 11/15] drm/i915/drv: " Jani Nikula
` (9 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Jani Nikula @ 2025-08-06 16:55 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Underneath, HAS_DISPLAY() really expects a struct intel_display. Switch
to it in preparation for removing the transitional __to_intel_display()
macro.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_switcheroo.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_switcheroo.c b/drivers/gpu/drm/i915/i915_switcheroo.c
index 4c02a04be681..231d27497706 100644
--- a/drivers/gpu/drm/i915/i915_switcheroo.c
+++ b/drivers/gpu/drm/i915/i915_switcheroo.c
@@ -15,13 +15,14 @@ static void i915_switcheroo_set_state(struct pci_dev *pdev,
enum vga_switcheroo_state state)
{
struct drm_i915_private *i915 = pdev_to_i915(pdev);
+ struct intel_display *display = i915->display;
pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
if (!i915) {
dev_err(&pdev->dev, "DRM not initialized, aborting switch.\n");
return;
}
- if (!HAS_DISPLAY(i915)) {
+ if (!HAS_DISPLAY(display)) {
dev_err(&pdev->dev, "Device state not initialized, aborting switch.\n");
return;
}
@@ -44,13 +45,14 @@ static void i915_switcheroo_set_state(struct pci_dev *pdev,
static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
{
struct drm_i915_private *i915 = pdev_to_i915(pdev);
+ struct intel_display *display = i915->display;
/*
* FIXME: open_count is protected by drm_global_mutex but that would lead to
* locking inversion with the driver load path. And the access here is
* completely racy anyway. So don't bother with locking for now.
*/
- return i915 && HAS_DISPLAY(i915) && atomic_read(&i915->drm.open_count) == 0;
+ return i915 && HAS_DISPLAY(display) && atomic_read(&i915->drm.open_count) == 0;
}
static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
--
2.39.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 11/15] drm/i915/drv: pass display to HAS_DISPLAY()
2025-08-06 16:55 [PATCH 00/15] drm/i915: drop __to_intel_display() transitional macro Jani Nikula
` (9 preceding siblings ...)
2025-08-06 16:55 ` [PATCH 10/15] drm/i915/switcheroo: " Jani Nikula
@ 2025-08-06 16:55 ` Jani Nikula
2025-08-06 16:55 ` [PATCH 12/15] drm/i915/uncore: pass display to HAS_FPGA_DBG_UNCLAIMED() Jani Nikula
` (8 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Jani Nikula @ 2025-08-06 16:55 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Underneath, HAS_DISPLAY() really expects a struct intel_display. Switch
to it in preparation for removing the transitional __to_intel_display()
macro.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_driver.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index c6263c6d3384..70f042ce8705 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -977,7 +977,7 @@ void i915_driver_shutdown(struct drm_i915_private *i915)
intel_power_domains_disable(display);
drm_client_dev_suspend(&i915->drm, false);
- if (HAS_DISPLAY(i915)) {
+ if (HAS_DISPLAY(display)) {
drm_kms_helper_poll_disable(&i915->drm);
intel_display_driver_disable_user_access(display);
@@ -989,7 +989,7 @@ void i915_driver_shutdown(struct drm_i915_private *i915)
intel_irq_suspend(i915);
intel_hpd_cancel_work(display);
- if (HAS_DISPLAY(i915))
+ if (HAS_DISPLAY(display))
intel_display_driver_suspend_access(display);
intel_encoder_suspend_all(display);
@@ -1060,7 +1060,7 @@ static int i915_drm_suspend(struct drm_device *dev)
* properly. */
intel_power_domains_disable(display);
drm_client_dev_suspend(dev, false);
- if (HAS_DISPLAY(dev_priv)) {
+ if (HAS_DISPLAY(display)) {
drm_kms_helper_poll_disable(dev);
intel_display_driver_disable_user_access(display);
}
@@ -1072,7 +1072,7 @@ static int i915_drm_suspend(struct drm_device *dev)
intel_irq_suspend(dev_priv);
intel_hpd_cancel_work(display);
- if (HAS_DISPLAY(dev_priv))
+ if (HAS_DISPLAY(display))
intel_display_driver_suspend_access(display);
intel_encoder_suspend_all(display);
@@ -1219,7 +1219,7 @@ static int i915_drm_resume(struct drm_device *dev)
*/
intel_irq_resume(dev_priv);
- if (HAS_DISPLAY(dev_priv))
+ if (HAS_DISPLAY(display))
drm_mode_config_reset(dev);
i915_gem_resume(dev_priv);
@@ -1228,14 +1228,14 @@ static int i915_drm_resume(struct drm_device *dev)
intel_clock_gating_init(dev_priv);
- if (HAS_DISPLAY(dev_priv))
+ if (HAS_DISPLAY(display))
intel_display_driver_resume_access(display);
intel_hpd_init(display);
intel_display_driver_resume(display);
- if (HAS_DISPLAY(dev_priv)) {
+ if (HAS_DISPLAY(display)) {
intel_display_driver_enable_user_access(display);
drm_kms_helper_poll_enable(dev);
}
--
2.39.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 12/15] drm/i915/uncore: pass display to HAS_FPGA_DBG_UNCLAIMED()
2025-08-06 16:55 [PATCH 00/15] drm/i915: drop __to_intel_display() transitional macro Jani Nikula
` (10 preceding siblings ...)
2025-08-06 16:55 ` [PATCH 11/15] drm/i915/drv: " Jani Nikula
@ 2025-08-06 16:55 ` Jani Nikula
2025-08-06 16:55 ` [PATCH 13/15] drm/i915/gvt: convert mmio table to struct intel_display Jani Nikula
` (7 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Jani Nikula @ 2025-08-06 16:55 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Underneath, HAS_FPGA_DBG_UNCLAIMED() really expects struct
intel_display. Switch to it in preparation for removing the transitional
__to_intel_display() macro.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 3 ++-
drivers/gpu/drm/i915/selftests/intel_uncore.c | 8 +++++---
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index c8e29fd72290..4ccba7c8ffb3 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -2502,6 +2502,7 @@ static int sanity_check_mmio_access(struct intel_uncore *uncore)
int intel_uncore_init_mmio(struct intel_uncore *uncore)
{
struct drm_i915_private *i915 = uncore->i915;
+ struct intel_display *display = i915->display;
int ret;
ret = sanity_check_mmio_access(uncore);
@@ -2536,7 +2537,7 @@ int intel_uncore_init_mmio(struct intel_uncore *uncore)
GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.read_fw_domains);
GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.write_fw_domains);
- if (HAS_FPGA_DBG_UNCLAIMED(i915))
+ if (HAS_FPGA_DBG_UNCLAIMED(display))
uncore->flags |= UNCORE_HAS_FPGA_DBG_UNCLAIMED;
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c b/drivers/gpu/drm/i915/selftests/intel_uncore.c
index 41eaa9b7f67d..58bcbdcef563 100644
--- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
+++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
@@ -277,13 +277,15 @@ static int live_forcewake_domains(void *arg)
#define FW_RANGE 0x40000
struct intel_gt *gt = arg;
struct intel_uncore *uncore = gt->uncore;
+ struct drm_i915_private *i915 = gt->i915;
+ struct intel_display *display = i915->display;
unsigned long *valid;
u32 offset;
int err;
- if (!HAS_FPGA_DBG_UNCLAIMED(gt->i915) &&
- !IS_VALLEYVIEW(gt->i915) &&
- !IS_CHERRYVIEW(gt->i915))
+ if (!HAS_FPGA_DBG_UNCLAIMED(display) &&
+ !IS_VALLEYVIEW(i915) &&
+ !IS_CHERRYVIEW(i915))
return 0;
/*
--
2.39.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 13/15] drm/i915/gvt: convert mmio table to struct intel_display
2025-08-06 16:55 [PATCH 00/15] drm/i915: drop __to_intel_display() transitional macro Jani Nikula
` (11 preceding siblings ...)
2025-08-06 16:55 ` [PATCH 12/15] drm/i915/uncore: pass display to HAS_FPGA_DBG_UNCLAIMED() Jani Nikula
@ 2025-08-06 16:55 ` Jani Nikula
2025-08-06 16:55 ` [PATCH 14/15] drm/i915/reg: separate VLV_DSPCLK_GATE_D from DSPCLK_GATE_D Jani Nikula
` (6 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Jani Nikula @ 2025-08-06 16:55 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Underneath, the register macros really expect a struct
intel_display. Switch to it in preparation for removing the transitional
__to_intel_display() macro.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 266 ++++++++++----------
1 file changed, 134 insertions(+), 132 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 87ac4446d306..ca57a3dd3148 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -62,6 +62,7 @@
static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
{
struct drm_i915_private *dev_priv = iter->i915;
+ struct intel_display *display = dev_priv->display;
MMIO_RING_D(RING_IMR);
MMIO_D(SDEIMR);
@@ -133,38 +134,38 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(_MMIO(0x650b4));
MMIO_D(_MMIO(0xc4040));
MMIO_D(DERRMR);
- MMIO_D(PIPEDSL(dev_priv, PIPE_A));
- MMIO_D(PIPEDSL(dev_priv, PIPE_B));
- MMIO_D(PIPEDSL(dev_priv, PIPE_C));
- MMIO_D(PIPEDSL(dev_priv, _PIPE_EDP));
- MMIO_D(TRANSCONF(dev_priv, TRANSCODER_A));
- MMIO_D(TRANSCONF(dev_priv, TRANSCODER_B));
- MMIO_D(TRANSCONF(dev_priv, TRANSCODER_C));
- MMIO_D(TRANSCONF(dev_priv, TRANSCODER_EDP));
- MMIO_D(PIPESTAT(dev_priv, PIPE_A));
- MMIO_D(PIPESTAT(dev_priv, PIPE_B));
- MMIO_D(PIPESTAT(dev_priv, PIPE_C));
- MMIO_D(PIPESTAT(dev_priv, _PIPE_EDP));
- MMIO_D(PIPE_FLIPCOUNT_G4X(dev_priv, PIPE_A));
- MMIO_D(PIPE_FLIPCOUNT_G4X(dev_priv, PIPE_B));
- MMIO_D(PIPE_FLIPCOUNT_G4X(dev_priv, PIPE_C));
- MMIO_D(PIPE_FLIPCOUNT_G4X(dev_priv, _PIPE_EDP));
- MMIO_D(PIPE_FRMCOUNT_G4X(dev_priv, PIPE_A));
- MMIO_D(PIPE_FRMCOUNT_G4X(dev_priv, PIPE_B));
- MMIO_D(PIPE_FRMCOUNT_G4X(dev_priv, PIPE_C));
- MMIO_D(PIPE_FRMCOUNT_G4X(dev_priv, _PIPE_EDP));
- MMIO_D(CURCNTR(dev_priv, PIPE_A));
- MMIO_D(CURCNTR(dev_priv, PIPE_B));
- MMIO_D(CURCNTR(dev_priv, PIPE_C));
- MMIO_D(CURPOS(dev_priv, PIPE_A));
- MMIO_D(CURPOS(dev_priv, PIPE_B));
- MMIO_D(CURPOS(dev_priv, PIPE_C));
- MMIO_D(CURBASE(dev_priv, PIPE_A));
- MMIO_D(CURBASE(dev_priv, PIPE_B));
- MMIO_D(CURBASE(dev_priv, PIPE_C));
- MMIO_D(CUR_FBC_CTL(dev_priv, PIPE_A));
- MMIO_D(CUR_FBC_CTL(dev_priv, PIPE_B));
- MMIO_D(CUR_FBC_CTL(dev_priv, PIPE_C));
+ MMIO_D(PIPEDSL(display, PIPE_A));
+ MMIO_D(PIPEDSL(display, PIPE_B));
+ MMIO_D(PIPEDSL(display, PIPE_C));
+ MMIO_D(PIPEDSL(display, _PIPE_EDP));
+ MMIO_D(TRANSCONF(display, TRANSCODER_A));
+ MMIO_D(TRANSCONF(display, TRANSCODER_B));
+ MMIO_D(TRANSCONF(display, TRANSCODER_C));
+ MMIO_D(TRANSCONF(display, TRANSCODER_EDP));
+ MMIO_D(PIPESTAT(display, PIPE_A));
+ MMIO_D(PIPESTAT(display, PIPE_B));
+ MMIO_D(PIPESTAT(display, PIPE_C));
+ MMIO_D(PIPESTAT(display, _PIPE_EDP));
+ MMIO_D(PIPE_FLIPCOUNT_G4X(display, PIPE_A));
+ MMIO_D(PIPE_FLIPCOUNT_G4X(display, PIPE_B));
+ MMIO_D(PIPE_FLIPCOUNT_G4X(display, PIPE_C));
+ MMIO_D(PIPE_FLIPCOUNT_G4X(display, _PIPE_EDP));
+ MMIO_D(PIPE_FRMCOUNT_G4X(display, PIPE_A));
+ MMIO_D(PIPE_FRMCOUNT_G4X(display, PIPE_B));
+ MMIO_D(PIPE_FRMCOUNT_G4X(display, PIPE_C));
+ MMIO_D(PIPE_FRMCOUNT_G4X(display, _PIPE_EDP));
+ MMIO_D(CURCNTR(display, PIPE_A));
+ MMIO_D(CURCNTR(display, PIPE_B));
+ MMIO_D(CURCNTR(display, PIPE_C));
+ MMIO_D(CURPOS(display, PIPE_A));
+ MMIO_D(CURPOS(display, PIPE_B));
+ MMIO_D(CURPOS(display, PIPE_C));
+ MMIO_D(CURBASE(display, PIPE_A));
+ MMIO_D(CURBASE(display, PIPE_B));
+ MMIO_D(CURBASE(display, PIPE_C));
+ MMIO_D(CUR_FBC_CTL(display, PIPE_A));
+ MMIO_D(CUR_FBC_CTL(display, PIPE_B));
+ MMIO_D(CUR_FBC_CTL(display, PIPE_C));
MMIO_D(_MMIO(0x700ac));
MMIO_D(_MMIO(0x710ac));
MMIO_D(_MMIO(0x720ac));
@@ -172,32 +173,32 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(_MMIO(0x70094));
MMIO_D(_MMIO(0x70098));
MMIO_D(_MMIO(0x7009c));
- MMIO_D(DSPCNTR(dev_priv, PIPE_A));
- MMIO_D(DSPADDR(dev_priv, PIPE_A));
- MMIO_D(DSPSTRIDE(dev_priv, PIPE_A));
- MMIO_D(DSPPOS(dev_priv, PIPE_A));
- MMIO_D(DSPSIZE(dev_priv, PIPE_A));
- MMIO_D(DSPSURF(dev_priv, PIPE_A));
- MMIO_D(DSPOFFSET(dev_priv, PIPE_A));
- MMIO_D(DSPSURFLIVE(dev_priv, PIPE_A));
+ MMIO_D(DSPCNTR(display, PIPE_A));
+ MMIO_D(DSPADDR(display, PIPE_A));
+ MMIO_D(DSPSTRIDE(display, PIPE_A));
+ MMIO_D(DSPPOS(display, PIPE_A));
+ MMIO_D(DSPSIZE(display, PIPE_A));
+ MMIO_D(DSPSURF(display, PIPE_A));
+ MMIO_D(DSPOFFSET(display, PIPE_A));
+ MMIO_D(DSPSURFLIVE(display, PIPE_A));
MMIO_D(REG_50080(PIPE_A, PLANE_PRIMARY));
- MMIO_D(DSPCNTR(dev_priv, PIPE_B));
- MMIO_D(DSPADDR(dev_priv, PIPE_B));
- MMIO_D(DSPSTRIDE(dev_priv, PIPE_B));
- MMIO_D(DSPPOS(dev_priv, PIPE_B));
- MMIO_D(DSPSIZE(dev_priv, PIPE_B));
- MMIO_D(DSPSURF(dev_priv, PIPE_B));
- MMIO_D(DSPOFFSET(dev_priv, PIPE_B));
- MMIO_D(DSPSURFLIVE(dev_priv, PIPE_B));
+ MMIO_D(DSPCNTR(display, PIPE_B));
+ MMIO_D(DSPADDR(display, PIPE_B));
+ MMIO_D(DSPSTRIDE(display, PIPE_B));
+ MMIO_D(DSPPOS(display, PIPE_B));
+ MMIO_D(DSPSIZE(display, PIPE_B));
+ MMIO_D(DSPSURF(display, PIPE_B));
+ MMIO_D(DSPOFFSET(display, PIPE_B));
+ MMIO_D(DSPSURFLIVE(display, PIPE_B));
MMIO_D(REG_50080(PIPE_B, PLANE_PRIMARY));
- MMIO_D(DSPCNTR(dev_priv, PIPE_C));
- MMIO_D(DSPADDR(dev_priv, PIPE_C));
- MMIO_D(DSPSTRIDE(dev_priv, PIPE_C));
- MMIO_D(DSPPOS(dev_priv, PIPE_C));
- MMIO_D(DSPSIZE(dev_priv, PIPE_C));
- MMIO_D(DSPSURF(dev_priv, PIPE_C));
- MMIO_D(DSPOFFSET(dev_priv, PIPE_C));
- MMIO_D(DSPSURFLIVE(dev_priv, PIPE_C));
+ MMIO_D(DSPCNTR(display, PIPE_C));
+ MMIO_D(DSPADDR(display, PIPE_C));
+ MMIO_D(DSPSTRIDE(display, PIPE_C));
+ MMIO_D(DSPPOS(display, PIPE_C));
+ MMIO_D(DSPSIZE(display, PIPE_C));
+ MMIO_D(DSPSURF(display, PIPE_C));
+ MMIO_D(DSPOFFSET(display, PIPE_C));
+ MMIO_D(DSPSURFLIVE(display, PIPE_C));
MMIO_D(REG_50080(PIPE_C, PLANE_PRIMARY));
MMIO_D(SPRCTL(PIPE_A));
MMIO_D(SPRLINOFF(PIPE_A));
@@ -238,73 +239,73 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(SPRSCALE(PIPE_C));
MMIO_D(SPRSURFLIVE(PIPE_C));
MMIO_D(REG_50080(PIPE_C, PLANE_SPRITE0));
- MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_A));
- MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_A));
- MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_A));
- MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_A));
- MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_A));
- MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_A));
- MMIO_D(BCLRPAT(dev_priv, TRANSCODER_A));
- MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_A));
- MMIO_D(PIPESRC(dev_priv, TRANSCODER_A));
- MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_B));
- MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_B));
- MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_B));
- MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_B));
- MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_B));
- MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_B));
- MMIO_D(BCLRPAT(dev_priv, TRANSCODER_B));
- MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_B));
- MMIO_D(PIPESRC(dev_priv, TRANSCODER_B));
- MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_C));
- MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_C));
- MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_C));
- MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_C));
- MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_C));
- MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_C));
- MMIO_D(BCLRPAT(dev_priv, TRANSCODER_C));
- MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_C));
- MMIO_D(PIPESRC(dev_priv, TRANSCODER_C));
- MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_EDP));
- MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_EDP));
- MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_EDP));
- MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_EDP));
- MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_EDP));
- MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_EDP));
- MMIO_D(BCLRPAT(dev_priv, TRANSCODER_EDP));
- MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_EDP));
- MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_A));
- MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_A));
- MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_A));
- MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_A));
- MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_A));
- MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_A));
- MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_A));
- MMIO_D(PIPE_LINK_N2(dev_priv, TRANSCODER_A));
- MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_B));
- MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_B));
- MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_B));
- MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_B));
- MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_B));
- MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_B));
- MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_B));
- MMIO_D(PIPE_LINK_N2(dev_priv, TRANSCODER_B));
- MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_C));
- MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_C));
- MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_C));
- MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_C));
- MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_C));
- MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_C));
- MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_C));
- MMIO_D(PIPE_LINK_N2(dev_priv, TRANSCODER_C));
- MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_EDP));
- MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_EDP));
- MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_EDP));
- MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_EDP));
- MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_EDP));
- MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_EDP));
- MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_EDP));
- MMIO_D(PIPE_LINK_N2(dev_priv, TRANSCODER_EDP));
+ MMIO_D(TRANS_HTOTAL(display, TRANSCODER_A));
+ MMIO_D(TRANS_HBLANK(display, TRANSCODER_A));
+ MMIO_D(TRANS_HSYNC(display, TRANSCODER_A));
+ MMIO_D(TRANS_VTOTAL(display, TRANSCODER_A));
+ MMIO_D(TRANS_VBLANK(display, TRANSCODER_A));
+ MMIO_D(TRANS_VSYNC(display, TRANSCODER_A));
+ MMIO_D(BCLRPAT(display, TRANSCODER_A));
+ MMIO_D(TRANS_VSYNCSHIFT(display, TRANSCODER_A));
+ MMIO_D(PIPESRC(display, TRANSCODER_A));
+ MMIO_D(TRANS_HTOTAL(display, TRANSCODER_B));
+ MMIO_D(TRANS_HBLANK(display, TRANSCODER_B));
+ MMIO_D(TRANS_HSYNC(display, TRANSCODER_B));
+ MMIO_D(TRANS_VTOTAL(display, TRANSCODER_B));
+ MMIO_D(TRANS_VBLANK(display, TRANSCODER_B));
+ MMIO_D(TRANS_VSYNC(display, TRANSCODER_B));
+ MMIO_D(BCLRPAT(display, TRANSCODER_B));
+ MMIO_D(TRANS_VSYNCSHIFT(display, TRANSCODER_B));
+ MMIO_D(PIPESRC(display, TRANSCODER_B));
+ MMIO_D(TRANS_HTOTAL(display, TRANSCODER_C));
+ MMIO_D(TRANS_HBLANK(display, TRANSCODER_C));
+ MMIO_D(TRANS_HSYNC(display, TRANSCODER_C));
+ MMIO_D(TRANS_VTOTAL(display, TRANSCODER_C));
+ MMIO_D(TRANS_VBLANK(display, TRANSCODER_C));
+ MMIO_D(TRANS_VSYNC(display, TRANSCODER_C));
+ MMIO_D(BCLRPAT(display, TRANSCODER_C));
+ MMIO_D(TRANS_VSYNCSHIFT(display, TRANSCODER_C));
+ MMIO_D(PIPESRC(display, TRANSCODER_C));
+ MMIO_D(TRANS_HTOTAL(display, TRANSCODER_EDP));
+ MMIO_D(TRANS_HBLANK(display, TRANSCODER_EDP));
+ MMIO_D(TRANS_HSYNC(display, TRANSCODER_EDP));
+ MMIO_D(TRANS_VTOTAL(display, TRANSCODER_EDP));
+ MMIO_D(TRANS_VBLANK(display, TRANSCODER_EDP));
+ MMIO_D(TRANS_VSYNC(display, TRANSCODER_EDP));
+ MMIO_D(BCLRPAT(display, TRANSCODER_EDP));
+ MMIO_D(TRANS_VSYNCSHIFT(display, TRANSCODER_EDP));
+ MMIO_D(PIPE_DATA_M1(display, TRANSCODER_A));
+ MMIO_D(PIPE_DATA_N1(display, TRANSCODER_A));
+ MMIO_D(PIPE_DATA_M2(display, TRANSCODER_A));
+ MMIO_D(PIPE_DATA_N2(display, TRANSCODER_A));
+ MMIO_D(PIPE_LINK_M1(display, TRANSCODER_A));
+ MMIO_D(PIPE_LINK_N1(display, TRANSCODER_A));
+ MMIO_D(PIPE_LINK_M2(display, TRANSCODER_A));
+ MMIO_D(PIPE_LINK_N2(display, TRANSCODER_A));
+ MMIO_D(PIPE_DATA_M1(display, TRANSCODER_B));
+ MMIO_D(PIPE_DATA_N1(display, TRANSCODER_B));
+ MMIO_D(PIPE_DATA_M2(display, TRANSCODER_B));
+ MMIO_D(PIPE_DATA_N2(display, TRANSCODER_B));
+ MMIO_D(PIPE_LINK_M1(display, TRANSCODER_B));
+ MMIO_D(PIPE_LINK_N1(display, TRANSCODER_B));
+ MMIO_D(PIPE_LINK_M2(display, TRANSCODER_B));
+ MMIO_D(PIPE_LINK_N2(display, TRANSCODER_B));
+ MMIO_D(PIPE_DATA_M1(display, TRANSCODER_C));
+ MMIO_D(PIPE_DATA_N1(display, TRANSCODER_C));
+ MMIO_D(PIPE_DATA_M2(display, TRANSCODER_C));
+ MMIO_D(PIPE_DATA_N2(display, TRANSCODER_C));
+ MMIO_D(PIPE_LINK_M1(display, TRANSCODER_C));
+ MMIO_D(PIPE_LINK_N1(display, TRANSCODER_C));
+ MMIO_D(PIPE_LINK_M2(display, TRANSCODER_C));
+ MMIO_D(PIPE_LINK_N2(display, TRANSCODER_C));
+ MMIO_D(PIPE_DATA_M1(display, TRANSCODER_EDP));
+ MMIO_D(PIPE_DATA_N1(display, TRANSCODER_EDP));
+ MMIO_D(PIPE_DATA_M2(display, TRANSCODER_EDP));
+ MMIO_D(PIPE_DATA_N2(display, TRANSCODER_EDP));
+ MMIO_D(PIPE_LINK_M1(display, TRANSCODER_EDP));
+ MMIO_D(PIPE_LINK_N1(display, TRANSCODER_EDP));
+ MMIO_D(PIPE_LINK_M2(display, TRANSCODER_EDP));
+ MMIO_D(PIPE_LINK_N2(display, TRANSCODER_EDP));
MMIO_D(PF_CTL(PIPE_A));
MMIO_D(PF_WIN_SZ(PIPE_A));
MMIO_D(PF_WIN_POS(PIPE_A));
@@ -513,12 +514,12 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(GAMMA_MODE(PIPE_A));
MMIO_D(GAMMA_MODE(PIPE_B));
MMIO_D(GAMMA_MODE(PIPE_C));
- MMIO_D(TRANS_MULT(dev_priv, TRANSCODER_A));
- MMIO_D(TRANS_MULT(dev_priv, TRANSCODER_B));
- MMIO_D(TRANS_MULT(dev_priv, TRANSCODER_C));
- MMIO_D(HSW_TVIDEO_DIP_CTL(dev_priv, TRANSCODER_A));
- MMIO_D(HSW_TVIDEO_DIP_CTL(dev_priv, TRANSCODER_B));
- MMIO_D(HSW_TVIDEO_DIP_CTL(dev_priv, TRANSCODER_C));
+ MMIO_D(TRANS_MULT(display, TRANSCODER_A));
+ MMIO_D(TRANS_MULT(display, TRANSCODER_B));
+ MMIO_D(TRANS_MULT(display, TRANSCODER_C));
+ MMIO_D(HSW_TVIDEO_DIP_CTL(display, TRANSCODER_A));
+ MMIO_D(HSW_TVIDEO_DIP_CTL(display, TRANSCODER_B));
+ MMIO_D(HSW_TVIDEO_DIP_CTL(display, TRANSCODER_C));
MMIO_D(SFUSE_STRAP);
MMIO_D(SBI_ADDR);
MMIO_D(SBI_DATA);
@@ -1111,6 +1112,7 @@ static int iterate_skl_plus_mmio(struct intel_gvt_mmio_table_iter *iter)
static int iterate_bxt_mmio(struct intel_gvt_mmio_table_iter *iter)
{
struct drm_i915_private *dev_priv = iter->i915;
+ struct intel_display *display = dev_priv->display;
MMIO_F(_MMIO(0x80000), 0x3000);
MMIO_D(GEN7_SAMPLER_INSTDONE);
@@ -1242,9 +1244,9 @@ static int iterate_bxt_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(BXT_DSI_PLL_ENABLE);
MMIO_D(GEN9_CLKGATE_DIS_0);
MMIO_D(GEN9_CLKGATE_DIS_4);
- MMIO_D(HSW_TVIDEO_DIP_GCP(dev_priv, TRANSCODER_A));
- MMIO_D(HSW_TVIDEO_DIP_GCP(dev_priv, TRANSCODER_B));
- MMIO_D(HSW_TVIDEO_DIP_GCP(dev_priv, TRANSCODER_C));
+ MMIO_D(HSW_TVIDEO_DIP_GCP(display, TRANSCODER_A));
+ MMIO_D(HSW_TVIDEO_DIP_GCP(display, TRANSCODER_B));
+ MMIO_D(HSW_TVIDEO_DIP_GCP(display, TRANSCODER_C));
MMIO_D(RC6_CTX_BASE);
MMIO_D(GEN8_PUSHBUS_CONTROL);
MMIO_D(GEN8_PUSHBUS_ENABLE);
--
2.39.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 14/15] drm/i915/reg: separate VLV_DSPCLK_GATE_D from DSPCLK_GATE_D
2025-08-06 16:55 [PATCH 00/15] drm/i915: drop __to_intel_display() transitional macro Jani Nikula
` (12 preceding siblings ...)
2025-08-06 16:55 ` [PATCH 13/15] drm/i915/gvt: convert mmio table to struct intel_display Jani Nikula
@ 2025-08-06 16:55 ` Jani Nikula
2025-08-06 16:55 ` [PATCH 15/15] drm/i915/display: drop __to_intel_display() usage Jani Nikula
` (5 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Jani Nikula @ 2025-08-06 16:55 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
All the places that use DSPCLK_GATE_D are specific to certain platforms,
and the parametrization of it to support VLV/CHV MMIO display base isn't
really buying us anything. Add a separate macro for VLV_DSPCLK_GATE_D
and use it.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power_well.c | 2 +-
drivers/gpu/drm/i915/display/intel_gmbus.c | 2 +-
drivers/gpu/drm/i915/display/intel_overlay.c | 5 ++---
drivers/gpu/drm/i915/display/vlv_dsi.c | 4 ++--
drivers/gpu/drm/i915/i915_reg.h | 3 ++-
drivers/gpu/drm/i915/intel_clock_gating.c | 4 ++--
6 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 6efe5524cbbf..31c2a07bb188 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -1209,7 +1209,7 @@ static void vlv_init_display_clock_gating(struct intel_display *display)
* (and never recovering) in this case. intel_dsi_post_disable() will
* clear it when we turn off the display.
*/
- intel_de_rmw(display, DSPCLK_GATE_D(display),
+ intel_de_rmw(display, VLV_DSPCLK_GATE_D,
~DPOUNIT_CLOCK_GATE_DISABLE, VRHUNIT_CLOCK_GATE_DISABLE);
/*
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index 6a74805570e1..063335053d13 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -219,7 +219,7 @@ static void pnv_gmbus_clock_gating(struct intel_display *display,
bool enable)
{
/* When using bit bashing for I2C, this bit needs to be set to 1 */
- intel_de_rmw(display, DSPCLK_GATE_D(display),
+ intel_de_rmw(display, DSPCLK_GATE_D,
PNV_GMBUSUNIT_CLOCK_GATE_DISABLE,
!enable ? PNV_GMBUSUNIT_CLOCK_GATE_DISABLE : 0);
}
diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c
index 159a5f998ea0..272f9e7af4d4 100644
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -217,10 +217,9 @@ static void i830_overlay_clock_gating(struct intel_display *display,
/* WA_OVERLAY_CLKGATE:alm */
if (enable)
- intel_de_write(display, DSPCLK_GATE_D(display), 0);
+ intel_de_write(display, DSPCLK_GATE_D, 0);
else
- intel_de_write(display, DSPCLK_GATE_D(display),
- OVRUNIT_CLOCK_GATE_DISABLE);
+ intel_de_write(display, DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
/* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */
pci_bus_read_config_byte(pdev->bus,
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index 6d9f3312de7e..c9a53fde79c4 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -761,7 +761,7 @@ static void intel_dsi_pre_enable(struct intel_atomic_state *state,
if (display->platform.valleyview || display->platform.cherryview) {
/* Disable DPOunit clock gating, can stall pipe */
- intel_de_rmw(display, DSPCLK_GATE_D(display),
+ intel_de_rmw(display, VLV_DSPCLK_GATE_D,
0, DPOUNIT_CLOCK_GATE_DISABLE);
}
@@ -918,7 +918,7 @@ static void intel_dsi_post_disable(struct intel_atomic_state *state,
} else {
vlv_dsi_pll_disable(encoder);
- intel_de_rmw(display, DSPCLK_GATE_D(display),
+ intel_de_rmw(display, VLV_DSPCLK_GATE_D,
DPOUNIT_CLOCK_GATE_DISABLE, 0);
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 03b895897f60..b283b25d8368 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -613,7 +613,8 @@
#define DSTATE_GFX_CLOCK_GATING (1 << 1)
#define DSTATE_DOT_CLOCK_GATING (1 << 0)
-#define DSPCLK_GATE_D(__i915) _MMIO(DISPLAY_MMIO_BASE(__i915) + 0x6200)
+#define DSPCLK_GATE_D _MMIO(0x6200)
+#define VLV_DSPCLK_GATE_D _MMIO(VLV_DISPLAY_BASE + 0x6200)
# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index e501f4937510..467740969431 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -620,7 +620,7 @@ static void g4x_init_clock_gating(struct drm_i915_private *i915)
OVCUNIT_CLOCK_GATE_DISABLE;
if (IS_GM45(i915))
dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
- intel_uncore_write(&i915->uncore, DSPCLK_GATE_D(i915), dspclk_gate);
+ intel_uncore_write(&i915->uncore, DSPCLK_GATE_D, dspclk_gate);
g4x_disable_trickle_feed(i915);
}
@@ -631,7 +631,7 @@ static void i965gm_init_clock_gating(struct drm_i915_private *i915)
intel_uncore_write(uncore, RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
intel_uncore_write(uncore, RENCLK_GATE_D2, 0);
- intel_uncore_write(uncore, DSPCLK_GATE_D(i915), 0);
+ intel_uncore_write(uncore, DSPCLK_GATE_D, 0);
intel_uncore_write(uncore, RAMCLK_GATE_D, 0);
intel_uncore_write16(uncore, DEUC, 0);
intel_uncore_write(uncore,
--
2.39.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 15/15] drm/i915/display: drop __to_intel_display() usage
2025-08-06 16:55 [PATCH 00/15] drm/i915: drop __to_intel_display() transitional macro Jani Nikula
` (13 preceding siblings ...)
2025-08-06 16:55 ` [PATCH 14/15] drm/i915/reg: separate VLV_DSPCLK_GATE_D from DSPCLK_GATE_D Jani Nikula
@ 2025-08-06 16:55 ` Jani Nikula
2025-08-06 17:07 ` ✓ CI.KUnit: success for drm/i915: drop __to_intel_display() transitional macro Patchwork
` (4 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Jani Nikula @ 2025-08-06 16:55 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
All the places that use __to_intel_display() now get passed a struct
intel_display pointer, and the transitional adaptation macro has served
its purpose. Remove the macro.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../gpu/drm/i915/display/intel_display_conversion.c | 2 +-
.../gpu/drm/i915/display/intel_display_conversion.h | 12 ------------
drivers/gpu/drm/i915/display/intel_display_device.h | 7 +++----
drivers/gpu/drm/i915/display/intel_pch.h | 4 +---
4 files changed, 5 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_conversion.c b/drivers/gpu/drm/i915/display/intel_display_conversion.c
index 4d565935e2cc..d56065f22655 100644
--- a/drivers/gpu/drm/i915/display/intel_display_conversion.c
+++ b/drivers/gpu/drm/i915/display/intel_display_conversion.c
@@ -4,7 +4,7 @@
#include "i915_drv.h"
#include "intel_display_conversion.h"
-struct intel_display *__i915_to_display(struct drm_i915_private *i915)
+static struct intel_display *__i915_to_display(struct drm_i915_private *i915)
{
return i915->display;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_conversion.h b/drivers/gpu/drm/i915/display/intel_display_conversion.h
index 46c7208d42ba..d497bc58a73f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_conversion.h
+++ b/drivers/gpu/drm/i915/display/intel_display_conversion.h
@@ -9,20 +9,8 @@
#define __INTEL_DISPLAY_CONVERSION__
struct drm_device;
-struct drm_i915_private;
struct intel_display;
-struct intel_display *__i915_to_display(struct drm_i915_private *i915);
struct intel_display *__drm_to_display(struct drm_device *drm);
-/*
- * Transitional macro to optionally convert struct drm_i915_private * to struct
- * intel_display *, also accepting the latter.
- */
-#define __to_intel_display(p) \
- _Generic(p, \
- const struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(p)), \
- struct drm_i915_private *: __i915_to_display((struct drm_i915_private *)(p)), \
- const struct intel_display *: (p), \
- struct intel_display *: (p))
#endif /* __INTEL_DISPLAY_CONVERSION__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 4308822f0415..6e87b763fe7c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -9,7 +9,6 @@
#include <linux/bitops.h>
#include <linux/types.h>
-#include "intel_display_conversion.h"
#include "intel_display_limits.h"
struct drm_printer;
@@ -224,8 +223,8 @@ struct intel_display_platforms {
(IS_DISPLAY_VERx100((__display), (ipver), (ipver)) && \
IS_DISPLAY_STEP((__display), (from), (until)))
-#define DISPLAY_INFO(__display) (__to_intel_display(__display)->info.__device_info)
-#define DISPLAY_RUNTIME_INFO(__display) (&__to_intel_display(__display)->info.__runtime_info)
+#define DISPLAY_INFO(__display) ((__display)->info.__device_info)
+#define DISPLAY_RUNTIME_INFO(__display) (&(__display)->info.__runtime_info)
#define DISPLAY_VER(__display) (DISPLAY_RUNTIME_INFO(__display)->ip.ver)
#define DISPLAY_VERx100(__display) (DISPLAY_RUNTIME_INFO(__display)->ip.ver * 100 + \
@@ -236,7 +235,7 @@ struct intel_display_platforms {
#define INTEL_DISPLAY_STEP(__display) (DISPLAY_RUNTIME_INFO(__display)->step)
#define IS_DISPLAY_STEP(__display, since, until) \
- (drm_WARN_ON(__to_intel_display(__display)->drm, INTEL_DISPLAY_STEP(__display) == STEP_NONE), \
+ (drm_WARN_ON((__display)->drm, INTEL_DISPLAY_STEP(__display) == STEP_NONE), \
INTEL_DISPLAY_STEP(__display) >= (since) && INTEL_DISPLAY_STEP(__display) < (until))
#define ARLS_HOST_BRIDGE_PCI_ID1 0x7D1C
diff --git a/drivers/gpu/drm/i915/display/intel_pch.h b/drivers/gpu/drm/i915/display/intel_pch.h
index cf4dab1b98bf..19cac7412d0a 100644
--- a/drivers/gpu/drm/i915/display/intel_pch.h
+++ b/drivers/gpu/drm/i915/display/intel_pch.h
@@ -6,8 +6,6 @@
#ifndef __INTEL_PCH__
#define __INTEL_PCH__
-#include "intel_display_conversion.h"
-
struct intel_display;
/*
@@ -36,7 +34,7 @@ enum intel_pch {
PCH_LNL,
};
-#define INTEL_PCH_TYPE(_display) (__to_intel_display(_display)->pch_type)
+#define INTEL_PCH_TYPE(_display) ((_display)->pch_type)
#define HAS_PCH_DG2(display) (INTEL_PCH_TYPE(display) == PCH_DG2)
#define HAS_PCH_ADP(display) (INTEL_PCH_TYPE(display) == PCH_ADP)
#define HAS_PCH_DG1(display) (INTEL_PCH_TYPE(display) == PCH_DG1)
--
2.39.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* ✓ CI.KUnit: success for drm/i915: drop __to_intel_display() transitional macro
2025-08-06 16:55 [PATCH 00/15] drm/i915: drop __to_intel_display() transitional macro Jani Nikula
` (14 preceding siblings ...)
2025-08-06 16:55 ` [PATCH 15/15] drm/i915/display: drop __to_intel_display() usage Jani Nikula
@ 2025-08-06 17:07 ` Patchwork
2025-08-06 17:21 ` ✗ CI.checksparse: warning " Patchwork
` (3 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2025-08-06 17:07 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-xe
== Series Details ==
Series: drm/i915: drop __to_intel_display() transitional macro
URL : https://patchwork.freedesktop.org/series/152595/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[17:06:01] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:06:05] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[17:06:32] Starting KUnit Kernel (1/1)...
[17:06:32] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:06:32] ================== guc_buf (11 subtests) ===================
[17:06:32] [PASSED] test_smallest
[17:06:32] [PASSED] test_largest
[17:06:32] [PASSED] test_granular
[17:06:32] [PASSED] test_unique
[17:06:32] [PASSED] test_overlap
[17:06:32] [PASSED] test_reusable
[17:06:32] [PASSED] test_too_big
[17:06:32] [PASSED] test_flush
[17:06:32] [PASSED] test_lookup
[17:06:32] [PASSED] test_data
[17:06:32] [PASSED] test_class
[17:06:32] ===================== [PASSED] guc_buf =====================
[17:06:32] =================== guc_dbm (7 subtests) ===================
[17:06:32] [PASSED] test_empty
[17:06:32] [PASSED] test_default
[17:06:32] ======================== test_size ========================
[17:06:32] [PASSED] 4
[17:06:32] [PASSED] 8
[17:06:32] [PASSED] 32
[17:06:32] [PASSED] 256
[17:06:32] ==================== [PASSED] test_size ====================
[17:06:32] ======================= test_reuse ========================
[17:06:32] [PASSED] 4
[17:06:32] [PASSED] 8
[17:06:32] [PASSED] 32
[17:06:32] [PASSED] 256
[17:06:32] =================== [PASSED] test_reuse ====================
[17:06:32] =================== test_range_overlap ====================
[17:06:32] [PASSED] 4
[17:06:32] [PASSED] 8
[17:06:32] [PASSED] 32
[17:06:32] [PASSED] 256
[17:06:32] =============== [PASSED] test_range_overlap ================
[17:06:32] =================== test_range_compact ====================
[17:06:32] [PASSED] 4
[17:06:32] [PASSED] 8
[17:06:32] [PASSED] 32
[17:06:32] [PASSED] 256
[17:06:32] =============== [PASSED] test_range_compact ================
[17:06:32] ==================== test_range_spare =====================
[17:06:32] [PASSED] 4
[17:06:32] [PASSED] 8
[17:06:32] [PASSED] 32
[17:06:32] [PASSED] 256
[17:06:32] ================ [PASSED] test_range_spare =================
[17:06:32] ===================== [PASSED] guc_dbm =====================
[17:06:32] =================== guc_idm (6 subtests) ===================
[17:06:32] [PASSED] bad_init
[17:06:32] [PASSED] no_init
[17:06:32] [PASSED] init_fini
[17:06:32] [PASSED] check_used
[17:06:32] [PASSED] check_quota
[17:06:32] [PASSED] check_all
[17:06:32] ===================== [PASSED] guc_idm =====================
[17:06:32] ================== no_relay (3 subtests) ===================
[17:06:32] [PASSED] xe_drops_guc2pf_if_not_ready
[17:06:32] [PASSED] xe_drops_guc2vf_if_not_ready
[17:06:32] [PASSED] xe_rejects_send_if_not_ready
[17:06:32] ==================== [PASSED] no_relay =====================
[17:06:32] ================== pf_relay (14 subtests) ==================
[17:06:32] [PASSED] pf_rejects_guc2pf_too_short
[17:06:32] [PASSED] pf_rejects_guc2pf_too_long
[17:06:32] [PASSED] pf_rejects_guc2pf_no_payload
[17:06:32] [PASSED] pf_fails_no_payload
[17:06:32] [PASSED] pf_fails_bad_origin
[17:06:32] [PASSED] pf_fails_bad_type
[17:06:32] [PASSED] pf_txn_reports_error
[17:06:32] [PASSED] pf_txn_sends_pf2guc
[17:06:32] [PASSED] pf_sends_pf2guc
[17:06:32] [SKIPPED] pf_loopback_nop
[17:06:32] [SKIPPED] pf_loopback_echo
[17:06:32] [SKIPPED] pf_loopback_fail
[17:06:32] [SKIPPED] pf_loopback_busy
[17:06:32] [SKIPPED] pf_loopback_retry
[17:06:32] ==================== [PASSED] pf_relay =====================
[17:06:32] ================== vf_relay (3 subtests) ===================
[17:06:32] [PASSED] vf_rejects_guc2vf_too_short
[17:06:32] [PASSED] vf_rejects_guc2vf_too_long
[17:06:32] [PASSED] vf_rejects_guc2vf_no_payload
[17:06:32] ==================== [PASSED] vf_relay =====================
[17:06:32] ===================== lmtt (1 subtest) =====================
[17:06:32] ======================== test_ops =========================
[17:06:32] [PASSED] 2-level
[17:06:32] [PASSED] multi-level
[17:06:32] ==================== [PASSED] test_ops =====================
[17:06:32] ====================== [PASSED] lmtt =======================
[17:06:32] ================= pf_service (11 subtests) =================
[17:06:32] [PASSED] pf_negotiate_any
[17:06:32] [PASSED] pf_negotiate_base_match
[17:06:32] [PASSED] pf_negotiate_base_newer
[17:06:32] [PASSED] pf_negotiate_base_next
[17:06:32] [SKIPPED] pf_negotiate_base_older
[17:06:32] [PASSED] pf_negotiate_base_prev
[17:06:32] [PASSED] pf_negotiate_latest_match
[17:06:32] [PASSED] pf_negotiate_latest_newer
[17:06:32] [PASSED] pf_negotiate_latest_next
[17:06:32] [SKIPPED] pf_negotiate_latest_older
[17:06:32] [SKIPPED] pf_negotiate_latest_prev
[17:06:32] =================== [PASSED] pf_service ====================
[17:06:32] =================== xe_mocs (2 subtests) ===================
[17:06:32] ================ xe_live_mocs_kernel_kunit ================
[17:06:32] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[17:06:32] ================ xe_live_mocs_reset_kunit =================
[17:06:32] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[17:06:32] ==================== [SKIPPED] xe_mocs =====================
[17:06:32] ================= xe_migrate (2 subtests) ==================
[17:06:32] ================= xe_migrate_sanity_kunit =================
[17:06:32] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[17:06:32] ================== xe_validate_ccs_kunit ==================
[17:06:32] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[17:06:32] =================== [SKIPPED] xe_migrate ===================
[17:06:32] ================== xe_dma_buf (1 subtest) ==================
[17:06:32] ==================== xe_dma_buf_kunit =====================
[17:06:32] ================ [SKIPPED] xe_dma_buf_kunit ================
[17:06:32] =================== [SKIPPED] xe_dma_buf ===================
[17:06:32] ================= xe_bo_shrink (1 subtest) =================
[17:06:32] =================== xe_bo_shrink_kunit ====================
[17:06:32] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[17:06:32] ================== [SKIPPED] xe_bo_shrink ==================
[17:06:32] ==================== xe_bo (2 subtests) ====================
[17:06:32] ================== xe_ccs_migrate_kunit ===================
[17:06:32] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[17:06:32] ==================== xe_bo_evict_kunit ====================
[17:06:32] =============== [SKIPPED] xe_bo_evict_kunit ================
[17:06:32] ===================== [SKIPPED] xe_bo ======================
[17:06:32] ==================== args (11 subtests) ====================
[17:06:32] [PASSED] count_args_test
[17:06:32] [PASSED] call_args_example
[17:06:32] [PASSED] call_args_test
[17:06:32] [PASSED] drop_first_arg_example
[17:06:32] [PASSED] drop_first_arg_test
[17:06:32] [PASSED] first_arg_example
[17:06:32] [PASSED] first_arg_test
[17:06:32] [PASSED] last_arg_example
[17:06:32] [PASSED] last_arg_test
[17:06:32] [PASSED] pick_arg_example
[17:06:32] [PASSED] sep_comma_example
[17:06:32] ====================== [PASSED] args =======================
[17:06:32] =================== xe_pci (3 subtests) ====================
[17:06:32] ==================== check_graphics_ip ====================
[17:06:32] [PASSED] 12.70 Xe_LPG
[17:06:32] [PASSED] 12.71 Xe_LPG
[17:06:32] [PASSED] 12.74 Xe_LPG+
[17:06:32] [PASSED] 20.01 Xe2_HPG
[17:06:32] [PASSED] 20.02 Xe2_HPG
[17:06:32] [PASSED] 20.04 Xe2_LPG
[17:06:32] [PASSED] 30.00 Xe3_LPG
[17:06:32] [PASSED] 30.01 Xe3_LPG
[17:06:32] [PASSED] 30.03 Xe3_LPG
[17:06:32] ================ [PASSED] check_graphics_ip ================
[17:06:32] ===================== check_media_ip ======================
[17:06:32] [PASSED] 13.00 Xe_LPM+
[17:06:32] [PASSED] 13.01 Xe2_HPM
[17:06:32] [PASSED] 20.00 Xe2_LPM
[17:06:32] [PASSED] 30.00 Xe3_LPM
[17:06:32] [PASSED] 30.02 Xe3_LPM
[17:06:32] ================= [PASSED] check_media_ip ==================
[17:06:32] ================= check_platform_gt_count =================
[17:06:32] [PASSED] 0x9A60 (TIGERLAKE)
[17:06:32] [PASSED] 0x9A68 (TIGERLAKE)
[17:06:32] [PASSED] 0x9A70 (TIGERLAKE)
[17:06:32] [PASSED] 0x9A40 (TIGERLAKE)
[17:06:32] [PASSED] 0x9A49 (TIGERLAKE)
[17:06:32] [PASSED] 0x9A59 (TIGERLAKE)
[17:06:32] [PASSED] 0x9A78 (TIGERLAKE)
[17:06:32] [PASSED] 0x9AC0 (TIGERLAKE)
[17:06:32] [PASSED] 0x9AC9 (TIGERLAKE)
[17:06:32] [PASSED] 0x9AD9 (TIGERLAKE)
[17:06:32] [PASSED] 0x9AF8 (TIGERLAKE)
[17:06:32] [PASSED] 0x4C80 (ROCKETLAKE)
[17:06:32] [PASSED] 0x4C8A (ROCKETLAKE)
[17:06:32] [PASSED] 0x4C8B (ROCKETLAKE)
[17:06:32] [PASSED] 0x4C8C (ROCKETLAKE)
[17:06:32] [PASSED] 0x4C90 (ROCKETLAKE)
[17:06:32] [PASSED] 0x4C9A (ROCKETLAKE)
[17:06:32] [PASSED] 0x4680 (ALDERLAKE_S)
[17:06:32] [PASSED] 0x4682 (ALDERLAKE_S)
[17:06:32] [PASSED] 0x4688 (ALDERLAKE_S)
[17:06:32] [PASSED] 0x468A (ALDERLAKE_S)
[17:06:32] [PASSED] 0x468B (ALDERLAKE_S)
[17:06:32] [PASSED] 0x4690 (ALDERLAKE_S)
[17:06:32] [PASSED] 0x4692 (ALDERLAKE_S)
[17:06:32] [PASSED] 0x4693 (ALDERLAKE_S)
[17:06:32] [PASSED] 0x46A0 (ALDERLAKE_P)
[17:06:32] [PASSED] 0x46A1 (ALDERLAKE_P)
[17:06:32] [PASSED] 0x46A2 (ALDERLAKE_P)
[17:06:32] [PASSED] 0x46A3 (ALDERLAKE_P)
[17:06:32] [PASSED] 0x46A6 (ALDERLAKE_P)
[17:06:32] [PASSED] 0x46A8 (ALDERLAKE_P)
[17:06:32] [PASSED] 0x46AA (ALDERLAKE_P)
[17:06:32] [PASSED] 0x462A (ALDERLAKE_P)
[17:06:32] [PASSED] 0x4626 (ALDERLAKE_P)
[17:06:32] [PASSED] 0x4628 (ALDERLAKE_P)
[17:06:32] [PASSED] 0x46B0 (ALDERLAKE_P)
[17:06:32] [PASSED] 0x46B1 (ALDERLAKE_P)
[17:06:32] [PASSED] 0x46B2 (ALDERLAKE_P)
[17:06:32] [PASSED] 0x46B3 (ALDERLAKE_P)
[17:06:32] [PASSED] 0x46C0 (ALDERLAKE_P)
[17:06:32] [PASSED] 0x46C1 (ALDERLAKE_P)
[17:06:32] [PASSED] 0x46C2 (ALDERLAKE_P)
[17:06:32] [PASSED] 0x46C3 (ALDERLAKE_P)
[17:06:32] [PASSED] 0x46D0 (ALDERLAKE_N)
[17:06:32] [PASSED] 0x46D1 (ALDERLAKE_N)
[17:06:32] [PASSED] 0x46D2 (ALDERLAKE_N)
[17:06:32] [PASSED] 0x46D3 (ALDERLAKE_N)
[17:06:32] [PASSED] 0x46D4 (ALDERLAKE_N)
[17:06:32] [PASSED] 0xA721 (ALDERLAKE_P)
[17:06:32] [PASSED] 0xA7A1 (ALDERLAKE_P)
[17:06:32] [PASSED] 0xA7A9 (ALDERLAKE_P)
[17:06:32] [PASSED] 0xA7AC (ALDERLAKE_P)
[17:06:32] [PASSED] 0xA7AD (ALDERLAKE_P)
[17:06:32] [PASSED] 0xA720 (ALDERLAKE_P)
[17:06:32] [PASSED] 0xA7A0 (ALDERLAKE_P)
[17:06:32] [PASSED] 0xA7A8 (ALDERLAKE_P)
[17:06:32] [PASSED] 0xA7AA (ALDERLAKE_P)
[17:06:32] [PASSED] 0xA7AB (ALDERLAKE_P)
[17:06:32] [PASSED] 0xA780 (ALDERLAKE_S)
[17:06:32] [PASSED] 0xA781 (ALDERLAKE_S)
[17:06:32] [PASSED] 0xA782 (ALDERLAKE_S)
[17:06:32] [PASSED] 0xA783 (ALDERLAKE_S)
[17:06:32] [PASSED] 0xA788 (ALDERLAKE_S)
[17:06:32] [PASSED] 0xA789 (ALDERLAKE_S)
[17:06:32] [PASSED] 0xA78A (ALDERLAKE_S)
[17:06:32] [PASSED] 0xA78B (ALDERLAKE_S)
[17:06:32] [PASSED] 0x4905 (DG1)
[17:06:32] [PASSED] 0x4906 (DG1)
[17:06:32] [PASSED] 0x4907 (DG1)
[17:06:32] [PASSED] 0x4908 (DG1)
[17:06:32] [PASSED] 0x4909 (DG1)
[17:06:32] [PASSED] 0x56C0 (DG2)
[17:06:32] [PASSED] 0x56C2 (DG2)
[17:06:32] [PASSED] 0x56C1 (DG2)
[17:06:32] [PASSED] 0x7D51 (METEORLAKE)
[17:06:32] [PASSED] 0x7DD1 (METEORLAKE)
[17:06:32] [PASSED] 0x7D41 (METEORLAKE)
[17:06:32] [PASSED] 0x7D67 (METEORLAKE)
[17:06:32] [PASSED] 0xB640 (METEORLAKE)
[17:06:32] [PASSED] 0x56A0 (DG2)
[17:06:32] [PASSED] 0x56A1 (DG2)
[17:06:32] [PASSED] 0x56A2 (DG2)
[17:06:32] [PASSED] 0x56BE (DG2)
[17:06:32] [PASSED] 0x56BF (DG2)
[17:06:32] [PASSED] 0x5690 (DG2)
[17:06:32] [PASSED] 0x5691 (DG2)
[17:06:32] [PASSED] 0x5692 (DG2)
[17:06:32] [PASSED] 0x56A5 (DG2)
[17:06:32] [PASSED] 0x56A6 (DG2)
[17:06:32] [PASSED] 0x56B0 (DG2)
[17:06:32] [PASSED] 0x56B1 (DG2)
[17:06:32] [PASSED] 0x56BA (DG2)
[17:06:32] [PASSED] 0x56BB (DG2)
[17:06:32] [PASSED] 0x56BC (DG2)
[17:06:32] [PASSED] 0x56BD (DG2)
[17:06:32] [PASSED] 0x5693 (DG2)
[17:06:32] [PASSED] 0x5694 (DG2)
[17:06:32] [PASSED] 0x5695 (DG2)
[17:06:32] [PASSED] 0x56A3 (DG2)
[17:06:32] [PASSED] 0x56A4 (DG2)
[17:06:32] [PASSED] 0x56B2 (DG2)
[17:06:32] [PASSED] 0x56B3 (DG2)
[17:06:32] [PASSED] 0x5696 (DG2)
[17:06:32] [PASSED] 0x5697 (DG2)
[17:06:32] [PASSED] 0xB69 (PVC)
[17:06:32] [PASSED] 0xB6E (PVC)
[17:06:32] [PASSED] 0xBD4 (PVC)
[17:06:32] [PASSED] 0xBD5 (PVC)
[17:06:32] [PASSED] 0xBD6 (PVC)
[17:06:32] [PASSED] 0xBD7 (PVC)
[17:06:32] [PASSED] 0xBD8 (PVC)
[17:06:32] [PASSED] 0xBD9 (PVC)
[17:06:32] [PASSED] 0xBDA (PVC)
[17:06:32] [PASSED] 0xBDB (PVC)
[17:06:32] [PASSED] 0xBE0 (PVC)
[17:06:32] [PASSED] 0xBE1 (PVC)
[17:06:32] [PASSED] 0xBE5 (PVC)
[17:06:32] [PASSED] 0x7D40 (METEORLAKE)
[17:06:32] [PASSED] 0x7D45 (METEORLAKE)
[17:06:32] [PASSED] 0x7D55 (METEORLAKE)
[17:06:32] [PASSED] 0x7D60 (METEORLAKE)
[17:06:32] [PASSED] 0x7DD5 (METEORLAKE)
[17:06:32] [PASSED] 0x6420 (LUNARLAKE)
[17:06:32] [PASSED] 0x64A0 (LUNARLAKE)
[17:06:32] [PASSED] 0x64B0 (LUNARLAKE)
[17:06:32] [PASSED] 0xE202 (BATTLEMAGE)
[17:06:32] [PASSED] 0xE209 (BATTLEMAGE)
[17:06:32] [PASSED] 0xE20B (BATTLEMAGE)
[17:06:32] [PASSED] 0xE20C (BATTLEMAGE)
[17:06:32] [PASSED] 0xE20D (BATTLEMAGE)
[17:06:32] [PASSED] 0xE210 (BATTLEMAGE)
[17:06:32] [PASSED] 0xE211 (BATTLEMAGE)
[17:06:32] [PASSED] 0xE212 (BATTLEMAGE)
[17:06:32] [PASSED] 0xE216 (BATTLEMAGE)
[17:06:32] [PASSED] 0xE220 (BATTLEMAGE)
[17:06:32] [PASSED] 0xE221 (BATTLEMAGE)
[17:06:32] [PASSED] 0xE222 (BATTLEMAGE)
[17:06:32] [PASSED] 0xE223 (BATTLEMAGE)
[17:06:32] [PASSED] 0xB080 (PANTHERLAKE)
[17:06:32] [PASSED] 0xB081 (PANTHERLAKE)
[17:06:32] [PASSED] 0xB082 (PANTHERLAKE)
[17:06:32] [PASSED] 0xB083 (PANTHERLAKE)
[17:06:32] [PASSED] 0xB084 (PANTHERLAKE)
[17:06:32] [PASSED] 0xB085 (PANTHERLAKE)
[17:06:32] [PASSED] 0xB086 (PANTHERLAKE)
[17:06:32] [PASSED] 0xB087 (PANTHERLAKE)
[17:06:32] [PASSED] 0xB08F (PANTHERLAKE)
[17:06:32] [PASSED] 0xB090 (PANTHERLAKE)
[17:06:32] [PASSED] 0xB0A0 (PANTHERLAKE)
[17:06:32] [PASSED] 0xB0B0 (PANTHERLAKE)
[17:06:32] [PASSED] 0xFD80 (PANTHERLAKE)
[17:06:32] [PASSED] 0xFD81 (PANTHERLAKE)
[17:06:32] ============= [PASSED] check_platform_gt_count =============
[17:06:32] ===================== [PASSED] xe_pci ======================
[17:06:32] =================== xe_rtp (2 subtests) ====================
[17:06:32] =============== xe_rtp_process_to_sr_tests ================
[17:06:32] [PASSED] coalesce-same-reg
[17:06:32] [PASSED] no-match-no-add
[17:06:32] [PASSED] match-or
[17:06:32] [PASSED] match-or-xfail
[17:06:32] [PASSED] no-match-no-add-multiple-rules
[17:06:32] [PASSED] two-regs-two-entries
[17:06:32] [PASSED] clr-one-set-other
[17:06:32] [PASSED] set-field
[17:06:32] [PASSED] conflict-duplicate
[17:06:32] [PASSED] conflict-not-disjoint
[17:06:32] [PASSED] conflict-reg-type
[17:06:32] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[17:06:32] ================== xe_rtp_process_tests ===================
[17:06:32] [PASSED] active1
[17:06:32] [PASSED] active2
[17:06:32] [PASSED] active-inactive
[17:06:32] [PASSED] inactive-active
[17:06:32] [PASSED] inactive-1st_or_active-inactive
[17:06:32] [PASSED] inactive-2nd_or_active-inactive
[17:06:32] [PASSED] inactive-last_or_active-inactive
[17:06:32] [PASSED] inactive-no_or_active-inactive
[17:06:32] ============== [PASSED] xe_rtp_process_tests ===============
[17:06:32] ===================== [PASSED] xe_rtp ======================
[17:06:32] ==================== xe_wa (1 subtest) =====================
[17:06:32] ======================== xe_wa_gt =========================
[17:06:32] [PASSED] TIGERLAKE (B0)
[17:06:32] [PASSED] DG1 (A0)
[17:06:32] [PASSED] DG1 (B0)
[17:06:32] [PASSED] ALDERLAKE_S (A0)
[17:06:32] [PASSED] ALDERLAKE_S (B0)
[17:06:32] [PASSED] ALDERLAKE_S (C0)
[17:06:32] [PASSED] ALDERLAKE_S (D0)
[17:06:32] [PASSED] ALDERLAKE_P (A0)
[17:06:32] [PASSED] ALDERLAKE_P (B0)
[17:06:32] [PASSED] ALDERLAKE_P (C0)
[17:06:32] [PASSED] ALDERLAKE_S_RPLS (D0)
[17:06:32] [PASSED] ALDERLAKE_P_RPLU (E0)
[17:06:32] [PASSED] DG2_G10 (C0)
[17:06:32] [PASSED] DG2_G11 (B1)
[17:06:32] [PASSED] DG2_G12 (A1)
[17:06:32] [PASSED] METEORLAKE (g:A0, m:A0)
[17:06:32] [PASSED] METEORLAKE (g:A0, m:A0)
[17:06:32] [PASSED] METEORLAKE (g:A0, m:A0)
[17:06:32] [PASSED] LUNARLAKE (g:A0, m:A0)
[17:06:32] [PASSED] LUNARLAKE (g:B0, m:A0)
stty: 'standard input': Inappropriate ioctl for device
[17:06:32] [PASSED] BATTLEMAGE (g:A0, m:A1)
[17:06:32] ==================== [PASSED] xe_wa_gt =====================
[17:06:32] ====================== [PASSED] xe_wa ======================
[17:06:32] ============================================================
[17:06:32] Testing complete. Ran 297 tests: passed: 281, skipped: 16
[17:06:33] Elapsed time: 31.648s total, 4.194s configuring, 27.087s building, 0.312s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[17:06:33] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:06:34] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[17:06:56] Starting KUnit Kernel (1/1)...
[17:06:56] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:06:56] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[17:06:56] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[17:06:56] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[17:06:56] =========== drm_validate_clone_mode (2 subtests) ===========
[17:06:56] ============== drm_test_check_in_clone_mode ===============
[17:06:56] [PASSED] in_clone_mode
[17:06:56] [PASSED] not_in_clone_mode
[17:06:56] ========== [PASSED] drm_test_check_in_clone_mode ===========
[17:06:56] =============== drm_test_check_valid_clones ===============
[17:06:56] [PASSED] not_in_clone_mode
[17:06:56] [PASSED] valid_clone
[17:06:56] [PASSED] invalid_clone
[17:06:56] =========== [PASSED] drm_test_check_valid_clones ===========
[17:06:56] ============= [PASSED] drm_validate_clone_mode =============
[17:06:56] ============= drm_validate_modeset (1 subtest) =============
[17:06:56] [PASSED] drm_test_check_connector_changed_modeset
[17:06:56] ============== [PASSED] drm_validate_modeset ===============
[17:06:56] ====== drm_test_bridge_get_current_state (2 subtests) ======
[17:06:56] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[17:06:56] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[17:06:56] ======== [PASSED] drm_test_bridge_get_current_state ========
[17:06:56] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[17:06:56] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[17:06:56] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[17:06:56] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[17:06:56] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[17:06:56] ============== drm_bridge_alloc (2 subtests) ===============
[17:06:56] [PASSED] drm_test_drm_bridge_alloc_basic
[17:06:56] [PASSED] drm_test_drm_bridge_alloc_get_put
[17:06:56] ================ [PASSED] drm_bridge_alloc =================
[17:06:56] ================== drm_buddy (7 subtests) ==================
[17:06:56] [PASSED] drm_test_buddy_alloc_limit
[17:06:56] [PASSED] drm_test_buddy_alloc_optimistic
[17:06:56] [PASSED] drm_test_buddy_alloc_pessimistic
[17:06:56] [PASSED] drm_test_buddy_alloc_pathological
[17:06:56] [PASSED] drm_test_buddy_alloc_contiguous
[17:06:56] [PASSED] drm_test_buddy_alloc_clear
[17:06:56] [PASSED] drm_test_buddy_alloc_range_bias
[17:06:56] ==================== [PASSED] drm_buddy ====================
[17:06:56] ============= drm_cmdline_parser (40 subtests) =============
[17:06:56] [PASSED] drm_test_cmdline_force_d_only
[17:06:56] [PASSED] drm_test_cmdline_force_D_only_dvi
[17:06:56] [PASSED] drm_test_cmdline_force_D_only_hdmi
[17:06:56] [PASSED] drm_test_cmdline_force_D_only_not_digital
[17:06:56] [PASSED] drm_test_cmdline_force_e_only
[17:06:56] [PASSED] drm_test_cmdline_res
[17:06:56] [PASSED] drm_test_cmdline_res_vesa
[17:06:56] [PASSED] drm_test_cmdline_res_vesa_rblank
[17:06:56] [PASSED] drm_test_cmdline_res_rblank
[17:06:56] [PASSED] drm_test_cmdline_res_bpp
[17:06:56] [PASSED] drm_test_cmdline_res_refresh
[17:06:56] [PASSED] drm_test_cmdline_res_bpp_refresh
[17:06:56] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[17:06:56] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[17:06:56] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[17:06:56] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[17:06:56] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[17:06:56] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[17:06:56] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[17:06:56] [PASSED] drm_test_cmdline_res_margins_force_on
[17:06:56] [PASSED] drm_test_cmdline_res_vesa_margins
[17:06:56] [PASSED] drm_test_cmdline_name
[17:06:56] [PASSED] drm_test_cmdline_name_bpp
[17:06:56] [PASSED] drm_test_cmdline_name_option
[17:06:56] [PASSED] drm_test_cmdline_name_bpp_option
[17:06:56] [PASSED] drm_test_cmdline_rotate_0
[17:06:56] [PASSED] drm_test_cmdline_rotate_90
[17:06:56] [PASSED] drm_test_cmdline_rotate_180
[17:06:56] [PASSED] drm_test_cmdline_rotate_270
[17:06:56] [PASSED] drm_test_cmdline_hmirror
[17:06:56] [PASSED] drm_test_cmdline_vmirror
[17:06:56] [PASSED] drm_test_cmdline_margin_options
[17:06:56] [PASSED] drm_test_cmdline_multiple_options
[17:06:56] [PASSED] drm_test_cmdline_bpp_extra_and_option
[17:06:56] [PASSED] drm_test_cmdline_extra_and_option
[17:06:56] [PASSED] drm_test_cmdline_freestanding_options
[17:06:56] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[17:06:56] [PASSED] drm_test_cmdline_panel_orientation
[17:06:56] ================ drm_test_cmdline_invalid =================
[17:06:56] [PASSED] margin_only
[17:06:56] [PASSED] interlace_only
[17:06:56] [PASSED] res_missing_x
[17:06:56] [PASSED] res_missing_y
[17:06:56] [PASSED] res_bad_y
[17:06:56] [PASSED] res_missing_y_bpp
[17:06:56] [PASSED] res_bad_bpp
[17:06:56] [PASSED] res_bad_refresh
[17:06:56] [PASSED] res_bpp_refresh_force_on_off
[17:06:56] [PASSED] res_invalid_mode
[17:06:56] [PASSED] res_bpp_wrong_place_mode
[17:06:56] [PASSED] name_bpp_refresh
[17:06:56] [PASSED] name_refresh
[17:06:56] [PASSED] name_refresh_wrong_mode
[17:06:56] [PASSED] name_refresh_invalid_mode
[17:06:56] [PASSED] rotate_multiple
[17:06:56] [PASSED] rotate_invalid_val
[17:06:56] [PASSED] rotate_truncated
[17:06:56] [PASSED] invalid_option
[17:06:56] [PASSED] invalid_tv_option
[17:06:56] [PASSED] truncated_tv_option
[17:06:56] ============ [PASSED] drm_test_cmdline_invalid =============
[17:06:56] =============== drm_test_cmdline_tv_options ===============
[17:06:56] [PASSED] NTSC
[17:06:56] [PASSED] NTSC_443
[17:06:56] [PASSED] NTSC_J
[17:06:56] [PASSED] PAL
[17:06:56] [PASSED] PAL_M
[17:06:56] [PASSED] PAL_N
[17:06:56] [PASSED] SECAM
[17:06:56] [PASSED] MONO_525
[17:06:56] [PASSED] MONO_625
[17:06:56] =========== [PASSED] drm_test_cmdline_tv_options ===========
[17:06:56] =============== [PASSED] drm_cmdline_parser ================
[17:06:56] ========== drmm_connector_hdmi_init (20 subtests) ==========
[17:06:56] [PASSED] drm_test_connector_hdmi_init_valid
[17:06:56] [PASSED] drm_test_connector_hdmi_init_bpc_8
[17:06:56] [PASSED] drm_test_connector_hdmi_init_bpc_10
[17:06:56] [PASSED] drm_test_connector_hdmi_init_bpc_12
[17:06:56] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[17:06:56] [PASSED] drm_test_connector_hdmi_init_bpc_null
[17:06:56] [PASSED] drm_test_connector_hdmi_init_formats_empty
[17:06:56] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[17:06:56] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[17:06:56] [PASSED] supported_formats=0x9 yuv420_allowed=1
[17:06:56] [PASSED] supported_formats=0x9 yuv420_allowed=0
[17:06:56] [PASSED] supported_formats=0x3 yuv420_allowed=1
[17:06:56] [PASSED] supported_formats=0x3 yuv420_allowed=0
[17:06:56] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[17:06:56] [PASSED] drm_test_connector_hdmi_init_null_ddc
[17:06:56] [PASSED] drm_test_connector_hdmi_init_null_product
[17:06:56] [PASSED] drm_test_connector_hdmi_init_null_vendor
[17:06:56] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[17:06:56] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[17:06:56] [PASSED] drm_test_connector_hdmi_init_product_valid
[17:06:56] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[17:06:56] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[17:06:56] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[17:06:56] ========= drm_test_connector_hdmi_init_type_valid =========
[17:06:56] [PASSED] HDMI-A
[17:06:56] [PASSED] HDMI-B
[17:06:56] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[17:06:56] ======== drm_test_connector_hdmi_init_type_invalid ========
[17:06:56] [PASSED] Unknown
[17:06:56] [PASSED] VGA
[17:06:56] [PASSED] DVI-I
[17:06:56] [PASSED] DVI-D
[17:06:56] [PASSED] DVI-A
[17:06:56] [PASSED] Composite
[17:06:56] [PASSED] SVIDEO
[17:06:56] [PASSED] LVDS
[17:06:56] [PASSED] Component
[17:06:56] [PASSED] DIN
[17:06:56] [PASSED] DP
[17:06:56] [PASSED] TV
[17:06:56] [PASSED] eDP
[17:06:56] [PASSED] Virtual
[17:06:56] [PASSED] DSI
[17:06:56] [PASSED] DPI
[17:06:56] [PASSED] Writeback
[17:06:56] [PASSED] SPI
[17:06:56] [PASSED] USB
[17:06:56] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[17:06:56] ============ [PASSED] drmm_connector_hdmi_init =============
[17:06:56] ============= drmm_connector_init (3 subtests) =============
[17:06:56] [PASSED] drm_test_drmm_connector_init
[17:06:56] [PASSED] drm_test_drmm_connector_init_null_ddc
[17:06:56] ========= drm_test_drmm_connector_init_type_valid =========
[17:06:56] [PASSED] Unknown
[17:06:56] [PASSED] VGA
[17:06:56] [PASSED] DVI-I
[17:06:56] [PASSED] DVI-D
[17:06:56] [PASSED] DVI-A
[17:06:56] [PASSED] Composite
[17:06:56] [PASSED] SVIDEO
[17:06:56] [PASSED] LVDS
[17:06:56] [PASSED] Component
[17:06:56] [PASSED] DIN
[17:06:56] [PASSED] DP
[17:06:56] [PASSED] HDMI-A
[17:06:56] [PASSED] HDMI-B
[17:06:56] [PASSED] TV
[17:06:56] [PASSED] eDP
[17:06:56] [PASSED] Virtual
[17:06:56] [PASSED] DSI
[17:06:56] [PASSED] DPI
[17:06:56] [PASSED] Writeback
[17:06:56] [PASSED] SPI
[17:06:56] [PASSED] USB
[17:06:56] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[17:06:56] =============== [PASSED] drmm_connector_init ===============
[17:06:56] ========= drm_connector_dynamic_init (6 subtests) ==========
[17:06:56] [PASSED] drm_test_drm_connector_dynamic_init
[17:06:56] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[17:06:56] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[17:06:56] [PASSED] drm_test_drm_connector_dynamic_init_properties
[17:06:56] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[17:06:56] [PASSED] Unknown
[17:06:56] [PASSED] VGA
[17:06:56] [PASSED] DVI-I
[17:06:56] [PASSED] DVI-D
[17:06:56] [PASSED] DVI-A
[17:06:56] [PASSED] Composite
[17:06:56] [PASSED] SVIDEO
[17:06:56] [PASSED] LVDS
[17:06:56] [PASSED] Component
[17:06:56] [PASSED] DIN
[17:06:56] [PASSED] DP
[17:06:56] [PASSED] HDMI-A
[17:06:56] [PASSED] HDMI-B
[17:06:56] [PASSED] TV
[17:06:56] [PASSED] eDP
[17:06:56] [PASSED] Virtual
[17:06:56] [PASSED] DSI
[17:06:56] [PASSED] DPI
[17:06:56] [PASSED] Writeback
[17:06:56] [PASSED] SPI
[17:06:56] [PASSED] USB
[17:06:56] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[17:06:56] ======== drm_test_drm_connector_dynamic_init_name =========
[17:06:56] [PASSED] Unknown
[17:06:56] [PASSED] VGA
[17:06:56] [PASSED] DVI-I
[17:06:56] [PASSED] DVI-D
[17:06:56] [PASSED] DVI-A
[17:06:56] [PASSED] Composite
[17:06:56] [PASSED] SVIDEO
[17:06:56] [PASSED] LVDS
[17:06:56] [PASSED] Component
[17:06:56] [PASSED] DIN
[17:06:56] [PASSED] DP
[17:06:56] [PASSED] HDMI-A
[17:06:56] [PASSED] HDMI-B
[17:06:56] [PASSED] TV
[17:06:56] [PASSED] eDP
[17:06:56] [PASSED] Virtual
[17:06:56] [PASSED] DSI
[17:06:56] [PASSED] DPI
[17:06:56] [PASSED] Writeback
[17:06:56] [PASSED] SPI
[17:06:56] [PASSED] USB
[17:06:56] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[17:06:56] =========== [PASSED] drm_connector_dynamic_init ============
[17:06:56] ==== drm_connector_dynamic_register_early (4 subtests) =====
[17:06:56] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[17:06:56] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[17:06:56] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[17:06:56] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[17:06:56] ====== [PASSED] drm_connector_dynamic_register_early =======
[17:06:56] ======= drm_connector_dynamic_register (7 subtests) ========
[17:06:56] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[17:06:56] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[17:06:56] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[17:06:56] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[17:06:56] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[17:06:56] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[17:06:56] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[17:06:56] ========= [PASSED] drm_connector_dynamic_register ==========
[17:06:56] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[17:06:56] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[17:06:56] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[17:06:56] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[17:06:56] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[17:06:56] ========== drm_test_get_tv_mode_from_name_valid ===========
[17:06:56] [PASSED] NTSC
[17:06:56] [PASSED] NTSC-443
[17:06:56] [PASSED] NTSC-J
[17:06:56] [PASSED] PAL
[17:06:56] [PASSED] PAL-M
[17:06:56] [PASSED] PAL-N
[17:06:56] [PASSED] SECAM
[17:06:56] [PASSED] Mono
[17:06:56] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[17:06:56] [PASSED] drm_test_get_tv_mode_from_name_truncated
[17:06:56] ============ [PASSED] drm_get_tv_mode_from_name ============
[17:06:56] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[17:06:56] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[17:06:56] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[17:06:56] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[17:06:56] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[17:06:56] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[17:06:56] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[17:06:56] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[17:06:56] [PASSED] VIC 96
[17:06:56] [PASSED] VIC 97
[17:06:56] [PASSED] VIC 101
[17:06:56] [PASSED] VIC 102
[17:06:56] [PASSED] VIC 106
[17:06:56] [PASSED] VIC 107
[17:06:56] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[17:06:56] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[17:06:56] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[17:06:56] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[17:06:56] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[17:06:56] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[17:06:56] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[17:06:56] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[17:06:56] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[17:06:56] [PASSED] Automatic
[17:06:56] [PASSED] Full
[17:06:56] [PASSED] Limited 16:235
[17:06:56] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[17:06:56] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[17:06:56] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[17:06:56] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[17:06:56] === drm_test_drm_hdmi_connector_get_output_format_name ====
[17:06:56] [PASSED] RGB
[17:06:56] [PASSED] YUV 4:2:0
[17:06:56] [PASSED] YUV 4:2:2
[17:06:56] [PASSED] YUV 4:4:4
[17:06:56] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[17:06:56] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[17:06:56] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[17:06:56] ============= drm_damage_helper (21 subtests) ==============
[17:06:56] [PASSED] drm_test_damage_iter_no_damage
[17:06:56] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[17:06:56] [PASSED] drm_test_damage_iter_no_damage_src_moved
[17:06:56] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[17:06:56] [PASSED] drm_test_damage_iter_no_damage_not_visible
[17:06:56] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[17:06:56] [PASSED] drm_test_damage_iter_no_damage_no_fb
[17:06:56] [PASSED] drm_test_damage_iter_simple_damage
[17:06:56] [PASSED] drm_test_damage_iter_single_damage
[17:06:56] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[17:06:56] [PASSED] drm_test_damage_iter_single_damage_outside_src
[17:06:56] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[17:06:56] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[17:06:56] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[17:06:56] [PASSED] drm_test_damage_iter_single_damage_src_moved
[17:06:56] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[17:06:56] [PASSED] drm_test_damage_iter_damage
[17:06:56] [PASSED] drm_test_damage_iter_damage_one_intersect
[17:06:56] [PASSED] drm_test_damage_iter_damage_one_outside
[17:06:56] [PASSED] drm_test_damage_iter_damage_src_moved
[17:06:56] [PASSED] drm_test_damage_iter_damage_not_visible
[17:06:56] ================ [PASSED] drm_damage_helper ================
[17:06:56] ============== drm_dp_mst_helper (3 subtests) ==============
[17:06:56] ============== drm_test_dp_mst_calc_pbn_mode ==============
[17:06:56] [PASSED] Clock 154000 BPP 30 DSC disabled
[17:06:56] [PASSED] Clock 234000 BPP 30 DSC disabled
[17:06:56] [PASSED] Clock 297000 BPP 24 DSC disabled
[17:06:56] [PASSED] Clock 332880 BPP 24 DSC enabled
[17:06:56] [PASSED] Clock 324540 BPP 24 DSC enabled
[17:06:56] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[17:06:56] ============== drm_test_dp_mst_calc_pbn_div ===============
[17:06:56] [PASSED] Link rate 2000000 lane count 4
[17:06:56] [PASSED] Link rate 2000000 lane count 2
[17:06:56] [PASSED] Link rate 2000000 lane count 1
[17:06:56] [PASSED] Link rate 1350000 lane count 4
[17:06:56] [PASSED] Link rate 1350000 lane count 2
[17:06:56] [PASSED] Link rate 1350000 lane count 1
[17:06:56] [PASSED] Link rate 1000000 lane count 4
[17:06:56] [PASSED] Link rate 1000000 lane count 2
[17:06:56] [PASSED] Link rate 1000000 lane count 1
[17:06:56] [PASSED] Link rate 810000 lane count 4
[17:06:56] [PASSED] Link rate 810000 lane count 2
[17:06:56] [PASSED] Link rate 810000 lane count 1
[17:06:56] [PASSED] Link rate 540000 lane count 4
[17:06:56] [PASSED] Link rate 540000 lane count 2
[17:06:56] [PASSED] Link rate 540000 lane count 1
[17:06:56] [PASSED] Link rate 270000 lane count 4
[17:06:56] [PASSED] Link rate 270000 lane count 2
[17:06:56] [PASSED] Link rate 270000 lane count 1
[17:06:56] [PASSED] Link rate 162000 lane count 4
[17:06:56] [PASSED] Link rate 162000 lane count 2
[17:06:56] [PASSED] Link rate 162000 lane count 1
[17:06:56] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[17:06:56] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[17:06:56] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[17:06:56] [PASSED] DP_POWER_UP_PHY with port number
[17:06:56] [PASSED] DP_POWER_DOWN_PHY with port number
[17:06:56] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[17:06:56] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[17:06:56] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[17:06:56] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[17:06:56] [PASSED] DP_QUERY_PAYLOAD with port number
[17:06:56] [PASSED] DP_QUERY_PAYLOAD with VCPI
[17:06:56] [PASSED] DP_REMOTE_DPCD_READ with port number
[17:06:56] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[17:06:56] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[17:06:56] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[17:06:56] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[17:06:56] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[17:06:56] [PASSED] DP_REMOTE_I2C_READ with port number
[17:06:56] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[17:06:56] [PASSED] DP_REMOTE_I2C_READ with transactions array
[17:06:56] [PASSED] DP_REMOTE_I2C_WRITE with port number
[17:06:56] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[17:06:56] [PASSED] DP_REMOTE_I2C_WRITE with data array
[17:06:56] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[17:06:56] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[17:06:56] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[17:06:56] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[17:06:56] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[17:06:56] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[17:06:56] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[17:06:56] ================ [PASSED] drm_dp_mst_helper ================
[17:06:56] ================== drm_exec (7 subtests) ===================
[17:06:56] [PASSED] sanitycheck
[17:06:56] [PASSED] test_lock
[17:06:56] [PASSED] test_lock_unlock
[17:06:56] [PASSED] test_duplicates
[17:06:56] [PASSED] test_prepare
[17:06:56] [PASSED] test_prepare_array
[17:06:56] [PASSED] test_multiple_loops
[17:06:56] ==================== [PASSED] drm_exec =====================
[17:06:56] =========== drm_format_helper_test (17 subtests) ===========
[17:06:56] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[17:06:56] [PASSED] single_pixel_source_buffer
[17:06:56] [PASSED] single_pixel_clip_rectangle
[17:06:56] [PASSED] well_known_colors
[17:06:56] [PASSED] destination_pitch
[17:06:56] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[17:06:56] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[17:06:56] [PASSED] single_pixel_source_buffer
[17:06:56] [PASSED] single_pixel_clip_rectangle
[17:06:56] [PASSED] well_known_colors
[17:06:56] [PASSED] destination_pitch
[17:06:56] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[17:06:56] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[17:06:56] [PASSED] single_pixel_source_buffer
[17:06:56] [PASSED] single_pixel_clip_rectangle
[17:06:56] [PASSED] well_known_colors
[17:06:56] [PASSED] destination_pitch
[17:06:56] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[17:06:56] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[17:06:56] [PASSED] single_pixel_source_buffer
[17:06:56] [PASSED] single_pixel_clip_rectangle
[17:06:56] [PASSED] well_known_colors
[17:06:56] [PASSED] destination_pitch
[17:06:56] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[17:06:56] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[17:06:56] [PASSED] single_pixel_source_buffer
[17:06:56] [PASSED] single_pixel_clip_rectangle
[17:06:56] [PASSED] well_known_colors
[17:06:56] [PASSED] destination_pitch
[17:06:56] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[17:06:56] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[17:06:56] [PASSED] single_pixel_source_buffer
[17:06:56] [PASSED] single_pixel_clip_rectangle
[17:06:56] [PASSED] well_known_colors
[17:06:56] [PASSED] destination_pitch
[17:06:56] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[17:06:56] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[17:06:56] [PASSED] single_pixel_source_buffer
[17:06:56] [PASSED] single_pixel_clip_rectangle
[17:06:56] [PASSED] well_known_colors
[17:06:56] [PASSED] destination_pitch
[17:06:56] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[17:06:56] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[17:06:56] [PASSED] single_pixel_source_buffer
[17:06:56] [PASSED] single_pixel_clip_rectangle
[17:06:56] [PASSED] well_known_colors
[17:06:56] [PASSED] destination_pitch
[17:06:56] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[17:06:56] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[17:06:56] [PASSED] single_pixel_source_buffer
[17:06:56] [PASSED] single_pixel_clip_rectangle
[17:06:56] [PASSED] well_known_colors
[17:06:56] [PASSED] destination_pitch
[17:06:56] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[17:06:56] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[17:06:56] [PASSED] single_pixel_source_buffer
[17:06:56] [PASSED] single_pixel_clip_rectangle
[17:06:56] [PASSED] well_known_colors
[17:06:56] [PASSED] destination_pitch
[17:06:56] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[17:06:56] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[17:06:56] [PASSED] single_pixel_source_buffer
[17:06:56] [PASSED] single_pixel_clip_rectangle
[17:06:56] [PASSED] well_known_colors
[17:06:56] [PASSED] destination_pitch
[17:06:56] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[17:06:56] ============== drm_test_fb_xrgb8888_to_mono ===============
[17:06:56] [PASSED] single_pixel_source_buffer
[17:06:56] [PASSED] single_pixel_clip_rectangle
[17:06:56] [PASSED] well_known_colors
[17:06:56] [PASSED] destination_pitch
[17:06:56] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[17:06:56] ==================== drm_test_fb_swab =====================
[17:06:56] [PASSED] single_pixel_source_buffer
[17:06:56] [PASSED] single_pixel_clip_rectangle
[17:06:56] [PASSED] well_known_colors
[17:06:56] [PASSED] destination_pitch
[17:06:56] ================ [PASSED] drm_test_fb_swab =================
[17:06:56] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[17:06:56] [PASSED] single_pixel_source_buffer
[17:06:56] [PASSED] single_pixel_clip_rectangle
[17:06:56] [PASSED] well_known_colors
[17:06:56] [PASSED] destination_pitch
[17:06:56] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[17:06:56] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[17:06:56] [PASSED] single_pixel_source_buffer
[17:06:56] [PASSED] single_pixel_clip_rectangle
[17:06:56] [PASSED] well_known_colors
[17:06:56] [PASSED] destination_pitch
[17:06:56] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[17:06:56] ================= drm_test_fb_clip_offset =================
[17:06:56] [PASSED] pass through
[17:06:56] [PASSED] horizontal offset
[17:06:56] [PASSED] vertical offset
[17:06:56] [PASSED] horizontal and vertical offset
[17:06:56] [PASSED] horizontal offset (custom pitch)
[17:06:56] [PASSED] vertical offset (custom pitch)
[17:06:56] [PASSED] horizontal and vertical offset (custom pitch)
[17:06:56] ============= [PASSED] drm_test_fb_clip_offset =============
[17:06:56] =================== drm_test_fb_memcpy ====================
[17:06:56] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[17:06:56] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[17:06:56] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[17:06:56] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[17:06:56] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[17:06:56] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[17:06:56] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[17:06:56] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[17:06:56] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[17:06:56] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[17:06:56] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[17:06:56] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[17:06:56] =============== [PASSED] drm_test_fb_memcpy ================
[17:06:56] ============= [PASSED] drm_format_helper_test ==============
[17:06:56] ================= drm_format (18 subtests) =================
[17:06:56] [PASSED] drm_test_format_block_width_invalid
[17:06:56] [PASSED] drm_test_format_block_width_one_plane
[17:06:56] [PASSED] drm_test_format_block_width_two_plane
[17:06:56] [PASSED] drm_test_format_block_width_three_plane
[17:06:56] [PASSED] drm_test_format_block_width_tiled
[17:06:56] [PASSED] drm_test_format_block_height_invalid
[17:06:56] [PASSED] drm_test_format_block_height_one_plane
[17:06:56] [PASSED] drm_test_format_block_height_two_plane
[17:06:56] [PASSED] drm_test_format_block_height_three_plane
[17:06:56] [PASSED] drm_test_format_block_height_tiled
[17:06:56] [PASSED] drm_test_format_min_pitch_invalid
[17:06:56] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[17:06:56] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[17:06:56] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[17:06:56] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[17:06:56] [PASSED] drm_test_format_min_pitch_two_plane
[17:06:56] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[17:06:56] [PASSED] drm_test_format_min_pitch_tiled
[17:06:56] =================== [PASSED] drm_format ====================
[17:06:56] ============== drm_framebuffer (10 subtests) ===============
[17:06:56] ========== drm_test_framebuffer_check_src_coords ==========
[17:06:56] [PASSED] Success: source fits into fb
[17:06:56] [PASSED] Fail: overflowing fb with x-axis coordinate
[17:06:56] [PASSED] Fail: overflowing fb with y-axis coordinate
[17:06:56] [PASSED] Fail: overflowing fb with source width
[17:06:56] [PASSED] Fail: overflowing fb with source height
[17:06:56] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[17:06:56] [PASSED] drm_test_framebuffer_cleanup
[17:06:56] =============== drm_test_framebuffer_create ===============
[17:06:56] [PASSED] ABGR8888 normal sizes
[17:06:56] [PASSED] ABGR8888 max sizes
[17:06:56] [PASSED] ABGR8888 pitch greater than min required
[17:06:56] [PASSED] ABGR8888 pitch less than min required
[17:06:56] [PASSED] ABGR8888 Invalid width
[17:06:56] [PASSED] ABGR8888 Invalid buffer handle
[17:06:56] [PASSED] No pixel format
[17:06:56] [PASSED] ABGR8888 Width 0
[17:06:56] [PASSED] ABGR8888 Height 0
[17:06:56] [PASSED] ABGR8888 Out of bound height * pitch combination
[17:06:56] [PASSED] ABGR8888 Large buffer offset
[17:06:56] [PASSED] ABGR8888 Buffer offset for inexistent plane
[17:06:56] [PASSED] ABGR8888 Invalid flag
[17:06:56] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[17:06:56] [PASSED] ABGR8888 Valid buffer modifier
[17:06:56] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[17:06:56] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[17:06:56] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[17:06:56] [PASSED] NV12 Normal sizes
[17:06:56] [PASSED] NV12 Max sizes
[17:06:56] [PASSED] NV12 Invalid pitch
[17:06:56] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[17:06:56] [PASSED] NV12 different modifier per-plane
[17:06:56] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[17:06:56] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[17:06:56] [PASSED] NV12 Modifier for inexistent plane
[17:06:56] [PASSED] NV12 Handle for inexistent plane
[17:06:56] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[17:06:56] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[17:06:56] [PASSED] YVU420 Normal sizes
[17:06:56] [PASSED] YVU420 Max sizes
[17:06:56] [PASSED] YVU420 Invalid pitch
[17:06:56] [PASSED] YVU420 Different pitches
[17:06:56] [PASSED] YVU420 Different buffer offsets/pitches
[17:06:56] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[17:06:56] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[17:06:56] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[17:06:56] [PASSED] YVU420 Valid modifier
[17:06:56] [PASSED] YVU420 Different modifiers per plane
[17:06:56] [PASSED] YVU420 Modifier for inexistent plane
[17:06:56] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[17:06:56] [PASSED] X0L2 Normal sizes
[17:06:56] [PASSED] X0L2 Max sizes
[17:06:56] [PASSED] X0L2 Invalid pitch
[17:06:56] [PASSED] X0L2 Pitch greater than minimum required
[17:06:56] [PASSED] X0L2 Handle for inexistent plane
[17:06:56] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[17:06:56] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[17:06:56] [PASSED] X0L2 Valid modifier
[17:06:56] [PASSED] X0L2 Modifier for inexistent plane
[17:06:56] =========== [PASSED] drm_test_framebuffer_create ===========
[17:06:56] [PASSED] drm_test_framebuffer_free
[17:06:56] [PASSED] drm_test_framebuffer_init
[17:06:56] [PASSED] drm_test_framebuffer_init_bad_format
[17:06:56] [PASSED] drm_test_framebuffer_init_dev_mismatch
[17:06:56] [PASSED] drm_test_framebuffer_lookup
[17:06:56] [PASSED] drm_test_framebuffer_lookup_inexistent
[17:06:56] [PASSED] drm_test_framebuffer_modifiers_not_supported
[17:06:56] ================= [PASSED] drm_framebuffer =================
[17:06:56] ================ drm_gem_shmem (8 subtests) ================
[17:06:56] [PASSED] drm_gem_shmem_test_obj_create
[17:06:56] [PASSED] drm_gem_shmem_test_obj_create_private
[17:06:56] [PASSED] drm_gem_shmem_test_pin_pages
[17:06:56] [PASSED] drm_gem_shmem_test_vmap
[17:06:56] [PASSED] drm_gem_shmem_test_get_pages_sgt
[17:06:56] [PASSED] drm_gem_shmem_test_get_sg_table
[17:06:56] [PASSED] drm_gem_shmem_test_madvise
[17:06:56] [PASSED] drm_gem_shmem_test_purge
[17:06:56] ================== [PASSED] drm_gem_shmem ==================
[17:06:56] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[17:06:56] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[17:06:56] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[17:06:56] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[17:06:56] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[17:06:56] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[17:06:56] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[17:06:56] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[17:06:56] [PASSED] Automatic
[17:06:56] [PASSED] Full
[17:06:56] [PASSED] Limited 16:235
[17:06:56] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[17:06:56] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[17:06:56] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[17:06:56] [PASSED] drm_test_check_disable_connector
[17:06:56] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[17:06:56] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[17:06:56] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[17:06:56] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[17:06:56] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[17:06:56] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[17:06:56] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[17:06:56] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[17:06:56] [PASSED] drm_test_check_output_bpc_dvi
[17:06:56] [PASSED] drm_test_check_output_bpc_format_vic_1
[17:06:56] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[17:06:56] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[17:06:56] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[17:06:56] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[17:06:56] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[17:06:56] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[17:06:56] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[17:06:56] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[17:06:56] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[17:06:56] [PASSED] drm_test_check_broadcast_rgb_value
[17:06:56] [PASSED] drm_test_check_bpc_8_value
[17:06:56] [PASSED] drm_test_check_bpc_10_value
[17:06:56] [PASSED] drm_test_check_bpc_12_value
[17:06:56] [PASSED] drm_test_check_format_value
[17:06:56] [PASSED] drm_test_check_tmds_char_value
[17:06:56] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[17:06:56] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[17:06:56] [PASSED] drm_test_check_mode_valid
[17:06:56] [PASSED] drm_test_check_mode_valid_reject
[17:06:56] [PASSED] drm_test_check_mode_valid_reject_rate
[17:06:56] [PASSED] drm_test_check_mode_valid_reject_max_clock
[17:06:56] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[17:06:56] ================= drm_managed (2 subtests) =================
[17:06:56] [PASSED] drm_test_managed_release_action
[17:06:56] [PASSED] drm_test_managed_run_action
[17:06:56] =================== [PASSED] drm_managed ===================
[17:06:56] =================== drm_mm (6 subtests) ====================
[17:06:56] [PASSED] drm_test_mm_init
[17:06:56] [PASSED] drm_test_mm_debug
[17:06:56] [PASSED] drm_test_mm_align32
[17:06:56] [PASSED] drm_test_mm_align64
[17:06:56] [PASSED] drm_test_mm_lowest
[17:06:56] [PASSED] drm_test_mm_highest
[17:06:56] ===================== [PASSED] drm_mm ======================
[17:06:56] ============= drm_modes_analog_tv (5 subtests) =============
[17:06:56] [PASSED] drm_test_modes_analog_tv_mono_576i
[17:06:56] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[17:06:56] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[17:06:56] [PASSED] drm_test_modes_analog_tv_pal_576i
[17:06:56] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[17:06:56] =============== [PASSED] drm_modes_analog_tv ===============
[17:06:56] ============== drm_plane_helper (2 subtests) ===============
[17:06:56] =============== drm_test_check_plane_state ================
[17:06:56] [PASSED] clipping_simple
[17:06:56] [PASSED] clipping_rotate_reflect
[17:06:56] [PASSED] positioning_simple
[17:06:56] [PASSED] upscaling
[17:06:56] [PASSED] downscaling
[17:06:56] [PASSED] rounding1
[17:06:56] [PASSED] rounding2
[17:06:56] [PASSED] rounding3
[17:06:56] [PASSED] rounding4
[17:06:56] =========== [PASSED] drm_test_check_plane_state ============
[17:06:56] =========== drm_test_check_invalid_plane_state ============
[17:06:56] [PASSED] positioning_invalid
[17:06:56] [PASSED] upscaling_invalid
[17:06:56] [PASSED] downscaling_invalid
[17:06:56] ======= [PASSED] drm_test_check_invalid_plane_state ========
[17:06:56] ================ [PASSED] drm_plane_helper =================
[17:06:56] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[17:06:56] ====== drm_test_connector_helper_tv_get_modes_check =======
[17:06:56] [PASSED] None
[17:06:56] [PASSED] PAL
[17:06:56] [PASSED] NTSC
[17:06:56] [PASSED] Both, NTSC Default
[17:06:56] [PASSED] Both, PAL Default
[17:06:56] [PASSED] Both, NTSC Default, with PAL on command-line
[17:06:56] [PASSED] Both, PAL Default, with NTSC on command-line
[17:06:56] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[17:06:56] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[17:06:56] ================== drm_rect (9 subtests) ===================
[17:06:56] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[17:06:56] [PASSED] drm_test_rect_clip_scaled_not_clipped
[17:06:56] [PASSED] drm_test_rect_clip_scaled_clipped
[17:06:56] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[17:06:56] ================= drm_test_rect_intersect =================
[17:06:56] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[17:06:56] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[17:06:56] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[17:06:56] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[17:06:56] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[17:06:56] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[17:06:56] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[17:06:56] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[17:06:56] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[17:06:56] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[17:06:56] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[17:06:56] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[17:06:56] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[17:06:56] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[17:06:56] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[17:06:56] ============= [PASSED] drm_test_rect_intersect =============
[17:06:56] ================ drm_test_rect_calc_hscale ================
[17:06:56] [PASSED] normal use
[17:06:56] [PASSED] out of max range
[17:06:56] [PASSED] out of min range
[17:06:56] [PASSED] zero dst
[17:06:56] [PASSED] negative src
[17:06:56] [PASSED] negative dst
[17:06:56] ============ [PASSED] drm_test_rect_calc_hscale ============
[17:06:56] ================ drm_test_rect_calc_vscale ================
[17:06:56] [PASSED] normal use
[17:06:56] [PASSED] out of max range
[17:06:56] [PASSED] out of min range
[17:06:56] [PASSED] zero dst
[17:06:56] [PASSED] negative src
[17:06:56] [PASSED] negative dst
[17:06:56] ============ [PASSED] drm_test_rect_calc_vscale ============
[17:06:56] ================== drm_test_rect_rotate ===================
[17:06:56] [PASSED] reflect-x
[17:06:56] [PASSED] reflect-y
[17:06:56] [PASSED] rotate-0
[17:06:56] [PASSED] rotate-90
[17:06:56] [PASSED] rotate-180
[17:06:56] [PASSED] rotate-270
stty: 'standard input': Inappropriate ioctl for device
[17:06:56] ============== [PASSED] drm_test_rect_rotate ===============
[17:06:56] ================ drm_test_rect_rotate_inv =================
[17:06:56] [PASSED] reflect-x
[17:06:56] [PASSED] reflect-y
[17:06:56] [PASSED] rotate-0
[17:06:56] [PASSED] rotate-90
[17:06:56] [PASSED] rotate-180
[17:06:56] [PASSED] rotate-270
[17:06:56] ============ [PASSED] drm_test_rect_rotate_inv =============
[17:06:56] ==================== [PASSED] drm_rect =====================
[17:06:56] ============ drm_sysfb_modeset_test (1 subtest) ============
[17:06:56] ============ drm_test_sysfb_build_fourcc_list =============
[17:06:56] [PASSED] no native formats
[17:06:56] [PASSED] XRGB8888 as native format
[17:06:56] [PASSED] remove duplicates
[17:06:56] [PASSED] convert alpha formats
[17:06:56] [PASSED] random formats
[17:06:56] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[17:06:56] ============= [PASSED] drm_sysfb_modeset_test ==============
[17:06:56] ============================================================
[17:06:56] Testing complete. Ran 616 tests: passed: 616
[17:06:56] Elapsed time: 23.851s total, 1.656s configuring, 22.023s building, 0.141s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[17:06:57] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:06:58] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[17:07:06] Starting KUnit Kernel (1/1)...
[17:07:06] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:07:06] ================= ttm_device (5 subtests) ==================
[17:07:06] [PASSED] ttm_device_init_basic
[17:07:06] [PASSED] ttm_device_init_multiple
[17:07:06] [PASSED] ttm_device_fini_basic
[17:07:06] [PASSED] ttm_device_init_no_vma_man
[17:07:06] ================== ttm_device_init_pools ==================
[17:07:06] [PASSED] No DMA allocations, no DMA32 required
[17:07:06] [PASSED] DMA allocations, DMA32 required
[17:07:06] [PASSED] No DMA allocations, DMA32 required
[17:07:06] [PASSED] DMA allocations, no DMA32 required
[17:07:06] ============== [PASSED] ttm_device_init_pools ==============
[17:07:06] =================== [PASSED] ttm_device ====================
[17:07:06] ================== ttm_pool (8 subtests) ===================
[17:07:06] ================== ttm_pool_alloc_basic ===================
[17:07:06] [PASSED] One page
[17:07:06] [PASSED] More than one page
[17:07:06] [PASSED] Above the allocation limit
[17:07:06] [PASSED] One page, with coherent DMA mappings enabled
[17:07:06] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[17:07:06] ============== [PASSED] ttm_pool_alloc_basic ===============
[17:07:06] ============== ttm_pool_alloc_basic_dma_addr ==============
[17:07:06] [PASSED] One page
[17:07:06] [PASSED] More than one page
[17:07:06] [PASSED] Above the allocation limit
[17:07:06] [PASSED] One page, with coherent DMA mappings enabled
[17:07:06] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[17:07:06] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[17:07:06] [PASSED] ttm_pool_alloc_order_caching_match
[17:07:06] [PASSED] ttm_pool_alloc_caching_mismatch
[17:07:06] [PASSED] ttm_pool_alloc_order_mismatch
[17:07:06] [PASSED] ttm_pool_free_dma_alloc
[17:07:06] [PASSED] ttm_pool_free_no_dma_alloc
[17:07:06] [PASSED] ttm_pool_fini_basic
[17:07:06] ==================== [PASSED] ttm_pool =====================
[17:07:06] ================ ttm_resource (8 subtests) =================
[17:07:06] ================= ttm_resource_init_basic =================
[17:07:06] [PASSED] Init resource in TTM_PL_SYSTEM
[17:07:06] [PASSED] Init resource in TTM_PL_VRAM
[17:07:06] [PASSED] Init resource in a private placement
[17:07:06] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[17:07:06] ============= [PASSED] ttm_resource_init_basic =============
[17:07:06] [PASSED] ttm_resource_init_pinned
[17:07:06] [PASSED] ttm_resource_fini_basic
[17:07:06] [PASSED] ttm_resource_manager_init_basic
[17:07:06] [PASSED] ttm_resource_manager_usage_basic
[17:07:06] [PASSED] ttm_resource_manager_set_used_basic
[17:07:06] [PASSED] ttm_sys_man_alloc_basic
[17:07:06] [PASSED] ttm_sys_man_free_basic
[17:07:06] ================== [PASSED] ttm_resource ===================
[17:07:06] =================== ttm_tt (15 subtests) ===================
[17:07:06] ==================== ttm_tt_init_basic ====================
[17:07:06] [PASSED] Page-aligned size
[17:07:06] [PASSED] Extra pages requested
[17:07:06] ================ [PASSED] ttm_tt_init_basic ================
[17:07:06] [PASSED] ttm_tt_init_misaligned
[17:07:06] [PASSED] ttm_tt_fini_basic
[17:07:06] [PASSED] ttm_tt_fini_sg
[17:07:06] [PASSED] ttm_tt_fini_shmem
[17:07:06] [PASSED] ttm_tt_create_basic
[17:07:06] [PASSED] ttm_tt_create_invalid_bo_type
[17:07:06] [PASSED] ttm_tt_create_ttm_exists
[17:07:06] [PASSED] ttm_tt_create_failed
[17:07:06] [PASSED] ttm_tt_destroy_basic
[17:07:06] [PASSED] ttm_tt_populate_null_ttm
[17:07:06] [PASSED] ttm_tt_populate_populated_ttm
[17:07:06] [PASSED] ttm_tt_unpopulate_basic
[17:07:06] [PASSED] ttm_tt_unpopulate_empty_ttm
[17:07:06] [PASSED] ttm_tt_swapin_basic
[17:07:06] ===================== [PASSED] ttm_tt ======================
[17:07:06] =================== ttm_bo (14 subtests) ===================
[17:07:06] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[17:07:06] [PASSED] Cannot be interrupted and sleeps
[17:07:06] [PASSED] Cannot be interrupted, locks straight away
[17:07:06] [PASSED] Can be interrupted, sleeps
[17:07:06] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[17:07:06] [PASSED] ttm_bo_reserve_locked_no_sleep
[17:07:06] [PASSED] ttm_bo_reserve_no_wait_ticket
[17:07:06] [PASSED] ttm_bo_reserve_double_resv
[17:07:06] [PASSED] ttm_bo_reserve_interrupted
[17:07:06] [PASSED] ttm_bo_reserve_deadlock
[17:07:06] [PASSED] ttm_bo_unreserve_basic
[17:07:06] [PASSED] ttm_bo_unreserve_pinned
[17:07:06] [PASSED] ttm_bo_unreserve_bulk
[17:07:06] [PASSED] ttm_bo_put_basic
[17:07:06] [PASSED] ttm_bo_put_shared_resv
[17:07:06] [PASSED] ttm_bo_pin_basic
[17:07:06] [PASSED] ttm_bo_pin_unpin_resource
[17:07:06] [PASSED] ttm_bo_multiple_pin_one_unpin
[17:07:06] ===================== [PASSED] ttm_bo ======================
[17:07:06] ============== ttm_bo_validate (21 subtests) ===============
[17:07:06] ============== ttm_bo_init_reserved_sys_man ===============
[17:07:06] [PASSED] Buffer object for userspace
[17:07:06] [PASSED] Kernel buffer object
[17:07:06] [PASSED] Shared buffer object
[17:07:06] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[17:07:06] ============== ttm_bo_init_reserved_mock_man ==============
[17:07:06] [PASSED] Buffer object for userspace
[17:07:06] [PASSED] Kernel buffer object
[17:07:06] [PASSED] Shared buffer object
[17:07:06] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[17:07:06] [PASSED] ttm_bo_init_reserved_resv
[17:07:06] ================== ttm_bo_validate_basic ==================
[17:07:06] [PASSED] Buffer object for userspace
[17:07:06] [PASSED] Kernel buffer object
[17:07:06] [PASSED] Shared buffer object
[17:07:06] ============== [PASSED] ttm_bo_validate_basic ==============
[17:07:06] [PASSED] ttm_bo_validate_invalid_placement
[17:07:06] ============= ttm_bo_validate_same_placement ==============
[17:07:06] [PASSED] System manager
[17:07:06] [PASSED] VRAM manager
[17:07:06] ========= [PASSED] ttm_bo_validate_same_placement ==========
[17:07:06] [PASSED] ttm_bo_validate_failed_alloc
[17:07:06] [PASSED] ttm_bo_validate_pinned
[17:07:06] [PASSED] ttm_bo_validate_busy_placement
[17:07:06] ================ ttm_bo_validate_multihop =================
[17:07:06] [PASSED] Buffer object for userspace
[17:07:06] [PASSED] Kernel buffer object
[17:07:06] [PASSED] Shared buffer object
[17:07:06] ============ [PASSED] ttm_bo_validate_multihop =============
[17:07:06] ========== ttm_bo_validate_no_placement_signaled ==========
[17:07:06] [PASSED] Buffer object in system domain, no page vector
[17:07:06] [PASSED] Buffer object in system domain with an existing page vector
[17:07:06] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[17:07:06] ======== ttm_bo_validate_no_placement_not_signaled ========
[17:07:06] [PASSED] Buffer object for userspace
[17:07:06] [PASSED] Kernel buffer object
[17:07:06] [PASSED] Shared buffer object
[17:07:06] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[17:07:06] [PASSED] ttm_bo_validate_move_fence_signaled
[17:07:06] ========= ttm_bo_validate_move_fence_not_signaled =========
[17:07:06] [PASSED] Waits for GPU
[17:07:06] [PASSED] Tries to lock straight away
[17:07:06] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[17:07:06] [PASSED] ttm_bo_validate_happy_evict
[17:07:06] [PASSED] ttm_bo_validate_all_pinned_evict
[17:07:06] [PASSED] ttm_bo_validate_allowed_only_evict
[17:07:06] [PASSED] ttm_bo_validate_deleted_evict
[17:07:06] [PASSED] ttm_bo_validate_busy_domain_evict
[17:07:06] [PASSED] ttm_bo_validate_evict_gutting
[17:07:06] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[17:07:06] ================= [PASSED] ttm_bo_validate =================
[17:07:06] ============================================================
[17:07:06] Testing complete. Ran 101 tests: passed: 101
[17:07:06] Elapsed time: 9.719s total, 1.639s configuring, 7.813s building, 0.227s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 22+ messages in thread* ✗ CI.checksparse: warning for drm/i915: drop __to_intel_display() transitional macro
2025-08-06 16:55 [PATCH 00/15] drm/i915: drop __to_intel_display() transitional macro Jani Nikula
` (15 preceding siblings ...)
2025-08-06 17:07 ` ✓ CI.KUnit: success for drm/i915: drop __to_intel_display() transitional macro Patchwork
@ 2025-08-06 17:21 ` Patchwork
2025-08-06 18:09 ` ✓ Xe.CI.BAT: success " Patchwork
` (2 subsequent siblings)
19 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2025-08-06 17:21 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-xe
== Series Details ==
Series: drm/i915: drop __to_intel_display() transitional macro
URL : https://patchwork.freedesktop.org/series/152595/
State : warning
== Summary ==
+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast 886b8d8ef3839f604e3e7f6187ac6c46eb21b802
Sparse version: 0.6.4 (Ubuntu: 0.6.4-4ubuntu3)
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i915/gt/intel_reset.c:1572:12: warning: context imbalance in '_intel_gt_reset_lock' - different lock contexts for basic block
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 22+ messages in thread* ✓ Xe.CI.BAT: success for drm/i915: drop __to_intel_display() transitional macro
2025-08-06 16:55 [PATCH 00/15] drm/i915: drop __to_intel_display() transitional macro Jani Nikula
` (16 preceding siblings ...)
2025-08-06 17:21 ` ✗ CI.checksparse: warning " Patchwork
@ 2025-08-06 18:09 ` Patchwork
2025-08-06 19:12 ` ✓ Xe.CI.Full: " Patchwork
2025-08-13 20:58 ` [PATCH 00/15] " Gustavo Sousa
19 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2025-08-06 18:09 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 871 bytes --]
== Series Details ==
Series: drm/i915: drop __to_intel_display() transitional macro
URL : https://patchwork.freedesktop.org/series/152595/
State : success
== Summary ==
CI Bug Log - changes from xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802_BAT -> xe-pw-152595v1_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (10 -> 9)
------------------------------
Missing (1): bat-adlp-vm
Changes
-------
No changes found
Build changes
-------------
* Linux: xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802 -> xe-pw-152595v1
IGT_8487: 8487
xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802: 886b8d8ef3839f604e3e7f6187ac6c46eb21b802
xe-pw-152595v1: 152595v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/index.html
[-- Attachment #2: Type: text/html, Size: 1419 bytes --]
^ permalink raw reply [flat|nested] 22+ messages in thread* ✓ Xe.CI.Full: success for drm/i915: drop __to_intel_display() transitional macro
2025-08-06 16:55 [PATCH 00/15] drm/i915: drop __to_intel_display() transitional macro Jani Nikula
` (17 preceding siblings ...)
2025-08-06 18:09 ` ✓ Xe.CI.BAT: success " Patchwork
@ 2025-08-06 19:12 ` Patchwork
2025-08-13 20:58 ` [PATCH 00/15] " Gustavo Sousa
19 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2025-08-06 19:12 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 34765 bytes --]
== Series Details ==
Series: drm/i915: drop __to_intel_display() transitional macro
URL : https://patchwork.freedesktop.org/series/152595/
State : success
== Summary ==
CI Bug Log - changes from xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802_FULL -> xe-pw-152595v1_FULL
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (4 -> 4)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in xe-pw-152595v1_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-adlp: [PASS][1] -> [DMESG-FAIL][2] ([Intel XE#4543]) +1 other test dmesg-fail
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-adlp-4/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-adlp-8/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-270:
- shard-dg2-set2: NOTRUN -> [SKIP][3] ([Intel XE#1124]) +1 other test skip
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-dg2-435/igt@kms_big_fb@yf-tiled-16bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-0:
- shard-bmg: NOTRUN -> [SKIP][4] ([Intel XE#1124]) +2 other tests skip
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-bmg-4/igt@kms_big_fb@yf-tiled-32bpp-rotate-0.html
* igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p:
- shard-bmg: [PASS][5] -> [SKIP][6] ([Intel XE#2314] / [Intel XE#2894])
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-8/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-bmg-6/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html
* igt@kms_bw@connected-linear-tiling-4-displays-3840x2160p:
- shard-bmg: NOTRUN -> [SKIP][7] ([Intel XE#2314] / [Intel XE#2894])
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-bmg-4/igt@kms_bw@connected-linear-tiling-4-displays-3840x2160p.html
* igt@kms_bw@linear-tiling-2-displays-2560x1440p:
- shard-dg2-set2: NOTRUN -> [SKIP][8] ([Intel XE#367])
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-dg2-433/igt@kms_bw@linear-tiling-2-displays-2560x1440p.html
* igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs-cc@pipe-d-dp-4:
- shard-dg2-set2: NOTRUN -> [SKIP][9] ([Intel XE#455] / [Intel XE#787]) +12 other tests skip
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-dg2-463/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs-cc@pipe-d-dp-4.html
* igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs:
- shard-bmg: NOTRUN -> [SKIP][10] ([Intel XE#2887])
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-bmg-4/igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs.html
* igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-6:
- shard-dg2-set2: NOTRUN -> [SKIP][11] ([Intel XE#787]) +90 other tests skip
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-dg2-463/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-6.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-d-dp-4:
- shard-dg2-set2: [PASS][12] -> [INCOMPLETE][13] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345] / [Intel XE#4522]) +1 other test incomplete
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-d-dp-4.html
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-d-dp-4.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-6:
- shard-dg2-set2: [PASS][14] -> [DMESG-WARN][15] ([Intel XE#1727] / [Intel XE#3113])
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-6.html
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-6.html
* igt@kms_cdclk@mode-transition@pipe-d-dp-4:
- shard-dg2-set2: NOTRUN -> [SKIP][16] ([Intel XE#4417]) +3 other tests skip
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-dg2-463/igt@kms_cdclk@mode-transition@pipe-d-dp-4.html
* igt@kms_chamelium_frames@dp-crc-single:
- shard-dg2-set2: NOTRUN -> [SKIP][17] ([Intel XE#373])
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-dg2-435/igt@kms_chamelium_frames@dp-crc-single.html
* igt@kms_content_protection@lic-type-0@pipe-a-dp-2:
- shard-bmg: NOTRUN -> [FAIL][18] ([Intel XE#1178])
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-bmg-3/igt@kms_content_protection@lic-type-0@pipe-a-dp-2.html
* igt@kms_content_protection@srm@pipe-a-dp-4:
- shard-dg2-set2: NOTRUN -> [FAIL][19] ([Intel XE#1178]) +1 other test fail
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-dg2-463/igt@kms_content_protection@srm@pipe-a-dp-4.html
* igt@kms_cursor_crc@cursor-sliding-max-size:
- shard-dg2-set2: NOTRUN -> [SKIP][20] ([Intel XE#455]) +1 other test skip
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-dg2-435/igt@kms_cursor_crc@cursor-sliding-max-size.html
* igt@kms_cursor_legacy@cursora-vs-flipb-legacy:
- shard-bmg: [PASS][21] -> [SKIP][22] ([Intel XE#2291]) +4 other tests skip
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-8/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-bmg-6/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html
* igt@kms_cursor_legacy@flip-vs-cursor-legacy:
- shard-bmg: [PASS][23] -> [FAIL][24] ([Intel XE#4633])
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-3/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-bmg-4/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
* igt@kms_dirtyfb@default-dirtyfb-ioctl:
- shard-adlp: [PASS][25] -> [DMESG-WARN][26] ([Intel XE#2953] / [Intel XE#4173]) +3 other tests dmesg-warn
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-adlp-9/igt@kms_dirtyfb@default-dirtyfb-ioctl.html
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-adlp-9/igt@kms_dirtyfb@default-dirtyfb-ioctl.html
* igt@kms_dp_link_training@non-uhbr-mst:
- shard-bmg: NOTRUN -> [SKIP][27] ([Intel XE#4354])
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-bmg-4/igt@kms_dp_link_training@non-uhbr-mst.html
* igt@kms_dp_link_training@non-uhbr-sst:
- shard-bmg: [PASS][28] -> [SKIP][29] ([Intel XE#4354])
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-8/igt@kms_dp_link_training@non-uhbr-sst.html
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-bmg-6/igt@kms_dp_link_training@non-uhbr-sst.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-lnl: [PASS][30] -> [FAIL][31] ([Intel XE#4164] / [i915#4767])
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-lnl-4/igt@kms_fbcon_fbt@fbc-suspend.html
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-lnl-2/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@2x-blocking-wf_vblank@ac-hdmi-a6-dp4:
- shard-dg2-set2: [PASS][32] -> [INCOMPLETE][33] ([Intel XE#2049]) +1 other test incomplete
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-dg2-463/igt@kms_flip@2x-blocking-wf_vblank@ac-hdmi-a6-dp4.html
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-dg2-466/igt@kms_flip@2x-blocking-wf_vblank@ac-hdmi-a6-dp4.html
* igt@kms_flip@2x-plain-flip:
- shard-bmg: [PASS][34] -> [SKIP][35] ([Intel XE#2316]) +4 other tests skip
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-8/igt@kms_flip@2x-plain-flip.html
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-bmg-6/igt@kms_flip@2x-plain-flip.html
* igt@kms_flip@basic-plain-flip@b-hdmi-a1:
- shard-adlp: [PASS][36] -> [DMESG-WARN][37] ([Intel XE#4543]) +2 other tests dmesg-warn
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-adlp-2/igt@kms_flip@basic-plain-flip@b-hdmi-a1.html
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-adlp-3/igt@kms_flip@basic-plain-flip@b-hdmi-a1.html
* igt@kms_flip@flip-vs-expired-vblank@b-edp1:
- shard-lnl: [PASS][38] -> [FAIL][39] ([Intel XE#301]) +1 other test fail
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-lnl-7/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling:
- shard-bmg: NOTRUN -> [SKIP][40] ([Intel XE#2293] / [Intel XE#2380])
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-bmg-4/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
- shard-bmg: NOTRUN -> [SKIP][41] ([Intel XE#2293])
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-bmg-4/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-msflip-blt:
- shard-dg2-set2: NOTRUN -> [SKIP][42] ([Intel XE#651]) +1 other test skip
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-dg2-435/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@drrs-rgb565-draw-render:
- shard-bmg: NOTRUN -> [SKIP][43] ([Intel XE#2311]) +2 other tests skip
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-rgb565-draw-render.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt:
- shard-bmg: NOTRUN -> [SKIP][44] ([Intel XE#2313])
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-bmg-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt.html
* igt@kms_joiner@basic-force-big-joiner:
- shard-bmg: [PASS][45] -> [SKIP][46] ([Intel XE#3012])
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-8/igt@kms_joiner@basic-force-big-joiner.html
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-bmg-6/igt@kms_joiner@basic-force-big-joiner.html
* igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf:
- shard-dg2-set2: NOTRUN -> [SKIP][47] ([Intel XE#1489])
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-dg2-435/igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf.html
* igt@kms_psr2_sf@pr-overlay-plane-update-sf-dmg-area:
- shard-bmg: NOTRUN -> [SKIP][48] ([Intel XE#1489])
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-bmg-4/igt@kms_psr2_sf@pr-overlay-plane-update-sf-dmg-area.html
* igt@kms_setmode@basic@pipe-b-edp-1:
- shard-lnl: [PASS][49] -> [FAIL][50] ([Intel XE#2883]) +2 other tests fail
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-lnl-3/igt@kms_setmode@basic@pipe-b-edp-1.html
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-lnl-7/igt@kms_setmode@basic@pipe-b-edp-1.html
* igt@xe_compute_preempt@compute-preempt-many:
- shard-dg2-set2: NOTRUN -> [SKIP][51] ([Intel XE#1280] / [Intel XE#455]) +1 other test skip
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-dg2-435/igt@xe_compute_preempt@compute-preempt-many.html
* igt@xe_eudebug@basic-vm-access-parameters:
- shard-bmg: NOTRUN -> [SKIP][52] ([Intel XE#4837])
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-bmg-4/igt@xe_eudebug@basic-vm-access-parameters.html
* igt@xe_eudebug_sriov@deny-eudebug:
- shard-dg2-set2: NOTRUN -> [SKIP][53] ([Intel XE#4518])
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-dg2-433/igt@xe_eudebug_sriov@deny-eudebug.html
* igt@xe_exec_basic@multigpu-no-exec-null-defer-bind:
- shard-dg2-set2: [PASS][54] -> [SKIP][55] ([Intel XE#1392]) +3 other tests skip
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-dg2-464/igt@xe_exec_basic@multigpu-no-exec-null-defer-bind.html
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-dg2-432/igt@xe_exec_basic@multigpu-no-exec-null-defer-bind.html
* igt@xe_exec_basic@multigpu-once-null-rebind:
- shard-bmg: NOTRUN -> [SKIP][56] ([Intel XE#2322]) +1 other test skip
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-bmg-4/igt@xe_exec_basic@multigpu-once-null-rebind.html
* igt@xe_exec_fault_mode@once-bindexecqueue-userptr-rebind-imm:
- shard-dg2-set2: NOTRUN -> [SKIP][57] ([Intel XE#288]) +1 other test skip
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-dg2-433/igt@xe_exec_fault_mode@once-bindexecqueue-userptr-rebind-imm.html
* igt@xe_exec_reset@parallel-gt-reset:
- shard-bmg: [PASS][58] -> [DMESG-WARN][59] ([Intel XE#3876])
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-1/igt@xe_exec_reset@parallel-gt-reset.html
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-bmg-8/igt@xe_exec_reset@parallel-gt-reset.html
* igt@xe_exec_sip_eudebug@breakpoint-writesip-twice:
- shard-dg2-set2: NOTRUN -> [SKIP][60] ([Intel XE#4837]) +1 other test skip
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-dg2-435/igt@xe_exec_sip_eudebug@breakpoint-writesip-twice.html
* igt@xe_exec_system_allocator@once-malloc-nomemset:
- shard-dg2-set2: NOTRUN -> [SKIP][61] ([Intel XE#4915]) +16 other tests skip
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-dg2-435/igt@xe_exec_system_allocator@once-malloc-nomemset.html
* igt@xe_exec_system_allocator@threads-many-execqueues-mmap-free-huge-nomemset:
- shard-bmg: NOTRUN -> [SKIP][62] ([Intel XE#4943]) +1 other test skip
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-bmg-4/igt@xe_exec_system_allocator@threads-many-execqueues-mmap-free-huge-nomemset.html
* igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-new-bo-map-nomemset:
- shard-lnl: [PASS][63] -> [FAIL][64] ([Intel XE#4937]) +1 other test fail
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-lnl-7/igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-new-bo-map-nomemset.html
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-lnl-8/igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-new-bo-map-nomemset.html
* igt@xe_module_load@reload-no-display:
- shard-dg2-set2: [PASS][65] -> [ABORT][66] ([Intel XE#5087])
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-dg2-432/igt@xe_module_load@reload-no-display.html
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-dg2-463/igt@xe_module_load@reload-no-display.html
* igt@xe_oa@mi-rpc:
- shard-dg2-set2: NOTRUN -> [SKIP][67] ([Intel XE#3573])
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-dg2-433/igt@xe_oa@mi-rpc.html
* igt@xe_query@multigpu-query-engines:
- shard-bmg: NOTRUN -> [SKIP][68] ([Intel XE#944])
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-bmg-4/igt@xe_query@multigpu-query-engines.html
#### Possible fixes ####
* igt@kms_async_flips@async-flip-suspend-resume:
- shard-adlp: [DMESG-WARN][69] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][70] +3 other tests pass
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-adlp-9/igt@kms_async_flips@async-flip-suspend-resume.html
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-adlp-9/igt@kms_async_flips@async-flip-suspend-resume.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
- shard-bmg: [INCOMPLETE][71] ([Intel XE#3862]) -> [PASS][72] +1 other test pass
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-2/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-bmg-4/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
- shard-bmg: [SKIP][73] ([Intel XE#2291]) -> [PASS][74] +1 other test pass
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-bmg-1/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic:
- shard-bmg: [FAIL][75] ([Intel XE#4633]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-6/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-bmg-6/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
* igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
- shard-bmg: [SKIP][77] ([Intel XE#2316]) -> [PASS][78] +1 other test pass
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-6/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-bmg-1/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html
* igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-hdmi-a1:
- shard-adlp: [DMESG-WARN][79] ([Intel XE#4543]) -> [PASS][80] +7 other tests pass
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-adlp-1/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-hdmi-a1.html
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-adlp-8/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-hdmi-a1.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-dg2-set2: [INCOMPLETE][81] ([Intel XE#2049] / [Intel XE#2597]) -> [PASS][82] +1 other test pass
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-dg2-436/igt@kms_flip@flip-vs-suspend-interruptible.html
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-dg2-433/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_flip@flip-vs-suspend-interruptible@d-hdmi-a1:
- shard-adlp: [DMESG-WARN][83] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#4543]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-adlp-1/igt@kms_flip@flip-vs-suspend-interruptible@d-hdmi-a1.html
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-adlp-9/igt@kms_flip@flip-vs-suspend-interruptible@d-hdmi-a1.html
* igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-to-x:
- shard-adlp: [FAIL][85] ([Intel XE#1874]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-adlp-1/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-to-x.html
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-adlp-8/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-to-x.html
* igt@kms_hdr@invalid-hdr:
- shard-dg2-set2: [SKIP][87] ([Intel XE#455]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-dg2-432/igt@kms_hdr@invalid-hdr.html
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-dg2-463/igt@kms_hdr@invalid-hdr.html
* igt@kms_hdr@static-toggle:
- shard-bmg: [SKIP][89] ([Intel XE#1503]) -> [PASS][90] +2 other tests pass
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-6/igt@kms_hdr@static-toggle.html
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-bmg-3/igt@kms_hdr@static-toggle.html
* igt@kms_plane_scaling@2x-scaler-multi-pipe:
- shard-bmg: [SKIP][91] ([Intel XE#2571]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-6/igt@kms_plane_scaling@2x-scaler-multi-pipe.html
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-bmg-1/igt@kms_plane_scaling@2x-scaler-multi-pipe.html
* igt@kms_vrr@cmrr@pipe-a-edp-1:
- shard-lnl: [FAIL][93] ([Intel XE#4459]) -> [PASS][94] +1 other test pass
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-lnl-4/igt@kms_vrr@cmrr@pipe-a-edp-1.html
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-lnl-2/igt@kms_vrr@cmrr@pipe-a-edp-1.html
* igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-rebind:
- shard-dg2-set2: [SKIP][95] ([Intel XE#1392]) -> [PASS][96] +7 other tests pass
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-dg2-432/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-rebind.html
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-dg2-463/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-rebind.html
* igt@xe_exec_system_allocator@threads-shared-vm-many-large-new-bo-map-nomemset:
- shard-lnl: [FAIL][97] ([Intel XE#5018]) -> [PASS][98]
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-lnl-2/igt@xe_exec_system_allocator@threads-shared-vm-many-large-new-bo-map-nomemset.html
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-lnl-4/igt@xe_exec_system_allocator@threads-shared-vm-many-large-new-bo-map-nomemset.html
#### Warnings ####
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
- shard-dg2-set2: [INCOMPLETE][99] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345] / [Intel XE#4522]) -> [INCOMPLETE][100] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#3124] / [Intel XE#4345])
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-dp-4:
- shard-dg2-set2: [INCOMPLETE][101] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4522]) -> [INCOMPLETE][102] ([Intel XE#3124])
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-dp-4.html
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-dp-4.html
* igt@kms_content_protection@lic-type-0:
- shard-bmg: [SKIP][103] ([Intel XE#2341]) -> [FAIL][104] ([Intel XE#1178])
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-6/igt@kms_content_protection@lic-type-0.html
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-bmg-3/igt@kms_content_protection@lic-type-0.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-adlp: [DMESG-WARN][105] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#4543]) -> [DMESG-WARN][106] ([Intel XE#4543])
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-adlp-1/igt@kms_flip@flip-vs-suspend-interruptible.html
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-adlp-9/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt:
- shard-bmg: [SKIP][107] ([Intel XE#2312]) -> [SKIP][108] ([Intel XE#2311]) +12 other tests skip
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt.html
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-bmg-3/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt:
- shard-bmg: [SKIP][109] ([Intel XE#2312]) -> [SKIP][110] ([Intel XE#5390]) +5 other tests skip
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt.html
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen:
- shard-bmg: [SKIP][111] ([Intel XE#5390]) -> [SKIP][112] ([Intel XE#2312]) +6 other tests skip
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen.html
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][113] ([Intel XE#2311]) -> [SKIP][114] ([Intel XE#2312]) +12 other tests skip
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt:
- shard-bmg: [SKIP][115] ([Intel XE#2312]) -> [SKIP][116] ([Intel XE#2313]) +13 other tests skip
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-bmg-3/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen:
- shard-bmg: [SKIP][117] ([Intel XE#2313]) -> [SKIP][118] ([Intel XE#2312]) +8 other tests skip
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-8/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen.html
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen.html
* igt@kms_hdr@brightness-with-hdr:
- shard-bmg: [SKIP][119] ([Intel XE#3544]) -> [SKIP][120] ([Intel XE#3374] / [Intel XE#3544])
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-bmg-5/igt@kms_hdr@brightness-with-hdr.html
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-bmg-6/igt@kms_hdr@brightness-with-hdr.html
* igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv:
- shard-lnl: [ABORT][121] ([Intel XE#4917] / [Intel XE#5466]) -> [ABORT][122] ([Intel XE#5466])
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802/shard-lnl-8/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/shard-lnl-5/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
[Intel XE#1280]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1280
[Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
[Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
[Intel XE#1874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1874
[Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
[Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
[Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
[Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
[Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
[Intel XE#2571]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2571
[Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
[Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
[Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
[Intel XE#2883]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2883
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
[Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#3012]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3012
[Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
[Intel XE#3124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3124
[Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
[Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
[Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
[Intel XE#3862]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3862
[Intel XE#3876]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3876
[Intel XE#4164]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4164
[Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
[Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
[Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
[Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
[Intel XE#4417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4417
[Intel XE#4459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4459
[Intel XE#4518]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4518
[Intel XE#4522]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4522
[Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
[Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
[Intel XE#4633]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4633
[Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
[Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
[Intel XE#4917]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4917
[Intel XE#4937]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4937
[Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
[Intel XE#5018]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5018
[Intel XE#5087]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5087
[Intel XE#5390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5390
[Intel XE#5466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5466
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
[i915#4767]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4767
Build changes
-------------
* Linux: xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802 -> xe-pw-152595v1
IGT_8487: 8487
xe-3510-886b8d8ef3839f604e3e7f6187ac6c46eb21b802: 886b8d8ef3839f604e3e7f6187ac6c46eb21b802
xe-pw-152595v1: 152595v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152595v1/index.html
[-- Attachment #2: Type: text/html, Size: 41395 bytes --]
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH 00/15] drm/i915: drop __to_intel_display() transitional macro
2025-08-06 16:55 [PATCH 00/15] drm/i915: drop __to_intel_display() transitional macro Jani Nikula
` (18 preceding siblings ...)
2025-08-06 19:12 ` ✓ Xe.CI.Full: " Patchwork
@ 2025-08-13 20:58 ` Gustavo Sousa
2025-08-14 10:21 ` Jani Nikula
19 siblings, 1 reply; 22+ messages in thread
From: Gustavo Sousa @ 2025-08-13 20:58 UTC (permalink / raw)
To: Jani Nikula, intel-gfx, intel-xe; +Cc: jani.nikula
Quoting Jani Nikula (2025-08-06 13:55:01-03:00)
>Switch to passing struct intel_display to all the macros that use
>__to_intel_display(), and once that's done, remove __to_intel_display().
>
>We'll still need to get rid of struct intel_display usage like this
>outside of display, but explicit is better than implicit, and this
>prevents new accidental struct drm_i915_private usages from cropping up.
>
>Jani Nikula (15):
> drm/i915/display: pass display to HAS_PCH_*() macros
> drm/i915/fb: pass display to HAS_GMCH() and DISPLAY_VER()
> drm/i915/clockgating: pass display to for_each_pipe()
> drm/i915/clockgating: pass display to HAS_PCH_*() macros
> drm/i915/clockgating: pass display to DSPCNTR and DSPSURF register
> macros
> drm/i915/irq: pass display to macros that expect display
> drm/i915/dram: pass display to macros that expect display
> drm/i915/gmch: pass display to DISPLAY_VER()
> drm/i915/gem: pass display to HAS_DISPLAY()
> drm/i915/switcheroo: pass display to HAS_DISPLAY()
> drm/i915/drv: pass display to HAS_DISPLAY()
> drm/i915/uncore: pass display to HAS_FPGA_DBG_UNCLAIMED()
> drm/i915/gvt: convert mmio table to struct intel_display
> drm/i915/reg: separate VLV_DSPCLK_GATE_D from DSPCLK_GATE_D
This one was a bit harder to review, but looks good as well.
The series is:
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
> drm/i915/display: drop __to_intel_display() usage
>
> .../i915/display/intel_display_conversion.c | 2 +-
> .../i915/display/intel_display_conversion.h | 12 -
> .../drm/i915/display/intel_display_device.h | 7 +-
> .../gpu/drm/i915/display/intel_display_irq.c | 9 +-
> .../i915/display/intel_display_power_well.c | 2 +-
> drivers/gpu/drm/i915/display/intel_fb_pin.c | 4 +-
> drivers/gpu/drm/i915/display/intel_gmbus.c | 2 +-
> drivers/gpu/drm/i915/display/intel_overlay.c | 5 +-
> drivers/gpu/drm/i915/display/intel_pch.h | 4 +-
> drivers/gpu/drm/i915/display/vlv_dsi.c | 4 +-
> .../i915/gem/selftests/i915_gem_client_blt.c | 3 +-
> drivers/gpu/drm/i915/i915_driver.c | 14 +-
> drivers/gpu/drm/i915/i915_irq.c | 13 +-
> drivers/gpu/drm/i915/i915_reg.h | 3 +-
> drivers/gpu/drm/i915/i915_switcheroo.c | 6 +-
> drivers/gpu/drm/i915/intel_clock_gating.c | 35 ++-
> drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 266 +++++++++---------
> drivers/gpu/drm/i915/intel_uncore.c | 3 +-
> drivers/gpu/drm/i915/selftests/intel_uncore.c | 8 +-
> drivers/gpu/drm/i915/soc/intel_dram.c | 5 +-
> drivers/gpu/drm/i915/soc/intel_gmch.c | 3 +-
> 21 files changed, 206 insertions(+), 204 deletions(-)
>
>--
>2.39.5
>
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH 00/15] drm/i915: drop __to_intel_display() transitional macro
2025-08-13 20:58 ` [PATCH 00/15] " Gustavo Sousa
@ 2025-08-14 10:21 ` Jani Nikula
0 siblings, 0 replies; 22+ messages in thread
From: Jani Nikula @ 2025-08-14 10:21 UTC (permalink / raw)
To: Gustavo Sousa, intel-gfx, intel-xe
On Wed, 13 Aug 2025, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
> Quoting Jani Nikula (2025-08-06 13:55:01-03:00)
>>Switch to passing struct intel_display to all the macros that use
>>__to_intel_display(), and once that's done, remove __to_intel_display().
>>
>>We'll still need to get rid of struct intel_display usage like this
>>outside of display, but explicit is better than implicit, and this
>>prevents new accidental struct drm_i915_private usages from cropping up.
>>
>>Jani Nikula (15):
>> drm/i915/display: pass display to HAS_PCH_*() macros
>> drm/i915/fb: pass display to HAS_GMCH() and DISPLAY_VER()
>> drm/i915/clockgating: pass display to for_each_pipe()
>> drm/i915/clockgating: pass display to HAS_PCH_*() macros
>> drm/i915/clockgating: pass display to DSPCNTR and DSPSURF register
>> macros
>> drm/i915/irq: pass display to macros that expect display
>> drm/i915/dram: pass display to macros that expect display
>> drm/i915/gmch: pass display to DISPLAY_VER()
>> drm/i915/gem: pass display to HAS_DISPLAY()
>> drm/i915/switcheroo: pass display to HAS_DISPLAY()
>> drm/i915/drv: pass display to HAS_DISPLAY()
>> drm/i915/uncore: pass display to HAS_FPGA_DBG_UNCLAIMED()
>> drm/i915/gvt: convert mmio table to struct intel_display
>> drm/i915/reg: separate VLV_DSPCLK_GATE_D from DSPCLK_GATE_D
>
> This one was a bit harder to review, but looks good as well.
>
> The series is:
>
> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Thanks a bunch, series merged to drm-intel-next.
BR,
Jani.
>
>> drm/i915/display: drop __to_intel_display() usage
>>
>> .../i915/display/intel_display_conversion.c | 2 +-
>> .../i915/display/intel_display_conversion.h | 12 -
>> .../drm/i915/display/intel_display_device.h | 7 +-
>> .../gpu/drm/i915/display/intel_display_irq.c | 9 +-
>> .../i915/display/intel_display_power_well.c | 2 +-
>> drivers/gpu/drm/i915/display/intel_fb_pin.c | 4 +-
>> drivers/gpu/drm/i915/display/intel_gmbus.c | 2 +-
>> drivers/gpu/drm/i915/display/intel_overlay.c | 5 +-
>> drivers/gpu/drm/i915/display/intel_pch.h | 4 +-
>> drivers/gpu/drm/i915/display/vlv_dsi.c | 4 +-
>> .../i915/gem/selftests/i915_gem_client_blt.c | 3 +-
>> drivers/gpu/drm/i915/i915_driver.c | 14 +-
>> drivers/gpu/drm/i915/i915_irq.c | 13 +-
>> drivers/gpu/drm/i915/i915_reg.h | 3 +-
>> drivers/gpu/drm/i915/i915_switcheroo.c | 6 +-
>> drivers/gpu/drm/i915/intel_clock_gating.c | 35 ++-
>> drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 266 +++++++++---------
>> drivers/gpu/drm/i915/intel_uncore.c | 3 +-
>> drivers/gpu/drm/i915/selftests/intel_uncore.c | 8 +-
>> drivers/gpu/drm/i915/soc/intel_dram.c | 5 +-
>> drivers/gpu/drm/i915/soc/intel_gmch.c | 3 +-
>> 21 files changed, 206 insertions(+), 204 deletions(-)
>>
>>--
>>2.39.5
>>
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 22+ messages in thread