* [PATCH 0/4] drm/i915/display: start switching to display specific reg types
@ 2026-04-08 13:15 Jani Nikula
2026-04-08 13:15 ` [PATCH 1/4] drm/i915/display: add typedef for intel_reg_t and use it Jani Nikula
` (5 more replies)
0 siblings, 6 replies; 7+ messages in thread
From: Jani Nikula @ 2026-04-08 13:15 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala
Add intel_reg_t for display, initially as an alias to i915_reg_t, and
use it in display.
There are probably dragons in converting everything, especially with gvt
usage of _MMIO() macro, but one thing at a time. I didn't go further
this time, to avoid clashing with whatever Ville is doing with
uncore. Also, this was mostly sed, and should be easy enough to rebase
if this conflicts with the uncore stuff.
BR,
Jani.
Jani Nikula (4):
drm/i915/display: add typedef for intel_reg_t and use it
drm/i915/display: add struct intel_irq_regs and use it
drm/i915/display: add struct intel_error_regs and use it
drm/i915/display: define and use intel_reg_{offset,equal,valid}()
helpers
drivers/gpu/drm/i915/display/g4x_dp.c | 4 +-
drivers/gpu/drm/i915/display/g4x_dp.h | 10 ++--
drivers/gpu/drm/i915/display/g4x_hdmi.c | 2 +-
drivers/gpu/drm/i915/display/g4x_hdmi.h | 6 +--
drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
drivers/gpu/drm/i915/display/intel_audio.c | 2 +-
drivers/gpu/drm/i915/display/intel_color.c | 4 +-
.../gpu/drm/i915/display/intel_combo_phy.c | 2 +-
drivers/gpu/drm/i915/display/intel_crt.c | 6 +--
drivers/gpu/drm/i915/display/intel_crt.h | 6 +--
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 2 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 26 +++++-----
drivers/gpu/drm/i915/display/intel_ddi.h | 6 +--
drivers/gpu/drm/i915/display/intel_de.c | 30 +++++------
drivers/gpu/drm/i915/display/intel_de.h | 48 +++++++++---------
drivers/gpu/drm/i915/display/intel_display.c | 8 +--
drivers/gpu/drm/i915/display/intel_display.h | 10 ++--
.../drm/i915/display/intel_display_device.c | 2 +-
.../gpu/drm/i915/display/intel_display_irq.c | 20 ++++----
.../drm/i915/display/intel_display_power.c | 4 +-
.../i915/display/intel_display_power_well.c | 8 +--
.../drm/i915/display/intel_display_reg_defs.h | 35 +++++++++++++
.../gpu/drm/i915/display/intel_display_regs.h | 50 +++++++++----------
.../drm/i915/display/intel_display_types.h | 12 ++---
drivers/gpu/drm/i915/display/intel_dmc.c | 50 +++++++++----------
drivers/gpu/drm/i915/display/intel_dmc_wl.c | 14 +++---
drivers/gpu/drm/i915/display/intel_dmc_wl.h | 6 +--
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_dp_aux.c | 28 +++++------
drivers/gpu/drm/i915/display/intel_dpio_phy.c | 8 +--
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 32 ++++++------
drivers/gpu/drm/i915/display/intel_dsb.c | 22 ++++----
drivers/gpu/drm/i915/display/intel_dsb.h | 10 ++--
drivers/gpu/drm/i915/display/intel_dvo_dev.h | 2 +-
drivers/gpu/drm/i915/display/intel_fdi.c | 12 ++---
.../drm/i915/display/intel_fifo_underrun.c | 4 +-
drivers/gpu/drm/i915/display/intel_gmbus.c | 4 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 28 +++++------
drivers/gpu/drm/i915/display/intel_lt_phy.c | 6 +--
drivers/gpu/drm/i915/display/intel_lvds.c | 6 +--
drivers/gpu/drm/i915/display/intel_lvds.h | 6 +--
drivers/gpu/drm/i915/display/intel_mchbar.c | 14 +++---
drivers/gpu/drm/i915/display/intel_mchbar.h | 8 +--
.../gpu/drm/i915/display/intel_pch_display.c | 14 +++---
drivers/gpu/drm/i915/display/intel_pps.c | 38 +++++++-------
drivers/gpu/drm/i915/display/intel_psr.c | 36 ++++++-------
drivers/gpu/drm/i915/display/intel_sdvo.c | 6 +--
drivers/gpu/drm/i915/display/intel_sdvo.h | 10 ++--
drivers/gpu/drm/i915/display/intel_snps_phy.c | 4 +-
drivers/gpu/drm/i915/display/intel_tc.c | 10 ++--
drivers/gpu/drm/i915/display/intel_vblank.c | 2 +-
drivers/gpu/drm/i915/display/intel_vdsc.c | 10 ++--
drivers/gpu/drm/i915/display/intel_vga.c | 4 +-
drivers/gpu/drm/i915/display/vlv_dsi.c | 16 +++---
55 files changed, 377 insertions(+), 342 deletions(-)
--
2.47.3
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH 1/4] drm/i915/display: add typedef for intel_reg_t and use it 2026-04-08 13:15 [PATCH 0/4] drm/i915/display: start switching to display specific reg types Jani Nikula @ 2026-04-08 13:15 ` Jani Nikula 2026-04-08 13:15 ` [PATCH 2/4] drm/i915/display: add struct intel_irq_regs " Jani Nikula ` (4 subsequent siblings) 5 siblings, 0 replies; 7+ messages in thread From: Jani Nikula @ 2026-04-08 13:15 UTC (permalink / raw) To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala Add a typedef alias intel_reg_t for i915_reg_t, and use it exclusively in display code. The goal is to eventually define a distinct type for display, but for now just use an alias. In a handful of places include intel_display_reg_defs.h instead of i915_reg_defs.h to get the definition, and isolate the i915_reg_defs.h include there. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/g4x_dp.c | 4 +- drivers/gpu/drm/i915/display/g4x_dp.h | 10 ++-- drivers/gpu/drm/i915/display/g4x_hdmi.c | 2 +- drivers/gpu/drm/i915/display/g4x_hdmi.h | 6 +-- drivers/gpu/drm/i915/display/icl_dsi.c | 2 +- drivers/gpu/drm/i915/display/intel_audio.c | 2 +- drivers/gpu/drm/i915/display/intel_color.c | 4 +- .../gpu/drm/i915/display/intel_combo_phy.c | 2 +- drivers/gpu/drm/i915/display/intel_crt.c | 6 +-- drivers/gpu/drm/i915/display/intel_crt.h | 6 +-- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 2 +- drivers/gpu/drm/i915/display/intel_ddi.c | 26 +++++----- drivers/gpu/drm/i915/display/intel_ddi.h | 6 +-- drivers/gpu/drm/i915/display/intel_de.c | 30 ++++++------ drivers/gpu/drm/i915/display/intel_de.h | 48 +++++++++---------- drivers/gpu/drm/i915/display/intel_display.c | 8 ++-- drivers/gpu/drm/i915/display/intel_display.h | 10 ++-- .../gpu/drm/i915/display/intel_display_irq.c | 10 ++-- .../drm/i915/display/intel_display_power.c | 4 +- .../i915/display/intel_display_power_well.c | 8 ++-- .../drm/i915/display/intel_display_reg_defs.h | 2 + .../drm/i915/display/intel_display_types.h | 8 ++-- drivers/gpu/drm/i915/display/intel_dmc.c | 24 +++++----- drivers/gpu/drm/i915/display/intel_dmc_wl.c | 8 ++-- drivers/gpu/drm/i915/display/intel_dmc_wl.h | 6 +-- drivers/gpu/drm/i915/display/intel_dp.c | 2 +- drivers/gpu/drm/i915/display/intel_dp_aux.c | 28 +++++------ drivers/gpu/drm/i915/display/intel_dpio_phy.c | 8 ++-- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 28 +++++------ drivers/gpu/drm/i915/display/intel_dsb.c | 12 ++--- drivers/gpu/drm/i915/display/intel_dsb.h | 10 ++-- drivers/gpu/drm/i915/display/intel_dvo_dev.h | 2 +- drivers/gpu/drm/i915/display/intel_fdi.c | 12 ++--- .../drm/i915/display/intel_fifo_underrun.c | 4 +- drivers/gpu/drm/i915/display/intel_gmbus.c | 4 +- drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 28 +++++------ drivers/gpu/drm/i915/display/intel_lt_phy.c | 6 +-- drivers/gpu/drm/i915/display/intel_lvds.c | 6 +-- drivers/gpu/drm/i915/display/intel_lvds.h | 6 +-- drivers/gpu/drm/i915/display/intel_mchbar.c | 10 ++-- drivers/gpu/drm/i915/display/intel_mchbar.h | 8 ++-- .../gpu/drm/i915/display/intel_pch_display.c | 14 +++--- drivers/gpu/drm/i915/display/intel_pps.c | 32 ++++++------- drivers/gpu/drm/i915/display/intel_psr.c | 36 +++++++------- drivers/gpu/drm/i915/display/intel_sdvo.c | 6 +-- drivers/gpu/drm/i915/display/intel_sdvo.h | 10 ++-- drivers/gpu/drm/i915/display/intel_snps_phy.c | 4 +- drivers/gpu/drm/i915/display/intel_tc.c | 10 ++-- drivers/gpu/drm/i915/display/intel_vblank.c | 2 +- drivers/gpu/drm/i915/display/intel_vdsc.c | 10 ++-- drivers/gpu/drm/i915/display/intel_vga.c | 4 +- drivers/gpu/drm/i915/display/vlv_dsi.c | 16 +++---- 53 files changed, 283 insertions(+), 281 deletions(-) diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c index 5e74d8a3ba5c..5ff1cdf4581a 100644 --- a/drivers/gpu/drm/i915/display/g4x_dp.c +++ b/drivers/gpu/drm/i915/display/g4x_dp.c @@ -273,7 +273,7 @@ static bool cpt_dp_port_selected(struct intel_display *display, } bool g4x_dp_port_enabled(struct intel_display *display, - i915_reg_t dp_reg, enum port port, + intel_reg_t dp_reg, enum port port, enum pipe *pipe) { bool ret; @@ -1280,7 +1280,7 @@ static const struct drm_encoder_funcs intel_dp_enc_funcs = { }; bool g4x_dp_init(struct intel_display *display, - i915_reg_t output_reg, enum port port) + intel_reg_t output_reg, enum port port) { const struct intel_bios_encoder_data *devdata; struct intel_digital_port *dig_port; diff --git a/drivers/gpu/drm/i915/display/g4x_dp.h b/drivers/gpu/drm/i915/display/g4x_dp.h index 0b28951b8365..99de690ebe7f 100644 --- a/drivers/gpu/drm/i915/display/g4x_dp.h +++ b/drivers/gpu/drm/i915/display/g4x_dp.h @@ -8,7 +8,7 @@ #include <linux/types.h> -#include "i915_reg_defs.h" +#include "intel_display_reg_defs.h" enum pipe; enum port; @@ -20,23 +20,23 @@ struct intel_encoder; #ifdef I915 const struct dpll *vlv_get_dpll(struct intel_display *display); bool g4x_dp_port_enabled(struct intel_display *display, - i915_reg_t dp_reg, enum port port, + intel_reg_t dp_reg, enum port port, enum pipe *pipe); bool g4x_dp_init(struct intel_display *display, - i915_reg_t output_reg, enum port port); + intel_reg_t output_reg, enum port port); #else static inline const struct dpll *vlv_get_dpll(struct intel_display *display) { return NULL; } static inline bool g4x_dp_port_enabled(struct intel_display *display, - i915_reg_t dp_reg, int port, + intel_reg_t dp_reg, int port, enum pipe *pipe) { return false; } static inline bool g4x_dp_init(struct intel_display *display, - i915_reg_t output_reg, int port) + intel_reg_t output_reg, int port) { return false; } diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c b/drivers/gpu/drm/i915/display/g4x_hdmi.c index 5fe5067c4237..9ea90a6d906f 100644 --- a/drivers/gpu/drm/i915/display/g4x_hdmi.c +++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c @@ -666,7 +666,7 @@ static bool assert_hdmi_port_valid(struct intel_display *display, enum port port } bool g4x_hdmi_init(struct intel_display *display, - i915_reg_t hdmi_reg, enum port port) + intel_reg_t hdmi_reg, enum port port) { const struct intel_bios_encoder_data *devdata; struct intel_digital_port *dig_port; diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.h b/drivers/gpu/drm/i915/display/g4x_hdmi.h index 039d2bdba06c..0557322efe5a 100644 --- a/drivers/gpu/drm/i915/display/g4x_hdmi.h +++ b/drivers/gpu/drm/i915/display/g4x_hdmi.h @@ -8,7 +8,7 @@ #include <linux/types.h> -#include "i915_reg_defs.h" +#include "intel_display_reg_defs.h" enum port; struct drm_atomic_state; @@ -17,12 +17,12 @@ struct intel_display; #ifdef I915 bool g4x_hdmi_init(struct intel_display *display, - i915_reg_t hdmi_reg, enum port port); + intel_reg_t hdmi_reg, enum port port); int g4x_hdmi_connector_atomic_check(struct drm_connector *connector, struct drm_atomic_state *state); #else static inline bool g4x_hdmi_init(struct intel_display *display, - i915_reg_t hdmi_reg, int port) + intel_reg_t hdmi_reg, int port) { return false; } diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index afbaa0465842..a549f1fac810 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -296,7 +296,7 @@ static void configure_dual_link_mode(struct intel_encoder *encoder, { struct intel_display *display = to_intel_display(encoder); struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); - i915_reg_t dss_ctl1_reg, dss_ctl2_reg; + intel_reg_t dss_ctl1_reg, dss_ctl2_reg; u32 dss_ctl1; /* FIXME: Move all DSS handling to intel_vdsc.c */ diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c index 081627e0d917..31108694a06a 100644 --- a/drivers/gpu/drm/i915/display/intel_audio.c +++ b/drivers/gpu/drm/i915/display/intel_audio.c @@ -595,7 +595,7 @@ static void hsw_audio_codec_enable(struct intel_encoder *encoder, } struct ibx_audio_regs { - i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2; + intel_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2; }; static void ibx_audio_regs_init(struct intel_display *display, diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index e7950655434b..2dfe30e6f2b2 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1348,7 +1348,7 @@ static void i965_load_luts(const struct intel_crtc_state *crtc_state) } static void ilk_lut_write(const struct intel_crtc_state *crtc_state, - i915_reg_t reg, u32 val) + intel_reg_t reg, u32 val) { struct intel_display *display = to_intel_display(crtc_state); @@ -1359,7 +1359,7 @@ static void ilk_lut_write(const struct intel_crtc_state *crtc_state, } static void ilk_lut_write_indexed(const struct intel_crtc_state *crtc_state, - i915_reg_t reg, u32 val) + intel_reg_t reg, u32 val) { struct intel_display *display = to_intel_display(crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c index f401558ac14e..9b4ecfbbed4f 100644 --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c @@ -92,7 +92,7 @@ static void icl_set_procmon_ref_values(struct intel_display *display, } static bool check_phy_reg(struct intel_display *display, - enum phy phy, i915_reg_t reg, u32 mask, + enum phy phy, intel_reg_t reg, u32 mask, u32 expected_val) { u32 val = intel_de_read(display, reg); diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c index 6aa6a1dd6e1b..c19e0c591a3c 100644 --- a/drivers/gpu/drm/i915/display/intel_crt.c +++ b/drivers/gpu/drm/i915/display/intel_crt.c @@ -77,7 +77,7 @@ struct intel_crt { struct intel_encoder base; bool force_hotplug_required; - i915_reg_t adpa_reg; + intel_reg_t adpa_reg; }; static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) @@ -91,7 +91,7 @@ static struct intel_crt *intel_attached_crt(struct intel_connector *connector) } bool intel_crt_port_enabled(struct intel_display *display, - i915_reg_t adpa_reg, enum pipe *pipe) + intel_reg_t adpa_reg, enum pipe *pipe) { u32 val; @@ -1011,7 +1011,7 @@ void intel_crt_init(struct intel_display *display) { struct intel_connector *connector; struct intel_crt *crt; - i915_reg_t adpa_reg; + intel_reg_t adpa_reg; u8 ddc_pin; u32 adpa; diff --git a/drivers/gpu/drm/i915/display/intel_crt.h b/drivers/gpu/drm/i915/display/intel_crt.h index e0abfe96a3d2..7d0ae8d8c28d 100644 --- a/drivers/gpu/drm/i915/display/intel_crt.h +++ b/drivers/gpu/drm/i915/display/intel_crt.h @@ -6,7 +6,7 @@ #ifndef __INTEL_CRT_H__ #define __INTEL_CRT_H__ -#include "i915_reg_defs.h" +#include "intel_display_reg_defs.h" enum pipe; struct drm_encoder; @@ -14,12 +14,12 @@ struct intel_display; #ifdef I915 bool intel_crt_port_enabled(struct intel_display *display, - i915_reg_t adpa_reg, enum pipe *pipe); + intel_reg_t adpa_reg, enum pipe *pipe); void intel_crt_init(struct intel_display *display); void intel_crt_reset(struct drm_encoder *encoder); #else static inline bool intel_crt_port_enabled(struct intel_display *display, - i915_reg_t adpa_reg, enum pipe *pipe) + intel_reg_t adpa_reg, enum pipe *pipe) { return false; } diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 7e59409bbf01..991b8683a269 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -2980,7 +2980,7 @@ void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder, struct intel_display *display = to_intel_display(encoder); enum port port = encoder->port; enum phy phy = intel_encoder_to_phy(encoder); - i915_reg_t buf_ctl2_reg = XELPDP_PORT_BUF_CTL2(display, port); + intel_reg_t buf_ctl2_reg = XELPDP_PORT_BUF_CTL2(display, port); int lane; intel_de_rmw(display, buf_ctl2_reg, diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index ebefa889bc8c..a725e3fc2caa 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -188,7 +188,7 @@ static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, trans->entries[level].hsw.trans2); } -static i915_reg_t intel_ddi_buf_status_reg(struct intel_display *display, enum port port) +static intel_reg_t intel_ddi_buf_status_reg(struct intel_display *display, enum port port) { if (DISPLAY_VER(display) >= 14) return XELPDP_PORT_BUF_CTL1(display, port); @@ -1556,7 +1556,7 @@ hsw_set_signal_levels(struct intel_encoder *encoder, intel_de_posting_read(display, DDI_BUF_CTL(port)); } -static void _icl_ddi_enable_clock(struct intel_display *display, i915_reg_t reg, +static void _icl_ddi_enable_clock(struct intel_display *display, intel_reg_t reg, u32 clk_sel_mask, u32 clk_sel, u32 clk_off) { mutex_lock(&display->dpll.lock); @@ -1572,7 +1572,7 @@ static void _icl_ddi_enable_clock(struct intel_display *display, i915_reg_t reg, mutex_unlock(&display->dpll.lock); } -static void _icl_ddi_disable_clock(struct intel_display *display, i915_reg_t reg, +static void _icl_ddi_disable_clock(struct intel_display *display, intel_reg_t reg, u32 clk_off) { mutex_lock(&display->dpll.lock); @@ -1582,14 +1582,14 @@ static void _icl_ddi_disable_clock(struct intel_display *display, i915_reg_t reg mutex_unlock(&display->dpll.lock); } -static bool _icl_ddi_is_clock_enabled(struct intel_display *display, i915_reg_t reg, +static bool _icl_ddi_is_clock_enabled(struct intel_display *display, intel_reg_t reg, u32 clk_off) { return !(intel_de_read(display, reg) & clk_off); } static struct intel_dpll * -_icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg, +_icl_ddi_get_pll(struct intel_display *display, intel_reg_t reg, u32 clk_sel_mask, u32 clk_sel_shift) { enum intel_dpll_id id; @@ -2270,8 +2270,8 @@ tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) return crtc_state->cpu_transcoder; } -i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state) +intel_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(encoder); @@ -2282,8 +2282,8 @@ i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, return DP_TP_CTL(encoder->port); } -static i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state) +static intel_reg_t dp_tp_status_reg(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(encoder); @@ -2559,7 +2559,7 @@ mtl_ddi_enable_d2d(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); enum port port = encoder->port; - i915_reg_t reg; + intel_reg_t reg; u32 set_bits, wait_bits; int ret; @@ -3059,7 +3059,7 @@ mtl_ddi_disable_d2d(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); enum port port = encoder->port; - i915_reg_t reg; + intel_reg_t reg; u32 clr_bits, wait_bits; int ret; @@ -3386,7 +3386,7 @@ static void intel_ddi_enable_dp(struct intel_atomic_state *state, trans_port_sync_stop_link_train(state, encoder, crtc_state); } -static i915_reg_t +static intel_reg_t gen9_chicken_trans_reg_by_port(struct intel_display *display, enum port port) { static const enum transcoder trans[] = { @@ -3439,7 +3439,7 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, * the bits affect a specific DDI port rather than * a specific transcoder. */ - i915_reg_t reg = gen9_chicken_trans_reg_by_port(display, port); + intel_reg_t reg = gen9_chicken_trans_reg_by_port(display, port); u32 val; val = intel_de_read(display, reg); diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h index f6f511bb0431..580ecb09b8b6 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.h +++ b/drivers/gpu/drm/i915/display/intel_ddi.h @@ -6,7 +6,7 @@ #ifndef __INTEL_DDI_H__ #define __INTEL_DDI_H__ -#include "i915_reg_defs.h" +#include "intel_display_reg_defs.h" struct drm_connector_state; struct intel_atomic_state; @@ -23,8 +23,8 @@ enum pipe; enum port; enum transcoder; -i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state); +intel_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state); void intel_ddi_clear_act_sent(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_de.c b/drivers/gpu/drm/i915/display/intel_de.c index a96e83d76eaa..6daee9e82503 100644 --- a/drivers/gpu/drm/i915/display/intel_de.c +++ b/drivers/gpu/drm/i915/display/intel_de.c @@ -10,9 +10,9 @@ #include "intel_de.h" static int __intel_de_wait_for_register(struct intel_display *display, - i915_reg_t reg, u32 mask, u32 value, + intel_reg_t reg, u32 mask, u32 value, unsigned int timeout_us, - u32 (*read)(struct intel_display *display, i915_reg_t reg), + u32 (*read)(struct intel_display *display, intel_reg_t reg), u32 *out_val, bool is_atomic) { const ktime_t end = ktime_add_us(ktime_get_raw(), timeout_us); @@ -61,10 +61,10 @@ static int __intel_de_wait_for_register(struct intel_display *display, } static int intel_de_wait_for_register(struct intel_display *display, - i915_reg_t reg, u32 mask, u32 value, + intel_reg_t reg, u32 mask, u32 value, unsigned int fast_timeout_us, unsigned int slow_timeout_us, - u32 (*read)(struct intel_display *display, i915_reg_t reg), + u32 (*read)(struct intel_display *display, intel_reg_t reg), u32 *out_value, bool is_atomic) { int ret = -EINVAL; @@ -82,7 +82,7 @@ static int intel_de_wait_for_register(struct intel_display *display, return ret; } -int intel_de_wait_us(struct intel_display *display, i915_reg_t reg, +int intel_de_wait_us(struct intel_display *display, intel_reg_t reg, u32 mask, u32 value, unsigned int timeout_us, u32 *out_value) { @@ -100,7 +100,7 @@ int intel_de_wait_us(struct intel_display *display, i915_reg_t reg, return ret; } -int intel_de_wait_ms(struct intel_display *display, i915_reg_t reg, +int intel_de_wait_ms(struct intel_display *display, intel_reg_t reg, u32 mask, u32 value, unsigned int timeout_ms, u32 *out_value) { @@ -118,7 +118,7 @@ int intel_de_wait_ms(struct intel_display *display, i915_reg_t reg, return ret; } -int intel_de_wait_fw_ms(struct intel_display *display, i915_reg_t reg, +int intel_de_wait_fw_ms(struct intel_display *display, intel_reg_t reg, u32 mask, u32 value, unsigned int timeout_ms, u32 *out_value) { @@ -128,7 +128,7 @@ int intel_de_wait_fw_ms(struct intel_display *display, i915_reg_t reg, out_value, false); } -int intel_de_wait_fw_us_atomic(struct intel_display *display, i915_reg_t reg, +int intel_de_wait_fw_us_atomic(struct intel_display *display, intel_reg_t reg, u32 mask, u32 value, unsigned int timeout_us, u32 *out_value) { @@ -138,31 +138,31 @@ int intel_de_wait_fw_us_atomic(struct intel_display *display, i915_reg_t reg, out_value, true); } -int intel_de_wait_for_set_us(struct intel_display *display, i915_reg_t reg, +int intel_de_wait_for_set_us(struct intel_display *display, intel_reg_t reg, u32 mask, unsigned int timeout_us) { return intel_de_wait_us(display, reg, mask, mask, timeout_us, NULL); } -int intel_de_wait_for_clear_us(struct intel_display *display, i915_reg_t reg, +int intel_de_wait_for_clear_us(struct intel_display *display, intel_reg_t reg, u32 mask, unsigned int timeout_us) { return intel_de_wait_us(display, reg, mask, 0, timeout_us, NULL); } -int intel_de_wait_for_set_ms(struct intel_display *display, i915_reg_t reg, +int intel_de_wait_for_set_ms(struct intel_display *display, intel_reg_t reg, u32 mask, unsigned int timeout_ms) { return intel_de_wait_ms(display, reg, mask, mask, timeout_ms, NULL); } -int intel_de_wait_for_clear_ms(struct intel_display *display, i915_reg_t reg, +int intel_de_wait_for_clear_ms(struct intel_display *display, intel_reg_t reg, u32 mask, unsigned int timeout_ms) { return intel_de_wait_ms(display, reg, mask, 0, timeout_ms, NULL); } -u8 intel_de_read8(struct intel_display *display, i915_reg_t reg) +u8 intel_de_read8(struct intel_display *display, intel_reg_t reg) { /* this is only used on VGA registers (possible on pre-g4x) */ drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 5 || display->platform.g4x); @@ -170,14 +170,14 @@ u8 intel_de_read8(struct intel_display *display, i915_reg_t reg) return intel_uncore_read8(__to_uncore(display), reg); } -void intel_de_write8(struct intel_display *display, i915_reg_t reg, u8 val) +void intel_de_write8(struct intel_display *display, intel_reg_t reg, u8 val) { drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 5 || display->platform.g4x); intel_uncore_write8(__to_uncore(display), reg, val); } -u16 intel_de_read16(struct intel_display *display, i915_reg_t reg) +u16 intel_de_read16(struct intel_display *display, intel_reg_t reg) { /* this is only used on MCHBAR registers on pre-SNB */ drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 6); diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h index 14f9dc7b6dfd..d17f14843f98 100644 --- a/drivers/gpu/drm/i915/display/intel_de.h +++ b/drivers/gpu/drm/i915/display/intel_de.h @@ -17,12 +17,12 @@ static inline struct intel_uncore *__to_uncore(struct intel_display *display) return to_intel_uncore(display->drm); } -u8 intel_de_read8(struct intel_display *display, i915_reg_t reg); -void intel_de_write8(struct intel_display *display, i915_reg_t reg, u8 val); -u16 intel_de_read16(struct intel_display *display, i915_reg_t reg); +u8 intel_de_read8(struct intel_display *display, intel_reg_t reg); +void intel_de_write8(struct intel_display *display, intel_reg_t reg, u8 val); +u16 intel_de_read16(struct intel_display *display, intel_reg_t reg); static inline u32 -intel_de_read(struct intel_display *display, i915_reg_t reg) +intel_de_read(struct intel_display *display, intel_reg_t reg) { u32 val; @@ -37,7 +37,7 @@ intel_de_read(struct intel_display *display, i915_reg_t reg) static inline u64 intel_de_read64_2x32_volatile(struct intel_display *display, - i915_reg_t lower_reg, i915_reg_t upper_reg) + intel_reg_t lower_reg, intel_reg_t upper_reg) { u64 val; @@ -54,9 +54,9 @@ intel_de_read64_2x32_volatile(struct intel_display *display, } static inline u64 -intel_de_read64_2x32(struct intel_display *display, i915_reg_t reg) +intel_de_read64_2x32(struct intel_display *display, intel_reg_t reg) { - i915_reg_t upper_reg = _MMIO(i915_mmio_reg_offset(reg) + 4); + intel_reg_t upper_reg = _MMIO(i915_mmio_reg_offset(reg) + 4); u32 lower, upper; lower = intel_de_read(display, reg); @@ -66,7 +66,7 @@ intel_de_read64_2x32(struct intel_display *display, i915_reg_t reg) } static inline void -intel_de_posting_read(struct intel_display *display, i915_reg_t reg) +intel_de_posting_read(struct intel_display *display, intel_reg_t reg) { intel_dmc_wl_get(display, reg); @@ -76,7 +76,7 @@ intel_de_posting_read(struct intel_display *display, i915_reg_t reg) } static inline void -intel_de_write(struct intel_display *display, i915_reg_t reg, u32 val) +intel_de_write(struct intel_display *display, intel_reg_t reg, u32 val) { intel_dmc_wl_get(display, reg); @@ -86,7 +86,7 @@ intel_de_write(struct intel_display *display, i915_reg_t reg, u32 val) } static inline u32 -intel_de_rmw(struct intel_display *display, i915_reg_t reg, u32 clear, u32 set) +intel_de_rmw(struct intel_display *display, intel_reg_t reg, u32 clear, u32 set) { u32 val; @@ -99,25 +99,25 @@ intel_de_rmw(struct intel_display *display, i915_reg_t reg, u32 clear, u32 set) return val; } -int intel_de_wait_us(struct intel_display *display, i915_reg_t reg, +int intel_de_wait_us(struct intel_display *display, intel_reg_t reg, u32 mask, u32 value, unsigned int timeout_us, u32 *out_value); -int intel_de_wait_ms(struct intel_display *display, i915_reg_t reg, +int intel_de_wait_ms(struct intel_display *display, intel_reg_t reg, u32 mask, u32 value, unsigned int timeout_ms, u32 *out_value); -int intel_de_wait_fw_ms(struct intel_display *display, i915_reg_t reg, +int intel_de_wait_fw_ms(struct intel_display *display, intel_reg_t reg, u32 mask, u32 value, unsigned int timeout_ms, u32 *out_value); -int intel_de_wait_fw_us_atomic(struct intel_display *display, i915_reg_t reg, +int intel_de_wait_fw_us_atomic(struct intel_display *display, intel_reg_t reg, u32 mask, u32 value, unsigned int timeout_us, u32 *out_value); -int intel_de_wait_for_set_us(struct intel_display *display, i915_reg_t reg, +int intel_de_wait_for_set_us(struct intel_display *display, intel_reg_t reg, u32 mask, unsigned int timeout_us); -int intel_de_wait_for_clear_us(struct intel_display *display, i915_reg_t reg, +int intel_de_wait_for_clear_us(struct intel_display *display, intel_reg_t reg, u32 mask, unsigned int timeout_us); -int intel_de_wait_for_set_ms(struct intel_display *display, i915_reg_t reg, +int intel_de_wait_for_set_ms(struct intel_display *display, intel_reg_t reg, u32 mask, unsigned int timeout_ms); -int intel_de_wait_for_clear_ms(struct intel_display *display, i915_reg_t reg, +int intel_de_wait_for_clear_ms(struct intel_display *display, intel_reg_t reg, u32 mask, unsigned int timeout_ms); /* @@ -129,7 +129,7 @@ int intel_de_wait_for_clear_ms(struct intel_display *display, i915_reg_t reg, * a more localised lock guarding all access to that bank of registers. */ static inline u32 -intel_de_read_fw(struct intel_display *display, i915_reg_t reg) +intel_de_read_fw(struct intel_display *display, intel_reg_t reg) { u32 val; @@ -140,14 +140,14 @@ intel_de_read_fw(struct intel_display *display, i915_reg_t reg) } static inline void -intel_de_write_fw(struct intel_display *display, i915_reg_t reg, u32 val) +intel_de_write_fw(struct intel_display *display, intel_reg_t reg, u32 val) { trace_i915_reg_rw(true, reg, val, sizeof(val), true); intel_uncore_write_fw(__to_uncore(display), reg, val); } static inline u32 -intel_de_rmw_fw(struct intel_display *display, i915_reg_t reg, u32 clear, u32 set) +intel_de_rmw_fw(struct intel_display *display, intel_reg_t reg, u32 clear, u32 set) { u32 old, val; @@ -159,20 +159,20 @@ intel_de_rmw_fw(struct intel_display *display, i915_reg_t reg, u32 clear, u32 se } static inline u32 -intel_de_read_notrace(struct intel_display *display, i915_reg_t reg) +intel_de_read_notrace(struct intel_display *display, intel_reg_t reg) { return intel_uncore_read_notrace(__to_uncore(display), reg); } static inline void -intel_de_write_notrace(struct intel_display *display, i915_reg_t reg, u32 val) +intel_de_write_notrace(struct intel_display *display, intel_reg_t reg, u32 val) { intel_uncore_write_notrace(__to_uncore(display), reg, val); } static __always_inline void intel_de_write_dsb(struct intel_display *display, struct intel_dsb *dsb, - i915_reg_t reg, u32 val) + intel_reg_t reg, u32 val) { if (dsb) intel_dsb_reg_write(dsb, reg, val); diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 10b6c6fcb03f..c621ad79cd1f 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2601,8 +2601,8 @@ void intel_zero_m_n(struct intel_link_m_n *m_n) void intel_set_m_n(struct intel_display *display, const struct intel_link_m_n *m_n, - i915_reg_t data_m_reg, i915_reg_t data_n_reg, - i915_reg_t link_m_reg, i915_reg_t link_n_reg) + intel_reg_t data_m_reg, intel_reg_t data_n_reg, + intel_reg_t link_m_reg, intel_reg_t link_n_reg) { intel_de_write(display, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); intel_de_write(display, data_n_reg, m_n->data_n); @@ -3364,8 +3364,8 @@ int ilk_get_lanes_required(int target_clock, int link_bw, int bpp) void intel_get_m_n(struct intel_display *display, struct intel_link_m_n *m_n, - i915_reg_t data_m_reg, i915_reg_t data_n_reg, - i915_reg_t link_m_reg, i915_reg_t link_n_reg) + intel_reg_t data_m_reg, intel_reg_t data_n_reg, + intel_reg_t link_m_reg, intel_reg_t link_n_reg) { m_n->link_m = intel_de_read(display, link_m_reg) & DATA_LINK_M_N_MASK; m_n->link_n = intel_de_read(display, link_n_reg) & DATA_LINK_M_N_MASK; diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index 552a59d19e0f..fafd9044dfd6 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -27,7 +27,7 @@ #include <drm/drm_util.h> -#include "i915_reg_defs.h" +#include "intel_display_reg_defs.h" #include "intel_display_limits.h" struct drm_atomic_state; @@ -440,12 +440,12 @@ bool intel_fuzzy_clock_check(int clock1, int clock2); void intel_zero_m_n(struct intel_link_m_n *m_n); void intel_set_m_n(struct intel_display *display, const struct intel_link_m_n *m_n, - i915_reg_t data_m_reg, i915_reg_t data_n_reg, - i915_reg_t link_m_reg, i915_reg_t link_n_reg); + intel_reg_t data_m_reg, intel_reg_t data_n_reg, + intel_reg_t link_m_reg, intel_reg_t link_n_reg); void intel_get_m_n(struct intel_display *display, struct intel_link_m_n *m_n, - i915_reg_t data_m_reg, i915_reg_t data_n_reg, - i915_reg_t link_m_reg, i915_reg_t link_n_reg); + intel_reg_t data_m_reg, intel_reg_t data_n_reg, + intel_reg_t link_m_reg, intel_reg_t link_n_reg); bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display, enum transcoder transcoder); void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index 70c1bba7c0a8..365e467dddaf 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -47,7 +47,7 @@ static void irq_reset(struct intel_display *display, struct i915_irq_regs regs) /* * We should clear IMR at preinstall/uninstall, and just check at postinstall. */ -static void assert_iir_is_zero(struct intel_display *display, i915_reg_t reg) +static void assert_iir_is_zero(struct intel_display *display, intel_reg_t reg) { u32 val = intel_de_read(display, reg); @@ -343,7 +343,7 @@ u32 i915_pipestat_enable_mask(struct intel_display *display, void i915_enable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask) { - i915_reg_t reg = PIPESTAT(display, pipe); + intel_reg_t reg = PIPESTAT(display, pipe); u32 enable_mask; drm_WARN_ONCE(display->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK, @@ -366,7 +366,7 @@ void i915_enable_pipestat(struct intel_display *display, void i915_disable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask) { - i915_reg_t reg = PIPESTAT(display, pipe); + intel_reg_t reg = PIPESTAT(display, pipe); u32 enable_mask; drm_WARN_ONCE(display->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK, @@ -543,7 +543,7 @@ void i9xx_pipestat_irq_ack(struct intel_display *display, } for_each_pipe(display, pipe) { - i915_reg_t reg; + intel_reg_t reg; u32 status_mask, enable_mask, iir_bit = 0; /* @@ -1284,7 +1284,7 @@ gen8_de_misc_irq_handler(struct intel_display *display, u32 iir) if (iir & GEN8_DE_EDP_PSR) { struct intel_encoder *encoder; u32 psr_iir; - i915_reg_t iir_reg; + intel_reg_t iir_reg; for_each_intel_encoder_with_psr(display->drm, encoder) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 4091b7c4914f..81fe5a67b07d 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -1069,7 +1069,7 @@ static void intel_power_domains_sync_hw(struct intel_display *display) static void gen9_dbuf_slice_set(struct intel_display *display, enum dbuf_slice slice, bool enable) { - i915_reg_t reg = DBUF_CTL_S(slice); + intel_reg_t reg = DBUF_CTL_S(slice); bool state; intel_de_rmw(display, reg, DBUF_POWER_REQUEST, @@ -1428,7 +1428,7 @@ static void hsw_disable_pc8(struct intel_display *display) static void intel_pch_reset_handshake(struct intel_display *display, bool enable) { - i915_reg_t reg; + intel_reg_t reg; u32 reset_bits; if (DISPLAY_VER(display) >= 35) diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c index 6fbfd46461b0..04bd0dde5bed 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c @@ -49,10 +49,10 @@ static enum skl_power_gate pw_idx_to_pg(struct intel_display *display, int pw_id } struct i915_power_well_regs { - i915_reg_t bios; - i915_reg_t driver; - i915_reg_t kvmr; - i915_reg_t debug; + intel_reg_t bios; + intel_reg_t driver; + intel_reg_t kvmr; + intel_reg_t debug; }; struct i915_power_well_ops { diff --git a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h index 175334b41bba..cb46863693cd 100644 --- a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h +++ b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h @@ -8,6 +8,8 @@ #include "i915_reg_defs.h" +typedef i915_reg_t intel_reg_t; + #define VLV_DISPLAY_BASE 0x180000 /* diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index e2496db1642a..677824ac0ffe 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1661,7 +1661,7 @@ struct intel_plane { container_of_const((fb), struct intel_framebuffer, base) struct intel_hdmi { - i915_reg_t hdmi_reg; + intel_reg_t hdmi_reg; struct { enum drm_dp_dual_mode_type type; int max_tmds_clock; @@ -1791,7 +1791,7 @@ struct intel_psr { }; struct intel_dp { - i915_reg_t output_reg; + intel_reg_t output_reg; u32 DP; int link_rate; u8 lane_count; @@ -1888,8 +1888,8 @@ struct intel_dp { u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes, u32 aux_clock_divider); - i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp); - i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index); + intel_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp); + intel_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index); /* This is called before a link training is starterd */ void (*prepare_link_retrain)(struct intel_dp *intel_dp, diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c index 2104164e136e..665842fb9eae 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -71,7 +71,7 @@ struct intel_dmc { } dc6_allowed; struct dmc_fw_info { u32 mmio_count; - i915_reg_t mmioaddr[20]; + intel_reg_t mmioaddr[20]; u32 mmiodata[20]; u32 dmc_offset; u32 start_mmioaddr; @@ -434,7 +434,7 @@ static void gen9_set_dc_state_debugmask(struct intel_display *display) } static void disable_event_handler(struct intel_display *display, - i915_reg_t ctl_reg, i915_reg_t htp_reg) + intel_reg_t ctl_reg, intel_reg_t htp_reg) { intel_de_write(display, ctl_reg, REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, @@ -538,7 +538,7 @@ static u32 dmc_evt_ctl_disable(u32 dmc_evt_ctl) } static bool is_dmc_evt_ctl_reg(struct intel_display *display, - enum intel_dmc_id dmc_id, i915_reg_t reg) + enum intel_dmc_id dmc_id, intel_reg_t reg) { u32 offset = i915_mmio_reg_offset(reg); u32 start = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, 0)); @@ -548,7 +548,7 @@ static bool is_dmc_evt_ctl_reg(struct intel_display *display, } static bool is_dmc_evt_htp_reg(struct intel_display *display, - enum intel_dmc_id dmc_id, i915_reg_t reg) + enum intel_dmc_id dmc_id, intel_reg_t reg) { u32 offset = i915_mmio_reg_offset(reg); u32 start = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, 0)); @@ -560,7 +560,7 @@ static bool is_dmc_evt_htp_reg(struct intel_display *display, static bool is_event_handler(struct intel_display *display, enum intel_dmc_id dmc_id, unsigned int event_id, - i915_reg_t reg, u32 data) + intel_reg_t reg, u32 data) { return is_dmc_evt_ctl_reg(display, dmc_id, reg) && REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == event_id; @@ -568,8 +568,8 @@ static bool is_event_handler(struct intel_display *display, static bool fixup_dmc_evt(struct intel_display *display, enum intel_dmc_id dmc_id, - i915_reg_t reg_ctl, u32 *data_ctl, - i915_reg_t reg_htp, u32 *data_htp) + intel_reg_t reg_ctl, u32 *data_ctl, + intel_reg_t reg_htp, u32 *data_htp) { if (!is_dmc_evt_ctl_reg(display, dmc_id, reg_ctl)) return false; @@ -613,7 +613,7 @@ static bool fixup_dmc_evt(struct intel_display *display, static bool disable_dmc_evt(struct intel_display *display, enum intel_dmc_id dmc_id, - i915_reg_t reg, u32 data) + intel_reg_t reg, u32 data) { if (!is_dmc_evt_ctl_reg(display, dmc_id, reg)) return false; @@ -696,7 +696,7 @@ static void assert_dmc_loaded(struct intel_display *display, dmc_id, expected, found); for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) { - i915_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i]; + intel_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i]; found = intel_de_read(display, reg); expected = dmc_mmiodata(display, dmc, dmc_id, i); @@ -847,7 +847,7 @@ static void dmc_configure_event(struct intel_display *display, int i; for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) { - i915_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i]; + intel_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i]; u32 data = dmc->dmc_info[dmc_id].mmiodata[i]; if (!is_event_handler(display, dmc_id, event_id, reg, data)) @@ -1618,7 +1618,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused) struct intel_display *display = m->private; struct intel_dmc *dmc = display_to_dmc(display); struct ref_tracker *wakeref; - i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG; + intel_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG; u32 dc6_allowed_count; if (!HAS_DMC(display)) @@ -1647,7 +1647,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused) DMC_VERSION_MINOR(dmc->version)); if (DISPLAY_VER(display) >= 12) { - i915_reg_t dc3co_reg; + intel_reg_t dc3co_reg; if (display->platform.dgfx || DISPLAY_VER(display) >= 14) { dc3co_reg = DG1_DMC_DEBUG3; diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm/i915/display/intel_dmc_wl.c index 73a3101514f3..763f004700ba 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c @@ -224,7 +224,7 @@ static void __intel_dmc_wl_take(struct intel_display *display) wl->taken = true; } -static bool intel_dmc_wl_reg_in_range(i915_reg_t reg, +static bool intel_dmc_wl_reg_in_range(intel_reg_t reg, const struct intel_dmc_wl_range ranges[]) { u32 offset = i915_mmio_reg_offset(reg); @@ -240,7 +240,7 @@ static bool intel_dmc_wl_reg_in_range(i915_reg_t reg, } static bool intel_dmc_wl_check_range(struct intel_display *display, - i915_reg_t reg, + intel_reg_t reg, u32 dc_state) { const struct intel_dmc_wl_range *ranges; @@ -431,7 +431,7 @@ void intel_dmc_wl_flush_release_work(struct intel_display *display) flush_delayed_work(&wl->work); } -void intel_dmc_wl_get(struct intel_display *display, i915_reg_t reg) +void intel_dmc_wl_get(struct intel_display *display, intel_reg_t reg) { struct intel_dmc_wl *wl = &display->wl; unsigned long flags; @@ -464,7 +464,7 @@ void intel_dmc_wl_get(struct intel_display *display, i915_reg_t reg) spin_unlock_irqrestore(&wl->lock, flags); } -void intel_dmc_wl_put(struct intel_display *display, i915_reg_t reg) +void intel_dmc_wl_put(struct intel_display *display, intel_reg_t reg) { struct intel_dmc_wl *wl = &display->wl; unsigned long flags; diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.h b/drivers/gpu/drm/i915/display/intel_dmc_wl.h index 5488fbdf29b8..215107f0a4f9 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.h +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.h @@ -10,7 +10,7 @@ #include <linux/workqueue.h> #include <linux/refcount.h> -#include "i915_reg_defs.h" +#include "intel_display_reg_defs.h" struct intel_display; @@ -33,8 +33,8 @@ void intel_dmc_wl_init(struct intel_display *display); void intel_dmc_wl_enable(struct intel_display *display, u32 dc_state); void intel_dmc_wl_disable(struct intel_display *display); void intel_dmc_wl_flush_release_work(struct intel_display *display); -void intel_dmc_wl_get(struct intel_display *display, i915_reg_t reg); -void intel_dmc_wl_put(struct intel_display *display, i915_reg_t reg); +void intel_dmc_wl_get(struct intel_display *display, intel_reg_t reg); +void intel_dmc_wl_put(struct intel_display *display, intel_reg_t reg); void intel_dmc_wl_get_noreg(struct intel_display *display); void intel_dmc_wl_put_noreg(struct intel_display *display); diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 4955bd8b11d7..c3e483293618 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5239,7 +5239,7 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder, const struct drm_connector_state *conn_state) { struct intel_display *display = to_intel_display(encoder); - i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display, crtc_state->cpu_transcoder); + intel_reg_t reg = HSW_TVIDEO_DIP_CTL(display, crtc_state->cpu_transcoder); u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK; diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c index b20ec3e589fa..ef33ecd81f28 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c @@ -58,7 +58,7 @@ static u32 intel_dp_aux_wait_done(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); - i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); + intel_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); const unsigned int timeout_ms = 10; u32 status; bool done; @@ -244,7 +244,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp, struct intel_display *display = to_intel_display(intel_dp); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct intel_encoder *encoder = &dig_port->base; - i915_reg_t ch_ctl, ch_data[5]; + intel_reg_t ch_ctl, ch_data[5]; u32 aux_clock_divider; enum intel_display_power_domain aux_domain; struct ref_tracker *aux_wakeref; @@ -554,7 +554,7 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) return ret; } -static i915_reg_t vlv_aux_ctl_reg(struct intel_dp *intel_dp) +static intel_reg_t vlv_aux_ctl_reg(struct intel_dp *intel_dp) { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); enum aux_ch aux_ch = dig_port->aux_ch; @@ -570,7 +570,7 @@ static i915_reg_t vlv_aux_ctl_reg(struct intel_dp *intel_dp) } } -static i915_reg_t vlv_aux_data_reg(struct intel_dp *intel_dp, int index) +static intel_reg_t vlv_aux_data_reg(struct intel_dp *intel_dp, int index) { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); enum aux_ch aux_ch = dig_port->aux_ch; @@ -586,7 +586,7 @@ static i915_reg_t vlv_aux_data_reg(struct intel_dp *intel_dp, int index) } } -static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp) +static intel_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp) { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); enum aux_ch aux_ch = dig_port->aux_ch; @@ -602,7 +602,7 @@ static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp) } } -static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index) +static intel_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index) { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); enum aux_ch aux_ch = dig_port->aux_ch; @@ -618,7 +618,7 @@ static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index) } } -static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp) +static intel_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp) { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); enum aux_ch aux_ch = dig_port->aux_ch; @@ -636,7 +636,7 @@ static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp) } } -static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index) +static intel_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index) { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); enum aux_ch aux_ch = dig_port->aux_ch; @@ -654,7 +654,7 @@ static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index) } } -static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp) +static intel_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp) { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); enum aux_ch aux_ch = dig_port->aux_ch; @@ -673,7 +673,7 @@ static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp) } } -static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index) +static intel_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index) { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); enum aux_ch aux_ch = dig_port->aux_ch; @@ -692,7 +692,7 @@ static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index) } } -static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp) +static intel_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp) { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); enum aux_ch aux_ch = dig_port->aux_ch; @@ -714,7 +714,7 @@ static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp) } } -static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index) +static intel_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index) { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); enum aux_ch aux_ch = dig_port->aux_ch; @@ -736,7 +736,7 @@ static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index) } } -static i915_reg_t xelpdp_aux_ctl_reg(struct intel_dp *intel_dp) +static intel_reg_t xelpdp_aux_ctl_reg(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); @@ -756,7 +756,7 @@ static i915_reg_t xelpdp_aux_ctl_reg(struct intel_dp *intel_dp) } } -static i915_reg_t xelpdp_aux_data_reg(struct intel_dp *intel_dp, int index) +static intel_reg_t xelpdp_aux_data_reg(struct intel_dp *intel_dp, int index) { struct intel_display *display = to_intel_display(intel_dp); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c index 0e16132d0923..ae5a7ac3dbcd 100644 --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c @@ -279,8 +279,8 @@ void bxt_port_to_phy_channel(struct intel_display *display, enum port port, * writes to the group register to write the same value to all the lanes. */ static u32 bxt_dpio_phy_rmw_grp(struct intel_display *display, - i915_reg_t reg_single, - i915_reg_t reg_group, + intel_reg_t reg_single, + intel_reg_t reg_group, u32 clear, u32 set) { u32 old, val; @@ -512,7 +512,7 @@ void bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy) static bool __printf(6, 7) __phy_reg_verify_state(struct intel_display *display, enum dpio_phy phy, - i915_reg_t reg, u32 mask, u32 expected, + intel_reg_t reg, u32 mask, u32 expected, const char *reg_fmt, ...) { struct va_format vaf; @@ -1172,7 +1172,7 @@ void vlv_wait_port_ready(struct intel_encoder *encoder, { struct intel_display *display = to_intel_display(encoder); u32 port_mask; - i915_reg_t dpll_reg; + intel_reg_t dpll_reg; u32 val; switch (encoder->port) { diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index f5d4f7146fbc..dba8eeb4de4b 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -220,7 +220,7 @@ enum intel_dpll_id mtl_port_to_pll_id(struct intel_display *display, enum port p } } -static i915_reg_t +static intel_reg_t intel_combo_pll_enable_reg(struct intel_display *display, struct intel_dpll *pll) { @@ -233,7 +233,7 @@ intel_combo_pll_enable_reg(struct intel_display *display, return ICL_DPLL_ENABLE(pll->info->id); } -static i915_reg_t +static intel_reg_t intel_tc_pll_enable_reg(struct intel_display *display, struct intel_dpll *pll) { @@ -1350,7 +1350,7 @@ static const struct intel_dpll_mgr hsw_pll_mgr = { }; struct skl_dpll_regs { - i915_reg_t ctl, cfgcr1, cfgcr2; + intel_reg_t ctl, cfgcr1, cfgcr2; }; /* this array is indexed by the *shared* pll id */ @@ -3603,7 +3603,7 @@ static bool mg_pll_get_hw_state(struct intel_display *display, bool ret = false; u32 val; - i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll); + intel_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll); wakeref = intel_display_power_get_if_enabled(display, POWER_DOMAIN_DISPLAY_CORE); @@ -3734,7 +3734,7 @@ static bool dkl_pll_get_hw_state(struct intel_display *display, static bool icl_pll_get_hw_state(struct intel_display *display, struct intel_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state, - i915_reg_t enable_reg) + intel_reg_t enable_reg) { struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; const enum intel_dpll_id id = pll->info->id; @@ -3796,7 +3796,7 @@ static bool combo_pll_get_hw_state(struct intel_display *display, struct intel_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { - i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll); + intel_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll); return icl_pll_get_hw_state(display, pll, dpll_hw_state, enable_reg); } @@ -3813,7 +3813,7 @@ static void icl_dpll_write(struct intel_display *display, const struct icl_dpll_hw_state *hw_state) { const enum intel_dpll_id id = pll->info->id; - i915_reg_t cfgcr0_reg, cfgcr1_reg, div0_reg = INVALID_MMIO_REG; + intel_reg_t cfgcr0_reg, cfgcr1_reg, div0_reg = INVALID_MMIO_REG; if (display->platform.alderlake_s) { cfgcr0_reg = ADLS_DPLL_CFGCR0(id); @@ -3960,7 +3960,7 @@ static void dkl_pll_write(struct intel_display *display, static void icl_pll_power_enable(struct intel_display *display, struct intel_dpll *pll, - i915_reg_t enable_reg) + intel_reg_t enable_reg) { intel_de_rmw(display, enable_reg, 0, PLL_POWER_ENABLE); @@ -3975,7 +3975,7 @@ static void icl_pll_power_enable(struct intel_display *display, static void icl_pll_enable(struct intel_display *display, struct intel_dpll *pll, - i915_reg_t enable_reg) + intel_reg_t enable_reg) { intel_de_rmw(display, enable_reg, 0, PLL_ENABLE); @@ -4013,7 +4013,7 @@ static void combo_pll_enable(struct intel_display *display, const struct intel_dpll_hw_state *dpll_hw_state) { const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; - i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll); + intel_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll); icl_pll_power_enable(display, pll, enable_reg); @@ -4058,7 +4058,7 @@ static void mg_pll_enable(struct intel_display *display, const struct intel_dpll_hw_state *dpll_hw_state) { const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; - i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll); + intel_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll); icl_pll_power_enable(display, pll, enable_reg); @@ -4080,7 +4080,7 @@ static void mg_pll_enable(struct intel_display *display, static void icl_pll_disable(struct intel_display *display, struct intel_dpll *pll, - i915_reg_t enable_reg) + intel_reg_t enable_reg) { /* The first steps are done by intel_ddi_post_disable(). */ @@ -4112,7 +4112,7 @@ static void icl_pll_disable(struct intel_display *display, static void combo_pll_disable(struct intel_display *display, struct intel_dpll *pll) { - i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll); + intel_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll); icl_pll_disable(display, pll, enable_reg); } @@ -4126,7 +4126,7 @@ static void icl_tbt_pll_disable(struct intel_display *display, static void mg_pll_disable(struct intel_display *display, struct intel_dpll *pll) { - i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll); + intel_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll); icl_pll_disable(display, pll, enable_reg); } diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index c8d3968f659f..ce4d452ae695 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -326,7 +326,7 @@ static void intel_dsb_emit(struct intel_dsb *dsb, u32 ldw, u32 udw) } static bool intel_dsb_prev_ins_is_write(struct intel_dsb *dsb, - u32 opcode, i915_reg_t reg) + u32 opcode, intel_reg_t reg) { u32 prev_opcode, prev_reg; @@ -344,7 +344,7 @@ static bool intel_dsb_prev_ins_is_write(struct intel_dsb *dsb, return prev_opcode == opcode && prev_reg == i915_mmio_reg_offset(reg); } -static bool intel_dsb_prev_ins_is_indexed_write(struct intel_dsb *dsb, i915_reg_t reg) +static bool intel_dsb_prev_ins_is_indexed_write(struct intel_dsb *dsb, intel_reg_t reg) { return intel_dsb_prev_ins_is_write(dsb, DSB_OPCODE_INDEXED_WRITE << DSB_OPCODE_SHIFT, @@ -365,7 +365,7 @@ static bool intel_dsb_prev_ins_is_indexed_write(struct intel_dsb *dsb, i915_reg_ * register. */ void intel_dsb_reg_write_indexed(struct intel_dsb *dsb, - i915_reg_t reg, u32 val) + intel_reg_t reg, u32 val) { /* * For example the buffer will look like below for 3 dwords for auto @@ -402,7 +402,7 @@ void intel_dsb_reg_write_indexed(struct intel_dsb *dsb, } void intel_dsb_reg_write(struct intel_dsb *dsb, - i915_reg_t reg, u32 val) + intel_reg_t reg, u32 val) { intel_dsb_emit(dsb, val, (DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT) | @@ -420,7 +420,7 @@ static u32 intel_dsb_mask_to_byte_en(u32 mask) /* Note: mask implemented via byte enables! */ void intel_dsb_reg_write_masked(struct intel_dsb *dsb, - i915_reg_t reg, u32 mask, u32 val) + intel_reg_t reg, u32 mask, u32 val) { intel_dsb_emit(dsb, val, (DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT) | @@ -550,7 +550,7 @@ void intel_dsb_wait_scanline_out(struct intel_atomic_state *state, } void intel_dsb_poll(struct intel_dsb *dsb, - i915_reg_t reg, u32 mask, u32 val, + intel_reg_t reg, u32 mask, u32 val, int wait_us, int count) { struct intel_crtc *crtc = dsb->crtc; diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h index 386a5a942572..3dcca9ed5371 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.h +++ b/drivers/gpu/drm/i915/display/intel_dsb.h @@ -8,7 +8,7 @@ #include <linux/types.h> -#include "i915_reg_defs.h" +#include "intel_display_reg_defs.h" struct intel_atomic_state; struct intel_crtc; @@ -37,11 +37,11 @@ void intel_dsb_gosub_finish(struct intel_dsb *dsb); void intel_dsb_cleanup(struct intel_dsb *dsb); int intel_dsb_exec_time_us(void); void intel_dsb_reg_write(struct intel_dsb *dsb, - i915_reg_t reg, u32 val); + intel_reg_t reg, u32 val); void intel_dsb_reg_write_indexed(struct intel_dsb *dsb, - i915_reg_t reg, u32 val); + intel_reg_t reg, u32 val); void intel_dsb_reg_write_masked(struct intel_dsb *dsb, - i915_reg_t reg, u32 mask, u32 val); + intel_reg_t reg, u32 mask, u32 val); void intel_dsb_noop(struct intel_dsb *dsb, int count); void intel_dsb_nonpost_start(struct intel_dsb *dsb); void intel_dsb_nonpost_end(struct intel_dsb *dsb); @@ -59,7 +59,7 @@ void intel_dsb_wait_scanline_out(struct intel_atomic_state *state, void intel_dsb_vblank_evade(struct intel_atomic_state *state, struct intel_dsb *dsb); void intel_dsb_poll(struct intel_dsb *dsb, - i915_reg_t reg, u32 mask, u32 val, + intel_reg_t reg, u32 mask, u32 val, int wait_us, int count); void intel_dsb_gosub(struct intel_dsb *dsb, struct intel_dsb *sub_dsb); diff --git a/drivers/gpu/drm/i915/display/intel_dvo_dev.h b/drivers/gpu/drm/i915/display/intel_dvo_dev.h index f1e939aaf7fa..1f049f79a534 100644 --- a/drivers/gpu/drm/i915/display/intel_dvo_dev.h +++ b/drivers/gpu/drm/i915/display/intel_dvo_dev.h @@ -23,7 +23,7 @@ #ifndef __INTEL_DVO_DEV_H__ #define __INTEL_DVO_DEV_H__ -#include "i915_reg_defs.h" +#include "intel_display_reg_defs.h" #include "intel_display_limits.h" diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c index 24ce8a7842c7..86975ff0d2f0 100644 --- a/drivers/gpu/drm/i915/display/intel_fdi.c +++ b/drivers/gpu/drm/i915/display/intel_fdi.c @@ -438,7 +438,7 @@ void intel_fdi_normal_train(struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(crtc); enum pipe pipe = crtc->pipe; - i915_reg_t reg; + intel_reg_t reg; u32 temp; /* enable normal train */ @@ -479,7 +479,7 @@ static void ilk_fdi_link_train(struct intel_crtc *crtc, { struct intel_display *display = to_intel_display(crtc); enum pipe pipe = crtc->pipe; - i915_reg_t reg; + intel_reg_t reg; u32 temp, tries; /* @@ -580,7 +580,7 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc, { struct intel_display *display = to_intel_display(crtc); enum pipe pipe = crtc->pipe; - i915_reg_t reg; + intel_reg_t reg; u32 temp, i, retry; /* @@ -715,7 +715,7 @@ static void ivb_manual_fdi_link_train(struct intel_crtc *crtc, { struct intel_display *display = to_intel_display(crtc); enum pipe pipe = crtc->pipe; - i915_reg_t reg; + intel_reg_t reg; u32 temp, i, j; ivb_update_fdi_bc_bifurcation(crtc_state); @@ -996,7 +996,7 @@ void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state) struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); enum pipe pipe = crtc->pipe; - i915_reg_t reg; + intel_reg_t reg; u32 temp; /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ @@ -1049,7 +1049,7 @@ void ilk_fdi_disable(struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(crtc); enum pipe pipe = crtc->pipe; - i915_reg_t reg; + intel_reg_t reg; u32 temp; /* disable CPU FDI tx and PCH FDI rx */ diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c index bf047180def9..02013e89d8f2 100644 --- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c +++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c @@ -189,7 +189,7 @@ static bool cpt_can_enable_serr_int(struct intel_display *display) static void i9xx_check_fifo_underruns(struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(crtc); - i915_reg_t reg = PIPESTAT(display, crtc->pipe); + intel_reg_t reg = PIPESTAT(display, crtc->pipe); u32 enable_mask; lockdep_assert_held(&display->irq.lock); @@ -209,7 +209,7 @@ static void i9xx_set_fifo_underrun_reporting(struct intel_display *display, enum pipe pipe, bool enable, bool old) { - i915_reg_t reg = PIPESTAT(display, pipe); + intel_reg_t reg = PIPESTAT(display, pipe); lockdep_assert_held(&display->irq.lock); diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c index ea5cf8f51b31..049157c41fe2 100644 --- a/drivers/gpu/drm/i915/display/intel_gmbus.c +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c @@ -48,7 +48,7 @@ struct intel_gmbus { #define GMBUS_FORCE_BIT_RETRY (1U << 31) u32 force_bit; u32 reg0; - i915_reg_t gpio_reg; + intel_reg_t gpio_reg; struct i2c_algo_bit_data bit_algo; struct intel_display *display; }; @@ -368,7 +368,7 @@ intel_gpio_post_xfer(struct i2c_adapter *adapter) } static void -intel_gpio_setup(struct intel_gmbus *bus, i915_reg_t gpio_reg) +intel_gpio_setup(struct intel_gmbus *bus, intel_reg_t gpio_reg) { struct i2c_algo_bit_data *algo; diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index 892eab4b6f92..8896faf4f96b 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -46,7 +46,7 @@ intel_hdcp_adjust_hdcp_line_rekeying(struct intel_encoder *encoder, bool enable) { struct intel_display *display = to_intel_display(encoder); - i915_reg_t rekey_reg; + intel_reg_t rekey_reg; u32 rekey_bit = 0; /* Here we assume HDMI is in TMDS mode of operation */ diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 05e898d10a2b..6fc022c76828 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -173,7 +173,7 @@ static u32 hsw_infoframe_enable(unsigned int type) } } -static i915_reg_t +static intel_reg_t hsw_dip_data_reg(struct intel_display *display, enum transcoder cpu_transcoder, unsigned int type, @@ -298,7 +298,7 @@ static void ibx_write_infoframe(struct intel_encoder *encoder, struct intel_display *display = to_intel_display(encoder); const u32 *data = frame; struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); + intel_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); u32 val = intel_de_read(display, reg); int i; @@ -351,7 +351,7 @@ static u32 ibx_infoframes_enabled(struct intel_encoder *encoder, { struct intel_display *display = to_intel_display(encoder); enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; - i915_reg_t reg = TVIDEO_DIP_CTL(pipe); + intel_reg_t reg = TVIDEO_DIP_CTL(pipe); u32 val = intel_de_read(display, reg); if ((val & VIDEO_DIP_ENABLE) == 0) @@ -373,7 +373,7 @@ static void cpt_write_infoframe(struct intel_encoder *encoder, struct intel_display *display = to_intel_display(encoder); const u32 *data = frame; struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); + intel_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); u32 val = intel_de_read(display, reg); int i; @@ -447,7 +447,7 @@ static void vlv_write_infoframe(struct intel_encoder *encoder, struct intel_display *display = to_intel_display(encoder); const u32 *data = frame; struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); + intel_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); u32 val = intel_de_read(display, reg); int i; @@ -523,7 +523,7 @@ void hsw_write_infoframe(struct intel_encoder *encoder, struct intel_display *display = to_intel_display(encoder); const u32 *data = frame; enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; - i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(display, cpu_transcoder); + intel_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(display, cpu_transcoder); int data_size; int i; u32 val = intel_de_read(display, ctl_reg); @@ -884,7 +884,7 @@ static void g4x_set_infoframes(struct intel_encoder *encoder, struct intel_display *display = to_intel_display(encoder); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct intel_hdmi *intel_hdmi = &dig_port->hdmi; - i915_reg_t reg = VIDEO_DIP_CTL; + intel_reg_t reg = VIDEO_DIP_CTL; u32 val = intel_de_read(display, reg); u32 port = VIDEO_DIP_PORT(encoder->port); @@ -995,7 +995,7 @@ static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder, { struct intel_display *display = to_intel_display(encoder); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - i915_reg_t reg; + intel_reg_t reg; if ((crtc_state->infoframes.enable & intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) @@ -1020,7 +1020,7 @@ void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder, { struct intel_display *display = to_intel_display(encoder); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - i915_reg_t reg; + intel_reg_t reg; if ((crtc_state->infoframes.enable & intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) @@ -1069,7 +1069,7 @@ static void ibx_set_infoframes(struct intel_encoder *encoder, struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct intel_hdmi *intel_hdmi = &dig_port->hdmi; - i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); + intel_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); u32 val = intel_de_read(display, reg); u32 port = VIDEO_DIP_PORT(encoder->port); @@ -1127,7 +1127,7 @@ static void cpt_set_infoframes(struct intel_encoder *encoder, struct intel_display *display = to_intel_display(encoder); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); - i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); + intel_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); u32 val = intel_de_read(display, reg); assert_hdmi_port_disabled(intel_hdmi); @@ -1176,7 +1176,7 @@ static void vlv_set_infoframes(struct intel_encoder *encoder, struct intel_display *display = to_intel_display(encoder); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); - i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); + intel_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); u32 val = intel_de_read(display, reg); u32 port = VIDEO_DIP_PORT(encoder->port); @@ -1231,7 +1231,7 @@ void intel_hdmi_fastset_infoframes(struct intel_encoder *encoder, const struct drm_connector_state *conn_state) { struct intel_display *display = to_intel_display(encoder); - i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display, + intel_reg_t reg = HSW_TVIDEO_DIP_CTL(display, crtc_state->cpu_transcoder); u32 val = intel_de_read(display, reg); @@ -1256,7 +1256,7 @@ static void hsw_set_infoframes(struct intel_encoder *encoder, const struct drm_connector_state *conn_state) { struct intel_display *display = to_intel_display(encoder); - i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display, + intel_reg_t reg = HSW_TVIDEO_DIP_CTL(display, crtc_state->cpu_transcoder); u32 val = intel_de_read(display, reg); diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c index 657ad5cb0eff..eee341d2b0a7 100644 --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c @@ -1007,7 +1007,7 @@ assert_dc_off(struct intel_display *display) static int __intel_lt_phy_p2p_write_once(struct intel_encoder *encoder, int lane, u16 addr, u8 data, - i915_reg_t mac_reg_addr, + intel_reg_t mac_reg_addr, u8 expected_mac_val) { struct intel_display *display = to_intel_display(encoder); @@ -1062,7 +1062,7 @@ static int __intel_lt_phy_p2p_write_once(struct intel_encoder *encoder, static void __intel_lt_phy_p2p_write(struct intel_encoder *encoder, int lane, u16 addr, u8 data, - i915_reg_t mac_reg_addr, + intel_reg_t mac_reg_addr, u8 expected_mac_val) { struct intel_display *display = to_intel_display(encoder); @@ -1086,7 +1086,7 @@ static void __intel_lt_phy_p2p_write(struct intel_encoder *encoder, static void intel_lt_phy_p2p_write(struct intel_encoder *encoder, u8 lane_mask, u16 addr, u8 data, - i915_reg_t mac_reg_addr, + intel_reg_t mac_reg_addr, u8 expected_mac_val) { int lane; diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c index cc6d4bfcff10..a60661d5c7ed 100644 --- a/drivers/gpu/drm/i915/display/intel_lvds.c +++ b/drivers/gpu/drm/i915/display/intel_lvds.c @@ -70,7 +70,7 @@ struct intel_lvds_encoder { struct intel_encoder base; bool is_dual_link; - i915_reg_t reg; + intel_reg_t reg; u32 a3_power; struct intel_lvds_pps init_pps; @@ -85,7 +85,7 @@ static struct intel_lvds_encoder *to_lvds_encoder(struct intel_encoder *encoder) } bool intel_lvds_port_enabled(struct intel_display *display, - i915_reg_t lvds_reg, enum pipe *pipe) + intel_reg_t lvds_reg, enum pipe *pipe) { u32 val; @@ -846,7 +846,7 @@ void intel_lvds_init(struct intel_display *display) struct intel_connector *connector; const struct drm_edid *drm_edid; struct intel_encoder *encoder; - i915_reg_t lvds_reg; + intel_reg_t lvds_reg; u32 lvds; u8 ddc_pin; diff --git a/drivers/gpu/drm/i915/display/intel_lvds.h b/drivers/gpu/drm/i915/display/intel_lvds.h index a6db1706a97c..6ac70d5e8ce6 100644 --- a/drivers/gpu/drm/i915/display/intel_lvds.h +++ b/drivers/gpu/drm/i915/display/intel_lvds.h @@ -8,20 +8,20 @@ #include <linux/types.h> -#include "i915_reg_defs.h" +#include "intel_display_reg_defs.h" enum pipe; struct intel_display; #ifdef I915 bool intel_lvds_port_enabled(struct intel_display *display, - i915_reg_t lvds_reg, enum pipe *pipe); + intel_reg_t lvds_reg, enum pipe *pipe); void intel_lvds_init(struct intel_display *display); struct intel_encoder *intel_get_lvds_encoder(struct intel_display *display); bool intel_is_dual_link_lvds(struct intel_display *display); #else static inline bool intel_lvds_port_enabled(struct intel_display *display, - i915_reg_t lvds_reg, enum pipe *pipe) + intel_reg_t lvds_reg, enum pipe *pipe) { return false; } diff --git a/drivers/gpu/drm/i915/display/intel_mchbar.c b/drivers/gpu/drm/i915/display/intel_mchbar.c index a0d0a796c6bb..8cfcee4a08a4 100644 --- a/drivers/gpu/drm/i915/display/intel_mchbar.c +++ b/drivers/gpu/drm/i915/display/intel_mchbar.c @@ -41,7 +41,7 @@ static u32 mchbar_mirror_len(struct intel_display *display) return mchbar_mirror_end(display) - mchbar_mirror_base(display) + 1; } -static bool is_mchbar_reg(struct intel_display *display, i915_reg_t reg) +static bool is_mchbar_reg(struct intel_display *display, intel_reg_t reg) { return has_mchbar_mirror(display) && in_range32(i915_mmio_reg_offset(reg), @@ -49,28 +49,28 @@ static bool is_mchbar_reg(struct intel_display *display, i915_reg_t reg) mchbar_mirror_len(display)); } -static void assert_is_mchbar_reg(struct intel_display *display, i915_reg_t reg) +static void assert_is_mchbar_reg(struct intel_display *display, intel_reg_t reg) { drm_WARN(display->drm, !is_mchbar_reg(display, reg), "Reading non-MCHBAR register 0x%x\n", i915_mmio_reg_offset(reg)); } -u16 intel_mchbar_read16(struct intel_display *display, i915_reg_t reg) +u16 intel_mchbar_read16(struct intel_display *display, intel_reg_t reg) { assert_is_mchbar_reg(display, reg); return intel_de_read16(display, reg); } -u32 intel_mchbar_read(struct intel_display *display, i915_reg_t reg) +u32 intel_mchbar_read(struct intel_display *display, intel_reg_t reg) { assert_is_mchbar_reg(display, reg); return intel_de_read(display, reg); } -u64 intel_mchbar_read64_2x32(struct intel_display *display, i915_reg_t reg) +u64 intel_mchbar_read64_2x32(struct intel_display *display, intel_reg_t reg) { assert_is_mchbar_reg(display, reg); diff --git a/drivers/gpu/drm/i915/display/intel_mchbar.h b/drivers/gpu/drm/i915/display/intel_mchbar.h index fb645c64796c..1ced5dc8a8fd 100644 --- a/drivers/gpu/drm/i915/display/intel_mchbar.h +++ b/drivers/gpu/drm/i915/display/intel_mchbar.h @@ -10,12 +10,12 @@ #include <drm/intel/mchbar_regs.h> -#include "i915_reg_defs.h" +#include "intel_display_reg_defs.h" struct intel_display; -u16 intel_mchbar_read16(struct intel_display *display, i915_reg_t reg); -u32 intel_mchbar_read(struct intel_display *display, i915_reg_t reg); -u64 intel_mchbar_read64_2x32(struct intel_display *display, i915_reg_t reg); +u16 intel_mchbar_read16(struct intel_display *display, intel_reg_t reg); +u32 intel_mchbar_read(struct intel_display *display, intel_reg_t reg); +u64 intel_mchbar_read64_2x32(struct intel_display *display, intel_reg_t reg); #endif /* __INTEL_MCHBAR_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c index 69c7952a1413..2fcf6c9c84cc 100644 --- a/drivers/gpu/drm/i915/display/intel_pch_display.c +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c @@ -40,7 +40,7 @@ enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc) static void assert_pch_dp_disabled(struct intel_display *display, enum pipe pipe, enum port port, - i915_reg_t dp_reg) + intel_reg_t dp_reg) { enum pipe port_pipe; bool state; @@ -59,7 +59,7 @@ static void assert_pch_dp_disabled(struct intel_display *display, static void assert_pch_hdmi_disabled(struct intel_display *display, enum pipe pipe, enum port port, - i915_reg_t hdmi_reg) + intel_reg_t hdmi_reg) { enum pipe port_pipe; bool state; @@ -115,7 +115,7 @@ static void assert_pch_transcoder_disabled(struct intel_display *display, } static void ibx_sanitize_pch_hdmi_port(struct intel_display *display, - enum port port, i915_reg_t hdmi_reg) + enum port port, intel_reg_t hdmi_reg) { u32 val = intel_de_read(display, hdmi_reg); @@ -134,7 +134,7 @@ static void ibx_sanitize_pch_hdmi_port(struct intel_display *display, } static void ibx_sanitize_pch_dp_port(struct intel_display *display, - enum port port, i915_reg_t dp_reg) + enum port port, intel_reg_t dp_reg) { u32 val = intel_de_read(display, dp_reg); @@ -247,7 +247,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state) struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); enum pipe pipe = crtc->pipe; - i915_reg_t reg; + intel_reg_t reg; u32 val, pipeconf_val; /* Make sure PCH DPLL is enabled */ @@ -313,7 +313,7 @@ static void ilk_disable_pch_transcoder(struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(crtc); enum pipe pipe = crtc->pipe; - i915_reg_t reg; + intel_reg_t reg; /* FDI relies on the transcoder */ assert_fdi_tx_disabled(display, pipe); @@ -417,7 +417,7 @@ void ilk_pch_enable(struct intel_atomic_state *state, &crtc_state->hw.adjusted_mode; u32 bpc = (intel_de_read(display, TRANSCONF(display, pipe)) & TRANSCONF_BPC_MASK) >> 5; - i915_reg_t reg = TRANS_DP_CTL(pipe); + intel_reg_t reg = TRANS_DP_CTL(pipe); enum port port; temp = intel_de_read(display, reg); diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index 2d799af73bb7..ea5e8f75acef 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -488,11 +488,11 @@ void bxt_pps_reset_all(struct intel_display *display) } struct pps_registers { - i915_reg_t pp_ctrl; - i915_reg_t pp_stat; - i915_reg_t pp_on; - i915_reg_t pp_off; - i915_reg_t pp_div; + intel_reg_t pp_ctrl; + intel_reg_t pp_stat; + intel_reg_t pp_on; + intel_reg_t pp_off; + intel_reg_t pp_div; }; static void intel_pps_get_registers(struct intel_dp *intel_dp, @@ -523,7 +523,7 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp, regs->pp_div = PP_DIVISOR(display, pps_idx); } -static i915_reg_t +static intel_reg_t _pp_ctrl_reg(struct intel_dp *intel_dp) { struct pps_registers regs; @@ -533,7 +533,7 @@ _pp_ctrl_reg(struct intel_dp *intel_dp) return regs.pp_ctrl; } -static i915_reg_t +static intel_reg_t _pp_stat_reg(struct intel_dp *intel_dp) { struct pps_registers regs; @@ -607,7 +607,7 @@ static void wait_panel_status(struct intel_dp *intel_dp, { struct intel_display *display = to_intel_display(intel_dp); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); - i915_reg_t pp_stat_reg, pp_ctrl_reg; + intel_reg_t pp_stat_reg, pp_ctrl_reg; int ret; u32 val; @@ -744,7 +744,7 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp) struct intel_display *display = to_intel_display(intel_dp); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); u32 pp; - i915_reg_t pp_stat_reg, pp_ctrl_reg; + intel_reg_t pp_stat_reg, pp_ctrl_reg; bool need_to_disable = !intel_dp->pps.want_panel_vdd; if (!intel_dp_is_edp(intel_dp)) @@ -826,7 +826,7 @@ static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp) struct intel_display *display = to_intel_display(intel_dp); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); u32 pp; - i915_reg_t pp_stat_reg, pp_ctrl_reg; + intel_reg_t pp_stat_reg, pp_ctrl_reg; lockdep_assert_held(&display->pps.mutex); @@ -955,7 +955,7 @@ void intel_pps_on_unlocked(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); u32 pp; - i915_reg_t pp_ctrl_reg; + intel_reg_t pp_ctrl_reg; lockdep_assert_held(&display->pps.mutex); @@ -1028,7 +1028,7 @@ void intel_pps_off_unlocked(struct intel_dp *intel_dp) struct intel_display *display = to_intel_display(intel_dp); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); u32 pp; - i915_reg_t pp_ctrl_reg; + intel_reg_t pp_ctrl_reg; lockdep_assert_held(&display->pps.mutex); @@ -1091,7 +1091,7 @@ void intel_pps_backlight_on(struct intel_dp *intel_dp) wait_backlight_on(intel_dp); with_intel_pps_lock(intel_dp) { - i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp); + intel_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp); u32 pp; pp = ilk_get_pp_control(intel_dp); @@ -1111,7 +1111,7 @@ void intel_pps_backlight_off(struct intel_dp *intel_dp) return; with_intel_pps_lock(intel_dp) { - i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp); + intel_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp); u32 pp; pp = ilk_get_pp_control(intel_dp); @@ -1155,7 +1155,7 @@ static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) struct intel_display *display = to_intel_display(intel_dp); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); enum pipe pipe = intel_dp->pps.vlv_pps_pipe; - i915_reg_t pp_on_reg = PP_ON_DELAYS(display, pipe); + intel_reg_t pp_on_reg = PP_ON_DELAYS(display, pipe); drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE); @@ -1814,7 +1814,7 @@ void intel_pps_connector_debugfs_add(struct intel_connector *connector) void assert_pps_unlocked(struct intel_display *display, enum pipe pipe) { - i915_reg_t pp_reg; + intel_reg_t pp_reg; u32 val; enum pipe panel_pipe = INVALID_PIPE; bool locked = true; diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index a927b73c3f6e..b05d7f01e8f7 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -303,8 +303,8 @@ static u32 psr_irq_mask_get(struct intel_dp *intel_dp) EDP_PSR_MASK(intel_dp->psr.transcoder); } -static i915_reg_t psr_ctl_reg(struct intel_display *display, - enum transcoder cpu_transcoder) +static intel_reg_t psr_ctl_reg(struct intel_display *display, + enum transcoder cpu_transcoder) { if (DISPLAY_VER(display) >= 8) return EDP_PSR_CTL(display, cpu_transcoder); @@ -312,8 +312,8 @@ static i915_reg_t psr_ctl_reg(struct intel_display *display, return HSW_SRD_CTL; } -static i915_reg_t psr_debug_reg(struct intel_display *display, - enum transcoder cpu_transcoder) +static intel_reg_t psr_debug_reg(struct intel_display *display, + enum transcoder cpu_transcoder) { if (DISPLAY_VER(display) >= 8) return EDP_PSR_DEBUG(display, cpu_transcoder); @@ -321,8 +321,8 @@ static i915_reg_t psr_debug_reg(struct intel_display *display, return HSW_SRD_DEBUG; } -static i915_reg_t psr_perf_cnt_reg(struct intel_display *display, - enum transcoder cpu_transcoder) +static intel_reg_t psr_perf_cnt_reg(struct intel_display *display, + enum transcoder cpu_transcoder) { if (DISPLAY_VER(display) >= 8) return EDP_PSR_PERF_CNT(display, cpu_transcoder); @@ -330,8 +330,8 @@ static i915_reg_t psr_perf_cnt_reg(struct intel_display *display, return HSW_SRD_PERF_CNT; } -static i915_reg_t psr_status_reg(struct intel_display *display, - enum transcoder cpu_transcoder) +static intel_reg_t psr_status_reg(struct intel_display *display, + enum transcoder cpu_transcoder) { if (DISPLAY_VER(display) >= 8) return EDP_PSR_STATUS(display, cpu_transcoder); @@ -339,8 +339,8 @@ static i915_reg_t psr_status_reg(struct intel_display *display, return HSW_SRD_STATUS; } -static i915_reg_t psr_imr_reg(struct intel_display *display, - enum transcoder cpu_transcoder) +static intel_reg_t psr_imr_reg(struct intel_display *display, + enum transcoder cpu_transcoder) { if (DISPLAY_VER(display) >= 12) return TRANS_PSR_IMR(display, cpu_transcoder); @@ -348,8 +348,8 @@ static i915_reg_t psr_imr_reg(struct intel_display *display, return EDP_PSR_IMR; } -static i915_reg_t psr_iir_reg(struct intel_display *display, - enum transcoder cpu_transcoder) +static intel_reg_t psr_iir_reg(struct intel_display *display, + enum transcoder cpu_transcoder) { if (DISPLAY_VER(display) >= 12) return TRANS_PSR_IIR(display, cpu_transcoder); @@ -357,8 +357,8 @@ static i915_reg_t psr_iir_reg(struct intel_display *display, return EDP_PSR_IIR; } -static i915_reg_t psr_aux_ctl_reg(struct intel_display *display, - enum transcoder cpu_transcoder) +static intel_reg_t psr_aux_ctl_reg(struct intel_display *display, + enum transcoder cpu_transcoder) { if (DISPLAY_VER(display) >= 8) return EDP_PSR_AUX_CTL(display, cpu_transcoder); @@ -366,8 +366,8 @@ static i915_reg_t psr_aux_ctl_reg(struct intel_display *display, return HSW_SRD_AUX_CTL; } -static i915_reg_t psr_aux_data_reg(struct intel_display *display, - enum transcoder cpu_transcoder, int i) +static intel_reg_t psr_aux_data_reg(struct intel_display *display, + enum transcoder cpu_transcoder, int i) { if (DISPLAY_VER(display) >= 8) return EDP_PSR_AUX_DATA(display, cpu_transcoder, i); @@ -2316,7 +2316,7 @@ static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); enum transcoder cpu_transcoder = intel_dp->psr.transcoder; - i915_reg_t psr_status; + intel_reg_t psr_status; u32 psr_status_mask; if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled || @@ -3347,7 +3347,7 @@ static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); enum transcoder cpu_transcoder = intel_dp->psr.transcoder; - i915_reg_t reg; + intel_reg_t reg; u32 mask; int err; diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c index 2e1af9e869de..56005b046f00 100644 --- a/drivers/gpu/drm/i915/display/intel_sdvo.c +++ b/drivers/gpu/drm/i915/display/intel_sdvo.c @@ -101,7 +101,7 @@ struct intel_sdvo { struct intel_sdvo_ddc ddc[3]; /* Register for the SDVO device: SDVOB or SDVOC */ - i915_reg_t sdvo_reg; + intel_reg_t sdvo_reg; /* * Capabilities of the SDVO device returned by @@ -1665,7 +1665,7 @@ static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector) } bool intel_sdvo_port_enabled(struct intel_display *display, - i915_reg_t sdvo_reg, enum pipe *pipe) + intel_reg_t sdvo_reg, enum pipe *pipe) { u32 val; @@ -3377,7 +3377,7 @@ static bool assert_sdvo_port_valid(struct intel_display *display, enum port port } bool intel_sdvo_init(struct intel_display *display, - i915_reg_t sdvo_reg, enum port port) + intel_reg_t sdvo_reg, enum port port) { struct intel_encoder *intel_encoder; struct intel_sdvo *intel_sdvo; diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.h b/drivers/gpu/drm/i915/display/intel_sdvo.h index 1a9e40fdd8a8..d1e1083de037 100644 --- a/drivers/gpu/drm/i915/display/intel_sdvo.h +++ b/drivers/gpu/drm/i915/display/intel_sdvo.h @@ -8,7 +8,7 @@ #include <linux/types.h> -#include "i915_reg_defs.h" +#include "intel_display_reg_defs.h" enum pipe; enum port; @@ -16,17 +16,17 @@ struct intel_display; #ifdef I915 bool intel_sdvo_port_enabled(struct intel_display *display, - i915_reg_t sdvo_reg, enum pipe *pipe); + intel_reg_t sdvo_reg, enum pipe *pipe); bool intel_sdvo_init(struct intel_display *display, - i915_reg_t reg, enum port port); + intel_reg_t reg, enum port port); #else static inline bool intel_sdvo_port_enabled(struct intel_display *display, - i915_reg_t sdvo_reg, enum pipe *pipe) + intel_reg_t sdvo_reg, enum pipe *pipe) { return false; } static inline bool intel_sdvo_init(struct intel_display *display, - i915_reg_t reg, enum port port) + intel_reg_t reg, enum port port) { return false; } diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c index 295030742294..8e883f1a014c 100644 --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c @@ -1822,7 +1822,7 @@ void intel_mpllb_enable(struct intel_encoder *encoder, struct intel_display *display = to_intel_display(encoder); const struct intel_mpllb_state *pll_state = &crtc_state->dpll_hw_state.mpllb; enum phy phy = intel_encoder_to_phy(encoder); - i915_reg_t enable_reg = (phy <= PHY_D ? + intel_reg_t enable_reg = (phy <= PHY_D ? DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0)); /* @@ -1879,7 +1879,7 @@ void intel_mpllb_disable(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); - i915_reg_t enable_reg = (phy <= PHY_D ? + intel_reg_t enable_reg = (phy <= PHY_D ? DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0)); /* diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c index a21dd4e3fe4c..ef1cf62749ec 100644 --- a/drivers/gpu/drm/i915/display/intel_tc.c +++ b/drivers/gpu/drm/i915/display/intel_tc.c @@ -294,7 +294,7 @@ get_pin_assignment(struct intel_tc_port *tc) struct intel_display *display = to_intel_display(tc->dig_port); enum tc_port tc_port = intel_encoder_to_tc(&tc->dig_port->base); enum intel_tc_pin_assignment pin_assignment; - i915_reg_t reg; + intel_reg_t reg; u32 mask; u32 val; @@ -1034,7 +1034,7 @@ xelpdp_tc_phy_tcss_power_is_enabled(struct intel_tc_port *tc) { struct intel_display *display = to_intel_display(tc->dig_port); enum port port = tc->dig_port->base.port; - i915_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port); + intel_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port); assert_tc_cold_blocked(tc); @@ -1094,7 +1094,7 @@ static void __xelpdp_tc_phy_enable_tcss_power(struct intel_tc_port *tc, bool ena { struct intel_display *display = to_intel_display(tc->dig_port); enum port port = tc->dig_port->base.port; - i915_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port); + intel_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port); u32 val; assert_tc_cold_blocked(tc); @@ -1141,7 +1141,7 @@ static void xelpdp_tc_phy_take_ownership(struct intel_tc_port *tc, bool take) { struct intel_display *display = to_intel_display(tc->dig_port); enum port port = tc->dig_port->base.port; - i915_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port); + intel_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port); u32 val; assert_tc_cold_blocked(tc); @@ -1158,7 +1158,7 @@ static bool xelpdp_tc_phy_is_owned(struct intel_tc_port *tc) { struct intel_display *display = to_intel_display(tc->dig_port); enum port port = tc->dig_port->base.port; - i915_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port); + intel_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port); assert_tc_cold_blocked(tc); diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c index 0726a2abed38..28d81199792e 100644 --- a/drivers/gpu/drm/i915/display/intel_vblank.c +++ b/drivers/gpu/drm/i915/display/intel_vblank.c @@ -482,7 +482,7 @@ int intel_get_crtc_scanline(struct intel_crtc *crtc) static bool pipe_scanline_is_moving(struct intel_display *display, enum pipe pipe) { - i915_reg_t reg = PIPEDSL(display, pipe); + intel_reg_t reg = PIPEDSL(display, pipe); u32 line1, line2; line1 = intel_de_read(display, reg) & PIPEDSL_LINE_MASK; diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 6c09c6d99ffe..8f06c3a4d56d 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -483,7 +483,7 @@ int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state) } static void intel_dsc_get_pps_reg(const struct intel_crtc_state *crtc_state, int pps, - i915_reg_t *dsc_reg, int dsc_reg_num) + intel_reg_t *dsc_reg, int dsc_reg_num) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; @@ -506,7 +506,7 @@ static void intel_dsc_pps_write(const struct intel_crtc_state *crtc_state, int pps, u32 pps_val) { struct intel_display *display = to_intel_display(crtc_state); - i915_reg_t dsc_reg[3]; + intel_reg_t dsc_reg[3]; int i, vdsc_per_pipe, dsc_reg_num; vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state); @@ -843,13 +843,13 @@ void intel_dsc_su_et_parameters_configure(struct intel_dsb *dsb, struct intel_en intel_de_write_dsb(display, dsb, LNL_DSC1_SU_PARAMETER_SET_0(pipe), val); } -static i915_reg_t dss_ctl1_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder) +static intel_reg_t dss_ctl1_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder) { return is_pipe_dsc(crtc, cpu_transcoder) ? ICL_PIPE_DSS_CTL1(crtc->pipe) : DSS_CTL1; } -static i915_reg_t dss_ctl2_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder) +static intel_reg_t dss_ctl2_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder) { return is_pipe_dsc(crtc, cpu_transcoder) ? ICL_PIPE_DSS_CTL2(crtc->pipe) : DSS_CTL2; @@ -929,7 +929,7 @@ static u32 intel_dsc_pps_read(struct intel_crtc_state *crtc_state, int pps, bool *all_equal) { struct intel_display *display = to_intel_display(crtc_state); - i915_reg_t dsc_reg[3]; + intel_reg_t dsc_reg[3]; int i, vdsc_per_pipe, dsc_reg_num; u32 val; diff --git a/drivers/gpu/drm/i915/display/intel_vga.c b/drivers/gpu/drm/i915/display/intel_vga.c index 9832a4ade318..4966fd7eea92 100644 --- a/drivers/gpu/drm/i915/display/intel_vga.c +++ b/drivers/gpu/drm/i915/display/intel_vga.c @@ -35,7 +35,7 @@ static bool intel_vga_decode_is_enabled(struct intel_display *display) return !(gmch_ctrl & INTEL_GMCH_VGA_DISABLE); } -static i915_reg_t intel_vga_cntrl_reg(struct intel_display *display) +static intel_reg_t intel_vga_cntrl_reg(struct intel_display *display) { if (display->platform.valleyview || display->platform.cherryview) return VLV_VGACNTRL; @@ -179,7 +179,7 @@ static void intel_vga_write(struct intel_display *display, u16 reg, u8 val, bool void intel_vga_disable(struct intel_display *display) { struct pci_dev *pdev = to_pci_dev(display->drm->dev); - i915_reg_t vga_reg = intel_vga_cntrl_reg(display); + intel_reg_t vga_reg = intel_vga_cntrl_reg(display); bool mmio = has_vga_mmio_access(display); bool io_decode; u8 msr, sr1; diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c index 76e8cd0f65a4..877eab75f19a 100644 --- a/drivers/gpu/drm/i915/display/vlv_dsi.c +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c @@ -99,7 +99,7 @@ void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port) } static void write_data(struct intel_display *display, - i915_reg_t reg, + intel_reg_t reg, const u8 *data, u32 len) { u32 i, j; @@ -115,7 +115,7 @@ static void write_data(struct intel_display *display, } static void read_data(struct intel_display *display, - i915_reg_t reg, + intel_reg_t reg, u8 *data, u32 len) { u32 i, j; @@ -138,7 +138,7 @@ static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, struct mipi_dsi_packet packet; ssize_t ret; const u8 *header; - i915_reg_t data_reg, ctrl_reg; + intel_reg_t data_reg, ctrl_reg; u32 data_mask, ctrl_mask; ret = mipi_dsi_create_packet(&packet, msg); @@ -559,7 +559,7 @@ static void glk_dsi_clear_device_ready(struct intel_encoder *encoder) glk_dsi_disable_mipi_io(encoder); } -static i915_reg_t port_ctrl_reg(struct intel_display *display, enum port port) +static intel_reg_t port_ctrl_reg(struct intel_display *display, enum port port) { return display->platform.geminilake || display->platform.broxton ? BXT_MIPI_PORT_CTRL(port) : VLV_MIPI_PORT_CTRL(port); @@ -574,7 +574,7 @@ static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) drm_dbg_kms(display->drm, "\n"); for_each_dsi_port(port, intel_dsi->ports) { /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */ - i915_reg_t port_ctrl = display->platform.broxton ? + intel_reg_t port_ctrl = display->platform.broxton ? BXT_MIPI_PORT_CTRL(port) : VLV_MIPI_PORT_CTRL(PORT_A); intel_de_write(display, MIPI_DEVICE_READY(display, port), @@ -631,7 +631,7 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder, } for_each_dsi_port(port, intel_dsi->ports) { - i915_reg_t port_ctrl = port_ctrl_reg(display, port); + intel_reg_t port_ctrl = port_ctrl_reg(display, port); u32 temp; temp = intel_de_read(display, port_ctrl); @@ -666,7 +666,7 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder) enum port port; for_each_dsi_port(port, intel_dsi->ports) { - i915_reg_t port_ctrl = port_ctrl_reg(display, port); + intel_reg_t port_ctrl = port_ctrl_reg(display, port); /* de-assert ip_tg_enable signal */ intel_de_rmw(display, port_ctrl, DPI_ENABLE, 0); @@ -957,7 +957,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, /* XXX: this only works for one DSI output */ for_each_dsi_port(port, intel_dsi->ports) { - i915_reg_t port_ctrl = port_ctrl_reg(display, port); + intel_reg_t port_ctrl = port_ctrl_reg(display, port); bool enabled = intel_de_read(display, port_ctrl) & DPI_ENABLE; /* -- 2.47.3 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/4] drm/i915/display: add struct intel_irq_regs and use it 2026-04-08 13:15 [PATCH 0/4] drm/i915/display: start switching to display specific reg types Jani Nikula 2026-04-08 13:15 ` [PATCH 1/4] drm/i915/display: add typedef for intel_reg_t and use it Jani Nikula @ 2026-04-08 13:15 ` Jani Nikula 2026-04-08 13:15 ` [PATCH 3/4] drm/i915/display: add struct intel_error_regs " Jani Nikula ` (3 subsequent siblings) 5 siblings, 0 replies; 7+ messages in thread From: Jani Nikula @ 2026-04-08 13:15 UTC (permalink / raw) To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala Add struct intel_irq_regs, a display version of struct i915_irq_regs, and use it. The goal is to reduce the dependency on i915 core types and headers. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- .../gpu/drm/i915/display/intel_display_irq.c | 4 +- .../drm/i915/display/intel_display_reg_defs.h | 10 ++++ .../gpu/drm/i915/display/intel_display_regs.h | 48 +++++++++---------- 3 files changed, 36 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index 365e467dddaf..8b6b4709989e 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -30,7 +30,7 @@ #include "intel_psr.h" #include "intel_psr_regs.h" -static void irq_reset(struct intel_display *display, struct i915_irq_regs regs) +static void irq_reset(struct intel_display *display, struct intel_irq_regs regs) { intel_de_write(display, regs.imr, 0xffffffff); intel_de_posting_read(display, regs.imr); @@ -63,7 +63,7 @@ static void assert_iir_is_zero(struct intel_display *display, intel_reg_t reg) intel_de_posting_read(display, reg); } -static void irq_init(struct intel_display *display, struct i915_irq_regs regs, +static void irq_init(struct intel_display *display, struct intel_irq_regs regs, u32 imr_val, u32 ier_val) { assert_iir_is_zero(display, regs.iir); diff --git a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h index cb46863693cd..d044967aa6d9 100644 --- a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h +++ b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h @@ -10,6 +10,16 @@ typedef i915_reg_t intel_reg_t; +/* A triplet for IMR/IER/IIR registers. */ +struct intel_irq_regs { + intel_reg_t imr; + intel_reg_t ier; + intel_reg_t iir; +}; + +#define INTEL_IRQ_REGS(_imr, _ier, _iir) \ + ((const struct intel_irq_regs){ .imr = (_imr), .ier = (_ier), .iir = (_iir) }) + #define VLV_DISPLAY_BASE 0x180000 /* diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h index dada8dc27ea4..4fc18e5ee239 100644 --- a/drivers/gpu/drm/i915/display/intel_display_regs.h +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h @@ -105,9 +105,9 @@ #define ERR_INT_FIFO_UNDERRUN_A (1 << 0) #define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3)) -#define VLV_IRQ_REGS I915_IRQ_REGS(VLV_IMR, \ - VLV_IER, \ - VLV_IIR) +#define VLV_IRQ_REGS INTEL_IRQ_REGS(VLV_IMR, \ + VLV_IER, \ + VLV_IIR) #define VLV_EIR _MMIO(VLV_DISPLAY_BASE + 0x20b0) #define VLV_EMR _MMIO(VLV_DISPLAY_BASE + 0x20b4) @@ -1116,9 +1116,9 @@ #define DEIIR _MMIO(0x44008) #define DEIER _MMIO(0x4400c) -#define DE_IRQ_REGS I915_IRQ_REGS(DEIMR, \ - DEIER, \ - DEIIR) +#define DE_IRQ_REGS INTEL_IRQ_REGS(DEIMR, \ + DEIER, \ + DEIIR) #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030) #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) @@ -1407,9 +1407,9 @@ #define GEN8_PIPE_VSYNC REG_BIT(1) #define GEN8_PIPE_VBLANK REG_BIT(0) -#define GEN8_DE_PIPE_IRQ_REGS(pipe) I915_IRQ_REGS(GEN8_DE_PIPE_IMR(pipe), \ - GEN8_DE_PIPE_IER(pipe), \ - GEN8_DE_PIPE_IIR(pipe)) +#define GEN8_DE_PIPE_IRQ_REGS(pipe) INTEL_IRQ_REGS(GEN8_DE_PIPE_IMR(pipe), \ + GEN8_DE_PIPE_IER(pipe), \ + GEN8_DE_PIPE_IIR(pipe)) #define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A) #define _HPD_PIN_TC(hpd_pin) ((hpd_pin) - HPD_PORT_TC1) @@ -1446,9 +1446,9 @@ #define TGL_DE_PORT_AUX_DDIB REG_BIT(1) #define TGL_DE_PORT_AUX_DDIA REG_BIT(0) -#define GEN8_DE_PORT_IRQ_REGS I915_IRQ_REGS(GEN8_DE_PORT_IMR, \ - GEN8_DE_PORT_IER, \ - GEN8_DE_PORT_IIR) +#define GEN8_DE_PORT_IRQ_REGS INTEL_IRQ_REGS(GEN8_DE_PORT_IMR, \ + GEN8_DE_PORT_IER, \ + GEN8_DE_PORT_IIR) /* interrupts */ #define DE_MASTER_IRQ_CONTROL (1 << 31) @@ -1499,9 +1499,9 @@ #define XELPDP_PMDEMAND_RSP REG_BIT(3) #define XE2LPD_DBUF_OVERLAP_DETECTED REG_BIT(1) -#define GEN8_DE_MISC_IRQ_REGS I915_IRQ_REGS(GEN8_DE_MISC_IMR, \ - GEN8_DE_MISC_IER, \ - GEN8_DE_MISC_IIR) +#define GEN8_DE_MISC_IRQ_REGS INTEL_IRQ_REGS(GEN8_DE_MISC_IMR, \ + GEN8_DE_MISC_IER, \ + GEN8_DE_MISC_IIR) #define GEN11_DISPLAY_INT_CTL _MMIO(0x44200) #define GEN11_DISPLAY_IRQ_ENABLE (1 << 31) @@ -1533,9 +1533,9 @@ GEN11_TBT_HOTPLUG(HPD_PORT_TC2) | \ GEN11_TBT_HOTPLUG(HPD_PORT_TC1)) -#define GEN11_DE_HPD_IRQ_REGS I915_IRQ_REGS(GEN11_DE_HPD_IMR, \ - GEN11_DE_HPD_IER, \ - GEN11_DE_HPD_IIR) +#define GEN11_DE_HPD_IRQ_REGS INTEL_IRQ_REGS(GEN11_DE_HPD_IMR, \ + GEN11_DE_HPD_IER, \ + GEN11_DE_HPD_IIR) #define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030) #define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038) @@ -1557,9 +1557,9 @@ #define XELPDP_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin)) #define XELPDP_TBT_HOTPLUG_MASK REG_GENMASK(3, 0) -#define PICAINTERRUPT_IRQ_REGS I915_IRQ_REGS(PICAINTERRUPT_IMR, \ - PICAINTERRUPT_IER, \ - PICAINTERRUPT_IIR) +#define PICAINTERRUPT_IRQ_REGS INTEL_IRQ_REGS(PICAINTERRUPT_IMR, \ + PICAINTERRUPT_IER, \ + PICAINTERRUPT_IIR) #define XELPDP_PORT_HOTPLUG_CTL(hpd_pin) _MMIO(0x16F270 + (_HPD_PIN_TC(hpd_pin) * 0x200)) #define XELPDP_TBT_HOTPLUG_ENABLE REG_BIT(6) @@ -1875,9 +1875,9 @@ #define SDEIIR _MMIO(0xc4008) #define SDEIER _MMIO(0xc400c) -#define SDE_IRQ_REGS I915_IRQ_REGS(SDEIMR, \ - SDEIER, \ - SDEIIR) +#define SDE_IRQ_REGS INTEL_IRQ_REGS(SDEIMR, \ + SDEIER, \ + SDEIIR) #define SERR_INT _MMIO(0xc4040) #define SERR_INT_POISON (1 << 31) -- 2.47.3 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 3/4] drm/i915/display: add struct intel_error_regs and use it 2026-04-08 13:15 [PATCH 0/4] drm/i915/display: start switching to display specific reg types Jani Nikula 2026-04-08 13:15 ` [PATCH 1/4] drm/i915/display: add typedef for intel_reg_t and use it Jani Nikula 2026-04-08 13:15 ` [PATCH 2/4] drm/i915/display: add struct intel_irq_regs " Jani Nikula @ 2026-04-08 13:15 ` Jani Nikula 2026-04-08 13:15 ` [PATCH 4/4] drm/i915/display: define and use intel_reg_{offset, equal, valid}() helpers Jani Nikula ` (2 subsequent siblings) 5 siblings, 0 replies; 7+ messages in thread From: Jani Nikula @ 2026-04-08 13:15 UTC (permalink / raw) To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala Add struct intel_error_regs, a display version of struct i915_error_regs, and use it. The goal is to reduce the dependency on i915 core types and headers. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_display_irq.c | 4 ++-- drivers/gpu/drm/i915/display/intel_display_reg_defs.h | 8 ++++++++ drivers/gpu/drm/i915/display/intel_display_regs.h | 2 +- 3 files changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index 8b6b4709989e..3869551cb9fd 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -73,7 +73,7 @@ static void irq_init(struct intel_display *display, struct intel_irq_regs regs, intel_de_posting_read(display, regs.imr); } -static void error_reset(struct intel_display *display, struct i915_error_regs regs) +static void error_reset(struct intel_display *display, struct intel_error_regs regs) { intel_de_write(display, regs.emr, 0xffffffff); intel_de_posting_read(display, regs.emr); @@ -84,7 +84,7 @@ static void error_reset(struct intel_display *display, struct i915_error_regs re intel_de_posting_read(display, regs.eir); } -static void error_init(struct intel_display *display, struct i915_error_regs regs, +static void error_init(struct intel_display *display, struct intel_error_regs regs, u32 emr_val) { intel_de_write(display, regs.eir, 0xffffffff); diff --git a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h index d044967aa6d9..a56f8ed055f6 100644 --- a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h +++ b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h @@ -20,6 +20,14 @@ struct intel_irq_regs { #define INTEL_IRQ_REGS(_imr, _ier, _iir) \ ((const struct intel_irq_regs){ .imr = (_imr), .ier = (_ier), .iir = (_iir) }) +struct intel_error_regs { + intel_reg_t emr; + intel_reg_t eir; +}; + +#define INTEL_ERROR_REGS(_emr, _eir) \ + ((const struct intel_error_regs){ .emr = (_emr), .eir = (_eir) }) + #define VLV_DISPLAY_BASE 0x180000 /* diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h index 4fc18e5ee239..d87e52d278c7 100644 --- a/drivers/gpu/drm/i915/display/intel_display_regs.h +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h @@ -117,7 +117,7 @@ #define VLV_ERROR_PAGE_TABLE (1 << 4) #define VLV_ERROR_CLAIM (1 << 0) -#define VLV_ERROR_REGS I915_ERROR_REGS(VLV_EMR, VLV_EIR) +#define VLV_ERROR_REGS INTEL_ERROR_REGS(VLV_EMR, VLV_EIR) #define _MBUS_ABOX0_CTL 0x45038 #define _MBUS_ABOX1_CTL 0x45048 -- 2.47.3 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 4/4] drm/i915/display: define and use intel_reg_{offset, equal, valid}() helpers 2026-04-08 13:15 [PATCH 0/4] drm/i915/display: start switching to display specific reg types Jani Nikula ` (2 preceding siblings ...) 2026-04-08 13:15 ` [PATCH 3/4] drm/i915/display: add struct intel_error_regs " Jani Nikula @ 2026-04-08 13:15 ` Jani Nikula 2026-04-08 13:22 ` ✗ CI.checkpatch: warning for drm/i915/display: start switching to display specific reg types Patchwork 2026-04-08 13:25 ` ✗ CI.KUnit: failure " Patchwork 5 siblings, 0 replies; 7+ messages in thread From: Jani Nikula @ 2026-04-08 13:15 UTC (permalink / raw) To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala Add display specific helpers for getting the register offset, checking for equality and validity. Add them as static inlines for increased type safety. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_de.h | 2 +- .../drm/i915/display/intel_display_device.c | 2 +- .../gpu/drm/i915/display/intel_display_irq.c | 2 +- .../drm/i915/display/intel_display_reg_defs.h | 15 +++++++++++ .../drm/i915/display/intel_display_types.h | 4 +-- drivers/gpu/drm/i915/display/intel_dmc.c | 26 +++++++++---------- drivers/gpu/drm/i915/display/intel_dmc_wl.c | 6 ++--- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 4 +-- drivers/gpu/drm/i915/display/intel_dsb.c | 10 +++---- drivers/gpu/drm/i915/display/intel_mchbar.c | 4 +-- drivers/gpu/drm/i915/display/intel_pps.c | 6 ++--- 11 files changed, 48 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h index d17f14843f98..102979019429 100644 --- a/drivers/gpu/drm/i915/display/intel_de.h +++ b/drivers/gpu/drm/i915/display/intel_de.h @@ -56,7 +56,7 @@ intel_de_read64_2x32_volatile(struct intel_display *display, static inline u64 intel_de_read64_2x32(struct intel_display *display, intel_reg_t reg) { - intel_reg_t upper_reg = _MMIO(i915_mmio_reg_offset(reg) + 4); + intel_reg_t upper_reg = _MMIO(intel_reg_offset(reg) + 4); u32 lower, upper; lower = intel_de_read(display, reg); diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index be55ef8ea617..51083e63bd1f 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -1525,7 +1525,7 @@ probe_gmdid_display(struct intel_display *display, struct intel_display_ip_ver * u32 val; int i; - addr = pci_iomap_range(pdev, 0, i915_mmio_reg_offset(GMD_ID_DISPLAY), sizeof(u32)); + addr = pci_iomap_range(pdev, 0, intel_reg_offset(GMD_ID_DISPLAY), sizeof(u32)); if (!addr) { drm_err(display->drm, "Cannot map MMIO BAR to read display GMD_ID\n"); diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index 3869551cb9fd..40dcc2a1d3fb 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -56,7 +56,7 @@ static void assert_iir_is_zero(struct intel_display *display, intel_reg_t reg) drm_WARN(display->drm, 1, "Interrupt register 0x%x is not zero: 0x%08x\n", - i915_mmio_reg_offset(reg), val); + intel_reg_offset(reg), val); intel_de_write(display, reg, 0xffffffff); intel_de_posting_read(display, reg); intel_de_write(display, reg, 0xffffffff); diff --git a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h index a56f8ed055f6..9220fcbfcb24 100644 --- a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h +++ b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h @@ -10,6 +10,21 @@ typedef i915_reg_t intel_reg_t; +static inline u32 intel_reg_offset(intel_reg_t r) +{ + return r.reg; +} + +static inline bool intel_reg_equal(intel_reg_t a, intel_reg_t b) +{ + return intel_reg_offset(a) == intel_reg_offset(b); +} + +static inline bool intel_reg_valid(intel_reg_t r) +{ + return !intel_reg_equal(r, INVALID_MMIO_REG); +} + /* A triplet for IMR/IER/IIR registers. */ struct intel_irq_regs { intel_reg_t imr; diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 677824ac0ffe..047462e92590 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -2116,7 +2116,7 @@ static inline bool intel_encoder_is_dp(struct intel_encoder *encoder) return true; case INTEL_OUTPUT_DDI: /* Skip pure HDMI/DVI DDI encoders */ - return i915_mmio_reg_valid(enc_to_intel_dp(encoder)->output_reg); + return intel_reg_valid(enc_to_intel_dp(encoder)->output_reg); default: return false; } @@ -2129,7 +2129,7 @@ static inline bool intel_encoder_is_hdmi(struct intel_encoder *encoder) return true; case INTEL_OUTPUT_DDI: /* See if the HDMI encoder is valid. */ - return i915_mmio_reg_valid(enc_to_intel_hdmi(encoder)->hdmi_reg); + return intel_reg_valid(enc_to_intel_hdmi(encoder)->hdmi_reg); default: return false; } diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c index 665842fb9eae..b90265e96a41 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -540,9 +540,9 @@ static u32 dmc_evt_ctl_disable(u32 dmc_evt_ctl) static bool is_dmc_evt_ctl_reg(struct intel_display *display, enum intel_dmc_id dmc_id, intel_reg_t reg) { - u32 offset = i915_mmio_reg_offset(reg); - u32 start = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, 0)); - u32 end = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); + u32 offset = intel_reg_offset(reg); + u32 start = intel_reg_offset(DMC_EVT_CTL(display, dmc_id, 0)); + u32 end = intel_reg_offset(DMC_EVT_CTL(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); return offset >= start && offset < end; } @@ -550,9 +550,9 @@ static bool is_dmc_evt_ctl_reg(struct intel_display *display, static bool is_dmc_evt_htp_reg(struct intel_display *display, enum intel_dmc_id dmc_id, intel_reg_t reg) { - u32 offset = i915_mmio_reg_offset(reg); - u32 start = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, 0)); - u32 end = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); + u32 offset = intel_reg_offset(reg); + u32 start = intel_reg_offset(DMC_EVT_HTP(display, dmc_id, 0)); + u32 end = intel_reg_offset(DMC_EVT_HTP(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); return offset >= start && offset < end; } @@ -578,8 +578,8 @@ static bool fixup_dmc_evt(struct intel_display *display, return false; /* make sure reg_ctl and reg_htp are for the same event */ - if (i915_mmio_reg_offset(reg_ctl) - i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, 0)) != - i915_mmio_reg_offset(reg_htp) - i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, 0))) + if (intel_reg_offset(reg_ctl) - intel_reg_offset(DMC_EVT_CTL(display, dmc_id, 0)) != + intel_reg_offset(reg_htp) - intel_reg_offset(DMC_EVT_HTP(display, dmc_id, 0))) return false; /* @@ -703,7 +703,7 @@ static void assert_dmc_loaded(struct intel_display *display, drm_WARN(display->drm, found != expected, "DMC %d mmio[%d]/0x%x incorrect (expected 0x%x, current 0x%x)\n", - dmc_id, i, i915_mmio_reg_offset(reg), expected, found); + dmc_id, i, intel_reg_offset(reg), expected, found); } } @@ -1146,17 +1146,17 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc, drm_dbg_kms(display->drm, " mmio[%d]: 0x%x = 0x%x->0x%x (EVT_CTL)\n", - i, i915_mmio_reg_offset(dmc_info->mmioaddr[i]), + i, intel_reg_offset(dmc_info->mmioaddr[i]), orig_mmiodata[0], dmc_info->mmiodata[i]); drm_dbg_kms(display->drm, " mmio[%d]: 0x%x = 0x%x->0x%x (EVT_HTP)\n", - i+1, i915_mmio_reg_offset(dmc_info->mmioaddr[i+1]), + i+1, intel_reg_offset(dmc_info->mmioaddr[i+1]), orig_mmiodata[1], dmc_info->mmiodata[i+1]); } for (i = 0; i < mmio_count; i++) { drm_dbg_kms(display->drm, " mmio[%d]: 0x%x = 0x%x%s%s\n", - i, i915_mmio_reg_offset(dmc_info->mmioaddr[i]), dmc_info->mmiodata[i], + i, intel_reg_offset(dmc_info->mmioaddr[i]), dmc_info->mmiodata[i], is_dmc_evt_ctl_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_CTL)" : is_dmc_evt_htp_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_HTP)" : "", disable_dmc_evt(display, dmc_id, dmc_info->mmioaddr[i], @@ -1672,7 +1672,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused) if (intel_dmc_get_dc6_allowed_count(display, &dc6_allowed_count)) seq_printf(m, "DC5 -> DC6 allowed count: %d\n", dc6_allowed_count); - else if (i915_mmio_reg_valid(dc6_reg)) + else if (intel_reg_valid(dc6_reg)) seq_printf(m, "DC5 -> DC6 count: %d\n", intel_de_read(display, dc6_reg)); diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm/i915/display/intel_dmc_wl.c index 763f004700ba..7b50f2b41f54 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c @@ -227,7 +227,7 @@ static void __intel_dmc_wl_take(struct intel_display *display) static bool intel_dmc_wl_reg_in_range(intel_reg_t reg, const struct intel_dmc_wl_range ranges[]) { - u32 offset = i915_mmio_reg_offset(reg); + u32 offset = intel_reg_offset(reg); for (int i = 0; ranges[i].start; i++) { u32 end = ranges[i].end ?: ranges[i].start; @@ -441,7 +441,7 @@ void intel_dmc_wl_get(struct intel_display *display, intel_reg_t reg) spin_lock_irqsave(&wl->lock, flags); - if (i915_mmio_reg_valid(reg) && + if (intel_reg_valid(reg) && !intel_dmc_wl_check_range(display, reg, wl->dc_state)) goto out_unlock; @@ -474,7 +474,7 @@ void intel_dmc_wl_put(struct intel_display *display, intel_reg_t reg) spin_lock_irqsave(&wl->lock, flags); - if (i915_mmio_reg_valid(reg) && + if (intel_reg_valid(reg) && !intel_dmc_wl_check_range(display, reg, wl->dc_state)) goto out_unlock; diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index dba8eeb4de4b..02f681fe903e 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -3842,9 +3842,9 @@ static void icl_dpll_write(struct intel_display *display, intel_de_write(display, cfgcr0_reg, hw_state->cfgcr0); intel_de_write(display, cfgcr1_reg, hw_state->cfgcr1); drm_WARN_ON_ONCE(display->drm, display->vbt.override_afc_startup && - !i915_mmio_reg_valid(div0_reg)); + !intel_reg_valid(div0_reg)); if (display->vbt.override_afc_startup && - i915_mmio_reg_valid(div0_reg)) + intel_reg_valid(div0_reg)) intel_de_rmw(display, div0_reg, TGL_DPLL0_DIV0_AFC_STARTUP_MASK, hw_state->div0); intel_de_posting_read(display, cfgcr1_reg); diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index ce4d452ae695..fec8a56e21ea 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -341,7 +341,7 @@ static bool intel_dsb_prev_ins_is_write(struct intel_dsb *dsb, prev_opcode = dsb->ins[1] & ~DSB_REG_VALUE_MASK; prev_reg = dsb->ins[1] & DSB_REG_VALUE_MASK; - return prev_opcode == opcode && prev_reg == i915_mmio_reg_offset(reg); + return prev_opcode == opcode && prev_reg == intel_reg_offset(reg); } static bool intel_dsb_prev_ins_is_indexed_write(struct intel_dsb *dsb, intel_reg_t reg) @@ -386,7 +386,7 @@ void intel_dsb_reg_write_indexed(struct intel_dsb *dsb, if (!intel_dsb_prev_ins_is_indexed_write(dsb, reg)) intel_dsb_emit(dsb, 0, /* count */ (DSB_OPCODE_INDEXED_WRITE << DSB_OPCODE_SHIFT) | - i915_mmio_reg_offset(reg)); + intel_reg_offset(reg)); if (!assert_dsb_has_room(dsb)) return; @@ -407,7 +407,7 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, intel_dsb_emit(dsb, val, (DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT) | (DSB_BYTE_EN << DSB_BYTE_EN_SHIFT) | - i915_mmio_reg_offset(reg)); + intel_reg_offset(reg)); } static u32 intel_dsb_mask_to_byte_en(u32 mask) @@ -425,7 +425,7 @@ void intel_dsb_reg_write_masked(struct intel_dsb *dsb, intel_dsb_emit(dsb, val, (DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT) | (intel_dsb_mask_to_byte_en(mask) << DSB_BYTE_EN_SHIFT) | - i915_mmio_reg_offset(reg)); + intel_reg_offset(reg)); } void intel_dsb_noop(struct intel_dsb *dsb, int count) @@ -565,7 +565,7 @@ void intel_dsb_poll(struct intel_dsb *dsb, intel_dsb_emit(dsb, val, (DSB_OPCODE_POLL << DSB_OPCODE_SHIFT) | - i915_mmio_reg_offset(reg)); + intel_reg_offset(reg)); } static void intel_dsb_align_tail(struct intel_dsb *dsb) diff --git a/drivers/gpu/drm/i915/display/intel_mchbar.c b/drivers/gpu/drm/i915/display/intel_mchbar.c index 8cfcee4a08a4..a3a69e11c390 100644 --- a/drivers/gpu/drm/i915/display/intel_mchbar.c +++ b/drivers/gpu/drm/i915/display/intel_mchbar.c @@ -44,7 +44,7 @@ static u32 mchbar_mirror_len(struct intel_display *display) static bool is_mchbar_reg(struct intel_display *display, intel_reg_t reg) { return has_mchbar_mirror(display) && - in_range32(i915_mmio_reg_offset(reg), + in_range32(intel_reg_offset(reg), mchbar_mirror_base(display), mchbar_mirror_len(display)); } @@ -53,7 +53,7 @@ static void assert_is_mchbar_reg(struct intel_display *display, intel_reg_t reg) { drm_WARN(display->drm, !is_mchbar_reg(display, reg), "Reading non-MCHBAR register 0x%x\n", - i915_mmio_reg_offset(reg)); + intel_reg_offset(reg)); } u16 intel_mchbar_read16(struct intel_display *display, intel_reg_t reg) diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index ea5e8f75acef..d4c98b150fa2 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -1388,7 +1388,7 @@ intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct intel_pps_delays *s seq->backlight_off = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off); seq->power_down = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off); - if (i915_mmio_reg_valid(regs.pp_div)) { + if (intel_reg_valid(regs.pp_div)) { u32 pp_div; pp_div = intel_de_read(display, regs.pp_div); @@ -1647,7 +1647,7 @@ static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd /* * Compute the divisor for the pp clock, simply match the Bspec formula. */ - if (i915_mmio_reg_valid(regs.pp_div)) + if (intel_reg_valid(regs.pp_div)) intel_de_write(display, regs.pp_div, REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | @@ -1662,7 +1662,7 @@ static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", intel_de_read(display, regs.pp_on), intel_de_read(display, regs.pp_off), - i915_mmio_reg_valid(regs.pp_div) ? + intel_reg_valid(regs.pp_div) ? intel_de_read(display, regs.pp_div) : (intel_de_read(display, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK)); } -- 2.47.3 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* ✗ CI.checkpatch: warning for drm/i915/display: start switching to display specific reg types 2026-04-08 13:15 [PATCH 0/4] drm/i915/display: start switching to display specific reg types Jani Nikula ` (3 preceding siblings ...) 2026-04-08 13:15 ` [PATCH 4/4] drm/i915/display: define and use intel_reg_{offset, equal, valid}() helpers Jani Nikula @ 2026-04-08 13:22 ` Patchwork 2026-04-08 13:25 ` ✗ CI.KUnit: failure " Patchwork 5 siblings, 0 replies; 7+ messages in thread From: Patchwork @ 2026-04-08 13:22 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-xe == Series Details == Series: drm/i915/display: start switching to display specific reg types URL : https://patchwork.freedesktop.org/series/164540/ State : warning == Summary == + KERNEL=/kernel + git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt Cloning into 'mt'... warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/ + git -C mt rev-list -n1 origin/master 1f57ba1afceae32108bd24770069f764d940a0e4 + cd /kernel + git config --global --add safe.directory /kernel + git log -n1 commit 206eb51f33797bae4f7fb95eabada92ef721de88 Author: Jani Nikula <jani.nikula@intel.com> Date: Wed Apr 8 16:15:51 2026 +0300 drm/i915/display: define and use intel_reg_{offset, equal, valid}() helpers Add display specific helpers for getting the register offset, checking for equality and validity. Add them as static inlines for increased type safety. Signed-off-by: Jani Nikula <jani.nikula@intel.com> + /mt/dim checkpatch 90b81c31521783f588ecc70b4cc869c347f7653c drm-intel d80051f59317 drm/i915/display: add typedef for intel_reg_t and use it -:809: WARNING:NEW_TYPEDEFS: do not add new typedefs #809: FILE: drivers/gpu/drm/i915/display/intel_display_reg_defs.h:11: +typedef i915_reg_t intel_reg_t; total: 0 errors, 1 warnings, 0 checks, 1982 lines checked 88f53202f3a8 drm/i915/display: add struct intel_irq_regs and use it -:92: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects? #92: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:1410: +#define GEN8_DE_PIPE_IRQ_REGS(pipe) INTEL_IRQ_REGS(GEN8_DE_PIPE_IMR(pipe), \ + GEN8_DE_PIPE_IER(pipe), \ + GEN8_DE_PIPE_IIR(pipe)) total: 0 errors, 0 warnings, 1 checks, 128 lines checked 25864bacbd36 drm/i915/display: add struct intel_error_regs and use it 206eb51f3379 drm/i915/display: define and use intel_reg_{offset, equal, valid}() helpers -:160: CHECK:SPACING: spaces preferred around that '+' (ctx:VxV) #160: FILE: drivers/gpu/drm/i915/display/intel_dmc.c:1153: + i+1, intel_reg_offset(dmc_info->mmioaddr[i+1]), ^ -:160: CHECK:SPACING: spaces preferred around that '+' (ctx:VxV) #160: FILE: drivers/gpu/drm/i915/display/intel_dmc.c:1153: + i+1, intel_reg_offset(dmc_info->mmioaddr[i+1]), ^ total: 0 errors, 0 warnings, 2 checks, 246 lines checked ^ permalink raw reply [flat|nested] 7+ messages in thread
* ✗ CI.KUnit: failure for drm/i915/display: start switching to display specific reg types 2026-04-08 13:15 [PATCH 0/4] drm/i915/display: start switching to display specific reg types Jani Nikula ` (4 preceding siblings ...) 2026-04-08 13:22 ` ✗ CI.checkpatch: warning for drm/i915/display: start switching to display specific reg types Patchwork @ 2026-04-08 13:25 ` Patchwork 5 siblings, 0 replies; 7+ messages in thread From: Patchwork @ 2026-04-08 13:25 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-xe == Series Details == Series: drm/i915/display: start switching to display specific reg types URL : https://patchwork.freedesktop.org/series/164540/ State : failure == Summary == + trap cleanup EXIT + /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig [13:23:00] Configuring KUnit Kernel ... Generating .config ... Populating config with: $ make ARCH=um O=.kunit olddefconfig [13:23:07] Building KUnit Kernel ... Populating config with: $ make ARCH=um O=.kunit olddefconfig Building with: $ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48 [13:24:12] Starting KUnit Kernel (1/1)... [13:24:12] ============================================================ Running tests with: $ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt [13:24:12] ================== guc_buf (11 subtests) =================== [13:24:12] [PASSED] test_smallest [13:24:12] [PASSED] test_largest [13:24:12] [PASSED] test_granular [13:24:12] [PASSED] test_unique [13:24:12] [PASSED] test_overlap [13:24:12] [PASSED] test_reusable [13:24:12] [PASSED] test_too_big [13:24:12] [PASSED] test_flush [13:24:12] [PASSED] test_lookup [13:24:12] [PASSED] test_data [13:24:12] [PASSED] test_class [13:24:12] ===================== [PASSED] guc_buf ===================== [13:24:12] =================== guc_dbm (7 subtests) =================== [13:24:12] [PASSED] test_empty [13:24:12] [PASSED] test_default [13:24:12] ======================== test_size ======================== [13:24:12] [PASSED] 4 [13:24:12] [PASSED] 8 [13:24:12] [PASSED] 32 [13:24:12] [PASSED] 256 [13:24:12] ==================== [PASSED] test_size ==================== [13:24:12] ======================= test_reuse ======================== [13:24:12] [PASSED] 4 [13:24:12] [PASSED] 8 [13:24:12] [PASSED] 32 [13:24:12] [PASSED] 256 [13:24:12] =================== [PASSED] test_reuse ==================== [13:24:12] =================== test_range_overlap ==================== [13:24:12] [PASSED] 4 [13:24:12] [PASSED] 8 [13:24:12] [PASSED] 32 [13:24:12] [PASSED] 256 [13:24:12] =============== [PASSED] test_range_overlap ================ [13:24:12] =================== test_range_compact ==================== [13:24:12] [PASSED] 4 [13:24:12] [PASSED] 8 [13:24:12] [PASSED] 32 [13:24:12] [PASSED] 256 [13:24:12] =============== [PASSED] test_range_compact ================ [13:24:12] ==================== test_range_spare ===================== [13:24:12] [PASSED] 4 [13:24:12] [PASSED] 8 [13:24:12] [PASSED] 32 [13:24:12] [PASSED] 256 [13:24:12] ================ [PASSED] test_range_spare ================= [13:24:12] ===================== [PASSED] guc_dbm ===================== [13:24:12] =================== guc_idm (6 subtests) =================== [13:24:12] [PASSED] bad_init [13:24:12] [PASSED] no_init [13:24:12] [PASSED] init_fini [13:24:12] [PASSED] check_used [13:24:12] [PASSED] check_quota [13:24:12] [PASSED] check_all [13:24:12] ===================== [PASSED] guc_idm ===================== [13:24:12] ================== no_relay (3 subtests) =================== [13:24:12] [PASSED] xe_drops_guc2pf_if_not_ready [13:24:12] [PASSED] xe_drops_guc2vf_if_not_ready [13:24:12] [PASSED] xe_rejects_send_if_not_ready [13:24:12] ==================== [PASSED] no_relay ===================== [13:24:12] ================== pf_relay (14 subtests) ================== [13:24:12] [PASSED] pf_rejects_guc2pf_too_short [13:24:12] [PASSED] pf_rejects_guc2pf_too_long [13:24:12] [PASSED] pf_rejects_guc2pf_no_payload [13:24:12] [PASSED] pf_fails_no_payload [13:24:12] [PASSED] pf_fails_bad_origin [13:24:12] [PASSED] pf_fails_bad_type [13:24:12] [PASSED] pf_txn_reports_error [13:24:12] [PASSED] pf_txn_sends_pf2guc [13:24:12] [PASSED] pf_sends_pf2guc [13:24:12] [SKIPPED] pf_loopback_nop [13:24:12] [SKIPPED] pf_loopback_echo [13:24:12] [SKIPPED] pf_loopback_fail [13:24:12] [SKIPPED] pf_loopback_busy [13:24:12] [SKIPPED] pf_loopback_retry [13:24:12] ==================== [PASSED] pf_relay ===================== [13:24:12] ================== vf_relay (3 subtests) =================== [13:24:12] [PASSED] vf_rejects_guc2vf_too_short [13:24:12] [PASSED] vf_rejects_guc2vf_too_long [13:24:12] [PASSED] vf_rejects_guc2vf_no_payload [13:24:12] ==================== [PASSED] vf_relay ===================== [13:24:12] ================ pf_gt_config (9 subtests) ================= [13:24:12] [PASSED] fair_contexts_1vf [13:24:12] [PASSED] fair_doorbells_1vf [13:24:12] [PASSED] fair_ggtt_1vf [13:24:12] ====================== fair_vram_1vf ====================== [13:24:12] [PASSED] 3.50 GiB [13:24:12] [PASSED] 11.5 GiB [13:24:12] [PASSED] 15.5 GiB [13:24:12] [PASSED] 31.5 GiB [13:24:12] [PASSED] 63.5 GiB [13:24:12] [PASSED] 1.91 GiB [13:24:12] ================== [PASSED] fair_vram_1vf ================== [13:24:12] ================ fair_vram_1vf_admin_only ================= [13:24:12] [PASSED] 3.50 GiB [13:24:12] [PASSED] 11.5 GiB [13:24:12] [PASSED] 15.5 GiB [13:24:12] [PASSED] 31.5 GiB [13:24:12] [PASSED] 63.5 GiB [13:24:12] [PASSED] 1.91 GiB [13:24:12] ============ [PASSED] fair_vram_1vf_admin_only ============= [13:24:12] ====================== fair_contexts ====================== [13:24:12] [PASSED] 1 VF [13:24:12] [PASSED] 2 VFs [13:24:12] [PASSED] 3 VFs [13:24:12] [PASSED] 4 VFs [13:24:12] [PASSED] 5 VFs [13:24:12] [PASSED] 6 VFs [13:24:12] [PASSED] 7 VFs [13:24:12] [PASSED] 8 VFs [13:24:12] [PASSED] 9 VFs [13:24:12] [PASSED] 10 VFs [13:24:12] [PASSED] 11 VFs [13:24:12] [PASSED] 12 VFs [13:24:12] [PASSED] 13 VFs [13:24:12] [PASSED] 14 VFs [13:24:12] [PASSED] 15 VFs [13:24:12] [PASSED] 16 VFs [13:24:12] [PASSED] 17 VFs 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[13:24:12] [PASSED] 55 VFs [13:24:12] [PASSED] 56 VFs [13:24:12] [PASSED] 57 VFs [13:24:12] [PASSED] 58 VFs [13:24:12] [PASSED] 59 VFs [13:24:12] [PASSED] 60 VFs [13:24:12] [PASSED] 61 VFs [13:24:12] [PASSED] 62 VFs [13:24:12] [PASSED] 63 VFs [13:24:12] ================== [PASSED] fair_contexts ================== [13:24:12] ===================== fair_doorbells ====================== [13:24:12] [PASSED] 1 VF [13:24:12] [PASSED] 2 VFs [13:24:12] [PASSED] 3 VFs [13:24:12] [PASSED] 4 VFs [13:24:12] [PASSED] 5 VFs [13:24:12] [PASSED] 6 VFs [13:24:12] [PASSED] 7 VFs [13:24:12] [PASSED] 8 VFs [13:24:12] [PASSED] 9 VFs [13:24:12] [PASSED] 10 VFs [13:24:12] [PASSED] 11 VFs [13:24:12] [PASSED] 12 VFs [13:24:12] [PASSED] 13 VFs [13:24:12] [PASSED] 14 VFs [13:24:12] [PASSED] 15 VFs [13:24:12] [PASSED] 16 VFs [13:24:12] [PASSED] 17 VFs [13:24:12] [PASSED] 18 VFs [13:24:12] [PASSED] 19 VFs [13:24:12] [PASSED] 20 VFs [13:24:12] [PASSED] 21 VFs [13:24:12] [PASSED] 22 VFs [13:24:12] [PASSED] 23 VFs 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[13:24:13] [PASSED] 61 VFs [13:24:13] [PASSED] 62 VFs [13:24:13] [PASSED] 63 VFs [13:24:13] ================= [PASSED] fair_doorbells ================== [13:24:13] ======================== fair_ggtt ======================== [13:24:13] [PASSED] 1 VF [13:24:13] [PASSED] 2 VFs [13:24:13] [PASSED] 3 VFs [13:24:13] [PASSED] 4 VFs [13:24:13] [PASSED] 5 VFs [13:24:13] [PASSED] 6 VFs [13:24:13] [PASSED] 7 VFs [13:24:13] [PASSED] 8 VFs [13:24:13] [PASSED] 9 VFs [13:24:13] [PASSED] 10 VFs [13:24:13] [PASSED] 11 VFs [13:24:13] [PASSED] 12 VFs [13:24:13] [PASSED] 13 VFs [13:24:13] [PASSED] 14 VFs [13:24:13] [PASSED] 15 VFs [13:24:13] [PASSED] 16 VFs [13:24:13] [PASSED] 17 VFs [13:24:13] [PASSED] 18 VFs [13:24:13] [PASSED] 19 VFs [13:24:13] [PASSED] 20 VFs [13:24:13] [PASSED] 21 VFs [13:24:13] [PASSED] 22 VFs [13:24:13] [PASSED] 23 VFs [13:24:13] [PASSED] 24 VFs [13:24:13] [PASSED] 25 VFs [13:24:13] [PASSED] 26 VFs [13:24:13] [PASSED] 27 VFs [13:24:13] [PASSED] 28 VFs [13:24:13] [PASSED] 29 VFs [13:24:13] [PASSED] 30 VFs [13:24:13] [PASSED] 31 VFs [13:24:13] [PASSED] 32 VFs [13:24:13] [PASSED] 33 VFs [13:24:13] [PASSED] 34 VFs [13:24:13] [PASSED] 35 VFs [13:24:13] [PASSED] 36 VFs [13:24:13] [PASSED] 37 VFs [13:24:13] [PASSED] 38 VFs [13:24:13] [PASSED] 39 VFs [13:24:13] [PASSED] 40 VFs [13:24:13] [PASSED] 41 VFs [13:24:13] [PASSED] 42 VFs [13:24:13] [PASSED] 43 VFs [13:24:13] [PASSED] 44 VFs [13:24:13] [PASSED] 45 VFs [13:24:13] [PASSED] 46 VFs [13:24:13] [PASSED] 47 VFs [13:24:13] [PASSED] 48 VFs [13:24:13] [PASSED] 49 VFs [13:24:13] [PASSED] 50 VFs [13:24:13] [PASSED] 51 VFs [13:24:13] [PASSED] 52 VFs [13:24:13] [PASSED] 53 VFs [13:24:13] [PASSED] 54 VFs [13:24:13] [PASSED] 55 VFs [13:24:13] [PASSED] 56 VFs [13:24:13] [PASSED] 57 VFs [13:24:13] [PASSED] 58 VFs [13:24:13] [PASSED] 59 VFs [13:24:13] [PASSED] 60 VFs [13:24:13] [PASSED] 61 VFs [13:24:13] [PASSED] 62 VFs [13:24:13] [PASSED] 63 VFs [13:24:13] ==================== [PASSED] fair_ggtt ==================== [13:24:13] ======================== fair_vram ======================== [13:24:13] [PASSED] 1 VF [13:24:13] [PASSED] 2 VFs [13:24:13] [PASSED] 3 VFs [13:24:13] [PASSED] 4 VFs [13:24:13] [PASSED] 5 VFs [13:24:13] [PASSED] 6 VFs [13:24:13] [PASSED] 7 VFs [13:24:13] [PASSED] 8 VFs [13:24:13] [PASSED] 9 VFs [13:24:13] [PASSED] 10 VFs [13:24:13] [PASSED] 11 VFs [13:24:13] [PASSED] 12 VFs [13:24:13] [PASSED] 13 VFs [13:24:13] [PASSED] 14 VFs [13:24:13] [PASSED] 15 VFs [13:24:13] [PASSED] 16 VFs [13:24:13] [PASSED] 17 VFs [13:24:13] [PASSED] 18 VFs [13:24:13] [PASSED] 19 VFs [13:24:13] [PASSED] 20 VFs [13:24:13] [PASSED] 21 VFs [13:24:13] [PASSED] 22 VFs [13:24:13] [PASSED] 23 VFs [13:24:13] [PASSED] 24 VFs [13:24:13] [PASSED] 25 VFs [13:24:13] [PASSED] 26 VFs [13:24:13] [PASSED] 27 VFs [13:24:13] [PASSED] 28 VFs [13:24:13] [PASSED] 29 VFs [13:24:13] [PASSED] 30 VFs [13:24:13] [PASSED] 31 VFs [13:24:13] [PASSED] 32 VFs [13:24:13] [PASSED] 33 VFs [13:24:13] [PASSED] 34 VFs [13:24:13] [PASSED] 35 VFs [13:24:13] [PASSED] 36 VFs [13:24:13] [PASSED] 37 VFs [13:24:13] [PASSED] 38 VFs [13:24:13] [PASSED] 39 VFs [13:24:13] [PASSED] 40 VFs [13:24:13] [PASSED] 41 VFs [13:24:13] [PASSED] 42 VFs [13:24:13] [PASSED] 43 VFs [13:24:13] [PASSED] 44 VFs [13:24:13] [PASSED] 45 VFs [13:24:13] [PASSED] 46 VFs [13:24:13] [PASSED] 47 VFs [13:24:13] [PASSED] 48 VFs [13:24:13] [PASSED] 49 VFs [13:24:13] [PASSED] 50 VFs [13:24:13] [PASSED] 51 VFs [13:24:13] [PASSED] 52 VFs [13:24:13] [PASSED] 53 VFs [13:24:13] [PASSED] 54 VFs [13:24:13] [PASSED] 55 VFs [13:24:13] [PASSED] 56 VFs [13:24:13] [PASSED] 57 VFs [13:24:13] [PASSED] 58 VFs [13:24:13] [PASSED] 59 VFs [13:24:13] [PASSED] 60 VFs [13:24:13] [PASSED] 61 VFs [13:24:13] [PASSED] 62 VFs [13:24:13] [PASSED] 63 VFs [13:24:13] ==================== [PASSED] fair_vram ==================== [13:24:13] ================== [PASSED] pf_gt_config =================== [13:24:13] ===================== lmtt (1 subtest) ===================== [13:24:13] ======================== test_ops ========================= [13:24:13] [PASSED] 2-level [13:24:13] [PASSED] multi-level [13:24:13] ==================== [PASSED] test_ops ===================== [13:24:13] ====================== [PASSED] lmtt ======================= [13:24:13] ================= pf_service (11 subtests) ================= [13:24:13] [PASSED] pf_negotiate_any [13:24:13] [PASSED] pf_negotiate_base_match [13:24:13] [PASSED] pf_negotiate_base_newer [13:24:13] [PASSED] pf_negotiate_base_next [13:24:13] [SKIPPED] pf_negotiate_base_older [13:24:13] [PASSED] pf_negotiate_base_prev [13:24:13] [PASSED] pf_negotiate_latest_match [13:24:13] [PASSED] pf_negotiate_latest_newer [13:24:13] [PASSED] pf_negotiate_latest_next [13:24:13] [SKIPPED] pf_negotiate_latest_older [13:24:13] [SKIPPED] pf_negotiate_latest_prev [13:24:13] =================== [PASSED] pf_service ==================== [13:24:13] ================= xe_guc_g2g (2 subtests) ================== [13:24:13] ============== xe_live_guc_g2g_kunit_default ============== [13:24:13] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ========== [13:24:13] ============== xe_live_guc_g2g_kunit_allmem =============== [13:24:13] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ========== [13:24:13] =================== [SKIPPED] xe_guc_g2g =================== [13:24:13] =================== xe_mocs (2 subtests) =================== [13:24:13] ================ xe_live_mocs_kernel_kunit ================ [13:24:13] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============ [13:24:13] ================ xe_live_mocs_reset_kunit ================= [13:24:13] ============ [SKIPPED] xe_live_mocs_reset_kunit ============ [13:24:13] ==================== [SKIPPED] xe_mocs ===================== [13:24:13] ================= xe_migrate (2 subtests) ================== [13:24:13] ================= xe_migrate_sanity_kunit ================= [13:24:13] ============ [SKIPPED] xe_migrate_sanity_kunit ============= [13:24:13] ================== xe_validate_ccs_kunit ================== [13:24:13] ============= [SKIPPED] xe_validate_ccs_kunit ============== [13:24:13] =================== [SKIPPED] xe_migrate =================== [13:24:13] ================== xe_dma_buf (1 subtest) ================== [13:24:13] ==================== xe_dma_buf_kunit ===================== [13:24:13] ================ [SKIPPED] xe_dma_buf_kunit ================ [13:24:13] =================== [SKIPPED] xe_dma_buf =================== [13:24:13] ================= xe_bo_shrink (1 subtest) ================= [13:24:13] =================== xe_bo_shrink_kunit ==================== [13:24:13] =============== [SKIPPED] xe_bo_shrink_kunit =============== [13:24:13] ================== [SKIPPED] xe_bo_shrink ================== [13:24:13] ==================== xe_bo (2 subtests) ==================== [13:24:13] ================== xe_ccs_migrate_kunit =================== [13:24:13] ============== [SKIPPED] xe_ccs_migrate_kunit ============== [13:24:13] ==================== xe_bo_evict_kunit ==================== [13:24:13] =============== [SKIPPED] xe_bo_evict_kunit ================ [13:24:13] ===================== [SKIPPED] xe_bo ====================== [13:24:13] ==================== args (13 subtests) ==================== [13:24:13] [PASSED] count_args_test [13:24:13] [PASSED] call_args_example [13:24:13] [PASSED] call_args_test [13:24:13] [PASSED] drop_first_arg_example [13:24:13] [PASSED] drop_first_arg_test [13:24:13] [PASSED] first_arg_example [13:24:13] [PASSED] first_arg_test [13:24:13] [PASSED] last_arg_example [13:24:13] [PASSED] last_arg_test [13:24:13] [PASSED] pick_arg_example [13:24:13] [PASSED] if_args_example [13:24:13] [PASSED] if_args_test [13:24:13] [PASSED] sep_comma_example [13:24:13] ====================== [PASSED] args ======================= [13:24:13] =================== xe_pci (3 subtests) ==================== [13:24:13] ==================== check_graphics_ip ==================== [13:24:13] [PASSED] 12.00 Xe_LP [13:24:13] [PASSED] 12.10 Xe_LP+ [13:24:13] [PASSED] 12.55 Xe_HPG [13:24:13] [PASSED] 12.60 Xe_HPC [13:24:13] [PASSED] 12.70 Xe_LPG [13:24:13] [PASSED] 12.71 Xe_LPG [13:24:13] [PASSED] 12.74 Xe_LPG+ [13:24:13] [PASSED] 20.01 Xe2_HPG [13:24:13] [PASSED] 20.02 Xe2_HPG [13:24:13] [PASSED] 20.04 Xe2_LPG [13:24:13] [PASSED] 30.00 Xe3_LPG [13:24:13] [PASSED] 30.01 Xe3_LPG [13:24:13] [PASSED] 30.03 Xe3_LPG [13:24:13] [PASSED] 30.04 Xe3_LPG [13:24:13] [PASSED] 30.05 Xe3_LPG [13:24:13] [PASSED] 35.10 Xe3p_LPG [13:24:13] [PASSED] 35.11 Xe3p_XPC [13:24:13] ================ [PASSED] check_graphics_ip ================ [13:24:13] ===================== check_media_ip ====================== [13:24:13] [PASSED] 12.00 Xe_M [13:24:13] [PASSED] 12.55 Xe_HPM [13:24:13] [PASSED] 13.00 Xe_LPM+ [13:24:13] [PASSED] 13.01 Xe2_HPM [13:24:13] [PASSED] 20.00 Xe2_LPM [13:24:13] [PASSED] 30.00 Xe3_LPM [13:24:13] [PASSED] 30.02 Xe3_LPM [13:24:13] [PASSED] 35.00 Xe3p_LPM [13:24:13] [PASSED] 35.03 Xe3p_HPM [13:24:13] ================= [PASSED] check_media_ip ================== [13:24:13] =================== check_platform_desc =================== [13:24:13] [PASSED] 0x9A60 (TIGERLAKE) [13:24:13] [PASSED] 0x9A68 (TIGERLAKE) [13:24:13] [PASSED] 0x9A70 (TIGERLAKE) [13:24:13] [PASSED] 0x9A40 (TIGERLAKE) [13:24:13] [PASSED] 0x9A49 (TIGERLAKE) [13:24:13] [PASSED] 0x9A59 (TIGERLAKE) [13:24:13] [PASSED] 0x9A78 (TIGERLAKE) [13:24:13] [PASSED] 0x9AC0 (TIGERLAKE) [13:24:13] [PASSED] 0x9AC9 (TIGERLAKE) [13:24:13] [PASSED] 0x9AD9 (TIGERLAKE) [13:24:13] [PASSED] 0x9AF8 (TIGERLAKE) [13:24:13] [PASSED] 0x4C80 (ROCKETLAKE) [13:24:13] [PASSED] 0x4C8A (ROCKETLAKE) [13:24:13] [PASSED] 0x4C8B (ROCKETLAKE) [13:24:13] [PASSED] 0x4C8C (ROCKETLAKE) [13:24:13] [PASSED] 0x4C90 (ROCKETLAKE) [13:24:13] [PASSED] 0x4C9A (ROCKETLAKE) [13:24:13] [PASSED] 0x4680 (ALDERLAKE_S) [13:24:13] [PASSED] 0x4682 (ALDERLAKE_S) [13:24:13] [PASSED] 0x4688 (ALDERLAKE_S) [13:24:13] [PASSED] 0x468A (ALDERLAKE_S) [13:24:13] [PASSED] 0x468B (ALDERLAKE_S) [13:24:13] [PASSED] 0x4690 (ALDERLAKE_S) [13:24:13] [PASSED] 0x4692 (ALDERLAKE_S) [13:24:13] [PASSED] 0x4693 (ALDERLAKE_S) [13:24:13] [PASSED] 0x46A0 (ALDERLAKE_P) [13:24:13] [PASSED] 0x46A1 (ALDERLAKE_P) [13:24:13] [PASSED] 0x46A2 (ALDERLAKE_P) [13:24:13] [PASSED] 0x46A3 (ALDERLAKE_P) [13:24:13] [PASSED] 0x46A6 (ALDERLAKE_P) [13:24:13] [PASSED] 0x46A8 (ALDERLAKE_P) [13:24:13] [PASSED] 0x46AA (ALDERLAKE_P) [13:24:13] [PASSED] 0x462A (ALDERLAKE_P) [13:24:13] [PASSED] 0x4626 (ALDERLAKE_P) [13:24:13] [PASSED] 0x4628 (ALDERLAKE_P) [13:24:13] [PASSED] 0x46B0 (ALDERLAKE_P) [13:24:13] [PASSED] 0x46B1 (ALDERLAKE_P) [13:24:13] [PASSED] 0x46B2 (ALDERLAKE_P) [13:24:13] [PASSED] 0x46B3 (ALDERLAKE_P) [13:24:13] [PASSED] 0x46C0 (ALDERLAKE_P) [13:24:13] [PASSED] 0x46C1 (ALDERLAKE_P) [13:24:13] [PASSED] 0x46C2 (ALDERLAKE_P) [13:24:13] [PASSED] 0x46C3 (ALDERLAKE_P) [13:24:13] [PASSED] 0x46D0 (ALDERLAKE_N) [13:24:13] [PASSED] 0x46D1 (ALDERLAKE_N) [13:24:13] [PASSED] 0x46D2 (ALDERLAKE_N) [13:24:13] [PASSED] 0x46D3 (ALDERLAKE_N) [13:24:13] [PASSED] 0x46D4 (ALDERLAKE_N) [13:24:13] [PASSED] 0xA721 (ALDERLAKE_P) [13:24:13] [PASSED] 0xA7A1 (ALDERLAKE_P) [13:24:13] [PASSED] 0xA7A9 (ALDERLAKE_P) [13:24:13] [PASSED] 0xA7AC (ALDERLAKE_P) [13:24:13] [PASSED] 0xA7AD (ALDERLAKE_P) [13:24:13] [PASSED] 0xA720 (ALDERLAKE_P) [13:24:13] [PASSED] 0xA7A0 (ALDERLAKE_P) [13:24:13] [PASSED] 0xA7A8 (ALDERLAKE_P) [13:24:13] [PASSED] 0xA7AA (ALDERLAKE_P) [13:24:13] [PASSED] 0xA7AB (ALDERLAKE_P) [13:24:13] [PASSED] 0xA780 (ALDERLAKE_S) [13:24:13] [PASSED] 0xA781 (ALDERLAKE_S) [13:24:13] [PASSED] 0xA782 (ALDERLAKE_S) [13:24:13] [PASSED] 0xA783 (ALDERLAKE_S) [13:24:13] [PASSED] 0xA788 (ALDERLAKE_S) [13:24:13] [PASSED] 0xA789 (ALDERLAKE_S) [13:24:13] [PASSED] 0xA78A (ALDERLAKE_S) [13:24:13] [PASSED] 0xA78B (ALDERLAKE_S) [13:24:13] [PASSED] 0x4905 (DG1) [13:24:13] [PASSED] 0x4906 (DG1) [13:24:13] [PASSED] 0x4907 (DG1) [13:24:13] [PASSED] 0x4908 (DG1) [13:24:13] [PASSED] 0x4909 (DG1) [13:24:13] [PASSED] 0x56C0 (DG2) [13:24:13] [PASSED] 0x56C2 (DG2) [13:24:13] [PASSED] 0x56C1 (DG2) [13:24:13] [PASSED] 0x7D51 (METEORLAKE) [13:24:13] [PASSED] 0x7DD1 (METEORLAKE) [13:24:13] [PASSED] 0x7D41 (METEORLAKE) [13:24:13] [PASSED] 0x7D67 (METEORLAKE) [13:24:13] [PASSED] 0xB640 (METEORLAKE) [13:24:13] [PASSED] 0x56A0 (DG2) [13:24:13] [PASSED] 0x56A1 (DG2) [13:24:13] [PASSED] 0x56A2 (DG2) [13:24:13] [PASSED] 0x56BE (DG2) [13:24:13] [PASSED] 0x56BF (DG2) [13:24:13] [PASSED] 0x5690 (DG2) [13:24:13] [PASSED] 0x5691 (DG2) [13:24:13] [PASSED] 0x5692 (DG2) [13:24:13] [PASSED] 0x56A5 (DG2) [13:24:13] [PASSED] 0x56A6 (DG2) [13:24:13] [PASSED] 0x56B0 (DG2) [13:24:13] [PASSED] 0x56B1 (DG2) [13:24:13] [PASSED] 0x56BA (DG2) [13:24:13] [PASSED] 0x56BB (DG2) [13:24:13] [PASSED] 0x56BC (DG2) [13:24:13] [PASSED] 0x56BD (DG2) [13:24:13] [PASSED] 0x5693 (DG2) [13:24:13] [PASSED] 0x5694 (DG2) [13:24:13] [PASSED] 0x5695 (DG2) [13:24:13] [PASSED] 0x56A3 (DG2) [13:24:13] [PASSED] 0x56A4 (DG2) [13:24:13] [PASSED] 0x56B2 (DG2) [13:24:13] [PASSED] 0x56B3 (DG2) [13:24:13] [PASSED] 0x5696 (DG2) [13:24:13] [PASSED] 0x5697 (DG2) [13:24:13] [PASSED] 0xB69 (PVC) [13:24:13] [PASSED] 0xB6E (PVC) [13:24:13] [PASSED] 0xBD4 (PVC) [13:24:13] [PASSED] 0xBD5 (PVC) [13:24:13] [PASSED] 0xBD6 (PVC) [13:24:13] [PASSED] 0xBD7 (PVC) [13:24:13] [PASSED] 0xBD8 (PVC) [13:24:13] [PASSED] 0xBD9 (PVC) [13:24:13] [PASSED] 0xBDA (PVC) [13:24:13] [PASSED] 0xBDB (PVC) [13:24:13] [PASSED] 0xBE0 (PVC) [13:24:13] [PASSED] 0xBE1 (PVC) [13:24:13] [PASSED] 0xBE5 (PVC) [13:24:13] [PASSED] 0x7D40 (METEORLAKE) [13:24:13] [PASSED] 0x7D45 (METEORLAKE) [13:24:13] [PASSED] 0x7D55 (METEORLAKE) [13:24:13] [PASSED] 0x7D60 (METEORLAKE) [13:24:13] [PASSED] 0x7DD5 (METEORLAKE) [13:24:13] [PASSED] 0x6420 (LUNARLAKE) [13:24:13] [PASSED] 0x64A0 (LUNARLAKE) [13:24:13] [PASSED] 0x64B0 (LUNARLAKE) [13:24:13] [PASSED] 0xE202 (BATTLEMAGE) [13:24:13] [PASSED] 0xE209 (BATTLEMAGE) [13:24:13] [PASSED] 0xE20B (BATTLEMAGE) [13:24:13] [PASSED] 0xE20C (BATTLEMAGE) [13:24:13] [PASSED] 0xE20D (BATTLEMAGE) [13:24:13] [PASSED] 0xE210 (BATTLEMAGE) [13:24:13] [PASSED] 0xE211 (BATTLEMAGE) [13:24:13] [PASSED] 0xE212 (BATTLEMAGE) [13:24:13] [PASSED] 0xE216 (BATTLEMAGE) [13:24:13] [PASSED] 0xE220 (BATTLEMAGE) [13:24:13] [PASSED] 0xE221 (BATTLEMAGE) [13:24:13] [PASSED] 0xE222 (BATTLEMAGE) [13:24:13] [PASSED] 0xE223 (BATTLEMAGE) [13:24:13] [PASSED] 0xB080 (PANTHERLAKE) [13:24:13] [PASSED] 0xB081 (PANTHERLAKE) [13:24:13] [PASSED] 0xB082 (PANTHERLAKE) [13:24:13] [PASSED] 0xB083 (PANTHERLAKE) [13:24:13] [PASSED] 0xB084 (PANTHERLAKE) [13:24:13] [PASSED] 0xB085 (PANTHERLAKE) [13:24:13] [PASSED] 0xB086 (PANTHERLAKE) [13:24:13] [PASSED] 0xB087 (PANTHERLAKE) [13:24:13] [PASSED] 0xB08F (PANTHERLAKE) [13:24:13] [PASSED] 0xB090 (PANTHERLAKE) [13:24:13] [PASSED] 0xB0A0 (PANTHERLAKE) [13:24:13] [PASSED] 0xB0B0 (PANTHERLAKE) [13:24:13] [PASSED] 0xFD80 (PANTHERLAKE) [13:24:13] [PASSED] 0xFD81 (PANTHERLAKE) [13:24:13] [PASSED] 0xD740 (NOVALAKE_S) [13:24:13] [PASSED] 0xD741 (NOVALAKE_S) [13:24:13] [PASSED] 0xD742 (NOVALAKE_S) [13:24:13] [PASSED] 0xD743 (NOVALAKE_S) [13:24:13] [PASSED] 0xD744 (NOVALAKE_S) [13:24:13] [PASSED] 0xD745 (NOVALAKE_S) [13:24:13] [PASSED] 0x674C (CRESCENTISLAND) [13:24:13] [PASSED] 0xD750 (NOVALAKE_P) [13:24:13] [PASSED] 0xD751 (NOVALAKE_P) [13:24:13] [PASSED] 0xD752 (NOVALAKE_P) [13:24:13] [PASSED] 0xD753 (NOVALAKE_P) [13:24:13] [PASSED] 0xD754 (NOVALAKE_P) [13:24:13] [PASSED] 0xD755 (NOVALAKE_P) [13:24:13] [PASSED] 0xD756 (NOVALAKE_P) [13:24:13] [PASSED] 0xD757 (NOVALAKE_P) [13:24:13] [PASSED] 0xD75F (NOVALAKE_P) [13:24:13] =============== [PASSED] check_platform_desc =============== [13:24:13] ===================== [PASSED] xe_pci ====================== [13:24:13] =================== xe_rtp (2 subtests) ==================== [13:24:13] =============== xe_rtp_process_to_sr_tests ================ [13:24:13] [PASSED] coalesce-same-reg [13:24:13] [PASSED] no-match-no-add [13:24:13] [PASSED] match-or [13:24:13] [PASSED] match-or-xfail [13:24:13] [PASSED] no-match-no-add-multiple-rules [13:24:13] [PASSED] two-regs-two-entries [13:24:13] [PASSED] clr-one-set-other [13:24:13] [PASSED] set-field [13:24:13] [PASSED] conflict-duplicate stty: 'standard input': Inappropriate ioctl for device [13:24:13] [PASSED] conflict-not-disjoint [13:24:13] [PASSED] conflict-reg-type [13:24:13] =========== [PASSED] xe_rtp_process_to_sr_tests ============ [13:24:13] ================== xe_rtp_process_tests =================== [13:24:13] [PASSED] active1 [13:24:13] [PASSED] active2 [13:24:13] [PASSED] active-inactive [13:24:13] [PASSED] inactive-active [13:24:13] [PASSED] inactive-1st_or_active-inactive [13:24:13] [PASSED] inactive-2nd_or_active-inactive [13:24:13] [PASSED] inactive-last_or_active-inactive [13:24:13] [PASSED] inactive-no_or_active-inactive [13:24:13] ============== [PASSED] xe_rtp_process_tests =============== [13:24:13] ===================== [PASSED] xe_rtp ====================== [13:24:13] ==================== xe_wa (1 subtest) ===================== [13:24:13] ======================== xe_wa_gt ========================= [13:24:13] [PASSED] TIGERLAKE B0 [13:24:13] [PASSED] DG1 A0 [13:24:13] [PASSED] DG1 B0 [13:24:13] [PASSED] ALDERLAKE_S A0 [13:24:13] [PASSED] ALDERLAKE_S B0 [13:24:13] [PASSED] ALDERLAKE_S C0 [13:24:13] [PASSED] ALDERLAKE_S D0 [13:24:13] [PASSED] ALDERLAKE_P A0 [13:24:13] [PASSED] ALDERLAKE_P B0 [13:24:13] [PASSED] ALDERLAKE_P C0 [13:24:13] [PASSED] ALDERLAKE_S RPLS D0 [13:24:13] [PASSED] ALDERLAKE_P RPLU E0 [13:24:13] [PASSED] DG2 G10 C0 [13:24:13] [PASSED] DG2 G11 B1 [13:24:13] [PASSED] DG2 G12 A1 [13:24:13] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0 [13:24:13] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0 [13:24:13] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0 [13:24:13] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0 [13:24:13] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0 [13:24:13] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1 [13:24:13] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0 [13:24:13] ==================== [PASSED] xe_wa_gt ===================== [13:24:13] ====================== [PASSED] xe_wa ====================== [13:24:13] ============================================================ [13:24:13] Testing complete. Ran 597 tests: passed: 579, skipped: 18 [13:24:13] Elapsed time: 73.066s total, 7.195s configuring, 64.745s building, 1.087s running + /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig [13:24:13] Configuring KUnit Kernel ... Regenerating .config ... Populating config with: $ make ARCH=um O=.kunit olddefconfig [13:24:16] Building KUnit Kernel ... Populating config with: $ make ARCH=um O=.kunit olddefconfig Building with: $ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48 [13:25:03] Starting KUnit Kernel (1/1)... [13:25:03] ============================================================ Running tests with: $ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt [13:25:03] ============ drm_test_pick_cmdline (2 subtests) ============ [13:25:03] [PASSED] drm_test_pick_cmdline_res_1920_1080_60 [13:25:03] =============== drm_test_pick_cmdline_named =============== [13:25:03] [PASSED] NTSC [13:25:03] [PASSED] NTSC-J [13:25:03] [PASSED] PAL [13:25:03] [PASSED] PAL-M [13:25:03] =========== [PASSED] drm_test_pick_cmdline_named =========== [13:25:03] ============== [PASSED] drm_test_pick_cmdline ============== [13:25:03] == drm_test_atomic_get_connector_for_encoder (1 subtest) === [13:25:03] [PASSED] drm_test_drm_atomic_get_connector_for_encoder [13:25:03] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ==== [13:25:03] =========== drm_validate_clone_mode (2 subtests) =========== [13:25:03] ============== drm_test_check_in_clone_mode =============== [13:25:03] [PASSED] in_clone_mode [13:25:03] [PASSED] not_in_clone_mode [13:25:03] ========== [PASSED] drm_test_check_in_clone_mode =========== [13:25:03] =============== drm_test_check_valid_clones =============== [13:25:03] [PASSED] not_in_clone_mode [13:25:03] [PASSED] valid_clone [13:25:03] [PASSED] invalid_clone [13:25:03] =========== [PASSED] drm_test_check_valid_clones =========== [13:25:03] ============= [PASSED] drm_validate_clone_mode ============= [13:25:03] ============= drm_validate_modeset (1 subtest) ============= [13:25:03] [PASSED] drm_test_check_connector_changed_modeset [13:25:03] ============== [PASSED] drm_validate_modeset =============== [13:25:03] ====== drm_test_bridge_get_current_state (2 subtests) ====== [13:25:03] [PASSED] drm_test_drm_bridge_get_current_state_atomic [13:25:03] [PASSED] drm_test_drm_bridge_get_current_state_legacy [13:25:03] ======== [PASSED] drm_test_bridge_get_current_state ======== [13:25:03] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ====== [13:25:03] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic [13:25:03] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled [13:25:03] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy [13:25:03] ======== [PASSED] drm_test_bridge_helper_reset_crtc ======== [13:25:03] ============== drm_bridge_alloc (2 subtests) =============== [13:25:03] [PASSED] drm_test_drm_bridge_alloc_basic [13:25:03] [PASSED] drm_test_drm_bridge_alloc_get_put [13:25:03] ================ [PASSED] drm_bridge_alloc ================= [13:25:03] ============= drm_cmdline_parser (40 subtests) ============= [13:25:03] [PASSED] drm_test_cmdline_force_d_only [13:25:03] [PASSED] drm_test_cmdline_force_D_only_dvi [13:25:03] [PASSED] drm_test_cmdline_force_D_only_hdmi [13:25:03] [PASSED] drm_test_cmdline_force_D_only_not_digital [13:25:03] [PASSED] drm_test_cmdline_force_e_only [13:25:03] [PASSED] drm_test_cmdline_res [13:25:03] [PASSED] drm_test_cmdline_res_vesa [13:25:03] [PASSED] drm_test_cmdline_res_vesa_rblank [13:25:03] [PASSED] drm_test_cmdline_res_rblank [13:25:03] [PASSED] drm_test_cmdline_res_bpp [13:25:03] [PASSED] drm_test_cmdline_res_refresh [13:25:03] [PASSED] drm_test_cmdline_res_bpp_refresh [13:25:03] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced [13:25:03] [PASSED] drm_test_cmdline_res_bpp_refresh_margins [13:25:03] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off [13:25:03] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on [13:25:03] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog [13:25:03] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital [13:25:03] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on [13:25:03] [PASSED] drm_test_cmdline_res_margins_force_on [13:25:03] [PASSED] drm_test_cmdline_res_vesa_margins [13:25:03] [PASSED] drm_test_cmdline_name [13:25:03] [PASSED] drm_test_cmdline_name_bpp [13:25:03] [PASSED] drm_test_cmdline_name_option [13:25:03] [PASSED] drm_test_cmdline_name_bpp_option [13:25:03] [PASSED] drm_test_cmdline_rotate_0 [13:25:03] [PASSED] drm_test_cmdline_rotate_90 [13:25:03] [PASSED] drm_test_cmdline_rotate_180 [13:25:03] [PASSED] drm_test_cmdline_rotate_270 [13:25:03] [PASSED] drm_test_cmdline_hmirror [13:25:03] [PASSED] drm_test_cmdline_vmirror [13:25:03] [PASSED] drm_test_cmdline_margin_options [13:25:03] [PASSED] drm_test_cmdline_multiple_options [13:25:03] [PASSED] drm_test_cmdline_bpp_extra_and_option [13:25:03] [PASSED] drm_test_cmdline_extra_and_option [13:25:03] [PASSED] drm_test_cmdline_freestanding_options [13:25:03] [PASSED] drm_test_cmdline_freestanding_force_e_and_options [13:25:03] [PASSED] drm_test_cmdline_panel_orientation [13:25:03] ================ drm_test_cmdline_invalid ================= [13:25:03] [PASSED] margin_only [13:25:03] [PASSED] interlace_only [13:25:03] [PASSED] res_missing_x [13:25:03] [PASSED] res_missing_y [13:25:03] [PASSED] res_bad_y [13:25:03] [PASSED] res_missing_y_bpp [13:25:03] [PASSED] res_bad_bpp [13:25:03] [PASSED] res_bad_refresh [13:25:03] [PASSED] res_bpp_refresh_force_on_off [13:25:03] [PASSED] res_invalid_mode [13:25:03] [PASSED] res_bpp_wrong_place_mode [13:25:03] [PASSED] name_bpp_refresh [13:25:03] [PASSED] name_refresh [13:25:03] [PASSED] name_refresh_wrong_mode [13:25:03] [PASSED] name_refresh_invalid_mode [13:25:03] [PASSED] rotate_multiple [13:25:03] [PASSED] rotate_invalid_val [13:25:03] [PASSED] rotate_truncated [13:25:03] [PASSED] invalid_option [13:25:03] [PASSED] invalid_tv_option [13:25:03] [PASSED] truncated_tv_option [13:25:03] ============ [PASSED] drm_test_cmdline_invalid ============= [13:25:03] =============== drm_test_cmdline_tv_options =============== [13:25:03] [PASSED] NTSC [13:25:03] [PASSED] NTSC_443 [13:25:03] [PASSED] NTSC_J [13:25:03] [PASSED] PAL [13:25:03] [PASSED] PAL_M [13:25:03] [PASSED] PAL_N [13:25:03] [PASSED] SECAM [13:25:03] [PASSED] MONO_525 [13:25:03] [PASSED] MONO_625 [13:25:03] =========== [PASSED] drm_test_cmdline_tv_options =========== [13:25:03] =============== [PASSED] drm_cmdline_parser ================ [13:25:03] ========== drmm_connector_hdmi_init (20 subtests) ========== [13:25:03] [PASSED] drm_test_connector_hdmi_init_valid [13:25:03] [PASSED] drm_test_connector_hdmi_init_bpc_8 [13:25:03] [PASSED] drm_test_connector_hdmi_init_bpc_10 [13:25:03] [PASSED] drm_test_connector_hdmi_init_bpc_12 [13:25:03] [PASSED] drm_test_connector_hdmi_init_bpc_invalid [13:25:03] [PASSED] drm_test_connector_hdmi_init_bpc_null [13:25:03] [PASSED] drm_test_connector_hdmi_init_formats_empty [13:25:03] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb [13:25:03] === drm_test_connector_hdmi_init_formats_yuv420_allowed === [13:25:03] [PASSED] supported_formats=0x9 yuv420_allowed=1 [13:25:03] [PASSED] supported_formats=0x9 yuv420_allowed=0 [13:25:03] [PASSED] supported_formats=0x5 yuv420_allowed=1 [13:25:03] [PASSED] supported_formats=0x5 yuv420_allowed=0 [13:25:03] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed === [13:25:03] [PASSED] drm_test_connector_hdmi_init_null_ddc [13:25:03] [PASSED] drm_test_connector_hdmi_init_null_product [13:25:03] [PASSED] drm_test_connector_hdmi_init_null_vendor [13:25:03] [PASSED] drm_test_connector_hdmi_init_product_length_exact [13:25:03] [PASSED] drm_test_connector_hdmi_init_product_length_too_long [13:25:03] [PASSED] drm_test_connector_hdmi_init_product_valid [13:25:03] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact [13:25:03] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long [13:25:03] [PASSED] drm_test_connector_hdmi_init_vendor_valid [13:25:03] ========= drm_test_connector_hdmi_init_type_valid ========= [13:25:03] [PASSED] HDMI-A [13:25:03] [PASSED] HDMI-B [13:25:03] ===== [PASSED] drm_test_connector_hdmi_init_type_valid ===== [13:25:03] ======== drm_test_connector_hdmi_init_type_invalid ======== [13:25:03] [PASSED] Unknown [13:25:03] [PASSED] VGA [13:25:03] [PASSED] DVI-I [13:25:03] [PASSED] DVI-D [13:25:03] [PASSED] DVI-A [13:25:03] [PASSED] Composite [13:25:03] [PASSED] SVIDEO [13:25:03] [PASSED] LVDS [13:25:03] [PASSED] Component [13:25:03] [PASSED] DIN [13:25:03] [PASSED] DP [13:25:03] [PASSED] TV [13:25:03] [PASSED] eDP [13:25:03] [PASSED] Virtual [13:25:03] [PASSED] DSI [13:25:03] [PASSED] DPI [13:25:03] [PASSED] Writeback [13:25:03] [PASSED] SPI [13:25:03] [PASSED] USB [13:25:03] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ==== [13:25:03] ============ [PASSED] drmm_connector_hdmi_init ============= [13:25:03] ============= drmm_connector_init (3 subtests) ============= [13:25:03] [PASSED] drm_test_drmm_connector_init [13:25:03] [PASSED] drm_test_drmm_connector_init_null_ddc [13:25:03] ========= drm_test_drmm_connector_init_type_valid ========= [13:25:03] [PASSED] Unknown [13:25:03] [PASSED] VGA [13:25:03] [PASSED] DVI-I [13:25:03] [PASSED] DVI-D [13:25:03] [PASSED] DVI-A [13:25:03] [PASSED] Composite [13:25:03] [PASSED] SVIDEO [13:25:03] [PASSED] LVDS [13:25:03] [PASSED] Component [13:25:03] [PASSED] DIN [13:25:03] [PASSED] DP [13:25:03] [PASSED] HDMI-A [13:25:03] [PASSED] HDMI-B [13:25:03] [PASSED] TV [13:25:03] [PASSED] eDP [13:25:03] [PASSED] Virtual [13:25:03] [PASSED] DSI [13:25:03] [PASSED] DPI [13:25:03] [PASSED] Writeback [13:25:03] [PASSED] SPI [13:25:03] [PASSED] USB [13:25:03] ===== [PASSED] drm_test_drmm_connector_init_type_valid ===== [13:25:03] =============== [PASSED] drmm_connector_init =============== [13:25:03] ========= drm_connector_dynamic_init (6 subtests) ========== [13:25:03] [PASSED] drm_test_drm_connector_dynamic_init [13:25:03] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc [13:25:03] [PASSED] drm_test_drm_connector_dynamic_init_not_added [13:25:03] [PASSED] drm_test_drm_connector_dynamic_init_properties [13:25:03] ===== drm_test_drm_connector_dynamic_init_type_valid ====== [13:25:03] [PASSED] Unknown [13:25:03] [PASSED] VGA [13:25:03] [PASSED] DVI-I [13:25:03] [PASSED] DVI-D [13:25:03] [PASSED] DVI-A [13:25:03] [PASSED] Composite [13:25:03] [PASSED] SVIDEO [13:25:03] [PASSED] LVDS [13:25:03] [PASSED] Component [13:25:03] [PASSED] DIN [13:25:03] [PASSED] DP [13:25:03] [PASSED] HDMI-A [13:25:03] [PASSED] HDMI-B [13:25:03] [PASSED] TV [13:25:03] [PASSED] eDP [13:25:03] [PASSED] Virtual [13:25:03] [PASSED] DSI [13:25:03] [PASSED] DPI [13:25:03] [PASSED] Writeback [13:25:03] [PASSED] SPI [13:25:03] [PASSED] USB [13:25:03] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid == [13:25:03] ======== drm_test_drm_connector_dynamic_init_name ========= [13:25:03] [PASSED] Unknown [13:25:03] [PASSED] VGA [13:25:03] [PASSED] DVI-I [13:25:03] [PASSED] DVI-D [13:25:03] [PASSED] DVI-A [13:25:03] [PASSED] Composite [13:25:03] [PASSED] SVIDEO [13:25:03] [PASSED] LVDS [13:25:03] [PASSED] Component [13:25:03] [PASSED] DIN [13:25:03] [PASSED] DP [13:25:03] [PASSED] HDMI-A [13:25:03] [PASSED] HDMI-B [13:25:03] [PASSED] TV [13:25:03] [PASSED] eDP [13:25:03] [PASSED] Virtual [13:25:03] [PASSED] DSI [13:25:03] [PASSED] DPI [13:25:03] [PASSED] Writeback [13:25:03] [PASSED] SPI [13:25:03] [PASSED] USB [13:25:03] ==== [PASSED] drm_test_drm_connector_dynamic_init_name ===== [13:25:03] =========== [PASSED] drm_connector_dynamic_init ============ [13:25:03] ==== drm_connector_dynamic_register_early (4 subtests) ===== [13:25:03] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list [13:25:03] [PASSED] drm_test_drm_connector_dynamic_register_early_defer [13:25:03] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init [13:25:03] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object [13:25:03] ====== [PASSED] drm_connector_dynamic_register_early ======= [13:25:03] ======= drm_connector_dynamic_register (7 subtests) ======== [13:25:03] [PASSED] drm_test_drm_connector_dynamic_register_on_list [13:25:03] [PASSED] drm_test_drm_connector_dynamic_register_no_defer [13:25:03] [PASSED] drm_test_drm_connector_dynamic_register_no_init [13:25:03] [PASSED] drm_test_drm_connector_dynamic_register_mode_object [13:25:03] [PASSED] drm_test_drm_connector_dynamic_register_sysfs [13:25:03] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name [13:25:03] [PASSED] drm_test_drm_connector_dynamic_register_debugfs [13:25:03] ========= [PASSED] drm_connector_dynamic_register ========== [13:25:03] = drm_connector_attach_broadcast_rgb_property (2 subtests) = [13:25:03] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property [13:25:03] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector [13:25:03] === [PASSED] drm_connector_attach_broadcast_rgb_property === [13:25:03] ========== drm_get_tv_mode_from_name (2 subtests) ========== [13:25:03] ========== drm_test_get_tv_mode_from_name_valid =========== [13:25:03] [PASSED] NTSC [13:25:03] [PASSED] NTSC-443 [13:25:03] [PASSED] NTSC-J [13:25:03] [PASSED] PAL [13:25:03] [PASSED] PAL-M [13:25:03] [PASSED] PAL-N [13:25:03] [PASSED] SECAM [13:25:03] [PASSED] Mono [13:25:03] ====== [PASSED] drm_test_get_tv_mode_from_name_valid ======= [13:25:03] [PASSED] drm_test_get_tv_mode_from_name_truncated [13:25:03] ============ [PASSED] drm_get_tv_mode_from_name ============ [13:25:03] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) = [13:25:03] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb [13:25:03] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc [13:25:03] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1 [13:25:03] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc [13:25:03] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1 [13:25:03] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double [13:25:03] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid = [13:25:03] [PASSED] VIC 96 [13:25:03] [PASSED] VIC 97 [13:25:03] [PASSED] VIC 101 [13:25:03] [PASSED] VIC 102 [13:25:03] [PASSED] VIC 106 [13:25:03] [PASSED] VIC 107 [13:25:03] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid === [13:25:03] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc [13:25:03] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc [13:25:03] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc [13:25:03] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc [13:25:03] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc [13:25:03] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ==== [13:25:03] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) == [13:25:03] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ==== [13:25:03] [PASSED] Automatic [13:25:03] [PASSED] Full [13:25:03] [PASSED] Limited 16:235 [13:25:03] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name === [13:25:03] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid [13:25:03] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ==== [13:25:03] == drm_hdmi_connector_get_output_format_name (2 subtests) == [13:25:03] === drm_test_drm_hdmi_connector_get_output_format_name ==== [13:25:03] [PASSED] RGB [13:25:03] [PASSED] YUV 4:2:0 [13:25:03] [PASSED] YUV 4:2:2 [13:25:03] [PASSED] YUV 4:4:4 [13:25:03] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name === [13:25:03] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid [13:25:03] ==== [PASSED] drm_hdmi_connector_get_output_format_name ==== [13:25:03] ============= drm_damage_helper (21 subtests) ============== [13:25:03] [PASSED] drm_test_damage_iter_no_damage [13:25:03] [PASSED] drm_test_damage_iter_no_damage_fractional_src [13:25:03] [PASSED] drm_test_damage_iter_no_damage_src_moved [13:25:03] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved [13:25:03] [PASSED] drm_test_damage_iter_no_damage_not_visible [13:25:03] [PASSED] drm_test_damage_iter_no_damage_no_crtc [13:25:03] [PASSED] drm_test_damage_iter_no_damage_no_fb [13:25:03] [PASSED] drm_test_damage_iter_simple_damage [13:25:03] [PASSED] drm_test_damage_iter_single_damage [13:25:03] [PASSED] drm_test_damage_iter_single_damage_intersect_src [13:25:03] [PASSED] drm_test_damage_iter_single_damage_outside_src [13:25:03] [PASSED] drm_test_damage_iter_single_damage_fractional_src [13:25:03] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src [13:25:03] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src [13:25:03] [PASSED] drm_test_damage_iter_single_damage_src_moved [13:25:03] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved [13:25:03] [PASSED] drm_test_damage_iter_damage [13:25:03] [PASSED] drm_test_damage_iter_damage_one_intersect [13:25:03] [PASSED] drm_test_damage_iter_damage_one_outside [13:25:03] [PASSED] drm_test_damage_iter_damage_src_moved [13:25:03] [PASSED] drm_test_damage_iter_damage_not_visible [13:25:03] ================ [PASSED] drm_damage_helper ================ [13:25:03] ============== drm_dp_mst_helper (3 subtests) ============== [13:25:03] ============== drm_test_dp_mst_calc_pbn_mode ============== [13:25:03] [PASSED] Clock 154000 BPP 30 DSC disabled [13:25:03] [PASSED] Clock 234000 BPP 30 DSC disabled [13:25:03] [PASSED] Clock 297000 BPP 24 DSC disabled [13:25:03] [PASSED] Clock 332880 BPP 24 DSC enabled [13:25:03] [PASSED] Clock 324540 BPP 24 DSC enabled [13:25:03] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ========== [13:25:03] ============== drm_test_dp_mst_calc_pbn_div =============== [13:25:03] [PASSED] Link rate 2000000 lane count 4 [13:25:03] [PASSED] Link rate 2000000 lane count 2 [13:25:03] [PASSED] Link rate 2000000 lane count 1 [13:25:03] [PASSED] Link rate 1350000 lane count 4 [13:25:03] [PASSED] Link rate 1350000 lane count 2 [13:25:03] [PASSED] Link rate 1350000 lane count 1 [13:25:03] [PASSED] Link rate 1000000 lane count 4 [13:25:03] [PASSED] Link rate 1000000 lane count 2 [13:25:03] [PASSED] Link rate 1000000 lane count 1 [13:25:03] [PASSED] Link rate 810000 lane count 4 [13:25:03] [PASSED] Link rate 810000 lane count 2 [13:25:03] [PASSED] Link rate 810000 lane count 1 [13:25:03] [PASSED] Link rate 540000 lane count 4 [13:25:03] [PASSED] Link rate 540000 lane count 2 [13:25:03] [PASSED] Link rate 540000 lane count 1 [13:25:03] [PASSED] Link rate 270000 lane count 4 [13:25:03] [PASSED] Link rate 270000 lane count 2 [13:25:03] [PASSED] Link rate 270000 lane count 1 [13:25:03] [PASSED] Link rate 162000 lane count 4 [13:25:03] [PASSED] Link rate 162000 lane count 2 [13:25:03] [PASSED] Link rate 162000 lane count 1 [13:25:03] ========== [PASSED] drm_test_dp_mst_calc_pbn_div =========== [13:25:03] ========= drm_test_dp_mst_sideband_msg_req_decode ========= [13:25:03] [PASSED] DP_ENUM_PATH_RESOURCES with port number [13:25:03] [PASSED] DP_POWER_UP_PHY with port number [13:25:03] [PASSED] DP_POWER_DOWN_PHY with port number [13:25:03] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks [13:25:03] [PASSED] DP_ALLOCATE_PAYLOAD with port number [13:25:03] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI [13:25:03] [PASSED] DP_ALLOCATE_PAYLOAD with PBN [13:25:03] [PASSED] DP_QUERY_PAYLOAD with port number [13:25:03] [PASSED] DP_QUERY_PAYLOAD with VCPI [13:25:03] [PASSED] DP_REMOTE_DPCD_READ with port number [13:25:03] [PASSED] DP_REMOTE_DPCD_READ with DPCD address [13:25:03] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes [13:25:03] [PASSED] DP_REMOTE_DPCD_WRITE with port number [13:25:03] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address [13:25:03] [PASSED] DP_REMOTE_DPCD_WRITE with data array [13:25:03] [PASSED] DP_REMOTE_I2C_READ with port number [13:25:03] [PASSED] DP_REMOTE_I2C_READ with I2C device ID [13:25:03] [PASSED] DP_REMOTE_I2C_READ with transactions array [13:25:03] [PASSED] DP_REMOTE_I2C_WRITE with port number [13:25:03] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID [13:25:03] [PASSED] DP_REMOTE_I2C_WRITE with data array [13:25:03] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID [13:25:03] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID [13:25:03] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event [13:25:03] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event [13:25:03] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior [13:25:03] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior [13:25:03] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode ===== [13:25:03] ================ [PASSED] drm_dp_mst_helper ================ [13:25:03] ================== drm_exec (7 subtests) =================== [13:25:03] [PASSED] sanitycheck [13:25:03] [PASSED] test_lock [13:25:03] [PASSED] test_lock_unlock [13:25:03] [PASSED] test_duplicates [13:25:03] [PASSED] test_prepare [13:25:03] [PASSED] test_prepare_array [13:25:03] [PASSED] test_multiple_loops [13:25:03] ==================== [PASSED] drm_exec ===================== [13:25:03] =========== drm_format_helper_test (17 subtests) =========== [13:25:03] ============== drm_test_fb_xrgb8888_to_gray8 ============== [13:25:03] [PASSED] single_pixel_source_buffer [13:25:03] [PASSED] single_pixel_clip_rectangle [13:25:03] [PASSED] well_known_colors [13:25:03] [PASSED] destination_pitch [13:25:03] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ========== [13:25:03] ============= drm_test_fb_xrgb8888_to_rgb332 ============== [13:25:03] [PASSED] single_pixel_source_buffer [13:25:03] [PASSED] single_pixel_clip_rectangle [13:25:03] [PASSED] well_known_colors [13:25:03] [PASSED] destination_pitch [13:25:03] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ========== [13:25:03] ============= drm_test_fb_xrgb8888_to_rgb565 ============== [13:25:03] [PASSED] single_pixel_source_buffer [13:25:03] [PASSED] single_pixel_clip_rectangle [13:25:03] [PASSED] well_known_colors [13:25:03] [PASSED] destination_pitch [13:25:03] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ========== [13:25:03] ============ drm_test_fb_xrgb8888_to_xrgb1555 ============= [13:25:03] [PASSED] single_pixel_source_buffer [13:25:03] [PASSED] single_pixel_clip_rectangle [13:25:03] [PASSED] well_known_colors [13:25:03] [PASSED] destination_pitch [13:25:03] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 ========= [13:25:03] ============ drm_test_fb_xrgb8888_to_argb1555 ============= [13:25:03] [PASSED] single_pixel_source_buffer [13:25:03] [PASSED] single_pixel_clip_rectangle [13:25:03] [PASSED] well_known_colors [13:25:03] [PASSED] destination_pitch [13:25:03] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 ========= [13:25:03] ============ drm_test_fb_xrgb8888_to_rgba5551 ============= [13:25:03] [PASSED] single_pixel_source_buffer [13:25:03] [PASSED] single_pixel_clip_rectangle [13:25:03] [PASSED] well_known_colors [13:25:03] [PASSED] destination_pitch [13:25:03] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 ========= [13:25:03] ============= drm_test_fb_xrgb8888_to_rgb888 ============== [13:25:03] [PASSED] single_pixel_source_buffer [13:25:03] [PASSED] single_pixel_clip_rectangle [13:25:03] [PASSED] well_known_colors [13:25:03] [PASSED] destination_pitch [13:25:03] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ========== [13:25:03] ============= drm_test_fb_xrgb8888_to_bgr888 ============== [13:25:03] [PASSED] single_pixel_source_buffer [13:25:03] [PASSED] single_pixel_clip_rectangle [13:25:03] [PASSED] well_known_colors [13:25:03] [PASSED] destination_pitch [13:25:03] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ========== [13:25:03] ============ drm_test_fb_xrgb8888_to_argb8888 ============= [13:25:03] [PASSED] single_pixel_source_buffer [13:25:03] [PASSED] single_pixel_clip_rectangle [13:25:03] [PASSED] well_known_colors [13:25:03] [PASSED] destination_pitch [13:25:03] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 ========= [13:25:03] =========== drm_test_fb_xrgb8888_to_xrgb2101010 =========== [13:25:03] [PASSED] single_pixel_source_buffer [13:25:03] [PASSED] single_pixel_clip_rectangle [13:25:03] [PASSED] well_known_colors [13:25:03] [PASSED] destination_pitch [13:25:03] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 ======= [13:25:03] =========== drm_test_fb_xrgb8888_to_argb2101010 =========== [13:25:03] [PASSED] single_pixel_source_buffer [13:25:03] [PASSED] single_pixel_clip_rectangle [13:25:03] [PASSED] well_known_colors [13:25:03] [PASSED] destination_pitch [13:25:03] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 ======= [13:25:03] ============== drm_test_fb_xrgb8888_to_mono =============== [13:25:03] [PASSED] single_pixel_source_buffer [13:25:03] [PASSED] single_pixel_clip_rectangle [13:25:03] [PASSED] well_known_colors [13:25:03] [PASSED] destination_pitch [13:25:03] ========== [PASSED] drm_test_fb_xrgb8888_to_mono =========== [13:25:03] ==================== drm_test_fb_swab ===================== [13:25:03] [PASSED] single_pixel_source_buffer [13:25:03] [PASSED] single_pixel_clip_rectangle [13:25:03] [PASSED] well_known_colors [13:25:03] [PASSED] destination_pitch [13:25:03] ================ [PASSED] drm_test_fb_swab ================= [13:25:03] ============ drm_test_fb_xrgb8888_to_xbgr8888 ============= [13:25:03] [PASSED] single_pixel_source_buffer [13:25:03] [PASSED] single_pixel_clip_rectangle [13:25:03] [PASSED] well_known_colors [13:25:03] [PASSED] destination_pitch [13:25:03] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 ========= [13:25:03] ============ drm_test_fb_xrgb8888_to_abgr8888 ============= [13:25:03] [PASSED] single_pixel_source_buffer [13:25:03] [PASSED] single_pixel_clip_rectangle [13:25:03] [PASSED] well_known_colors [13:25:03] [PASSED] destination_pitch [13:25:03] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 ========= [13:25:03] ================= drm_test_fb_clip_offset ================= [13:25:03] [PASSED] pass through [13:25:03] [PASSED] horizontal offset [13:25:03] [PASSED] vertical offset [13:25:03] [PASSED] horizontal and vertical offset [13:25:03] [PASSED] horizontal offset (custom pitch) [13:25:03] [PASSED] vertical offset (custom pitch) [13:25:03] [PASSED] horizontal and vertical offset (custom pitch) [13:25:03] ============= [PASSED] drm_test_fb_clip_offset ============= [13:25:03] =================== drm_test_fb_memcpy ==================== [13:25:03] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258) [13:25:03] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258) [13:25:03] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559) [13:25:03] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258) [13:25:03] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258) [13:25:03] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559) [13:25:03] [PASSED] well_known_colors: XB24 little-endian (0x34324258) [13:25:03] [PASSED] well_known_colors: XRA8 little-endian (0x38415258) [13:25:03] [PASSED] well_known_colors: YU24 little-endian (0x34325559) [13:25:03] [PASSED] destination_pitch: XB24 little-endian (0x34324258) [13:25:03] [PASSED] destination_pitch: XRA8 little-endian (0x38415258) [13:25:03] [PASSED] destination_pitch: YU24 little-endian (0x34325559) [13:25:03] =============== [PASSED] drm_test_fb_memcpy ================ [13:25:03] ============= [PASSED] drm_format_helper_test ============== [13:25:03] ================= drm_format (18 subtests) ================= [13:25:03] [PASSED] drm_test_format_block_width_invalid [13:25:03] [PASSED] drm_test_format_block_width_one_plane [13:25:03] [PASSED] drm_test_format_block_width_two_plane [13:25:03] [PASSED] drm_test_format_block_width_three_plane [13:25:03] [PASSED] drm_test_format_block_width_tiled [13:25:03] [PASSED] drm_test_format_block_height_invalid [13:25:03] [PASSED] drm_test_format_block_height_one_plane [13:25:03] [PASSED] drm_test_format_block_height_two_plane [13:25:03] [PASSED] drm_test_format_block_height_three_plane [13:25:03] [PASSED] drm_test_format_block_height_tiled [13:25:03] [PASSED] drm_test_format_min_pitch_invalid [13:25:03] [PASSED] drm_test_format_min_pitch_one_plane_8bpp [13:25:03] [PASSED] drm_test_format_min_pitch_one_plane_16bpp [13:25:03] [PASSED] drm_test_format_min_pitch_one_plane_24bpp [13:25:03] [PASSED] drm_test_format_min_pitch_one_plane_32bpp [13:25:03] [PASSED] drm_test_format_min_pitch_two_plane [13:25:03] [PASSED] drm_test_format_min_pitch_three_plane_8bpp [13:25:03] [PASSED] drm_test_format_min_pitch_tiled [13:25:03] =================== [PASSED] drm_format ==================== [13:25:03] ============== drm_framebuffer (10 subtests) =============== [13:25:03] ========== drm_test_framebuffer_check_src_coords ========== [13:25:03] [PASSED] Success: source fits into fb [13:25:03] [PASSED] Fail: overflowing fb with x-axis coordinate [13:25:03] [PASSED] Fail: overflowing fb with y-axis coordinate [13:25:03] [PASSED] Fail: overflowing fb with source width [13:25:03] [PASSED] Fail: overflowing fb with source height [13:25:03] ====== [PASSED] drm_test_framebuffer_check_src_coords ====== [13:25:03] [PASSED] drm_test_framebuffer_cleanup [13:25:03] =============== drm_test_framebuffer_create =============== [13:25:03] [PASSED] ABGR8888 normal sizes [13:25:03] [PASSED] ABGR8888 max sizes [13:25:03] [PASSED] ABGR8888 pitch greater than min required [13:25:03] [PASSED] ABGR8888 pitch less than min required [13:25:03] [PASSED] ABGR8888 Invalid width [13:25:03] [PASSED] ABGR8888 Invalid buffer handle [13:25:03] [PASSED] No pixel format [13:25:03] [PASSED] ABGR8888 Width 0 [13:25:03] [PASSED] ABGR8888 Height 0 [13:25:03] [PASSED] ABGR8888 Out of bound height * pitch combination [13:25:03] [PASSED] ABGR8888 Large buffer offset [13:25:03] [PASSED] ABGR8888 Buffer offset for inexistent plane [13:25:03] [PASSED] ABGR8888 Invalid flag [13:25:03] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers [13:25:03] [PASSED] ABGR8888 Valid buffer modifier [13:25:03] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE) [13:25:03] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS [13:25:03] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS [13:25:03] [PASSED] NV12 Normal sizes [13:25:03] [PASSED] NV12 Max sizes [13:25:03] [PASSED] NV12 Invalid pitch [13:25:03] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag [13:25:03] [PASSED] NV12 different modifier per-plane [13:25:03] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE [13:25:03] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS [13:25:03] [PASSED] NV12 Modifier for inexistent plane [13:25:03] [PASSED] NV12 Handle for inexistent plane [13:25:03] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS [13:25:03] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier [13:25:03] [PASSED] YVU420 Normal sizes [13:25:03] [PASSED] YVU420 Max sizes [13:25:03] [PASSED] YVU420 Invalid pitch [13:25:03] [PASSED] YVU420 Different pitches [13:25:03] [PASSED] YVU420 Different buffer offsets/pitches [13:25:03] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS [13:25:03] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS [13:25:03] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS [13:25:03] [PASSED] YVU420 Valid modifier [13:25:03] [PASSED] YVU420 Different modifiers per plane [13:25:03] [PASSED] YVU420 Modifier for inexistent plane [13:25:03] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR) [13:25:03] [PASSED] X0L2 Normal sizes [13:25:03] [PASSED] X0L2 Max sizes [13:25:03] [PASSED] X0L2 Invalid pitch [13:25:03] [PASSED] X0L2 Pitch greater than minimum required [13:25:03] [PASSED] X0L2 Handle for inexistent plane [13:25:03] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set [13:25:03] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set [13:25:03] [PASSED] X0L2 Valid modifier [13:25:03] [PASSED] X0L2 Modifier for inexistent plane [13:25:03] =========== [PASSED] drm_test_framebuffer_create =========== [13:25:03] [PASSED] drm_test_framebuffer_free [13:25:03] [PASSED] drm_test_framebuffer_init [13:25:03] [PASSED] drm_test_framebuffer_init_bad_format [13:25:03] [PASSED] drm_test_framebuffer_init_dev_mismatch [13:25:03] [PASSED] drm_test_framebuffer_lookup [13:25:03] [PASSED] drm_test_framebuffer_lookup_inexistent [13:25:03] [PASSED] drm_test_framebuffer_modifiers_not_supported [13:25:03] ================= [PASSED] drm_framebuffer ================= [13:25:03] ================ drm_gem_shmem (8 subtests) ================ [13:25:03] [PASSED] drm_gem_shmem_test_obj_create [13:25:03] [PASSED] drm_gem_shmem_test_obj_create_private [13:25:03] [PASSED] drm_gem_shmem_test_pin_pages [13:25:03] [PASSED] drm_gem_shmem_test_vmap [13:25:03] [PASSED] drm_gem_shmem_test_get_sg_table [13:25:03] [PASSED] drm_gem_shmem_test_get_pages_sgt [13:25:03] [PASSED] drm_gem_shmem_test_madvise [13:25:03] [PASSED] drm_gem_shmem_test_purge [13:25:03] ================== [PASSED] drm_gem_shmem ================== [13:25:03] === drm_atomic_helper_connector_hdmi_check (27 subtests) === [13:25:03] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode [13:25:03] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1 [13:25:03] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode [13:25:03] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1 [13:25:03] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode [13:25:03] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1 [13:25:03] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 ======= [13:25:03] [PASSED] Automatic [13:25:03] [PASSED] Full [13:25:03] [PASSED] Limited 16:235 [13:25:03] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 === [13:25:03] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed [13:25:03] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed [13:25:03] [PASSED] drm_test_check_disable_connector [13:25:03] [PASSED] drm_test_check_hdmi_funcs_reject_rate [13:25:03] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb [13:25:03] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420 [13:25:03] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422 [13:25:03] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420 [13:25:03] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420 [13:25:03] [PASSED] drm_test_check_output_bpc_crtc_mode_changed [13:25:03] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed [13:25:03] [PASSED] drm_test_check_output_bpc_dvi [13:25:03] [PASSED] drm_test_check_output_bpc_format_vic_1 [13:25:03] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only [13:25:03] [PASSED] drm_test_check_output_bpc_format_display_rgb_only [13:25:03] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only [13:25:03] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only [13:25:03] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc [13:25:03] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc [13:25:03] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc [13:25:03] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ====== [13:25:03] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ==== [13:25:03] [PASSED] drm_test_check_broadcast_rgb_value [13:25:03] [PASSED] drm_test_check_bpc_8_value [13:25:03] [PASSED] drm_test_check_bpc_10_value [13:25:03] [PASSED] drm_test_check_bpc_12_value [13:25:03] [PASSED] drm_test_check_format_value [13:25:03] [PASSED] drm_test_check_tmds_char_value [13:25:03] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ====== [13:25:03] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) = [13:25:03] [PASSED] drm_test_check_mode_valid [13:25:03] [PASSED] drm_test_check_mode_valid_reject [13:25:03] [PASSED] drm_test_check_mode_valid_reject_rate [13:25:03] [PASSED] drm_test_check_mode_valid_reject_max_clock [13:25:03] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid === [13:25:03] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) = [13:25:03] [PASSED] drm_test_check_infoframes [13:25:03] [PASSED] drm_test_check_reject_avi_infoframe [13:25:03] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8 [13:25:03] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10 [13:25:03] [PASSED] drm_test_check_reject_audio_infoframe [13:25:03] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes === [13:25:03] ================= drm_managed (2 subtests) ================= [13:25:03] [PASSED] drm_test_managed_release_action [13:25:03] [PASSED] drm_test_managed_run_action [13:25:03] =================== [PASSED] drm_managed =================== [13:25:03] =================== drm_mm (6 subtests) ==================== [13:25:03] [PASSED] drm_test_mm_init [13:25:03] [PASSED] drm_test_mm_debug [13:25:03] [PASSED] drm_test_mm_align32 [13:25:03] [PASSED] drm_test_mm_align64 [13:25:03] [PASSED] drm_test_mm_lowest [13:25:03] [PASSED] drm_test_mm_highest [13:25:03] ===================== [PASSED] drm_mm ====================== [13:25:03] ============= drm_modes_analog_tv (5 subtests) ============= [13:25:03] [PASSED] drm_test_modes_analog_tv_mono_576i [13:25:03] [PASSED] drm_test_modes_analog_tv_ntsc_480i [13:25:03] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined [13:25:03] [PASSED] drm_test_modes_analog_tv_pal_576i [13:25:03] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined [13:25:03] =============== [PASSED] drm_modes_analog_tv =============== [13:25:03] ============== drm_plane_helper (2 subtests) =============== [13:25:03] =============== drm_test_check_plane_state ================ [13:25:03] [PASSED] clipping_simple [13:25:03] [PASSED] clipping_rotate_reflect [13:25:03] [PASSED] positioning_simple [13:25:03] [PASSED] upscaling [13:25:03] [PASSED] downscaling [13:25:03] [PASSED] rounding1 [13:25:03] [PASSED] rounding2 [13:25:03] [PASSED] rounding3 [13:25:03] [PASSED] rounding4 [13:25:03] =========== [PASSED] drm_test_check_plane_state ============ [13:25:03] =========== drm_test_check_invalid_plane_state ============ [13:25:03] [PASSED] positioning_invalid [13:25:03] [PASSED] upscaling_invalid [13:25:03] [PASSED] downscaling_invalid [13:25:03] ======= [PASSED] drm_test_check_invalid_plane_state ======== [13:25:03] ================ [PASSED] drm_plane_helper ================= [13:25:03] ====== drm_connector_helper_tv_get_modes (1 subtest) ======= [13:25:03] ====== drm_test_connector_helper_tv_get_modes_check ======= [13:25:03] [PASSED] None [13:25:03] [PASSED] PAL [13:25:03] [PASSED] NTSC [13:25:03] [PASSED] Both, NTSC Default [13:25:03] [PASSED] Both, PAL Default [13:25:03] [PASSED] Both, NTSC Default, with PAL on command-line [13:25:03] [PASSED] Both, PAL Default, with NTSC on command-line [13:25:03] == [PASSED] drm_test_connector_helper_tv_get_modes_check === [13:25:03] ======== [PASSED] drm_connector_helper_tv_get_modes ======== [13:25:03] ================== drm_rect (9 subtests) =================== [13:25:03] [PASSED] drm_test_rect_clip_scaled_div_by_zero [13:25:03] [PASSED] drm_test_rect_clip_scaled_not_clipped [13:25:03] [PASSED] drm_test_rect_clip_scaled_clipped [13:25:03] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned [13:25:03] ================= drm_test_rect_intersect ================= [13:25:03] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0 [13:25:03] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1 [13:25:03] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0 [13:25:03] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1 [13:25:03] [PASSED] right x left: 2x1+0+0 x 3x1+1+0 [13:25:03] [PASSED] left x right: 3x1+1+0 x 2x1+0+0 [13:25:03] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1 [13:25:03] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0 [13:25:03] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1 [13:25:03] [PASSED] touching side: 1x1+0+0 x 1x1+1+0 [13:25:03] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0 [13:25:03] [PASSED] inside another: 2x2+0+0 x 1x1+1+1 [13:25:03] [PASSED] far away: 1x1+0+0 x 1x1+3+6 [13:25:03] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10 [13:25:03] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10 [13:25:03] ============= [PASSED] drm_test_rect_intersect ============= [13:25:03] ================ drm_test_rect_calc_hscale ================ [13:25:03] [PASSED] normal use [13:25:03] [PASSED] out of max range [13:25:03] [PASSED] out of min range [13:25:03] [PASSED] zero dst [13:25:03] [PASSED] negative src [13:25:03] [PASSED] negative dst [13:25:03] ============ [PASSED] drm_test_rect_calc_hscale ============ [13:25:03] ================ drm_test_rect_calc_vscale ================ [13:25:03] [PASSED] normal use [13:25:03] [PASSED] out of max range [13:25:03] [PASSED] out of min range [13:25:03] [PASSED] zero dst [13:25:03] [PASSED] negative src [13:25:03] [PASSED] negative dst stty: 'standard input': Inappropriate ioctl for device [13:25:03] ============ [PASSED] drm_test_rect_calc_vscale ============ [13:25:03] ================== drm_test_rect_rotate =================== [13:25:03] [PASSED] reflect-x [13:25:03] [PASSED] reflect-y [13:25:03] [PASSED] rotate-0 [13:25:03] [PASSED] rotate-90 [13:25:03] [PASSED] rotate-180 [13:25:03] [PASSED] rotate-270 [13:25:03] ============== [PASSED] drm_test_rect_rotate =============== [13:25:03] ================ drm_test_rect_rotate_inv ================= [13:25:03] [PASSED] reflect-x [13:25:03] [PASSED] reflect-y [13:25:03] [PASSED] rotate-0 [13:25:03] [PASSED] rotate-90 [13:25:03] [PASSED] rotate-180 [13:25:03] [PASSED] rotate-270 [13:25:03] ============ [PASSED] drm_test_rect_rotate_inv ============= [13:25:03] ==================== [PASSED] drm_rect ===================== [13:25:03] ============ drm_sysfb_modeset_test (1 subtest) ============ [13:25:03] ============ drm_test_sysfb_build_fourcc_list ============= [13:25:03] [PASSED] no native formats [13:25:03] [PASSED] XRGB8888 as native format [13:25:03] [PASSED] remove duplicates [13:25:03] [PASSED] convert alpha formats [13:25:03] [PASSED] random formats [13:25:03] ======== [PASSED] drm_test_sysfb_build_fourcc_list ========= [13:25:03] ============= [PASSED] drm_sysfb_modeset_test ============== [13:25:03] ================== drm_fixp (2 subtests) =================== [13:25:03] [PASSED] drm_test_int2fixp [13:25:03] [PASSED] drm_test_sm2fixp [13:25:03] ==================== [PASSED] drm_fixp ===================== [13:25:03] ============================================================ [13:25:03] Testing complete. Ran 621 tests: passed: 621 [13:25:03] Elapsed time: 50.252s total, 2.959s configuring, 47.021s building, 0.256s running + /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig stty: 'standard input': Inappropriate ioctl for device [13:25:04] Configuring KUnit Kernel ... Regenerating .config ... Populating config with: $ make ARCH=um O=.kunit olddefconfig [13:25:07] Building KUnit Kernel ... Populating config with: $ make ARCH=um O=.kunit olddefconfig Building with: $ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48 [13:25:24] Starting KUnit Kernel (1/1)... [13:25:24] ============================================================ Running tests with: $ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt [13:25:24] ================= ttm_device (5 subtests) ================== [13:25:24] [PASSED] ttm_device_init_basic [13:25:24] [PASSED] ttm_device_init_multiple [13:25:24] [PASSED] ttm_device_fini_basic [13:25:24] [PASSED] ttm_device_init_no_vma_man [13:25:24] ================== ttm_device_init_pools ================== [13:25:24] [PASSED] No DMA allocations, no DMA32 required [13:25:24] # ttm_device_init_pools: ASSERTION FAILED at drivers/gpu/drm/ttm/tests/ttm_device_test.c:178 [13:25:24] Expected !list_lru_count(&pt.pages) to be false, but is true [13:25:24] [FAILED] DMA allocations, DMA32 required [13:25:24] [PASSED] No DMA allocations, DMA32 required [13:25:24] # ttm_device_init_pools: ASSERTION FAILED at drivers/gpu/drm/ttm/tests/ttm_device_test.c:178 [13:25:24] Expected !list_lru_count(&pt.pages) to be false, but is true [13:25:24] ------------[ cut here ]------------ [13:25:24] WARNING: lib/refcount.c:28 at devres_release_all+0xaa/0x100, CPU#0: kunit_try_catch/46 [13:25:24] refcount_t: underflow; use-after-free. [13:25:24] CPU: 0 UID: 0 PID: 46 Comm: kunit_try_catch Tainted: G W N 7.0.0-rc7-g206eb51f3379 #3 VOLUNTARY [13:25:24] Tainted: [W]=WARN, [N]=TEST [13:25:24] Stack: [13:25:24] 6044ed8b 00000000 00000000 00000001 [13:25:24] ffffff00 6044ed8b 6032367a 00000009 [13:25:24] 0000001c 60043e88 6002381c b30cbd40 [13:25:24] Call Trace: [13:25:24] [<6032367a>] ? devres_release_all+0xaa/0x100 [13:25:24] [<60043e88>] ? dump_stack_lvl+0x5e/0x7a [13:25:24] [<6002381c>] ? _printk+0x0/0x65 [13:25:24] [<6001f09f>] ? __warn.cold+0x79/0x11f [13:25:24] [<6001f1d9>] ? warn_slowpath_fmt+0x94/0xa1 [13:25:24] [<601ef1a0>] ? kernfs_free_rcu+0x0/0x70 [13:25:24] [<60052e36>] ? um_set_signals+0x36/0x60 [13:25:24] [<600c5a42>] ? call_rcu+0x52/0x90 [13:25:24] [<6001f145>] ? warn_slowpath_fmt+0x0/0xa1 [13:25:24] [<60147f50>] ? kfree+0x0/0x250 [13:25:24] [<6032367a>] ? devres_release_all+0xaa/0x100 [13:25:24] [<60396bb0>] ? mutex_unlock+0x0/0x30 [13:25:24] [<6031c3c0>] ? bus_notify+0x0/0x60 [13:25:24] [<60396bb0>] ? mutex_unlock+0x0/0x30 [13:25:24] [<60398620>] ? mutex_lock+0x0/0x40 [13:25:24] [<6031ca24>] ? device_unbind_cleanup+0x14/0xb0 [13:25:24] [<6031e1f6>] ? device_release_driver_internal+0x256/0x2b0 [13:25:24] [<60372210>] ? kobject_put+0x0/0x150 [13:25:24] [<601f3d40>] ? sysfs_remove_file_ns+0x0/0x20 [13:25:24] [<6031c00f>] ? bus_remove_device+0x10f/0x1a0 [13:25:24] [<601f3d40>] ? sysfs_remove_file_ns+0x0/0x20 [13:25:24] [<601f17b8>] ? kernfs_remove_by_name_ns+0x98/0x130 [13:25:24] [<60315a8c>] ? device_del+0x1bc/0x600 [13:25:24] [<60052e00>] ? um_set_signals+0x0/0x60 [13:25:24] [<6025b2a0>] ? device_unregister_wrapper+0x0/0x10 [13:25:24] [<60052e00>] ? um_set_signals+0x0/0x60 [13:25:24] [<60315ee4>] ? device_unregister+0x14/0x40 [13:25:24] [<60257e66>] ? kunit_release_action+0xf6/0x170 [13:25:24] [<60257d70>] ? kunit_release_action+0x0/0x170 [13:25:24] [<6025b2e2>] ? kunit_device_unregister+0x32/0x80 [13:25:24] [<60259890>] ? kunit_generic_run_threadfn_adapter+0x0/0x30 [13:25:24] [<6025748e>] ? kunit_try_run_case_cleanup+0x2e/0x40 [13:25:24] [<602598a6>] ? kunit_generic_run_threadfn_adapter+0x16/0x30 [13:25:24] [<60081e36>] ? kthread+0xe6/0x150 [13:25:24] [<60046435>] ? new_thread_handler+0x45/0x60 [13:25:24] ---[ end trace 0000000000000000 ]--- [13:25:24] [FAILED] DMA allocations, no DMA32 required [13:25:24] # ttm_device_init_pools: pass:2 fail:2 skip:0 total:4 [13:25:24] ============== [FAILED] ttm_device_init_pools ============== [13:25:24] # module: ttm_device_test [13:25:24] # ttm_device: pass:4 fail:1 skip:0 total:5 [13:25:24] # Totals: pass:6 fail:2 skip:0 total:8 [13:25:24] =================== [FAILED] ttm_device ==================== [13:25:24] ================== ttm_pool (8 subtests) =================== [13:25:24] ================== ttm_pool_alloc_basic =================== [13:25:24] [PASSED] One page [13:25:24] [PASSED] More than one page [13:25:24] [PASSED] Above the allocation limit [13:25:24] [PASSED] One page, with coherent DMA mappings enabled [13:25:24] [PASSED] Above the allocation limit, with coherent DMA mappings enabled [13:25:24] ============== [PASSED] ttm_pool_alloc_basic =============== [13:25:24] ============== ttm_pool_alloc_basic_dma_addr ============== [13:25:24] [PASSED] One page [13:25:24] [PASSED] More than one page [13:25:24] [PASSED] Above the allocation limit [13:25:24] [PASSED] One page, with coherent DMA mappings enabled [13:25:24] [PASSED] Above the allocation limit, with coherent DMA mappings enabled [13:25:24] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ========== [13:25:24] [PASSED] ttm_pool_alloc_order_caching_match [13:25:24] [PASSED] ttm_pool_alloc_caching_mismatch [13:25:24] [PASSED] ttm_pool_alloc_order_mismatch [13:25:24] [PASSED] ttm_pool_free_dma_alloc [13:25:25] [ERROR] Test: ttm_pool: missing expected subtest! [13:25:25] [13:25:25] Pid: 75, comm: kunit_try_catch Tainted: G W N 7.0.0-rc7-g206eb51f3379 [13:25:25] RIP: 0033:list_lru_count_node+0xe/0x20 [13:25:25] RSP: 00000000b30cbed8 EFLAGS: 00010246 [13:25:25] RAX: 0000000000000000 RBX: 00000000b3003c90 RCX: 000000007324c7d8 [13:25:25] RDX: 0000000000000000 RSI: 0000000000000000 RDI: 0000000073086880 [13:25:25] RBP: 0000000073086800 R08: 00000000b1a68c28 R09: 0000000073050c80 [13:25:25] R10: 0000000000000000 R11: 0000000000000000 R12: 0000000073050c80 [13:25:25] R13: 0000000060440770 R14: 000000006010eb50 R15: 0000000073086880 [13:25:25] Kernel panic - not syncing: Segfault with no mm [13:25:25] [CRASHED] [13:25:25] [ERROR] Test: ttm_pool: missing expected subtest! [13:25:25] [CRASHED] [13:25:25] [ERROR] Test: ttm_pool: missing subtest result line! [13:25:25] # module: ttm_pool_test [13:25:25] ==================== [CRASHED] ttm_pool ==================== [13:25:25] [ERROR] Test: main: missing expected subtest! [13:25:25] [CRASHED] [13:25:25] [ERROR] Test: main: missing expected subtest! [13:25:25] [CRASHED] [13:25:25] [ERROR] Test: main: missing expected subtest! [13:25:25] [CRASHED] [13:25:25] [ERROR] Test: main: missing expected subtest! [13:25:25] [CRASHED] [13:25:25] ============================================================ [13:25:25] Testing complete. Ran 28 tests: passed: 20, failed: 2, crashed: 6, errors: 7 The kernel seems to have crashed; you can decode the stack traces with: $ scripts/decode_stacktrace.sh .kunit/vmlinux .kunit < .kunit/test.log | tee .kunit/decoded.log | /kernel/tools/testing/kunit/kunit.py parse [13:25:25] Elapsed time: 21.088s total, 2.994s configuring, 17.672s building, 0.422s running + cleanup ++ stat -c %u:%g /kernel + chown -R 1003:1003 /kernel ^ permalink raw reply [flat|nested] 7+ messages in thread
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2026-04-08 13:15 [PATCH 0/4] drm/i915/display: start switching to display specific reg types Jani Nikula
2026-04-08 13:15 ` [PATCH 1/4] drm/i915/display: add typedef for intel_reg_t and use it Jani Nikula
2026-04-08 13:15 ` [PATCH 2/4] drm/i915/display: add struct intel_irq_regs " Jani Nikula
2026-04-08 13:15 ` [PATCH 3/4] drm/i915/display: add struct intel_error_regs " Jani Nikula
2026-04-08 13:15 ` [PATCH 4/4] drm/i915/display: define and use intel_reg_{offset, equal, valid}() helpers Jani Nikula
2026-04-08 13:22 ` ✗ CI.checkpatch: warning for drm/i915/display: start switching to display specific reg types Patchwork
2026-04-08 13:25 ` ✗ CI.KUnit: failure " Patchwork
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