From: Jani Nikula <jani.nikula@intel.com>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>,
intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org,
uma.shankar@intel.com, dibin.moolakadan.subrahmanian@intel.com
Subject: Re: [PATCH v3 03/12] drm/i915/cmtg: set timings for CMTG
Date: Tue, 07 Apr 2026 14:03:23 +0300 [thread overview]
Message-ID: <d048866d707e0f02a811c2bc8ba866cda2a16b38@intel.com> (raw)
In-Reply-To: <adTVoIgNc0K3_Zok@intel.com>
On Tue, 07 Apr 2026, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Tue, Apr 07, 2026 at 11:03:37AM +0300, Jani Nikula wrote:
>> On Fri, 13 Mar 2026, Animesh Manna <animesh.manna@intel.com> wrote:
>> > +#define TRANS_HTOTAL_CMTG(trans) _MMIO(0x6F000 + (trans) * 0x100)
>> > +#define TRANS_HBLANK_CMTG(trans) _MMIO(0x6F004 + (trans) * 0x100)
>> > +#define TRANS_HSYNC_CMTG(trans) _MMIO(0x6F008 + (trans) * 0x100)
>> > +#define TRANS_VTOTAL_CMTG(trans) _MMIO(0x6F00C + (trans) * 0x100)
>> > +#define TRANS_VBLANK_CMTG(trans) _MMIO(0x6F010 + (trans) * 0x100)
>> > +#define TRANS_VSYNC_CMTG(trans) _MMIO(0x6F014 + (trans) * 0x100)
>> > +
>> > +#define TRANS_SET_CTX_LATENCY_CMTG(trans) _MMIO(0x6F07C + (trans) * 0x100)
>
> These are all just normal transcoder registers, so no new definitions
> should be necessary at all.
Right, so the question becomes why are their writes duplicated, and
what's with the whole "Timing registers are separate for CMTG" part in
the commit message???
BR,
Jani.
>
>>
>> We have a bunch of helpers to avoid doing the manual multiplication
>> here.
>>
>> BR,
>> Jani.
>>
>>
>> --
>> Jani Nikula, Intel
--
Jani Nikula, Intel
next prev parent reply other threads:[~2026-04-07 11:03 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-13 15:32 [PATCH v3 00/12] CMTG enablement Animesh Manna
2026-03-13 15:32 ` [PATCH v3 01/12] drm/i915/cmtg: add is_enable_allowed() for cmtg Animesh Manna
2026-04-06 18:48 ` Shankar, Uma
2026-04-07 8:59 ` Dibin Moolakadan Subrahmanian
2026-04-07 10:03 ` Ville Syrjälä
2026-03-13 15:32 ` [PATCH v3 02/12] drm/i915/cmtg: set CMTG clock select Animesh Manna
2026-04-06 19:02 ` Shankar, Uma
2026-03-13 15:32 ` [PATCH v3 03/12] drm/i915/cmtg: set timings for CMTG Animesh Manna
2026-04-06 19:24 ` Shankar, Uma
2026-04-07 8:03 ` Jani Nikula
2026-04-07 10:00 ` Ville Syrjälä
2026-04-07 11:03 ` Jani Nikula [this message]
2026-04-09 14:00 ` Manna, Animesh
2026-03-13 15:32 ` [PATCH v3 04/12] drm/i915/cmtg: program VRR registers of CMTG Animesh Manna
2026-04-06 19:35 ` Shankar, Uma
2026-03-13 15:32 ` [PATCH v3 05/12] drm/i915/cmtg: set transcoder mn for CMTG Animesh Manna
2026-04-06 19:43 ` Shankar, Uma
2026-03-13 15:32 ` [PATCH v3 06/12] drm/i915/cmtg: add hook to enable CMTG with sync to port Animesh Manna
2026-04-06 19:52 ` Shankar, Uma
2026-03-13 15:32 ` [PATCH v3 07/12] drm/i915/cmtg: add a hook to enable ddi for CMTG Animesh Manna
2026-04-06 20:07 ` Shankar, Uma
2026-03-13 15:32 ` [PATCH v3 08/12] drm/i915/cmtg: modify existing hook to disable CMTG Animesh Manna
2026-04-06 20:13 ` Shankar, Uma
2026-03-13 15:32 ` [PATCH v3 09/12] drm/i915/cmtg: Add trigger to enable/disable cmtg Animesh Manna
2026-04-06 20:50 ` Shankar, Uma
2026-03-13 15:32 ` [PATCH v3 10/12] drm/i915/cmtg: Add CMTG interrupt handling Animesh Manna
2026-04-06 21:37 ` Shankar, Uma
2026-03-13 15:32 ` [PATCH v3 11/12] drm/i915/cmtg: set dc3co_enable flag for lobf/psr2/pr-alpm Animesh Manna
2026-04-06 21:39 ` Shankar, Uma
2026-03-13 15:33 ` [PATCH v3 12/12] drm/i915/cmtg: disable CMTG if dc3co entry condition not met Animesh Manna
2026-04-06 21:42 ` Shankar, Uma
2026-03-13 16:10 ` ✓ CI.KUnit: success for CMTG enablement (rev4) Patchwork
2026-03-13 17:01 ` ✓ Xe.CI.BAT: " Patchwork
2026-03-14 21:15 ` ✓ Xe.CI.FULL: " Patchwork
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