Re: [PATCH 18/22] drm/i915/display: Use fixed rr timings in intel_set_transcoder_timings_lrr()

["Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com>]

On 3/5/2025 12:26 AM, Ville Syrjälä wrote:
> On Tue, Mar 04, 2025 at 01:49:44PM +0530, Ankit Nautiyal wrote:
>> To have Guardband/Pipeline_full reconfigured seamlessly, move the
>> guardband and pipeline_full from intel_pipe_config_compare() to fastboot
>> exception.
>> Update the intel_set_transcoder_timings_lrr() function to use
>> fixed refresh rate timings for platforms which always use
>> VRR timing generator.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_display.c | 9 +++++++--
>>   drivers/gpu/drm/i915/display/intel_vrr.c     | 1 -
>>   drivers/gpu/drm/i915/display/intel_vrr.h     | 1 +
>>   3 files changed, 8 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index 3e8ceafcbbb4..c31a87d8afd3 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -2768,6 +2768,9 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
>>   	intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder),
>>   		       VACTIVE(crtc_vdisplay - 1) |
>>   		       VTOTAL(crtc_vtotal - 1));
>> +
>> +	intel_vrr_set_fixed_rr_timings(crtc_state);
>> +	intel_vrr_transcoder_enable(crtc_state);
>>   }
>>   
>>   static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
>> @@ -5418,8 +5421,10 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>>   		PIPE_CONF_CHECK_BOOL(cmrr.enable);
>>   	}
>>   
>> -	PIPE_CONF_CHECK_I(vrr.pipeline_full);
>> -	PIPE_CONF_CHECK_I(vrr.guardband);
>> +	if (!fastset && !allow_vblank_delay_fastset(current_config)) {
> Should be ||, but I think this would still break LRR.


Will fix to ||.


Yes this is breaking seamless switch to LRR, as also mentioned in last 
version.

The Bspec: 68917 mentions to disable VRR first for LNL.

For PTL it seems to just mention to set Flipline = Vmax and the fact 
that Vmin/Flipline/Vmax can be set to any refresh rate supported by panel.

Whether its safe to change guardband for PTL, not much sure.

Regards,
Ankit
>
>> +		PIPE_CONF_CHECK_I(vrr.pipeline_full);
>> +		PIPE_CONF_CHECK_I(vrr.guardband);
>> +	}
>>   
>>   #undef PIPE_CONF_CHECK_X
>>   #undef PIPE_CONF_CHECK_I
>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
>> index 11f23affd13a..0dfe6220ff4a 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
>> @@ -284,7 +284,6 @@ int intel_vrr_fixed_rr_flipline(const struct intel_crtc_state *crtc_state)
>>   	return intel_vrr_fixed_rr_vtotal(crtc_state);
>>   }
>>   
>> -static
>>   void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state)
>>   {
>>   	struct intel_display *display = to_intel_display(crtc_state);
>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
>> index c81f98f83b58..0e1becd7a0c0 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vrr.h
>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.h
>> @@ -38,5 +38,6 @@ int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state);
>>   int intel_vrr_vblank_delay(const struct intel_crtc_state *crtc_state);
>>   void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state);
>>   void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state);
>> +void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state);
>>   
>>   #endif /* __INTEL_VRR_H__ */
>> -- 
>> 2.45.2