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d="scan'208";a="255477419" Received: from carterle-desk.ger.corp.intel.com (HELO localhost) ([10.245.246.184]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Mar 2026 04:47:21 -0700 From: Jani Nikula To: Ville Syrjala , intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org Subject: Re: [PATCH 12/12] drm/i915/rom: Use intel_de for SPI ROM register access In-Reply-To: <20260325185342.11482-13-ville.syrjala@linux.intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs Bertel Jungin Aukio 5, 02600 Espoo, Finland References: <20260325185342.11482-1-ville.syrjala@linux.intel.com> <20260325185342.11482-13-ville.syrjala@linux.intel.com> Date: Thu, 26 Mar 2026 13:47:17 +0200 Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Wed, 25 Mar 2026, Ville Syrjala wrote: > From: Ville Syrj=C3=A4l=C3=A4 > > Since we moved intel_rom.c back into the display code, juse > use intel_de_{read,write}() for the register accesses. > > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/intel_rom.c | 19 ++++++++++--------- > 1 file changed, 10 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_rom.c b/drivers/gpu/drm/i= 915/display/intel_rom.c > index d573059fb0d9..54f842c09fb0 100644 > --- a/drivers/gpu/drm/i915/display/intel_rom.c > +++ b/drivers/gpu/drm/i915/display/intel_rom.c > @@ -7,8 +7,9 @@ >=20=20 > #include >=20=20 > +#include "intel_de.h" > +#include "intel_display_types.h" > #include "intel_rom.h" > -#include "intel_uncore.h" > #include "intel_oprom_regs.h" >=20=20 > struct intel_rom { > @@ -17,7 +18,7 @@ struct intel_rom { > void __iomem *oprom; >=20=20 > /* for SPI */ > - struct intel_uncore *uncore; > + struct intel_display *display; > loff_t offset; >=20=20 > size_t size; > @@ -30,10 +31,10 @@ struct intel_rom { >=20=20 > static u32 spi_read32(struct intel_rom *rom, loff_t offset) > { > - intel_uncore_write(rom->uncore, PRIMARY_SPI_ADDRESS, > - rom->offset + offset); > + intel_de_write(rom->display, PRIMARY_SPI_ADDRESS, > + rom->offset + offset); >=20=20 > - return intel_uncore_read(rom->uncore, PRIMARY_SPI_TRIGGER); > + return intel_de_read(rom->display, PRIMARY_SPI_TRIGGER); > } >=20=20 > static u16 spi_read16(struct intel_rom *rom, loff_t offset) > @@ -50,13 +51,13 @@ struct intel_rom *intel_rom_spi(struct drm_device *dr= m) > if (!rom) > return NULL; >=20=20 > - rom->uncore =3D to_intel_uncore(drm); > + rom->display =3D to_intel_display(drm); >=20=20 > - static_region =3D intel_uncore_read(rom->uncore, SPI_STATIC_REGIONS); > + static_region =3D intel_de_read(rom->display, SPI_STATIC_REGIONS); > static_region &=3D OPTIONROM_SPI_REGIONID_MASK; > - intel_uncore_write(rom->uncore, PRIMARY_SPI_REGIONID, static_region); > + intel_de_write(rom->display, PRIMARY_SPI_REGIONID, static_region); >=20=20 > - rom->offset =3D intel_uncore_read(rom->uncore, OROM_OFFSET) & OROM_OFFS= ET_MASK; > + rom->offset =3D intel_de_read(rom->display, OROM_OFFSET) & OROM_OFFSET_= MASK; >=20=20 > rom->size =3D 0x200000; --=20 Jani Nikula, Intel