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Increment > DC Balance Flip count before every send push to indicate DMC > firmware about new flip occurrence. This is tracked separately > from legacy FLIP_COUNT register also Reset DC balance flip > count value while disabling VRR adaptive mode, this is to > start with fresh counts when VRR adaptive refresh mode is > triggered again. > > Signed-off-by: Mitul Golani > --- > drivers/gpu/drm/i915/display/intel_color.c | 2 ++ > drivers/gpu/drm/i915/display/intel_display.c | 3 ++- > .../drm/i915/display/intel_display_types.h | 4 ++++ > drivers/gpu/drm/i915/display/intel_vrr.c | 23 +++++++++++++++++++ > drivers/gpu/drm/i915/display/intel_vrr.h | 3 +++ > 5 files changed, 34 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c > index a217a67ceb43..115f6d7eb874 100644 > --- a/drivers/gpu/drm/i915/display/intel_color.c > +++ b/drivers/gpu/drm/i915/display/intel_color.c > @@ -2013,6 +2013,8 @@ void intel_color_prepare_commit(struct intel_atomic_state *state, > display->funcs.color->load_luts(crtc_state); > > if (crtc_state->use_dsb && intel_color_uses_chained_dsb(crtc_state)) { > + intel_vrr_dcb_increment_flip_count(crtc_state->dsb_color, > + crtc_state, crtc); I still think we need to do this for MMIO path along with the DSB path. Perhaps add the flip count increment at last in intel_update_crtc() then we do not need to use DSB. I am not very sure about this. Regards, Ankit > intel_vrr_send_push(crtc_state->dsb_color, crtc_state); > intel_dsb_wait_for_delayed_vblank(state, crtc_state->dsb_color); > intel_vrr_check_push_sent(crtc_state->dsb_color, crtc_state); > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index df5d1554538d..e7fda3b2944c 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -7378,7 +7378,8 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state, > > if (new_crtc_state->use_dsb && !intel_color_uses_chained_dsb(new_crtc_state)) { > intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1); > - > + intel_vrr_dcb_increment_flip_count(new_crtc_state->dsb_commit, > + new_crtc_state, crtc); > intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state); > intel_dsb_wait_for_delayed_vblank(state, new_crtc_state->dsb_commit); > intel_vrr_check_push_sent(new_crtc_state->dsb_commit, > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h > index 8eb0ace7d918..740c5fc9fe1e 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -1501,6 +1501,10 @@ struct intel_crtc { > struct intel_link_m_n m_n, m2_n2; > } drrs; > > + struct { > + u64 flip_count; > + } dc_balance; > + > int scanline_offset; > > struct { > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c > index 5e24ac3e6c75..788e93cea29d 100644 > --- a/drivers/gpu/drm/i915/display/intel_vrr.c > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c > @@ -624,6 +624,28 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state) > EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start)); > } > > +void > +intel_vrr_dcb_increment_flip_count(struct intel_dsb *dsb, > + struct intel_crtc_state *crtc_state, > + struct intel_crtc *crtc) > +{ > + struct intel_display *display = to_intel_display(crtc_state); > + enum pipe pipe = crtc->pipe; > + > + if (!crtc_state->vrr.dc_balance.enable) > + return; > + > + if (dsb) > + intel_dsb_nonpost_start(dsb); > + > + intel_de_write_dsb(display, dsb, > + PIPEDMC_DCB_FLIP_COUNT(pipe), > + ++crtc->dc_balance.flip_count); > + > + if (dsb) > + intel_dsb_nonpost_end(dsb); > +} > + > void > intel_vrr_dcb_reset(const struct intel_crtc_state *crtc_state, > struct intel_crtc *crtc) > @@ -634,6 +656,7 @@ intel_vrr_dcb_reset(const struct intel_crtc_state *crtc_state, > if (!crtc_state->vrr.dc_balance.enable) > return; > > + intel_de_write(display, PIPEDMC_DCB_FLIP_COUNT(pipe), 0); > intel_de_write(display, PIPEDMC_DCB_BALANCE_RESET(pipe), 0); > } > > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h > index 1a11d288dfb4..7aa1f31ee287 100644 > --- a/drivers/gpu/drm/i915/display/intel_vrr.h > +++ b/drivers/gpu/drm/i915/display/intel_vrr.h > @@ -29,6 +29,9 @@ void intel_vrr_send_push(struct intel_dsb *dsb, > const struct intel_crtc_state *crtc_state); > void intel_vrr_check_push_sent(struct intel_dsb *dsb, > const struct intel_crtc_state *crtc_state); > +void intel_vrr_dcb_increment_flip_count(struct intel_dsb *dsb, > + struct intel_crtc_state *crtc_state, > + struct intel_crtc *crtc); > bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state); > void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state); > void intel_vrr_get_config(struct intel_crtc_state *crtc_state);