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* [PATCH 00/19] drm/i915/tc: Fix enabled/disconnected DP-alt sink handling
@ 2025-08-05  7:36 Imre Deak
  2025-08-05  7:36 ` [PATCH 01/19] drm/i915/lnl+/tc: Fix handling of an enabled/disconnected dp-alt sink Imre Deak
                   ` (30 more replies)
  0 siblings, 31 replies; 65+ messages in thread
From: Imre Deak @ 2025-08-05  7:36 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: Charlton Lin, Khaled Almahallawy

This patchset fixes an issue on LNL+, where the TypeC PHY's mode/state
is detected incorrectly during HW readout for a DP-alt sink that got
enabled by BIOS/GOP, but later the sink got disconnected by the user
before the driver got loaded.

The issue in the driver is due to overlooking a change on LNL+ in the
way the PHY ready flag and pin assignment is set/cleared in the PHY
registers by the HW/FW wrt. how this works on all the earlier (ICL-MTL)
TypeC platforms.

The first 5 patches fix the issue, the rest refactor the PHY's max lane
count and pin assignment query functions, sanitizing the code, removing
duplications and validating the register values read out from the HW.

Reported-by: Charlton Lin <charlton.lin@intel.com>
Tested-by: Khaled Almahallawy <khaled.almahallawy@intel.com>

Imre Deak (19):
  drm/i915/lnl+/tc: Fix handling of an enabled/disconnected dp-alt sink
  drm/i915/icl+/tc: Cache the max lane count value
  drm/i915/lnl+/tc: Fix max lane count HW readout
  drm/i915/lnl+/tc: Use the cached max lane count value
  drm/i915/icl+/tc: Convert AUX powered WARN to a debug message
  drm/i915/tc: Use the cached max lane count value
  drm/i915/tc: Move getting the power domain before reading DFLEX
    registers
  drm/i915/tc: Move asserting the power state after reading
    TCSS_DDI_STATUS
  drm/i915/tc: Add an enum for the TypeC pin assignment
  drm/i915/tc: Pass pin assignment value around using the pin assignment
    enum
  drm/i915/tc: Handle pin assignment NONE on all platforms
  drm/i915/tc: Validate the pin assignment on all platforms
  drm/i915/tc: Unify the way to get the pin assignment on all platforms
  drm/i915/tc: Unify the way to get the max lane count value on MTL+
  drm/i915/tc: Handle non-TC encoders when getting the pin assignment
  drm/i915/tc: Pass intel_tc_port to internal lane mask/count helpers
  dmc/i915/tc: Report pin assignment NONE in TBT-alt mode
  drm/i915/tc: Cache the pin assignment value
  drm/i915/tc: Debug print the pin assignment and max lane count

 drivers/gpu/drm/i915/display/intel_ddi.c      |  19 +-
 .../gpu/drm/i915/display/intel_display_regs.h |   2 +
 drivers/gpu/drm/i915/display/intel_tc.c       | 217 ++++++++++++------
 drivers/gpu/drm/i915/display/intel_tc.h       |  72 +++++-
 4 files changed, 225 insertions(+), 85 deletions(-)

-- 
2.49.1


^ permalink raw reply	[flat|nested] 65+ messages in thread

end of thread, other threads:[~2025-08-13 12:44 UTC | newest]

Thread overview: 65+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-08-05  7:36 [PATCH 00/19] drm/i915/tc: Fix enabled/disconnected DP-alt sink handling Imre Deak
2025-08-05  7:36 ` [PATCH 01/19] drm/i915/lnl+/tc: Fix handling of an enabled/disconnected dp-alt sink Imre Deak
2025-08-07  7:06   ` Kahola, Mika
2025-08-07 10:59   ` Luca Coelho
2025-08-07 11:38     ` Imre Deak
2025-08-07 12:19       ` Jani Nikula
2025-08-07 12:32         ` Imre Deak
2025-08-07 12:50           ` Imre Deak
2025-08-07 13:05             ` Jani Nikula
2025-08-07 13:24               ` Imre Deak
2025-08-07 14:10             ` Luca Coelho
2025-08-05  7:36 ` [PATCH 02/19] drm/i915/icl+/tc: Cache the max lane count value Imre Deak
2025-08-05  9:33   ` [PATCH v2 " Imre Deak
2025-08-07  8:07     ` Kahola, Mika
2025-08-05  7:36 ` [PATCH 03/19] drm/i915/lnl+/tc: Fix max lane count HW readout Imre Deak
2025-08-05  9:33   ` [PATCH v2 " Imre Deak
2025-08-07  8:36     ` Kahola, Mika
2025-08-05  7:36 ` [PATCH 04/19] drm/i915/lnl+/tc: Use the cached max lane count value Imre Deak
2025-08-07  8:49   ` Kahola, Mika
2025-08-05  7:36 ` [PATCH 05/19] drm/i915/icl+/tc: Convert AUX powered WARN to a debug message Imre Deak
2025-08-07 12:29   ` Kahola, Mika
2025-08-05  7:36 ` [PATCH 06/19] drm/i915/tc: Use the cached max lane count value Imre Deak
2025-08-06 12:02   ` Kahola, Mika
2025-08-05  7:36 ` [PATCH 07/19] drm/i915/tc: Move getting the power domain before reading DFLEX registers Imre Deak
2025-08-06 12:56   ` Kahola, Mika
2025-08-05  7:36 ` [PATCH 08/19] drm/i915/tc: Move asserting the power state after reading TCSS_DDI_STATUS Imre Deak
2025-08-06 13:22   ` Kahola, Mika
2025-08-05  7:36 ` [PATCH 09/19] drm/i915/tc: Add an enum for the TypeC pin assignment Imre Deak
2025-08-07 12:39   ` Kahola, Mika
2025-08-05  7:36 ` [PATCH 10/19] drm/i915/tc: Pass pin assignment value around using the pin assignment enum Imre Deak
2025-08-07 12:56   ` Kahola, Mika
2025-08-05  7:36 ` [PATCH 11/19] drm/i915/tc: Handle pin assignment NONE on all platforms Imre Deak
2025-08-07 12:57   ` Kahola, Mika
2025-08-05  7:36 ` [PATCH 12/19] drm/i915/tc: Validate the pin assignment " Imre Deak
2025-08-07 13:08   ` Kahola, Mika
2025-08-05  7:36 ` [PATCH 13/19] drm/i915/tc: Unify the way to get " Imre Deak
2025-08-08  6:44   ` Kahola, Mika
2025-08-05  7:36 ` [PATCH 14/19] drm/i915/tc: Unify the way to get the max lane count value on MTL+ Imre Deak
2025-08-08  7:32   ` Kahola, Mika
2025-08-05  7:36 ` [PATCH 15/19] drm/i915/tc: Handle non-TC encoders when getting the pin assignment Imre Deak
2025-08-08  7:45   ` Kahola, Mika
2025-08-05  7:36 ` [PATCH 16/19] drm/i915/tc: Pass intel_tc_port to internal lane mask/count helpers Imre Deak
2025-08-08  8:25   ` Kahola, Mika
2025-08-05  7:36 ` [PATCH 17/19] dmc/i915/tc: Report pin assignment NONE in TBT-alt mode Imre Deak
2025-08-08  8:26   ` Kahola, Mika
2025-08-05  7:36 ` [PATCH 18/19] drm/i915/tc: Cache the pin assignment value Imre Deak
2025-08-08  8:27   ` Kahola, Mika
2025-08-05  7:37 ` [PATCH 19/19] drm/i915/tc: Debug print the pin assignment and max lane count Imre Deak
2025-08-08  8:28   ` Kahola, Mika
2025-08-05  7:46 ` ✗ CI.checkpatch: warning for drm/i915/tc: Fix enabled/disconnected DP-alt sink handling Patchwork
2025-08-05  7:47 ` ✓ CI.KUnit: success " Patchwork
2025-08-05  8:02 ` ✗ CI.checksparse: warning " Patchwork
2025-08-05  8:49 ` ✗ Xe.CI.BAT: failure " Patchwork
2025-08-05 10:08 ` ✓ Xe.CI.Full: success " Patchwork
2025-08-05 11:41 ` ✗ CI.checkpatch: warning for drm/i915/tc: Fix enabled/disconnected DP-alt sink handling (rev3) Patchwork
2025-08-05 11:42 ` ✓ CI.KUnit: success " Patchwork
2025-08-05 11:57 ` ✗ CI.checksparse: warning " Patchwork
2025-08-05 13:02 ` ✓ Xe.CI.BAT: success " Patchwork
2025-08-05 15:31 ` ✓ Xe.CI.Full: " Patchwork
2025-08-06 11:44 ` [PATCH 00/19] drm/i915/tc: Fix enabled/disconnected DP-alt sink handling Luca Coelho
2025-08-06 11:54   ` Imre Deak
2025-08-06 12:54     ` Luca Coelho
2025-08-06 13:12       ` Imre Deak
2025-08-06 13:16         ` Luca Coelho
     [not found] ` <175439829105.213103.3969215907569188087@1538d3639d33>
2025-08-13 12:43   ` ✗ i915.CI.Full: failure for drm/i915/tc: Fix enabled/disconnected DP-alt sink handling (rev3) Imre Deak

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