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X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 --------------NxpqxcZZbz59UT0ZazBF2ymA Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit On 11-11-2026 06:00 pm, Riana Tauro wrote: > Add support for handling PCIe subsystem errors. PCIe subsystem power > management errors require a Seconday bus reset(SBR) for recovery. Treat all > others as recovered and take no further action. > > Signed-off-by: Riana Tauro > --- > v2: add mapping to cper severity (Badal, Rodrigo) > add abbreviations > fix punctuations (Raag) > --- > drivers/gpu/drm/xe/xe_ras.c | 16 ++++++++++++++++ > drivers/gpu/drm/xe/xe_ras_types.h | 2 ++ > 2 files changed, 18 insertions(+) > > diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c > index 2c01c183d02b..bd3ad017f013 100644 > --- a/drivers/gpu/drm/xe/xe_ras.c > +++ b/drivers/gpu/drm/xe/xe_ras.c > @@ -698,6 +698,19 @@ static u8 handle_device_memory_errors(struct xe_device *xe, struct xe_ras_error_ > return XE_RAS_RECOVERY_ACTION_RECOVERED; > } > > +static u8 handle_pcie_errors(struct xe_device *xe, struct xe_ras_error_array *arr) > +{ > + struct xe_ras_ieh_error *info = (void *)arr->details; > + > + xe_log_comp(xe, ras_sev_to_cper_sev(arr->counter.common.severity), PCIE, &arr->counter, > + sizeof(arr->counter), "error detected\n"); For consistency, start message with capital letter and log global_error_status as well. Thanks, -/Mallesh > + > + if (info->global_error_status & XE_RAS_PCIE_IEH_GPMA) > + return XE_RAS_RECOVERY_ACTION_RESET; > + > + return XE_RAS_RECOVERY_ACTION_RECOVERED; > +} > + > void xe_ras_counter_threshold_crossed(struct xe_device *xe, > struct xe_sysctrl_event_response *response) > { > @@ -889,6 +902,9 @@ enum xe_ras_recovery_action xe_ras_process_errors(struct xe_device *xe) > case XE_RAS_COMP_DEVICE_MEMORY: > action = handle_device_memory_errors(xe, arr); > break; > + case XE_RAS_COMP_PCIE: > + action = handle_pcie_errors(xe, arr); > + break; > default: > /* For any other component, reset */ > action = XE_RAS_RECOVERY_ACTION_RESET; > diff --git a/drivers/gpu/drm/xe/xe_ras_types.h b/drivers/gpu/drm/xe/xe_ras_types.h > index a86f9d2b8c92..36435a3f52e7 100644 > --- a/drivers/gpu/drm/xe/xe_ras_types.h > +++ b/drivers/gpu/drm/xe/xe_ras_types.h > @@ -14,6 +14,8 @@ > #define XE_RAS_NUM_PAGES 25 > /* Error bits in IEH global error status register */ > #define XE_RAS_SOC_IEH_PUNIT BIT(1) > +#define XE_RAS_PCIE_IEH_GPMA BIT(5) > + > /* Device memory error categories */ > #define XE_RAS_MEMORY_DB_ECC BIT(1) > #define XE_RAS_MEMORY_POISON BIT(2) --------------NxpqxcZZbz59UT0ZazBF2ymA Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: 8bit


On 11-11-2026 06:00 pm, Riana Tauro wrote:
Add support for handling PCIe subsystem errors. PCIe subsystem power
management errors require a Seconday bus reset(SBR) for recovery. Treat all
others as recovered and take no further action.

Signed-off-by: Riana Tauro <riana.tauro@intel.com>
---
v2: add mapping to cper severity (Badal, Rodrigo)
    add abbreviations
    fix punctuations (Raag)
---
 drivers/gpu/drm/xe/xe_ras.c       | 16 ++++++++++++++++
 drivers/gpu/drm/xe/xe_ras_types.h |  2 ++
 2 files changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
index 2c01c183d02b..bd3ad017f013 100644
--- a/drivers/gpu/drm/xe/xe_ras.c
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -698,6 +698,19 @@ static u8 handle_device_memory_errors(struct xe_device *xe, struct xe_ras_error_
 	return XE_RAS_RECOVERY_ACTION_RECOVERED;
 }
 
+static u8 handle_pcie_errors(struct xe_device *xe, struct xe_ras_error_array *arr)
+{
+	struct xe_ras_ieh_error *info = (void *)arr->details;
+
+	xe_log_comp(xe, ras_sev_to_cper_sev(arr->counter.common.severity), PCIE, &arr->counter,
+		    sizeof(arr->counter), "error detected\n");

For consistency, start message with capital letter and log global_error_status as well.

Thanks,

-/Mallesh

+
+	if (info->global_error_status & XE_RAS_PCIE_IEH_GPMA)
+		return XE_RAS_RECOVERY_ACTION_RESET;
+
+	return XE_RAS_RECOVERY_ACTION_RECOVERED;
+}
+
 void xe_ras_counter_threshold_crossed(struct xe_device *xe,
 				      struct xe_sysctrl_event_response *response)
 {
@@ -889,6 +902,9 @@ enum xe_ras_recovery_action xe_ras_process_errors(struct xe_device *xe)
 			case XE_RAS_COMP_DEVICE_MEMORY:
 				action = handle_device_memory_errors(xe, arr);
 				break;
+			case XE_RAS_COMP_PCIE:
+				action = handle_pcie_errors(xe, arr);
+				break;
 			default:
 				/* For any other component, reset */
 				action = XE_RAS_RECOVERY_ACTION_RESET;
diff --git a/drivers/gpu/drm/xe/xe_ras_types.h b/drivers/gpu/drm/xe/xe_ras_types.h
index a86f9d2b8c92..36435a3f52e7 100644
--- a/drivers/gpu/drm/xe/xe_ras_types.h
+++ b/drivers/gpu/drm/xe/xe_ras_types.h
@@ -14,6 +14,8 @@
 #define XE_RAS_NUM_PAGES			25
 /* Error bits in IEH global error status register */
 #define XE_RAS_SOC_IEH_PUNIT			BIT(1)
+#define XE_RAS_PCIE_IEH_GPMA			BIT(5)
+
 /* Device memory error categories */
 #define XE_RAS_MEMORY_DB_ECC			BIT(1)
 #define XE_RAS_MEMORY_POISON			BIT(2)
--------------NxpqxcZZbz59UT0ZazBF2ymA--