Re: [PATCH 4/7] drm/i915/psr: Add new macro for accessing cached PSR DPCD registers

[Jani Nikula <jani.nikula@linux.intel.com>]

On Wed, 08 Apr 2026, Jouni Högander <jouni.hogander@intel.com> wrote:
> Add new macro to ease accessing cached PSR DPCD registers.
>
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index e2496db1642a..7d04867e3053 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -584,6 +584,7 @@ struct intel_connector {
>  
>  		struct {
>  			u8 dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
> +#define INTEL_PSR_DPCD_INDEX(psr_dpcd_register)	((psr_dpcd_register) - DP_PSR_SUPPORT)

Dunno, feels like maybe this should be in intel_psr.c. The point being,
that the whole member should basically be off-limits outside of
intel_psr.c.

BR,
Jani.

>  
>  			bool support;
>  			bool su_support;

-- 
Jani Nikula, Intel