From: "Sundaresan, Sujaritha" <sujaritha.sundaresan@intel.com>
To: "Gupta, Anshuman" <anshuman.gupta@intel.com>,
"intel-xe@lists.freedesktop.org" <intel-xe@lists.freedesktop.org>
Subject: Re: [Intel-xe] [PATCH 2/2] drm/xe: Sysfs entries to query vram fused min, max frequency
Date: Tue, 29 Aug 2023 10:46:19 +0530 [thread overview]
Message-ID: <e72d7788-7c54-341d-53a5-e8d67f0f6bfe@intel.com> (raw)
In-Reply-To: <CY5PR11MB6211CCF155D51F1A42496166951EA@CY5PR11MB6211.namprd11.prod.outlook.com>
On 8/21/2023 6:55 PM, Gupta, Anshuman wrote:
>
>> -----Original Message-----
>> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of
>> Sujaritha Sundaresan
>> Sent: Monday, August 21, 2023 5:37 PM
>> To: intel-xe@lists.freedesktop.org
>> Cc: Sundaresan, Sujaritha <sujaritha.sundaresan@intel.com>
>> Subject: [Intel-xe] [PATCH 2/2] drm/xe: Sysfs entries to query vram fused
>> min, max frequency
>>
>> Add sysfs entries to query fused min and max frequency of vram
>>
>> Signed-off-by: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
>> ---
>> drivers/gpu/drm/xe/xe_guc_pc.c | 55
>> +++++++++++++++++++++++++++++++
>> drivers/gpu/drm/xe/xe_pcode_api.h | 8 +++++
>> 2 files changed, 63 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c
>> b/drivers/gpu/drm/xe/xe_guc_pc.c index c03bb58e7049..d7e9609c74c0
>> 100644
>> --- a/drivers/gpu/drm/xe/xe_guc_pc.c
>> +++ b/drivers/gpu/drm/xe/xe_guc_pc.c
>> @@ -20,6 +20,7 @@
>> #include "xe_map.h"
>> #include "xe_mmio.h"
>> #include "xe_pcode.h"
>> +#include "xe_pcode_api.h"
>>
>> #define MCHBAR_MIRROR_BASE_SNB 0x140000
>>
>> @@ -568,6 +569,54 @@ static ssize_t freq_max_store(struct device *dev,
>> struct device_attribute *attr, } static DEVICE_ATTR_RW(freq_max);
>>
>> +static ssize_t freq_vram_rp0_show(struct device *dev, struct
>> device_attribute *attr,
>> + char *buff)
>> +{
>> + struct xe_guc_pc *pc = dev_to_pc(dev);
>> + struct xe_gt *gt = pc_to_gt(pc);
>> + u32 val;
>> + int err;
>> +
>> + err = xe_pcode_read_p(gt, XEHP_PCODE_FREQUENCY_CONFIG,
>> + PCODE_MBOX_FC_SC_READ_FUSED_P0,
>> + PCODE_MBOX_DOMAIN_HBM, &val);
>> + if (err)
>> + return err;
>> +
>> + /* data_out - Fused P0 for domain ID in units of 50 MHz */
>> + val *= GT_FREQUENCY_MULTIPLIER;
>> +
>> + return sysfs_emit(buff, "%u\n", val);
>> +}
>> +static DEVICE_ATTR_RO(freq_vram_rp0);
>> +
>> +static ssize_t freq_vram_rpn_show(struct device *dev, struct
>> device_attribute *attr,
>> + char *buff)
>> +{
>> + struct xe_guc_pc *pc = dev_to_pc(dev);
>> + struct xe_gt *gt = pc_to_gt(pc);
>> + u32 val;
>> + int err;
>> +
>> + err = xe_pcode_read_p(gt, XEHP_PCODE_FREQUENCY_CONFIG,
>> + PCODE_MBOX_FC_SC_READ_FUSED_PN,
>> + PCODE_MBOX_DOMAIN_HBM, &val);
>> + if (err)
>> + return err;
>> +
>> + /* data_out - Fused P0 for domain ID in units of 50 MHz */
>> + val *= GT_FREQUENCY_MULTIPLIER;
>> +
>> + return sysfs_emit(buff, "%u\n", val);
>> +}
>> +static DEVICE_ATTR_RO(freq_vram_rpn);
>> +
>> +static const struct attribute *vram_freq_attrs[] = {
>> + &dev_attr_freq_vram_rp0.attr,
>> + &dev_attr_freq_vram_rpn.attr,
>> + NULL
>> +};
>> +
>> /**
>> * xe_guc_pc_c_status - get the current GT C state
>> * @pc: XE_GuC_PC instance
>> @@ -921,6 +970,12 @@ int xe_guc_pc_init(struct xe_guc_pc *pc)
>>
>> pc_init_fused_rp_values(pc);
>>
>> + if (IS_DGFX(xe) && xe->info.platform != XE_DG2) {
> Let's be specific add this only for PVC.
>> + err = sysfs_create_files(gt->sysfs, vram_freq_attrs);
>> + if (err)
>> + return err;
>> + }
>> +
>> err = sysfs_create_files(gt->sysfs, pc_attrs);
>> if (err)
>> return err;
>> diff --git a/drivers/gpu/drm/xe/xe_pcode_api.h
>> b/drivers/gpu/drm/xe/xe_pcode_api.h
>> index 837ff7c71280..846c99aba3bc 100644
>> --- a/drivers/gpu/drm/xe/xe_pcode_api.h
>> +++ b/drivers/gpu/drm/xe/xe_pcode_api.h
>> @@ -25,6 +25,14 @@
>> #define PCODE_DATA0 XE_REG(0x138128)
>> #define PCODE_DATA1 XE_REG(0x13812C)
>>
>> +#define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* xehp, pvc
>> */
>> +/* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
>> +#define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0
>> +#define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1
>> +/* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */
>> +/* XEHP_PCODE_FREQUENCY_CONFIG param2 */
>> +#define PCODE_MBOX_DOMAIN_HBM 0x2
>> +
>> /* Min Freq QOS Table */
>> #define PCODE_WRITE_MIN_FREQ_TABLE 0x8
>> #define PCODE_READ_MIN_FREQ_TABLE 0x9
>> --
>> 2.25.1
Hi Anshuman,
Should these just be moved to xe_tile_sysfs.c ?`
Thanks,
Suja
next prev parent reply other threads:[~2023-08-29 5:16 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-21 12:07 [Intel-xe] [RFC][PATCH 0/2] Add vram frequency sysfs attributes Sujaritha Sundaresan
2023-08-21 12:07 ` [Intel-xe] [RFC][PATCH 1/2] drm/xe: Add a couple of pcode helpers Sujaritha Sundaresan
2023-08-21 13:16 ` Gupta, Anshuman
2023-08-22 5:03 ` Sundaresan, Sujaritha
2023-08-21 12:07 ` [Intel-xe] [PATCH 2/2] drm/xe: Sysfs entries to query vram fused min, max frequency Sujaritha Sundaresan
2023-08-21 13:25 ` Gupta, Anshuman
2023-08-22 5:05 ` Sundaresan, Sujaritha
2023-08-21 13:25 ` Gupta, Anshuman
2023-08-29 5:16 ` Sundaresan, Sujaritha [this message]
2023-08-31 19:52 ` Rodrigo Vivi
2023-08-21 12:13 ` [Intel-xe] ✓ CI.Patch_applied: success for Add vram frequency sysfs attributes Patchwork
2023-08-21 12:14 ` [Intel-xe] ✗ CI.checkpatch: warning " Patchwork
2023-08-21 12:15 ` [Intel-xe] ✓ CI.KUnit: success " Patchwork
2023-08-21 12:19 ` [Intel-xe] ✓ CI.Build: " Patchwork
2023-08-21 12:19 ` [Intel-xe] ✓ CI.Hooks: " Patchwork
2023-08-21 12:19 ` [Intel-xe] ✗ CI.checksparse: warning " Patchwork
2023-08-21 12:43 ` [Intel-xe] ✓ CI.BAT: success " Patchwork
2023-08-21 13:09 ` [Intel-xe] [RFC][PATCH 0/2] " Gupta, Anshuman
2023-08-22 4:59 ` Sundaresan, Sujaritha
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