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46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: vevxe3CnfEePuf/W9m6BtagfFde3ACoyiqwzB9DAurD8dCidqDsqyYu3I9IgeVoIazYjG5EKy6qrb/lioax5xpqLNOgIm9zQKg0hoxRO4so= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR11MB8017 X-OriginatorOrg: intel.com X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On 4/2/2025 6:26 PM, Nemesa Garg wrote: > The sharpness strength value is determined by user input, > while the winsize is based on the resolution. > The casf_enable flag should be set if the platform supports > sharpness adjustments and the user API strength is not zero. > Once sharpness is enabled, update the strength bit of the > register whenever the user changes the strength value, > as the enable bit and winsize bit remain constant. > > v2: Introduce get_config for casf[Ankit] > > Signed-off-by: Nemesa Garg > Reviewed-by: Ankit Nautiyal > --- > drivers/gpu/drm/i915/Makefile | 1 + > drivers/gpu/drm/i915/display/intel_casf.c | 102 ++++++++++++++++++ > drivers/gpu/drm/i915/display/intel_casf.h | 17 +++ > .../gpu/drm/i915/display/intel_casf_regs.h | 22 ++++ > .../drm/i915/display/intel_display_types.h | 7 ++ > drivers/gpu/drm/i915/display/skl_scaler.c | 1 + > drivers/gpu/drm/xe/Makefile | 1 + > 7 files changed, 151 insertions(+) > create mode 100644 drivers/gpu/drm/i915/display/intel_casf.c > create mode 100644 drivers/gpu/drm/i915/display/intel_casf.h > create mode 100644 drivers/gpu/drm/i915/display/intel_casf_regs.h > > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile > index c8fc271b33b7..a955960d09ec 100644 > --- a/drivers/gpu/drm/i915/Makefile > +++ b/drivers/gpu/drm/i915/Makefile > @@ -230,6 +230,7 @@ i915-y += \ > display/intel_bios.o \ > display/intel_bo.o \ > display/intel_bw.o \ > + display/intel_casf.o \ > display/intel_cdclk.o \ > display/intel_cmtg.o \ > display/intel_color.o \ > diff --git a/drivers/gpu/drm/i915/display/intel_casf.c b/drivers/gpu/drm/i915/display/intel_casf.c > new file mode 100644 > index 000000000000..79a59e768c32 > --- /dev/null > +++ b/drivers/gpu/drm/i915/display/intel_casf.c > @@ -0,0 +1,102 @@ > +// SPDX-License-Identifier: MIT > +/* > + * Copyright © 2025 Intel Corporation > + * > + */ > + > +#include > + > +#include "i915_reg.h" > +#include "intel_casf.h" > +#include "intel_casf_regs.h" > +#include "intel_de.h" > +#include "intel_display_types.h" > + > +#define MAX_PIXELS_FOR_3_TAP_FILTER (1920 * 1080) > +#define MAX_PIXELS_FOR_5_TAP_FILTER (3840 * 2160) > + > +/** > + * DOC: Content Adaptive Sharpness Filter (CASF) > + * > + * Starting from LNL the display engine supports an > + * adaptive sharpening filter, enhancing the image > + * quality. The display hardware utilizes one of the > + * pipe scaler for implementing CASF. > + * This filter operates on a region of pixels based > + * on the tap size. Coefficients are used to generate > + * an alpha value which blends the sharpened image to > + * original image. > + */ > + > +void intel_casf_update_strength(struct intel_crtc_state *crtc_state) > +{ > + struct intel_display *display = to_intel_display(crtc_state); > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > + > + intel_de_rmw(display, SHARPNESS_CTL(crtc->pipe), 0, > + FILTER_STRENGTH(crtc_state->hw.casf_params.strength)); Need to clear FILTER_SIZE_MASK instead of passing 0. Regards, Ankit > +} > + > +static void intel_casf_compute_win_size(struct intel_crtc_state *crtc_state) > +{ > + const struct drm_display_mode *mode = &crtc_state->hw.adjusted_mode; > + u16 total_pixels = mode->hdisplay * mode->vdisplay; > + > + if (total_pixels <= MAX_PIXELS_FOR_3_TAP_FILTER) > + crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_3X3; > + else if (total_pixels <= MAX_PIXELS_FOR_5_TAP_FILTER) > + crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_5X5; > + else > + crtc_state->hw.casf_params.win_size = SHARPNESS_FILTER_SIZE_7X7; > +} > + > +int intel_casf_compute_config(struct intel_crtc_state *crtc_state) > +{ > + struct intel_display *display = to_intel_display(crtc_state); > + > + if (!HAS_CASF(display)) > + return 0; > + > + if (crtc_state->uapi.sharpness_strength == 0) { > + crtc_state->hw.casf_params.casf_enable = false; > + crtc_state->hw.casf_params.strength = 0; > + return 0; > + } > + > + crtc_state->hw.casf_params.casf_enable = true; > + > + /* > + * HW takes a value in form (1.0 + strength) in 4.4 fixed format. > + * Strength is from 0.0-14.9375 ie from 0-239. > + * User can give value from 0-255 but is clamped to 239. > + * Ex. User gives 85 which is 5.3125 and adding 1.0 gives 6.3125. > + * 6.3125 in 4.4 format is b01100101 which is equal to 101. > + * Also 85 + 16 = 101. > + */ > + crtc_state->hw.casf_params.strength = > + min(crtc_state->uapi.sharpness_strength, 0xEF) + 0x10; > + > + intel_casf_compute_win_size(crtc_state); > + > + return 0; > +} > + > +void intel_casf_sharpness_get_config(struct intel_crtc_state *crtc_state) > +{ > + struct intel_display *display = to_intel_display(crtc_state); > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > + u32 sharp; > + > + sharp = intel_de_read(display, SHARPNESS_CTL(crtc->pipe)); > + if (sharp & FILTER_EN) { > + if (drm_WARN_ON(display->drm, > + REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp) < 16)) > + crtc_state->hw.casf_params.strength = 0; > + else > + crtc_state->hw.casf_params.strength = > + REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp); > + crtc_state->hw.casf_params.casf_enable = true; > + crtc_state->hw.casf_params.win_size = > + REG_FIELD_GET(FILTER_SIZE_MASK, sharp); > + } > +} > diff --git a/drivers/gpu/drm/i915/display/intel_casf.h b/drivers/gpu/drm/i915/display/intel_casf.h > new file mode 100644 > index 000000000000..83523fe66c48 > --- /dev/null > +++ b/drivers/gpu/drm/i915/display/intel_casf.h > @@ -0,0 +1,17 @@ > +/* SPDX-License-Identifier: MIT */ > +/* > + * Copyright © 2025 Intel Corporation > + */ > + > +#ifndef __INTEL_CASF_H__ > +#define __INTEL_CASF_H__ > + > +#include > + > +struct intel_crtc_state; > + > +int intel_casf_compute_config(struct intel_crtc_state *crtc_state); > +void intel_casf_update_strength(struct intel_crtc_state *new_crtc_state); > +void intel_casf_sharpness_get_config(struct intel_crtc_state *crtc_state); > + > +#endif /* __INTEL_CASF_H__ */ > diff --git a/drivers/gpu/drm/i915/display/intel_casf_regs.h b/drivers/gpu/drm/i915/display/intel_casf_regs.h > new file mode 100644 > index 000000000000..c24ba281ae37 > --- /dev/null > +++ b/drivers/gpu/drm/i915/display/intel_casf_regs.h > @@ -0,0 +1,22 @@ > +/* SPDX-License-Identifier: MIT */ > +/* > + * Copyright © 2025 Intel Corporation > + */ > + > +#ifndef __INTEL_CASF_REGS_H__ > +#define __INTEL_CASF_REGS_H__ > + > +#include "intel_display_reg_defs.h" > + > +#define _SHARPNESS_CTL_A 0x682B0 > +#define _SHARPNESS_CTL_B 0x68AB0 > +#define SHARPNESS_CTL(pipe) _MMIO_PIPE(pipe, _SHARPNESS_CTL_A, _SHARPNESS_CTL_B) > +#define FILTER_EN REG_BIT(31) > +#define FILTER_STRENGTH_MASK REG_GENMASK(15, 8) > +#define FILTER_STRENGTH(x) REG_FIELD_PREP(FILTER_STRENGTH_MASK, (x)) > +#define FILTER_SIZE_MASK REG_GENMASK(1, 0) > +#define SHARPNESS_FILTER_SIZE_3X3 REG_FIELD_PREP(FILTER_SIZE_MASK, 0) > +#define SHARPNESS_FILTER_SIZE_5X5 REG_FIELD_PREP(FILTER_SIZE_MASK, 1) > +#define SHARPNESS_FILTER_SIZE_7X7 REG_FIELD_PREP(FILTER_SIZE_MASK, 2) > + > +#endif /* __INTEL_CASF_REGS__ */ > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h > index 367b53a9eae2..f920143920cd 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -931,6 +931,12 @@ struct intel_csc_matrix { > u16 postoff[3]; > }; > > +struct intel_casf { > + u8 strength; > + u8 win_size; > + bool casf_enable; > +}; > + > void intel_io_mmio_fw_write(void *ctx, i915_reg_t reg, u32 val); > > typedef void (*intel_io_reg_write)(void *ctx, i915_reg_t reg, u32 val); > @@ -971,6 +977,7 @@ struct intel_crtc_state { > struct drm_property_blob *degamma_lut, *gamma_lut, *ctm; > struct drm_display_mode mode, pipe_mode, adjusted_mode; > enum drm_scaling_filter scaling_filter; > + struct intel_casf casf_params; > } hw; > > /* actual state of LUTs */ > diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c > index ee81220a7c88..f0cf966211c9 100644 > --- a/drivers/gpu/drm/i915/display/skl_scaler.c > +++ b/drivers/gpu/drm/i915/display/skl_scaler.c > @@ -5,6 +5,7 @@ > > #include "i915_drv.h" > #include "i915_reg.h" > +#include "intel_casf_regs.h" > #include "intel_de.h" > #include "intel_display_trace.h" > #include "intel_display_types.h" > diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile > index 72eaadc4cbee..fb6d8e4edd91 100644 > --- a/drivers/gpu/drm/xe/Makefile > +++ b/drivers/gpu/drm/xe/Makefile > @@ -210,6 +210,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \ > i915-display/intel_backlight.o \ > i915-display/intel_bios.o \ > i915-display/intel_bw.o \ > + i915-display/intel_casf.o \ > i915-display/intel_cdclk.o \ > i915-display/intel_cmtg.o \ > i915-display/intel_color.o \