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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from DM4PR11MB5341.namprd11.prod.outlook.com (2603:10b6:5:390::22) by CH3PR11MB8384.namprd11.prod.outlook.com (2603:10b6:610:176::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9366.11; Fri, 28 Nov 2025 13:34:35 +0000 Received: from DM4PR11MB5341.namprd11.prod.outlook.com ([fe80::397:7566:d626:e839]) by DM4PR11MB5341.namprd11.prod.outlook.com ([fe80::397:7566:d626:e839%7]) with mapi id 15.20.9366.012; Fri, 28 Nov 2025 13:34:34 +0000 Message-ID: Date: Fri, 28 Nov 2025 19:04:27 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v9 10/17] drm/i915/vrr: Write DC balance params to hw registers To: Mitul Golani , CC: , References: <20251127091614.648791-1-mitulkumar.ajitkumar.golani@intel.com> <20251127091614.648791-11-mitulkumar.ajitkumar.golani@intel.com> Content-Language: en-US From: "Nautiyal, Ankit K" In-Reply-To: <20251127091614.648791-11-mitulkumar.ajitkumar.golani@intel.com> Content-Type: text/plain; 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(Ankit) > > --v3: > - Write registers at compute config. > - Update condition for write. > > --v4: > - Address issue with state checker. > > --v5: > - Initialise some more dc balance register while enabling VRR. > > --v6: > - FLIPLINE_CFG need to be configure at last, as it is double buffer > arming point. > > --v7: > - Initialise and reset live value of vmax and vmin as well. > > --v8: > - Add separate functions while writing hw registers. (Ankit) > > --v9: > - Add DC Balance counter enable bit to this patch. (Ankit) > > --v10: > - Add rigister writes to vrr_enable/disable. (Ankit) > > Signed-off-by: Mitul Golani Reviewed-by: Ankit Nautiyal > --- > drivers/gpu/drm/i915/display/intel_vrr.c | 76 ++++++++++++++++++++++++ > 1 file changed, 76 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c > index 411ae5da3824..11f06a5b854a 100644 > --- a/drivers/gpu/drm/i915/display/intel_vrr.c > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c > @@ -767,6 +767,80 @@ static void intel_vrr_set_vrr_timings(const struct intel_crtc_state *crtc_state) > intel_vrr_hw_flipline(crtc_state) - 1); > } > > +static void > +intel_vrr_enable_dc_balancing(const struct intel_crtc_state *crtc_state) > +{ > + struct intel_display *display = to_intel_display(crtc_state); > + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > + enum pipe pipe = crtc->pipe; > + > + if (!crtc_state->vrr.dc_balance.enable) > + return; > + > + intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG(cpu_transcoder), > + VRR_DCB_ADJ_VMAX(crtc_state->vrr.vmax - 1)); > + intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(cpu_transcoder), > + VRR_DCB_ADJ_VMAX(crtc_state->vrr.vmax - 1)); > + intel_de_write(display, TRANS_VRR_DCB_VMAX(cpu_transcoder), > + VRR_DCB_VMAX(crtc_state->vrr.vmax - 1)); > + intel_de_write(display, TRANS_VRR_DCB_VMAX_LIVE(cpu_transcoder), > + VRR_DCB_VMAX(crtc_state->vrr.vmax - 1)); > + intel_de_write(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder), > + VRR_DCB_FLIPLINE(crtc_state->vrr.flipline - 1)); > + intel_de_write(display, TRANS_VRR_DCB_FLIPLINE_LIVE(cpu_transcoder), > + VRR_DCB_FLIPLINE(crtc_state->vrr.flipline - 1)); > + intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(cpu_transcoder), > + VRR_DCB_ADJ_FLIPLINE(crtc_state->vrr.flipline - 1)); > + intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder), > + VRR_DCB_ADJ_FLIPLINE(crtc_state->vrr.flipline - 1)); > + intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), > + crtc_state->vrr.dc_balance.vmin - 1); > + intel_de_write(display, PIPEDMC_DCB_VMAX(pipe), > + crtc_state->vrr.dc_balance.vmax - 1); > + intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(pipe), > + crtc_state->vrr.dc_balance.max_increase); > + intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(pipe), > + crtc_state->vrr.dc_balance.max_decrease); > + intel_de_write(display, PIPEDMC_DCB_GUARDBAND(pipe), > + crtc_state->vrr.dc_balance.guardband); > + intel_de_write(display, PIPEDMC_DCB_SLOPE(pipe), > + crtc_state->vrr.dc_balance.slope); > + intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe), > + crtc_state->vrr.dc_balance.vblank_target); > + intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder), > + ADAPTIVE_SYNC_COUNTER_EN); > +} > + > +static void > +intel_vrr_disable_dc_balancing(const struct intel_crtc_state *old_crtc_state) > +{ > + struct intel_display *display = to_intel_display(old_crtc_state); > + enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; > + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); > + enum pipe pipe = crtc->pipe; > + > + if (!old_crtc_state->vrr.dc_balance.enable) > + return; > + > + intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder), 0); > + intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), 0); > + intel_de_write(display, PIPEDMC_DCB_VMAX(pipe), 0); > + intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(pipe), 0); > + intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(pipe), 0); > + intel_de_write(display, PIPEDMC_DCB_GUARDBAND(pipe), 0); > + intel_de_write(display, PIPEDMC_DCB_SLOPE(pipe), 0); > + intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe), 0); > + intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(cpu_transcoder), 0); > + intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(cpu_transcoder), 0); > + intel_de_write(display, TRANS_VRR_DCB_VMAX_LIVE(cpu_transcoder), 0); > + intel_de_write(display, TRANS_VRR_DCB_FLIPLINE_LIVE(cpu_transcoder), 0); > + intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG(cpu_transcoder), 0); > + intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder), 0); > + intel_de_write(display, TRANS_VRR_DCB_VMAX(cpu_transcoder), 0); > + intel_de_write(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder), 0); > +} > + > static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state, > bool cmrr_enable) > { > @@ -813,6 +887,7 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state) > return; > > intel_vrr_set_vrr_timings(crtc_state); > + intel_vrr_enable_dc_balancing(crtc_state); > > if (!intel_vrr_always_use_vrr_tg(display)) > intel_vrr_tg_enable(crtc_state, crtc_state->cmrr.enable); > @@ -828,6 +903,7 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) > if (!intel_vrr_always_use_vrr_tg(display)) > intel_vrr_tg_disable(old_crtc_state); > > + intel_vrr_disable_dc_balancing(old_crtc_state); > intel_vrr_set_fixed_rr_timings(old_crtc_state); > } >