Re: [PATCH 12/19] drm/i915/display: PSR2: Set idle_frames to 0 for DC3CO

Dibin Moolakadan Subrahmanian
2026-04-22T14:38:14Z

On 14-04-2026 03:26, Shankar, Uma wrote:
>
>> -----Original Message-----
>> From: Dibin Moolakadan Subrahmanian
>> <dibin.moolakadan.subrahmanian@intel.com>
>> Sent: Thursday, March 26, 2026 10:46 PM
>> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
>> Cc: Manna, Animesh <animesh.manna@intel.com>; Shankar, Uma
>> <uma.shankar@intel.com>; Kurmi, Suresh Kumar
>> <suresh.kumar.kurmi@intel.com>
>> Subject: [PATCH 12/19] drm/i915/display: PSR2: Set idle_frames to 0 for DC3CO
>>
>> Force idle_frames to 0 when DC3CO is eligible.
>>
>> BSpec: 75253
>> Signed-off-by: Dibin Moolakadan Subrahmanian
>> <dibin.moolakadan.subrahmanian@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_psr.c | 9 ++++++---
>> 1 file changed, 6 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
>> b/drivers/gpu/drm/i915/display/intel_psr.c
>> index bab254700a62..16a9f4111ac8 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>> @@ -1040,10 +1040,13 @@ static void hsw_activate_psr2(struct intel_dp
>> *intel_dp)
>> u32 psr_val = 0;
>> u8 idle_frames;
>>
>> + /* DC3CO requires idle_frames = 0 */
>> + if (intel_dp->psr.dc3co_eligible)
>> + idle_frames = 0;
>> /* Wa_16025596647 */
>> - if ((DISPLAY_VER(display) == 20 ||
>> - IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0))
>> &&
>> - is_dc5_dc6_blocked(intel_dp) && intel_dp->psr.pkg_c_latency_used)
>> + else if ((DISPLAY_VER(display) == 20 ||
>> + IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0,
>> STEP_B0)) &&
>> + is_dc5_dc6_blocked(intel_dp) && intel_dp-
>>> psr.pkg_c_latency_used)
>> idle_frames = 0;
> This condition itself can be extended instead of a new if block.

I will add dc3co condition to the existing block.

>
>> else
>> idle_frames = psr_compute_idle_frames(intel_dp);
>> --
>> 2.43.0