Re: [PATCH 02/19] drm/i915/display: Replace DC_STATE_EN_DC3CO with DC_STATE_EN_UPTO_DC3CO

Dibin Moolakadan Subrahmanian
2026-04-20T12:04:28Z

On 14-04-2026 02:21, Shankar, Uma wrote:
>
>> -----Original Message-----
>> From: Dibin Moolakadan Subrahmanian
>> <dibin.moolakadan.subrahmanian@intel.com>
>> Sent: Thursday, March 26, 2026 10:46 PM
>> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
>> Cc: Manna, Animesh <animesh.manna@intel.com>; Shankar, Uma
>> <uma.shankar@intel.com>; Kurmi, Suresh Kumar
>> <suresh.kumar.kurmi@intel.com>
>> Subject: [PATCH 02/19] drm/i915/display: Replace DC_STATE_EN_DC3CO with
>> DC_STATE_EN_UPTO_DC3CO
> Nit: Patch header can be re-phrased "Switch DC3Co enable from standalone bit to DC level encoding"
>
> Changes look Good to me.
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>

I will update the patch header as suggested.

>> On platforms prior to xe3, DC3CO was controlled via a standalone enable bit.
>> Starting with xe3 DC3CO is encoded as part of the existing
>> DC_STATE_EN_UPTO_DC* field.
>>
>> No functional change, as DC3CO is not enabled on platforms prior to xe3.
>>
>> Signed-off-by: Dibin Moolakadan Subrahmanian
>> <dibin.moolakadan.subrahmanian@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_display_power.c | 6 +++---
>> drivers/gpu/drm/i915/display/intel_display_power_well.c | 4 ++--
>> drivers/gpu/drm/i915/display/intel_display_regs.h | 2 +-
>> drivers/gpu/drm/i915/display/intel_dmc_wl.c | 2 +-
>> 4 files changed, 7 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
>> b/drivers/gpu/drm/i915/display/intel_display_power.c
>> index ec96b141c74c..0afae5c2f62b 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> @@ -267,7 +267,7 @@ sanitize_target_dc_state(struct intel_display *display,
>> static const u32 states[] = {
>> DC_STATE_EN_UPTO_DC6,
>> DC_STATE_EN_UPTO_DC5,
>> - DC_STATE_EN_DC3CO,
>> + DC_STATE_EN_UPTO_DC3CO,
>> DC_STATE_DISABLE,
>> };
>> int i;
>> @@ -999,10 +999,10 @@ static u32 get_allowed_dc_mask(struct intel_display
>> *display, int enable_dc)
>>
>> switch (requested_dc) {
>> case 4:
>> - mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6;
>> + mask |= DC_STATE_EN_UPTO_DC3CO |
>> DC_STATE_EN_UPTO_DC6;
>> break;
>> case 3:
>> - mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC5;
>> + mask |= DC_STATE_EN_UPTO_DC3CO |
>> DC_STATE_EN_UPTO_DC5;
>> break;
>> case 2:
>> mask |= DC_STATE_EN_UPTO_DC6;
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> b/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> index 6d5f07f7f590..9a948f5e2164 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> @@ -773,7 +773,7 @@ static u32 gen9_dc_mask(struct intel_display *display)
>> mask = DC_STATE_EN_UPTO_DC5;
>>
>> if (DISPLAY_VER(display) >= 12)
>> - mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6
>> + mask |= DC_STATE_EN_UPTO_DC3CO |
>> DC_STATE_EN_UPTO_DC6
>> | DC_STATE_EN_DC9;
>> else if (DISPLAY_VER(display) == 11)
>> mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
>> @@ -1023,7 +1023,7 @@ static void bxt_verify_dpio_phy_power_wells(struct
>> intel_display *display) static bool gen9_dc_off_power_well_enabled(struct
>> intel_display *display,
>> struct i915_power_well *power_well) {
>> - return ((intel_de_read(display, DC_STATE_EN) &
>> DC_STATE_EN_DC3CO) == 0 &&
>> + return ((intel_de_read(display, DC_STATE_EN) &
>> DC_STATE_EN_UPTO_DC3CO)
>> +== 0 &&
>> (intel_de_read(display, DC_STATE_EN) &
>> DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0); }
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h
>> b/drivers/gpu/drm/i915/display/intel_display_regs.h
>> index 5838338f495a..d0196d4ad234 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
>> @@ -3044,13 +3044,13 @@ enum skl_power_gate {
>> /* GEN9 DC */
>> #define DC_STATE_EN _MMIO(0x45504)
>> #define DC_STATE_DISABLE 0
>> -#define DC_STATE_EN_DC3CO REG_BIT(30)
>> #define DC_STATE_DC3CO_STATUS REG_BIT(29)
>> #define HOLD_PHY_CLKREQ_PG1_LATCH REG_BIT(21)
>> #define HOLD_PHY_PG1_LATCH REG_BIT(20)
>> #define DC_STATE_EN_UPTO_DC5 (1 << 0)
>> #define DC_STATE_EN_DC9 (1 << 3)
>> #define DC_STATE_EN_UPTO_DC6 (2 << 0)
>> +#define DC_STATE_EN_UPTO_DC3CO (3 << 0)
>> #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3
>>
>> #define DC_STATE_DEBUG _MMIO(0x45520)
>> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
>> b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
>> index 73a3101514f3..9f403b7820ab 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
>> @@ -260,7 +260,7 @@ static bool intel_dmc_wl_check_range(struct intel_display
>> *display,
>> * the DMC and requires a DC exit for proper access.
>> */
>> switch (dc_state) {
>> - case DC_STATE_EN_DC3CO:
>> + case DC_STATE_EN_UPTO_DC3CO:
>> ranges = xe3lpd_dc3co_dmc_ranges;
>> break;
>> case DC_STATE_EN_UPTO_DC5:
>> --
>> 2.43.0