[PATCH 04/19] drm/i915/display: Add DC3CO DC_STATE enable/disable support

Dibin Moolakadan Subrahmanian
2026-03-26T17:15:24Z

Add DC3CO handling to the dc_off power well sequencing and disable the
DMC wakelock when exiting DC3CO.

BSpec:75253
Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
---
.../drm/i915/display/intel_display_power_well.c | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 9a948f5e2164..cb3dcd1460b2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -867,6 +867,13 @@ void gen9_set_dc_state(struct intel_display *display, u32 state)
power_domains->dc_state = val & mask;
}

+static void xe3lpd_enable_dc3co(struct intel_display *display)
+{
+ drm_dbg_kms(display->drm, "Enabling DC3CO\n");
+ intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC3CO);
+ gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC3CO);
+}
+
static void assert_can_enable_dc5(struct intel_display *display)
{
enum i915_power_well_id high_pg;
@@ -1055,9 +1062,13 @@ void gen9_disable_dc_states(struct intel_display *display)
}

if (old_state == DC_STATE_EN_UPTO_DC5 ||
- old_state == DC_STATE_EN_UPTO_DC6)
+ old_state == DC_STATE_EN_UPTO_DC6 ||
+ old_state == DC_STATE_EN_UPTO_DC3CO)
intel_dmc_wl_disable(display);

+ if (old_state == DC_STATE_EN_UPTO_DC3CO)
+ return;
+
intel_cdclk_get_cdclk(display, &cdclk_config);
/* Can't read out voltage_level so can't use intel_cdclk_changed() */
drm_WARN_ON(display->drm,
@@ -1093,6 +1104,9 @@ static void gen9_dc_off_power_well_disable(struct intel_display *display,
return;

switch (power_domains->target_dc_state) {
+ case DC_STATE_EN_UPTO_DC3CO:
+ xe3lpd_enable_dc3co(display);
+ break;
case DC_STATE_EN_UPTO_DC6:
skl_enable_dc6(display);
break;
--
2.43.0