RE: [PATCH 11/19] drm/i915/display: Store DC3CO eligibility in PSR state

Shankar, Uma
2026-04-13T21:54:54Z

> -----Original Message-----
> From: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> Sent: Thursday, March 26, 2026 10:46 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Manna, Animesh <animesh.manna@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>; Kurmi, Suresh Kumar
> <suresh.kumar.kurmi@intel.com>
> Subject: [PATCH 11/19] drm/i915/display: Store DC3CO eligibility in PSR state
>
> Store DC3CO eligibility in intel_dp->psr during
> intel_psr_post_plane_update() so PSR configuration can take DC3CO into
> account.
>
> This will be used to control PSR2 parameters such as idle frames
>
> Signed-off-by: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display_types.h | 2 ++
> drivers/gpu/drm/i915/display/intel_psr.c | 5 +++++
> 2 files changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 0a327c4df98d..d0d2cda3d669 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1783,6 +1783,8 @@ struct intel_psr {
> ktime_t last_exit;
> bool sink_not_reliable;
> bool irq_aux_error;
> + /* DC3CO eligibility used to control PSR configuration */
> + bool dc3co_eligible;
> u16 su_w_granularity;
> u16 su_y_granularity;
> bool source_panel_replay_support;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 987d49536548..bab254700a62 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -2239,6 +2239,8 @@ static void intel_psr_disable_locked(struct intel_dp
> *intel_dp)
> intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
> intel_dp->psr.active_non_psr_pipes = 0;
> intel_dp->psr.pkg_c_latency_used = 0;
> + intel_dp->psr.dc3co_eligible = false;
> +

Drop the blank line.

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> }
>
> /**
> @@ -3061,6 +3063,9 @@ void intel_psr_post_plane_update(struct
> intel_atomic_state *state,
> */
> intel_dp->psr.busy_frontbuffer_bits = 0;
>
> + intel_dp->psr.dc3co_eligible = intel_dc3co_allowed(state) &&
> + intel_display_power_dc3co_supported(display);
> +
> mutex_unlock(&psr->lock);
> }
> }
> --
> 2.43.0