RE: [PATCH 16/19] drm/i915/display: Add helper to enable DC counter

Shankar, Uma
2026-04-13T22:14:17Z

> -----Original Message-----
> From: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> Sent: Thursday, March 26, 2026 10:46 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Manna, Animesh <animesh.manna@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>; Kurmi, Suresh Kumar
> <suresh.kumar.kurmi@intel.com>
> Subject: [PATCH 16/19] drm/i915/display: Add helper to enable DC counter
>
> Add xe3lpd_enable_dc_count() to enable the DC_COUNT_EN register.
> Also define DC_STATE_DC3CO_RESIDENCY to read DC3CO residency.
> Needed to retrieve DC residency for DC3CO.

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display_power_well.c | 5 +++++
> drivers/gpu/drm/i915/display/intel_display_power_well.h | 1 +
> drivers/gpu/drm/i915/display/intel_display_regs.h | 5 +++++
> drivers/gpu/drm/i915/display/intel_dmc.c | 3 +++
> 4 files changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index cb3dcd1460b2..15521442e6d4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -867,6 +867,11 @@ void gen9_set_dc_state(struct intel_display *display,
> u32 state)
> power_domains->dc_state = val & mask;
> }
>
> +void xe3lpd_enable_dc_count(struct intel_display *display) {
> + intel_de_write(display, DC_COUNT_EN,
> DC_COUNT_EN_COUNTER_ENABLE); }
> +
> static void xe3lpd_enable_dc3co(struct intel_display *display) {
> drm_dbg_kms(display->drm, "Enabling DC3CO\n"); diff --git
> a/drivers/gpu/drm/i915/display/intel_display_power_well.h
> b/drivers/gpu/drm/i915/display/intel_display_power_well.h
> index 8f5524da2d06..0ce64b894436 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
> @@ -159,6 +159,7 @@ void gen9_set_dc_state(struct intel_display *display, u32
> state); void gen9_disable_dc_states(struct intel_display *display); void
> bxt_enable_dc9(struct intel_display *display); void bxt_disable_dc9(struct
> intel_display *display);
> +void xe3lpd_enable_dc_count(struct intel_display *display);
>
> extern const struct i915_power_well_ops i9xx_always_on_power_well_ops;
> extern const struct i915_power_well_ops chv_pipe_power_well_ops; diff --git
> a/drivers/gpu/drm/i915/display/intel_display_regs.h
> b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 2bace331437c..8b59e1ff2590 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -3058,6 +3058,11 @@ enum skl_power_gate {
> #define DC_STATE_DEBUG_MASK_CORES (1 << 0)
> #define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1)
>
> +#define DC_COUNT_EN _MMIO(0x457B4)
> +#define DC_COUNT_EN_COUNTER_ENABLE REG_BIT(31)
> +
> +#define DC_STATE_DC3CO_RESIDENCY _MMIO(0x457B8)
> +
> #define D_COMP_BDW _MMIO(0x138144)
>
> /* Pipe WM_LINETIME - watermark line time */ diff --git
> a/drivers/gpu/drm/i915/display/intel_dmc.c
> b/drivers/gpu/drm/i915/display/intel_dmc.c
> index 90ba932d940a..74d18806d01f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -937,6 +937,9 @@ void intel_dmc_load_program(struct intel_display
> *display)
>
> gen9_set_dc_state_debugmask(display);
>
> + if (DISPLAY_VER(display) >= 35)
> + xe3lpd_enable_dc_count(display);
> +
> pipedmc_clock_gating_wa(display, false); }
>
> --
> 2.43.0