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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from DM4PR11MB5341.namprd11.prod.outlook.com (2603:10b6:5:390::22) by SA3PR11MB7556.namprd11.prod.outlook.com (2603:10b6:806:31f::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9298.7; Wed, 5 Nov 2025 04:24:24 +0000 Received: from DM4PR11MB5341.namprd11.prod.outlook.com ([fe80::397:7566:d626:e839]) by DM4PR11MB5341.namprd11.prod.outlook.com ([fe80::397:7566:d626:e839%7]) with mapi id 15.20.9253.013; Wed, 5 Nov 2025 04:24:24 +0000 Message-ID: Date: Wed, 5 Nov 2025 09:54:18 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [RESEND, 05/22] drm/i915/vrr: Add DC Balance params to crtc_state To: Mitul Golani , CC: , , References: <20251103053002.3002695-1-mitulkumar.ajitkumar.golani@intel.com> <20251103053002.3002695-6-mitulkumar.ajitkumar.golani@intel.com> Content-Language: en-US From: "Nautiyal, Ankit K" In-Reply-To: <20251103053002.3002695-6-mitulkumar.ajitkumar.golani@intel.com> Content-Type: text/plain; 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(Ankit) > > --v4: > - Update commit message and header. (Ankit) > - Add +1 to VMIN and VMAX only when it is non-zero. (Ankit) > > --v5: > - Add headers in sorted order. (Jani Nikula) > > Signed-off-by: Mitul Golani > Reviewed-by: Ankit Nautiyal > --- > drivers/gpu/drm/i915/display/intel_display.c | 7 ++++++ > .../drm/i915/display/intel_display_types.h | 7 ++++++ > drivers/gpu/drm/i915/display/intel_vrr.c | 22 +++++++++++++++++++ > 3 files changed, 36 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 42ec78798666..a00625f882e8 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -5470,6 +5470,13 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, > PIPE_CONF_CHECK_LLI(cmrr.cmrr_m); > PIPE_CONF_CHECK_LLI(cmrr.cmrr_n); > PIPE_CONF_CHECK_BOOL(cmrr.enable); > + PIPE_CONF_CHECK_I(vrr.dc_balance.vmin); > + PIPE_CONF_CHECK_I(vrr.dc_balance.vmax); > + PIPE_CONF_CHECK_I(vrr.dc_balance.guardband); > + PIPE_CONF_CHECK_I(vrr.dc_balance.slope); > + PIPE_CONF_CHECK_I(vrr.dc_balance.max_increase); > + PIPE_CONF_CHECK_I(vrr.dc_balance.max_decrease); > + PIPE_CONF_CHECK_I(vrr.dc_balance.vblank_target); > } > > if (!fastset || intel_vrr_always_use_vrr_tg(display)) { > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h > index 00600134bda0..33fb70716110 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -1358,6 +1358,13 @@ struct intel_crtc_state { > u8 pipeline_full; > u16 flipline, vmin, vmax, guardband; > u32 vsync_end, vsync_start; > + struct { > + bool enable; > + u16 vmin, vmax; > + u16 guardband, slope; > + u16 max_increase, max_decrease; > + u16 vblank_target; > + } dc_balance; > } vrr; > > /* Content Match Refresh Rate state */ > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c > index 68dde96583c0..3c30c8d3e206 100644 > --- a/drivers/gpu/drm/i915/display/intel_vrr.c > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c > @@ -9,6 +9,7 @@ > #include "intel_de.h" > #include "intel_display_regs.h" > #include "intel_display_types.h" > +#include "intel_dmc_regs.h" > #include "intel_dp.h" > #include "intel_psr.h" > #include "intel_vrr.h" > @@ -789,6 +790,8 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) > { > struct intel_display *display = to_intel_display(crtc_state); > enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > + enum pipe pipe = crtc->pipe; > u32 trans_vrr_ctl, trans_vrr_vsync; > bool vrr_enable; > > @@ -866,6 +869,25 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) > else > crtc_state->vrr.enable = vrr_enable; > > + if (HAS_VRR_DC_BALANCE(display)) { > + crtc_state->vrr.dc_balance.vmin = > + intel_de_read(display, PIPEDMC_DCB_VMIN(pipe)) ? > + intel_de_read(display, PIPEDMC_DCB_VMIN(pipe)) + 1 : 0; Instead of reading it twice, can we just use a temp variable: reg = intel_de_read(display, PIPEDMC_DCB_VMIN(pipe)) ; crtc_state->vrr.dc_balance.vmin = reg ? reg + 1 :0; reg = intel_de_read(display, PIPEDMC_DCB_VMAX(pipe)) ; crtc_state->vrr.dc_balance.vmax = reg ? reg + 1 :0; Regards, Ankit > + crtc_state->vrr.dc_balance.vmax = > + intel_de_read(display, PIPEDMC_DCB_VMAX(pipe)) ? > + intel_de_read(display, PIPEDMC_DCB_VMAX(pipe)) + 1 : 0; > + crtc_state->vrr.dc_balance.guardband = > + intel_de_read(display, PIPEDMC_DCB_GUARDBAND(pipe)); > + crtc_state->vrr.dc_balance.max_increase = > + intel_de_read(display, PIPEDMC_DCB_MAX_INCREASE(pipe)); > + crtc_state->vrr.dc_balance.max_decrease = > + intel_de_read(display, PIPEDMC_DCB_MAX_DECREASE(pipe)); > + crtc_state->vrr.dc_balance.slope = > + intel_de_read(display, PIPEDMC_DCB_SLOPE(pipe)); > + crtc_state->vrr.dc_balance.vblank_target = > + intel_de_read(display, PIPEDMC_DCB_VBLANK(pipe)); > + } > + > /* > * #TODO: For Both VRR and CMRR the flag I915_MODE_FLAG_VRR is set for mode_flags. > * Since CMRR is currently disabled, set this flag for VRR for now.