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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from DM4PR11MB5341.namprd11.prod.outlook.com (2603:10b6:5:390::22) by SA3PR11MB7556.namprd11.prod.outlook.com (2603:10b6:806:31f::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9298.7; Wed, 5 Nov 2025 04:15:52 +0000 Received: from DM4PR11MB5341.namprd11.prod.outlook.com ([fe80::397:7566:d626:e839]) by DM4PR11MB5341.namprd11.prod.outlook.com ([fe80::397:7566:d626:e839%7]) with mapi id 15.20.9253.013; Wed, 5 Nov 2025 04:15:52 +0000 Message-ID: Date: Wed, 5 Nov 2025 09:45:45 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [RESEND, 02/22] drm/i915/dmc: Add pipe dmc registers and bits for DC Balance To: Mitul Golani , CC: , , References: <20251103053002.3002695-1-mitulkumar.ajitkumar.golani@intel.com> <20251103053002.3002695-3-mitulkumar.ajitkumar.golani@intel.com> Content-Language: en-US From: "Nautiyal, Ankit K" In-Reply-To: <20251103053002.3002695-3-mitulkumar.ajitkumar.golani@intel.com> Content-Type: text/plain; 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(Ankit) > - Use MMIO pipe macros instead of transcoder ones. (Ankit) > - Remove dev_priv use. (Jani, Nikula) > > --v3: > - Add all register address, from capital alphabet to small. (Ankit) > - Add EVT CTL registers. > - Add co-author tag. > - Add event flag for Triggering DC Balance. > > --v4: > - Add DCB Flip count and balance reset registers. > > Co-authored-by: Mitul Golani > Signed-off-by: Ville Syrjälä > Signed-off-by: Mitul Golani > Reviewed-by: Ankit Nautiyal > --- > drivers/gpu/drm/i915/display/intel_dmc_regs.h | 61 ++++++++++++++++++- > 1 file changed, 60 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h > index c5aa49921cb9..225dbe3ac137 100644 > --- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h > @@ -583,5 +583,64 @@ enum pipedmc_event_id { > /* undocumented magic DMC variables */ > #define PTL_PIPEDMC_EXEC_TIME_LINES(start_mmioaddr) _MMIO((start_mmioaddr) + 0x6b8) > #define PTL_PIPEDMC_END_OF_EXEC_GB(start_mmioaddr) _MMIO((start_mmioaddr) + 0x6c0) > - > +#define _PIPEDMC_DCB_CTL_A 0x5f1a0 > +#define _PIPEDMC_DCB_CTL_B 0x5f5a0 > +#define PIPEDMC_DCB_CTL(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_CTL_A,\ > + _PIPEDMC_DCB_CTL_B) > +#define PIPEDMC_ADAPTIVE_DCB_ENABLE REG_BIT(31) Missed to point this out earlier, quoting fromi915_reg.h : Indent the register content macros using two extra spaces between ``#define`` and the macro name. > + > +#define _PIPEDMC_DCB_VBLANK_A 0x5f1bc > +#define _PIPEDMC_DCB_VBLANK_B 0x5f5bc > +#define PIPEDMC_DCB_VBLANK(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_VBLANK_A,\ > + _PIPEDMC_DCB_VBLANK_B) > + > +#define _PIPEDMC_DCB_SLOPE_A 0x5f1b8 > +#define _PIPEDMC_DCB_SLOPE_B 0x5f5b8 > +#define PIPEDMC_DCB_SLOPE(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_SLOPE_A,\ > + _PIPEDMC_DCB_SLOPE_B) > + > +#define _PIPEDMC_DCB_GUARDBAND_A 0x5f1b4 > +#define _PIPEDMC_DCB_GUARDBAND_B 0x5f5b4 > +#define PIPEDMC_DCB_GUARDBAND(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_GUARDBAND_A,\ > + _PIPEDMC_DCB_GUARDBAND_B) > + > +#define _PIPEDMC_DCB_MAX_INCREASE_A 0x5f1ac > +#define _PIPEDMC_DCB_MAX_INCREASE_B 0x5f5ac > +#define PIPEDMC_DCB_MAX_INCREASE(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_MAX_INCREASE_A,\ > + _PIPEDMC_DCB_MAX_INCREASE_B) > + > +#define _PIPEDMC_DCB_MAX_DECREASE_A 0x5f1b0 > +#define _PIPEDMC_DCB_MAX_DECREASE_B 0x5f5b0 > +#define PIPEDMC_DCB_MAX_DECREASE(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_MAX_DECREASE_A,\ > + _PIPEDMC_DCB_MAX_DECREASE_B) > + > +#define _PIPEDMC_DCB_VMIN_A 0x5f1a4 > +#define _PIPEDMC_DCB_VMIN_B 0x5f5a4 > +#define PIPEDMC_DCB_VMIN(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_VMIN_A,\ > + _PIPEDMC_DCB_VMIN_B) > + > +#define _PIPEDMC_DCB_VMAX_A 0x5f1a8 > +#define _PIPEDMC_DCB_VMAX_B 0x5f5a8 > +#define PIPEDMC_DCB_VMAX(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_VMAX_A,\ > + _PIPEDMC_DCB_VMAX_B) > + > +#define _PIPEDMC_DCB_DEBUG_A 0x5f1c0 > +#define _PIPEDMC_DCB_DEBUG_B 0x5f5c0 > +#define PIPEDMC_DCB_DEBUG(pipe) _MMIO_PIPE(pipe, _PIPEDMC_DCB_DEBUG_A,\ > + _PIPEDMC_DCB_DEBUG_B) > + > +#define _PIPEDMC_EVT_CTL_3_A 0x5f040 > +#define _PIPEDMC_EVT_CTL_3_B 0x5f440 > +#define PIPEDMC_EVT_CTL_3(pipe) _MMIO_PIPE(pipe, _PIPEDMC_EVT_CTL_3_A,\ > + _PIPEDMC_EVT_CTL_3_B) > + > +#define _PIPEDMC_DCB_FLIP_COUNT_A 0x906A4 > +#define _PIPEDMC_DCB_FLIP_COUNT_B 0x986A4 > +#define PIPEDMC_DCB_FLIP_COUNT(pipe) _MMIO_PIPE(pipe, _PIPEDMC_EVT_CTL_3_A,\ > + _PIPEDMC_DCB_FLIP_COUNT_B) This doesn’t seem to be right. Regards, Ankit > + > +#define _PIPEDMC_DCB_BALANCE_RESET_A 0x906A8 > +#define _PIPEDMC_DCB_BALANCE_RESET_B 0x986A8 > +#define PIPEDMC_DCB_BALANCE_RESET(pipe) _MMIO_PIPE(pipe, _PIPEDMC_DCB_BALANCE_RESET_A,\ > + _PIPEDMC_DCB_BALANCE_RESET_B) > #endif /* __INTEL_DMC_REGS_H__ */