From: sashiko-bot@kernel.org
To: "Nareshkumar Gollakoti" <naresh.kumar.g@intel.com>
Cc: intel-xe@lists.freedesktop.org
Subject: Re: [PATCH v4 6/7] drm/xe: capture L3 node status registers in devcoredump
Date: Mon, 12 Oct 2026 15:06:00 +0000 [thread overview]
Message-ID: <sashiko-outbox-168313@kernel.org> (raw)
In-Reply-To: <20261012145237.3788198-7-naresh.kumar.g@intel.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] drm/xe: NULL pointer dereference of q in devcoredump_snapshot()
--
commit 6161ac10e80fa8c54c67e54542cd9c6bcb0ef507
Author: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
drm/xe: capture L3 node status registers in devcoredump
This commit adds L3_NODE_IDLE and L3STAT_LBCF_GFX registers and captures
them in the devcoredump snapshot. It also extends the register descriptor
to support reading MCR registers.
> diff --git a/drivers/gpu/drm/xe/xe_devcoredump.c b/drivers/gpu/drm/xe/xe_devcoredump.c
> index a2a3437ec2f62..db7ccee12006a 100644
> --- a/drivers/gpu/drm/xe/xe_devcoredump.c
> +++ b/drivers/gpu/drm/xe/xe_devcoredump.c
[ ... ]
> @@ -639,13 +663,15 @@ static void devcoredump_snapshot(struct xe_devcoredump *coredump,
> other_gt,
> XE_DBG_REGSET_GAM_PF,
> XE_GT_TYPE_MAIN);
> -
> + ss->ns = xe_dbg_gt_snapshot_capture(q->gt,
> + other_gt,
> + XE_DBG_REGSET_L3_NODE,
> + XE_GT_TYPE_MAIN);
[Severity: High]
If q is NULL, will accessing q->gt cause a NULL pointer dereference here?
When a devcoredump is triggered for a GT-level hang not tied to an exec queue
(such as a TLB invalidation timeout via xe_devcoredump_gt()), q can be NULL,
which is why the code immediately below checks if (q).
Should this capture use the gt parameter that is passed into
devcoredump_snapshot() instead of q->gt, or should it be moved inside the
if (q) block?
> if (q) {
> ss->ge = xe_guc_exec_queue_snapshot_capture(q);
> if (job)
> ss->job = xe_sched_job_snapshot_capture(job);
> ss->vm = xe_vm_snapshot_capture(q->vm);
> -
> xe_engine_snapshot_capture_for_queue(q);
> }
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261012145237.3788198-1-naresh.kumar.g@intel.com?part=6
next prev parent reply other threads:[~2026-10-12 15:06 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-12 14:52 [PATCH v4 0/7] drm/xe: Capture additional HW register state in devcoredump Nareshkumar Gollakoti
2026-10-12 14:52 ` [PATCH v4 1/7] drm/xe/devcoredump: Capture GT fuse registers " Nareshkumar Gollakoti
2026-10-12 15:02 ` sashiko-bot
2026-10-12 14:52 ` [PATCH v4 2/7] drm/xe/devcoredump: Add GuC register snapshot to devcoredump Nareshkumar Gollakoti
2026-10-12 15:03 ` sashiko-bot
2026-10-12 14:52 ` [PATCH v4 3/7] drm/xe/guc: Print register addresses in capture snapshot output Nareshkumar Gollakoti
2026-10-12 14:52 ` [PATCH v4 4/7] drm/xe: dump GAM page fault report registers in devcoredump Nareshkumar Gollakoti
2026-10-12 15:02 ` sashiko-bot
2026-10-12 14:52 ` [PATCH v4 5/7] drm/xe/guc: add TDL, SLICE gfx registers to capture list Nareshkumar Gollakoti
2026-10-12 14:52 ` [PATCH v4 6/7] drm/xe: capture L3 node status registers in devcoredump Nareshkumar Gollakoti
2026-10-12 15:06 ` sashiko-bot [this message]
2026-10-12 14:52 ` [PATCH v4 7/7] drm/xe/guc: capture additional engine state registers Nareshkumar Gollakoti
2026-10-12 15:07 ` sashiko-bot
2026-10-12 18:56 ` ✗ CI.checkpatch: warning for drm/xe: Capture additional HW register state in devcoredump (rev4) Patchwork
2026-10-12 18:58 ` ✓ CI.KUnit: success " Patchwork
2026-10-12 22:04 ` ✓ Xe.CI.BAT: " Patchwork
2026-10-13 4:36 ` ✓ Xe.CI.FULL: " Patchwork
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