From: sashiko-bot@kernel.org
To: "Suraj Kandpal" <suraj.kandpal@intel.com>,
intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Subject: Re: [PATCH v6 02/11] drm/i915/dp: Limit M/N ratio for DP
Date: Wed, 21 Oct 2026 07:40:43 +0000 [thread overview]
Message-ID: <sashiko-outbox-179922@kernel.org> (raw)
In-Reply-To: <20261021072438.1164249-3-suraj.kandpal@intel.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] drm/i915/dp: misordered M/N ratio filter in intel_dp_compute_config_limits()
--
commit 46d07c1bdb22b62954414e63e1d33e15eab315fb
Author: Suraj Kandpal <suraj.kandpal@intel.com>
drm/i915/dp: Limit M/N ratio for DP
This commit restricts DisplayPort link configurations to those whose ceiling
Link M/Link N ratio fits within the transcoder timing generator limit during
link config limit computation, and prunes modes in mode_valid when no link
configuration can satisfy the ratio.
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index d8c0d9381471d..7ceb7c02b597b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
[ ... ]
> @@ -2656,6 +2725,48 @@ intel_dp_dsc_compute_pipe_bpp_limits(struct intel_connector *connector,
> return true;
> }
>
> +static bool
> +intel_dp_compute_m_n_ratio_limits(struct intel_dp *intel_dp,
> + struct drm_connector_state *conn_state,
> + const struct intel_crtc_state *crtc_state,
> + struct link_config_limits *limits)
> +{
> + struct intel_display *display = to_intel_display(intel_dp);
> + struct intel_connector *connector = to_intel_connector(conn_state->connector);
> + struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
> + struct intel_dp_link_caps_order order =
> + intel_dp_link_caps_connector_compute_order(connector);
> + struct intel_dp_link_caps_filter new_filter = INTEL_DP_LINK_CAPS_FILTER_NONE;
> + int pixel_clock = intel_dp_mso_pixel_clock(intel_dp,
> + intel_dp_mode_clock(crtc_state, conn_state));
> + struct intel_dp_link_config link_config;
> + struct intel_dp_link_caps_iter iter;
> + bool found = false;
> +
> + intel_dp_link_caps_iter_start(&iter, link_caps, order, limits->link_config_filter);
> + for_each_dp_link_config(&iter, &link_config) {
> + if (!intel_dp_can_support_m_n(display, pixel_clock, link_config.rate))
> + continue;
> +
> + intel_dp_link_caps_filter_add(link_caps, &new_filter, &link_config);
> + found = true;
> + }
> + intel_dp_link_caps_iter_end(&iter);
> +
> + if (!found) {
> + drm_dbg_kms(display->drm,
> + "[CONNECTOR:%d:%s] No link config with a Link M/N ratio <= %d\n",
> + connector->base.base.id, connector->base.name,
> + intel_dp_get_max_m_n_ratio(display));
> +
> + return false;
> + }
> +
> + limits->link_config_filter = new_filter;
> +
> + return true;
> +}
> +
> bool
> intel_dp_compute_config_limits(struct intel_dp *intel_dp,
> struct drm_connector_state *conn_state,
> @@ -2772,6 +2883,9 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
> limits->link_config_filter = new_filter;
> }
>
> + if (!intel_dp_compute_m_n_ratio_limits(intel_dp, conn_state, crtc_state, limits))
> + return false;
> +
> if (!intel_dp_test_compute_config(connector, crtc_state, limits))
> return false;
>
[Severity: Medium]
Should intel_dp_compute_m_n_ratio_limits() be called earlier in
intel_dp_compute_config_limits() in drivers/gpu/drm/i915/display/intel_dp.c,
and should intel_dp_test_compute_config() also run before or intersect with
that filter?
Right before the new intel_dp_compute_m_n_ratio_limits() call,
intel_dp_compute_config_limits() narrows limits->link_config_filter to a
single max_config when is_mst or intel_dp->use_max_params is set:
drivers/gpu/drm/i915/display/intel_dp.c:intel_dp_compute_config_limits() {
...
if (is_mst || intel_dp->use_max_params) {
struct intel_dp_link_caps_filter new_filter = INTEL_DP_LINK_CAPS_FILTER_NONE;
struct intel_dp_link_config max_config;
...
if (!intel_dp_get_connector_max_link_config(connector, limits, &max_config))
return false;
if (!intel_dp_link_caps_filter_add(link_caps, &new_filter, &max_config))
return false;
limits->link_config_filter = new_filter;
}
if (!intel_dp_compute_m_n_ratio_limits(intel_dp, conn_state, crtc_state, limits))
return false;
if (!intel_dp_test_compute_config(connector, crtc_state, limits))
return false;
...
}
Because the link symbol clock is not monotonic with link rate or bandwidth
(e.g., 128b/132b rates divide by 32 while 8b/10b rates divide by 10),
intel_dp_get_connector_max_link_config() can pick a high-rate configuration
with a lower symbol clock that violates intel_dp_can_support_m_n(), even
when a lower link rate in link_caps has a higher symbol clock that satisfies
the ratio.
Since limits->link_config_filter has already been restricted to that single
max_config before intel_dp_compute_m_n_ratio_limits() runs, won't
intel_dp_compute_m_n_ratio_limits() fail the modeset instead of allowing
intel_dp_get_connector_max_link_config() to select the highest configuration
among those that satisfy the ratio?
Conversely, intel_dp_test_compute_config() runs immediately after
intel_dp_compute_m_n_ratio_limits(). When a compliance link training request
is active, intel_dp_test_compute_config() -> set_filter_for_link_params() ->
set_filter_for_link_config() in drivers/gpu/drm/i915/display/intel_dp_test.c
replaces limits->link_config_filter with a fresh filter built from link_caps:
drivers/gpu/drm/i915/display/intel_dp_test.c:set_filter_for_link_config() {
struct intel_dp_link_caps_filter new_filter = INTEL_DP_LINK_CAPS_FILTER_NONE;
if (!intel_dp_link_caps_filter_add(link_caps, &new_filter, link_params))
return false;
limits->link_config_filter = new_filter;
return true;
}
Won't that overwrite and discard the filter computed by
intel_dp_compute_m_n_ratio_limits()?
[ ... ]
>
>
>
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261021072438.1164249-1-suraj.kandpal@intel.com?part=2
next prev parent reply other threads:[~2026-10-21 7:40 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-21 7:24 [PATCH v6 00/11] Implement Wa_14021768792 to bypass m_n ratio limit Suraj Kandpal
2026-10-21 7:24 ` [PATCH v6 01/11] drm/i915/display: Add helper to compute link M/N ratio for reuse Suraj Kandpal
2026-10-21 7:24 ` [PATCH v6 02/11] drm/i915/dp: Limit M/N ratio for DP Suraj Kandpal
2026-10-21 7:40 ` sashiko-bot [this message]
2026-10-21 7:24 ` [PATCH v6 03/11] drm/i915/display_wa: Add support for Wa_14014191401 Suraj Kandpal
2026-10-21 7:24 ` [PATCH v6 04/11] drm/i915/dp_mst: Limit M/N ratio for MST Suraj Kandpal
2026-10-21 7:24 ` [PATCH v6 05/11] drm/i915/dp: Add M/N ratio check for DP link config Suraj Kandpal
2026-10-21 17:02 ` Golani, Mitulkumar Ajitkumar
2026-10-22 2:49 ` Kandpal, Suraj
2026-10-21 7:24 ` [PATCH v6 06/11] drm/i915/display: Add bits for link_n_extended for DISPLAY >= 14 Suraj Kandpal
2026-10-21 7:24 ` [PATCH v6 07/11] drm/i915/display_wa: Add support for Wa_14021768792 Suraj Kandpal
2026-10-21 7:24 ` [PATCH v6 08/11] drm/i915/display: Add bits for Wa_14021768792 for linkm/n ratio > 10 Suraj Kandpal
2026-10-21 16:56 ` Golani, Mitulkumar Ajitkumar
2026-10-22 2:42 ` Kandpal, Suraj
2026-10-21 7:24 ` [PATCH v6 09/11] drm/i915/display: Implement Wa_14021768792 for BMG DP for link_m/n " Suraj Kandpal
2026-10-21 16:31 ` Golani, Mitulkumar Ajitkumar
2026-10-21 7:24 ` [PATCH v6 10/11] drm/i915/dp: Extend intel_dp_can_support_m_n() for BMG M/N bypass Suraj Kandpal
2026-10-21 7:24 ` [PATCH v6 11/11] drm/i915/dp: Bump the max Link M/N ratio to 22 for DISPLAY_VER >= 35 Suraj Kandpal
2026-10-21 7:33 ` ✓ CI.KUnit: success for Implement Wa_14021768792 to bypass m_n ratio limit (rev10) Patchwork
2026-10-21 8:11 ` ✓ Xe.CI.BAT: " Patchwork
2026-10-21 11:17 ` ✗ Xe.CI.FULL: failure " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2026-09-17 5:06 [PATCH v4 00/10] Implement Wa_14021768792 to bypass m_n ratio limit Suraj Kandpal
2026-10-21 7:13 ` [PATCH v6 00/11] " Suraj Kandpal
2026-10-21 7:13 ` [PATCH v6 02/11] drm/i915/dp: Limit M/N ratio for DP Suraj Kandpal
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