From mboxrd@z Thu Jan 1 00:00:00 1970 From: Vinod Koul Date: Tue, 18 Oct 2016 13:48:44 +0000 Subject: Re: [patch] ASoC: Intel: Skylake: Fix a shift wrapping bug Message-Id: <20161018135606.GV2467@localhost> List-Id: References: <20161013085548.GK16198@mwanda> In-Reply-To: <20161013085548.GK16198@mwanda> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: Dan Carpenter Cc: Liam Girdwood , Dharageswari R , Mark Brown , Jaroslav Kysela , Takashi Iwai , Shreyas NC , Senthilnathan Veppur , Ramesh Babu , Colin Ian King , alsa-devel@alsa-project.org, kernel-janitors@vger.kernel.org, Kranthi G On Thu, Oct 13, 2016 at 11:55:48AM +0300, Dan Carpenter wrote: > "*val" is a u64. It definitely looks like we intend to use the high 32 > bits as well. > > Fixes: 700a9a63f9c1 ("ASoC: Intel: Skylake: Add module instance id generation APIs") > Signed-off-by: Dan Carpenter Acked-by: Vinod Koul Tested-by: Kranthi G -- ~Vinod