From: "Valdis Klētnieks" <valdis.kletnieks@vt.edu>
To: Wonhyuk Yang <vvghjk1234@gmail.com>
Cc: kernelnewbies <kernelnewbies@kernelnewbies.org>
Subject: Re: arm64: Question about barriers with the mmu off
Date: Mon, 16 Nov 2020 21:14:28 -0500 [thread overview]
Message-ID: <213088.1605579268@turing-police> (raw)
In-Reply-To: <CAEcHRTre6z_16yLrpr-_m+mjeY4ZHCNzx=DQEhRnbhftM5sf-g@mail.gmail.com>
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On Mon, 16 Nov 2020 20:58:52 +0900, Wonhyuk Yang said:
> str w0, [x1]
So we dirtied the cache line.
> dmb sys
> dc ivac, x1 // Invalidate potentially stale cache line
So we invalidate it.
> Is there any problem, if the dc operation precedes the store operation?
If you swap them, you get...
dc ivac,x1 // invalidate a cache line that's probably OK
str w0,[x1 // and now we do a store that leaves a possibly stale cache line
In other words, if you swap them you may leave an un-invalidated
stale cache line.
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next prev parent reply other threads:[~2020-11-17 2:15 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-16 11:58 arm64: Question about barriers with the mmu off Wonhyuk Yang
2020-11-17 2:14 ` Valdis Klētnieks [this message]
2020-11-17 3:00 ` Wonhyuk Yang
2020-11-17 3:45 ` Valdis Klētnieks
2020-11-17 5:08 ` Wonhyuk Yang
2020-11-17 6:25 ` Valdis Klētnieks
2020-11-18 0:53 ` Wonhyuk Yang
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