From: "Valdis Klētnieks" <valdis.kletnieks@vt.edu>
To: Wonhyuk Yang <vvghjk1234@gmail.com>
Cc: kernelnewbies <kernelnewbies@kernelnewbies.org>
Subject: Re: arm64: Question about barriers with the mmu off
Date: Mon, 16 Nov 2020 22:45:21 -0500 [thread overview]
Message-ID: <218162.1605584721@turing-police> (raw)
In-Reply-To: <CAEcHRTqfaKHy1rky2N1U6idogTWnYEC33-HUV4Uk=bNBQDp1Bg@mail.gmail.com>
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On Tue, 17 Nov 2020 12:00:32 +0900, Wonhyuk Yang said:
> > If you swap them, you get...
> >
> > dc ivac,x1 // invalidate a cache line that's probably OK
> > str w0,[x1 // and now we do a store that leaves a possibly stale cache line
> >
> > In other words, if you swap them you may leave an un-invalidated
> > stale cache line.
>
> You mean, even if STCLR_EL1.{C, M} is cleared, store doesn't bypass the
> cache?
That's the problem. The store bypasses the cache line, and the next reference
that uses the cache can get stale data. So you have to flush the cache line
so the next reference has to refresh the cache on the memory read.
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next prev parent reply other threads:[~2020-11-17 3:46 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-16 11:58 arm64: Question about barriers with the mmu off Wonhyuk Yang
2020-11-17 2:14 ` Valdis Klētnieks
2020-11-17 3:00 ` Wonhyuk Yang
2020-11-17 3:45 ` Valdis Klētnieks [this message]
2020-11-17 5:08 ` Wonhyuk Yang
2020-11-17 6:25 ` Valdis Klētnieks
2020-11-18 0:53 ` Wonhyuk Yang
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