From: "Valdis Klētnieks" <valdis.kletnieks@vt.edu>
To: Wonhyuk Yang <vvghjk1234@gmail.com>
Cc: kernelnewbies <kernelnewbies@kernelnewbies.org>
Subject: Re: arm64: Question about barriers with the mmu off
Date: Tue, 17 Nov 2020 01:25:55 -0500 [thread overview]
Message-ID: <227506.1605594355@turing-police> (raw)
In-Reply-To: <CAEcHRTrE7Hyp=M2p6n8pHQOVAK9OVGp6JCLN7rKVhCSOvKLr6Q@mail.gmail.com>
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On Tue, 17 Nov 2020 14:08:02 +0900, Wonhyuk Yang said:
> > > > dc ivac,x1 // invalidate a cache line that's probably OK
> > > > str w0,[x1 // and now we do a store that leaves a possibly stale cache line
> Could you explain me why the store still leaves stale cache?
> We invalidated the cacheline and store will not make footprint in the cache.
There's a race condition...
Invalidate the cache line.... then another CPU manages to fetch the cache line.
and then we do a store that doesn't update the cache - and the other CPU
is still looking at the old data.
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next prev parent reply other threads:[~2020-11-17 6:27 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-16 11:58 arm64: Question about barriers with the mmu off Wonhyuk Yang
2020-11-17 2:14 ` Valdis Klētnieks
2020-11-17 3:00 ` Wonhyuk Yang
2020-11-17 3:45 ` Valdis Klētnieks
2020-11-17 5:08 ` Wonhyuk Yang
2020-11-17 6:25 ` Valdis Klētnieks [this message]
2020-11-18 0:53 ` Wonhyuk Yang
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