cache policy of arm mmu

cache policy of arm mmu

[Jacky lin]

Hi all,

I found that the cache policy in after ARMv6 is always set as writeback
mode in mmu.c.

static int __init early_cachepolicy(char *p)
{
   ...
    if (cpu_architecture() >= CPU_ARCH_ARMv6) {
        printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6
and later\n");
        cachepolicy = CPOLICY_WRITEBACK;
    }
   ...
}

Does anyone know why and provide some documents or links for that?

Thanks so much!

Cheers,
Jacky
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cache policy of arm mmu

[Cunsuo Guo]

Hi Jacky?
I think the information of printk has already tell us the reason.

2012/5/29 Jacky lin <h.t.jacky@gmail.com>:
> Hi all,
>
> I found that the cache policy in after ARMv6 is always set as writeback mode
> in mmu.c.
>
> static int __init early_cachepolicy(char *p)
> {
>    ...
>     if (cpu_architecture() >= CPU_ARCH_ARMv6) {
>         printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6
> and later\n");
>         cachepolicy = CPOLICY_WRITEBACK;
>     }
>    ...
> }
>
> Does anyone know why and provide some documents or links for that?
>
> Thanks so much!
>
> Cheers,
> Jacky
>
> _______________________________________________
> Kernelnewbies mailing list
> Kernelnewbies at kernelnewbies.org
> http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
>

Re: cache policy of arm mmu

[h.t.jacky]

Hi Cunsuo,

Thanks for you prompt reply.
But I'm just wondering why the other policies(such as writethrough) are abandoned, does anyone know the architecture difference? 

Cheers,
Jacky
Sent from my HTC

----- Reply message -----
From: "Cunsuo Guo" <cunsuo.guo@gmail.com>
To: "Jacky lin" <h.t.jacky@gmail.com>
Cc: <kernelnewbies@kernelnewbies.org>
Subject: cache policy of arm mmu
Date: Tue, May 29, 2012 09:10


Hi Jacky?
I think the information of printk has already tell us the reason.

2012/5/29 Jacky lin <h.t.jacky@gmail.com>:
> Hi all,
>
> I found that the cache policy in after ARMv6 is always set as writeback mode
> in mmu.c.
>
> static int __init early_cachepolicy(char *p)
> {
>    ...
>     if (cpu_architecture() >= CPU_ARCH_ARMv6) {
>         printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6
> and later\n");
>         cachepolicy = CPOLICY_WRITEBACK;
>     }
>    ...
> }
>
> Does anyone know why and provide some documents or links for that?
>
> Thanks so much!
>
> Cheers,
> Jacky
>
> _______________________________________________
> Kernelnewbies mailing list
> Kernelnewbies at kernelnewbies.org
> http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
>
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cache policy of arm mmu

[Arun KS]

Hello Jacky,

On Tue, May 29, 2012 at 10:09 AM, h.t.jacky at gmail.com
<h.t.jacky@gmail.com> wrote:
> Hi Cunsuo,
>
> Thanks for you prompt reply.
> But I'm just wondering why the other policies(such as writethrough) are
> abandoned, does anyone know the architecture difference?

They are not abandoned from architecture.

If you do a git log -p on arch/arm/mm/mmu.c, this is what we get.

commit 4b46d6416548fb6a0940dfd9911fd895eb6247b3
Author: Russell King <rmk+kernel@arm.linux.org.uk>
Date:   Sun Nov 1 17:44:24 2009 +0000

    ARM: ensure initial page tables are setup for SMP systems

    Mapping the same memory using two different attributes (memory
    type, shareability, cacheability) is unpredictable.  During boot,
    we encounter a situation when we're updating the kernel's page
    tables which can lead to dirty cache lines existing in the cache
    which are subsequently missed.  This causes stack corruption,
    and therefore a crash.

    Therefore, ensure that the shared and cacheability settings
    matches the configuration that will be used later; this together
    with the restriction in early_cachepolicy() ensures that we won't
    create a mismatch during boot.

    Acked-by: Catalin Marinas <catalin.marinas@arm.com>
    Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 02243ee..ea67be0 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -117,6 +117,13 @@ static void __init early_cachepolicy(char **p)
        }
        if (i == ARRAY_SIZE(cache_policies))
                printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
+       /*
+        * This restriction is partly to do with the way we boot; it is
+        * unpredictable to have memory mapped using two different sets of
+        * memory attributes (shared, type, and cache attribs).  We can not
+        * change these attributes once the initial assembly has setup the
+        * page tables.
+        */
        if (cpu_architecture() >= CPU_ARCH_ARMv6) {
                printk(KERN_WARNING "Only cachepolicy=writeback
supported on ARMv6 and later\n");
                cachepolicy = CPOLICY_WRITEBACK;

Thanks,
Arun
>
> Cheers,
> Jacky
> Sent from my HTC
>
>
> ----- Reply message -----
> From: "Cunsuo Guo" <cunsuo.guo@gmail.com>
> To: "Jacky lin" <h.t.jacky@gmail.com>
> Cc: <kernelnewbies@kernelnewbies.org>
> Subject: cache policy of arm mmu
> Date: Tue, May 29, 2012 09:10
>
>
> Hi Jacky?
> I think the information of printk has already tell us the reason.
>
> 2012/5/29 Jacky lin <h.t.jacky@gmail.com>:
>> Hi all,
>>
>> I found that the cache policy in after ARMv6 is always set as writeback
>> mode
>> in mmu.c.
>>
>> static int __init early_cachepolicy(char *p)
>> {
>> ? ?...
>> ? ? if (cpu_architecture() >= CPU_ARCH_ARMv6) {
>> ? ? ? ? printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6
>> and later\n");
>> ? ? ? ? cachepolicy = CPOLICY_WRITEBACK;
>> ? ? }
>> ? ?...
>> }
>>
>> Does anyone know why and provide some documents or links for that?
>>
>> Thanks so much!
>>
>> Cheers,
>> Jacky
>>
>> _______________________________________________
>> Kernelnewbies mailing list
>> Kernelnewbies at kernelnewbies.org
>> http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
>>
>
> _______________________________________________
> Kernelnewbies mailing list
> Kernelnewbies at kernelnewbies.org
> http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
>

cache policy of arm mmu

[Jacky lin]

Dear Arus,

Thanks for your reply, well I checked this commit you mentioned as
following:
But I still could not get a clue about where the cache policy is set
outside mmu.c.
So do you know if I put the "cachepolicy=writethrough" in cmd line, where
will that be parsed?
Thanks a lot!

diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 02243ee..ea67be0 100644
Author: Russell King <rmk+kernel@arm.linux.org.uk>
Date:   Sun Nov 1 17:44:24 2009 +0000

    ARM: ensure initial page tables are setup for SMP systems

    Mapping the same memory using two different attributes (memory
    type, shareability, cacheability) is unpredictable.  During boot,
    we encounter a situation when we're updating the kernel's page
    tables which can lead to dirty cache lines existing in the cache
    which are subsequently missed.  This causes stack corruption,
    and therefore a crash.

    Therefore, ensure that the shared and cacheability settings
    matches the configuration that will be used later; this together
    with the restriction in early_cachepolicy() ensures that we won't
    create a mismatch during boot.

    Acked-by: Catalin Marinas <catalin.marinas@arm.com>
    Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 02243ee..ea67be0 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -117,6 +117,13 @@ static void __init early_cachepolicy(char **p)
        }
        if (i == ARRAY_SIZE(cache_policies))
                printk(KERN_ERR "ERROR: unknown or unsupported cache
policy\n");
+       /*
+        * This restriction is partly to do with the way we boot; it is
+        * unpredictable to have memory mapped using two different sets of
+        * memory attributes (shared, type, and cache attribs).  We can not
+        * change these attributes once the initial assembly has setup the
+        * page tables.
+        */
        if (cpu_architecture() >= CPU_ARCH_ARMv6) {
                printk(KERN_WARNING "Only cachepolicy=writeback supported
on ARMv6 and later\n");
                cachepolicy = CPOLICY_WRITEBACK;
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 194737d..70f75d2 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -32,8 +32,10 @@

 #ifndef CONFIG_SMP
 #define TTB_FLAGS      TTB_RGN_WBWA
+#define PMD_FLAGS      PMD_SECT_WB
 #else
 #define TTB_FLAGS      TTB_RGN_WBWA|TTB_S
+#define PMD_FLAGS      PMD_SECT_WBWA|PMD_SECT_S
 #endif

 ENTRY(cpu_v6_proc_init)
@@ -222,10 +224,9 @@ __v6_proc_info:
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -32,8 +32,10 @@

 #ifndef CONFIG_SMP
 #define TTB_FLAGS      TTB_RGN_WBWA
@@ -32,8 +32,10 @@

 #ifndef CONFIG_SMP
 #define TTB_FLAGS      TTB_RGN_WBWA
+#define PMD_FLAGS      PMD_SECT_WB
 #else
 #define TTB_FLAGS      TTB_RGN_WBWA|TTB_S
+#define PMD_FLAGS      PMD_SECT_WBWA|PMD_SECT_S
 #endif

 ENTRY(cpu_v6_proc_init)
@@ -222,10 +224,9 @@ __v6_proc_info:
        .long   0x0007b000
        .long   0x0007f000
        .long   PMD_TYPE_SECT | \
-               PMD_SECT_BUFFERABLE | \
-               PMD_SECT_CACHEABLE | \
                PMD_SECT_AP_WRITE | \
-               PMD_SECT_AP_READ
+               PMD_SECT_AP_READ | \
+               PMD_FLAGS
        .long   PMD_TYPE_SECT | \
                PMD_SECT_XN | \
                PMD_SECT_AP_WRITE | \
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 23ebcf6..eeeed01 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -33,9 +33,11 @@
 #ifndef CONFIG_SMP
 /* PTWs cacheable, inner WB not shareable, outer WB not shareable */
 #define TTB_FLAGS      TTB_IRGN_WB|TTB_RGN_OC_WB
+#define PMD_FLAGS      PMD_SECT_WB
 #else
 /* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
 #define TTB_FLAGS      TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
+#define PMD_FLAGS      PMD_SECT_WBWA|PMD_SECT_S
 #endif

 ENTRY(cpu_v7_proc_init)
@@ -326,10 +328,9 @@ __v7_proc_info:
        .long   0x000f0000              @ Required ID value
        .long   0x000f0000              @ Mask for ID
        .long   PMD_TYPE_SECT | \
-               PMD_SECT_BUFFERABLE | \
-               PMD_SECT_CACHEABLE | \
                PMD_SECT_AP_WRITE | \
-               PMD_SECT_AP_READ
+               PMD_SECT_AP_READ | \
+               PMD_FLAGS
        .long   PMD_TYPE_SECT | \
                PMD_SECT_XN | \
                PMD_SECT_AP_WRITE | \

Cheers,
Jacky
On Tue, May 29, 2012 at 6:07 PM, Arun KS <getarunks@gmail.com> wrote:

> Hello Jacky,
>
> On Tue, May 29, 2012 at 10:09 AM, h.t.jacky at gmail.com
> <h.t.jacky@gmail.com> wrote:
> > Hi Cunsuo,
> >
> > Thanks for you prompt reply.
> > But I'm just wondering why the other policies(such as writethrough) are
> > abandoned, does anyone know the architecture difference?
>
> They are not abandoned from architecture.
>
> If you do a git log -p on arch/arm/mm/mmu.c, this is what we get.
>
> commit 4b46d6416548fb6a0940dfd9911fd895eb6247b3
> Author: Russell King <rmk+kernel@arm.linux.org.uk>
> Date:   Sun Nov 1 17:44:24 2009 +0000
>
>    ARM: ensure initial page tables are setup for SMP systems
>
>    Mapping the same memory using two different attributes (memory
>    type, shareability, cacheability) is unpredictable.  During boot,
>    we encounter a situation when we're updating the kernel's page
>    tables which can lead to dirty cache lines existing in the cache
>    which are subsequently missed.  This causes stack corruption,
>    and therefore a crash.
>
>    Therefore, ensure that the shared and cacheability settings
>    matches the configuration that will be used later; this together
>    with the restriction in early_cachepolicy() ensures that we won't
>    create a mismatch during boot.
>
>    Acked-by: Catalin Marinas <catalin.marinas@arm.com>
>    Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
>
> diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
> index 02243ee..ea67be0 100644
> --- a/arch/arm/mm/mmu.c
> +++ b/arch/arm/mm/mmu.c
> @@ -117,6 +117,13 @@ static void __init early_cachepolicy(char **p)
>        }
>        if (i == ARRAY_SIZE(cache_policies))
>                printk(KERN_ERR "ERROR: unknown or unsupported cache
> policy\n");
> +       /*
> +        * This restriction is partly to do with the way we boot; it is
> +        * unpredictable to have memory mapped using two different sets of
> +        * memory attributes (shared, type, and cache attribs).  We can not
> +        * change these attributes once the initial assembly has setup the
> +        * page tables.
> +        */
>         if (cpu_architecture() >= CPU_ARCH_ARMv6) {
>                printk(KERN_WARNING "Only cachepolicy=writeback
> supported on ARMv6 and later\n");
>                cachepolicy = CPOLICY_WRITEBACK;
>
> Thanks,
> Arun
> >
> > Cheers,
> > Jacky
> > Sent from my HTC
> >
> >
> > ----- Reply message -----
> > From: "Cunsuo Guo" <cunsuo.guo@gmail.com>
> > To: "Jacky lin" <h.t.jacky@gmail.com>
> > Cc: <kernelnewbies@kernelnewbies.org>
> > Subject: cache policy of arm mmu
> > Date: Tue, May 29, 2012 09:10
> >
> >
> > Hi Jacky?
> > I think the information of printk has already tell us the reason.
> >
> > 2012/5/29 Jacky lin <h.t.jacky@gmail.com>:
> >> Hi all,
> >>
> >> I found that the cache policy in after ARMv6 is always set as writeback
> >> mode
> >> in mmu.c.
> >>
> >> static int __init early_cachepolicy(char *p)
> >> {
> >>    ...
> >>     if (cpu_architecture() >= CPU_ARCH_ARMv6) {
> >>         printk(KERN_WARNING "Only cachepolicy=writeback supported on
> ARMv6
> >> and later\n");
> >>         cachepolicy = CPOLICY_WRITEBACK;
> >>     }
> >>    ...
> >> }
> >>
> >> Does anyone know why and provide some documents or links for that?
> >>
> >> Thanks so much!
> >>
> >> Cheers,
> >> Jacky
> >>
> >> _______________________________________________
> >> Kernelnewbies mailing list
> >> Kernelnewbies at kernelnewbies.org
> >> http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
> >>
> >
> > _______________________________________________
> > Kernelnewbies mailing list
> > Kernelnewbies at kernelnewbies.org
> > http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
> >
>
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