* returned dma address value of dma_alloc_coherent, is it always in the lower 4GB range?
@ 2023-03-13 12:28 Chan Kim
2023-03-14 5:14 ` Valdis Klētnieks
0 siblings, 1 reply; 3+ messages in thread
From: Chan Kim @ 2023-03-13 12:28 UTC (permalink / raw)
To: kernelnewbies
Hello experts,
I was reading the well known DMA-API-HOWTO document
(https://www.kernel.org/doc/Documentation/DMA-API-HOWTO.txt),
(I've read this document a couple of times before in the past.)
In the " Using Consistent DMA mappings" section it says :
-----------------------------
dma_addr_t dma_handle;
cpu_addr = dma_alloc_coherent(dev, size, &dma_handle, gfp);
...
The consistent DMA mapping interfaces, will by default return a DMA address
which is 32-bit addressable. Even if the device indicates (via the DMA
mask)
that it may address the upper 32-bits, consistent allocation will only
return > 32-bit addresses for DMA if the consistent DMA mask has been
explicitly changed via dma_set_coherent_mask(). This is true of the
dma_pool interface as well.
------------------------------
I understand by 'DMA address', it means dma_handle (the address the device
will use for DMA).
I can't understand the expression "consistent allocation will only return >
32-bit addresses".
Does it mean that when the driver sets the coherent_dma_mask, for example,
to DMA_BIT_MAST(64) and it was successful, does it return the dma_handle in
lower 32 bit address? What does "return > 32-bit addresses" mean? The ">"
syntax here is so obscure with no clear definition of usage.
By context I guess it returns the address in lower 32bit address range even
it the coherent_dma_mask is set to some bigger value.
(And I know generally, dma address(= bus address) is not equal to the
physical address and is assigned by the OS for convenience)
Thank you.
Chan Kim
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^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: returned dma address value of dma_alloc_coherent, is it always in the lower 4GB range?
2023-03-13 12:28 returned dma address value of dma_alloc_coherent, is it always in the lower 4GB range? Chan Kim
@ 2023-03-14 5:14 ` Valdis Klētnieks
2023-03-14 8:03 ` Chan Kim
0 siblings, 1 reply; 3+ messages in thread
From: Valdis Klētnieks @ 2023-03-14 5:14 UTC (permalink / raw)
To: Chan Kim; +Cc: kernelnewbies
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On Mon, 13 Mar 2023 21:28:28 +0900, "Chan Kim" said:
> which is 32-bit addressable. Even if the device indicates (via the DMA
> mask)
> that it may address the upper 32-bits, consistent allocation will only
> return > 32-bit addresses for DMA if the consistent DMA mask has been
> explicitly changed via dma_set_coherent_mask(). This is true of the
> dma_pool interface as well.
> ------------------------------
> By context I guess it returns the address in lower 32bit address range even
> it the coherent_dma_mask is set to some bigger value.
No, you have that backwards. It's not "even if". It wil give you a 32-bit
address *UNLESS* the driver has called dma_set_coherent_mask() to set a wider
mask *and* the device indicates it supports more than 32 bit addresses...
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* RE: returned dma address value of dma_alloc_coherent, is it always in the lower 4GB range?
2023-03-14 5:14 ` Valdis Klētnieks
@ 2023-03-14 8:03 ` Chan Kim
0 siblings, 0 replies; 3+ messages in thread
From: Chan Kim @ 2023-03-14 8:03 UTC (permalink / raw)
To: 'Valdis Klētnieks'; +Cc: kernelnewbies
Hello Valdis,
>-----Original Message-----
>From: Valdis Kletnieks <valdis@vt.edu> On Behalf Of Valdis Kl?tnieks
>Sent: Tuesday, March 14, 2023 2:15 PM
>To: Chan Kim <ckim@etri.re.kr>
>Cc: kernelnewbies@kernelnewbies.org
>Subject: Re: returned dma address value of dma_alloc_coherent, is it always
>in the lower 4GB range?
>
>On Mon, 13 Mar 2023 21:28:28 +0900, "Chan Kim" said:
>
>> which is 32-bit addressable. Even if the device indicates (via the
>> DMA
>> mask)
>> that it may address the upper 32-bits, consistent allocation will only
>> return > 32-bit addresses for DMA if the consistent DMA mask has been
>> explicitly changed via dma_set_coherent_mask(). This is true of the
>> dma_pool interface as well.
>> ------------------------------
>
>> By context I guess it returns the address in lower 32bit address range
>> even it the coherent_dma_mask is set to some bigger value.
>
>No, you have that backwards. It's not "even if". It wil give you a
32-bit
>address *UNLESS* the driver has called dma_set_coherent_mask() to set a
>wider mask *and* the device indicates it supports more than 32 bit
>addresses...
I'm sorry but please allow me to ask one more time.
1. "The consistent DMA mapping interfaces, will by default return a DMA
address
which is 32-bit addressable."
==> so by default consistent dma mapping API returns 32-bit address, and
this 32-bit address means dma address, not physical address. Am I correct?
(because the dma address will be translated to physical address by the iommu
anyway)
2. " Even if the device indicates (via the DMA mask)
that it may address the upper 32-bits, consistent allocation will only
return > 32-bit addresses for DMA if the consistent DMA mask has been
explicitly changed via dma_set_coherent_mask(). This is true of the
dma_pool interface as well."
==> So I now understand the first 'even if' is for streaming dma mask
('dma_mask' in the struct device), and the second 'if' is for the
'coherent_dma_mask' in the struct device. And when coherent_dma_mask is not
set, by default, the coherent mapping returns 32 bit address, but if the
coherent_dma_mask is set to use wider than 32 bit addresses, it returns the
wider address which seems obvious now.
Please correct me if I'm wrong.
Thank you!
Chan Kim
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2023-03-13 12:28 returned dma address value of dma_alloc_coherent, is it always in the lower 4GB range? Chan Kim
2023-03-14 5:14 ` Valdis Klētnieks
2023-03-14 8:03 ` Chan Kim
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