From mboxrd@z Thu Jan 1 00:00:00 1970 From: gprabhunath@gmail.com (Prabhu nath) Date: Mon, 27 Jun 2011 16:45:18 +0530 Subject: Basic HighMeM Question In-Reply-To: References: Message-ID: To: kernelnewbies@lists.kernelnewbies.org List-Id: kernelnewbies.lists.kernelnewbies.org On Mon, Jun 27, 2011 at 3:58 PM, Paraneetharan Chandrasekaran < paraneetharanc@gmail.com> wrote: > > > On 27 June 2011 14:58, Prabhu nath wrote: > >> Please see inline. >> >> On Mon, Jun 27, 2011 at 2:42 PM, piyush moghe wrote: >> >>> I have very basic some question's related to HighMem Memory Mapping: >>> >>> 1) Why can't we directly map memory in highmemory? >>> >> This question is incorrect ? Typically on a intel architecture, >> the physical address space is divided into LOWMEM and HIGHMEM region. Lower >> 896 MB is marked as LOWMEM region and >896MB as HIGHMEM. More likely in the >> intel architecture the memory is always decoded from 0x00000000. For Eg. If >> you have memory of 1GB, then 896MB is decoded to LOWMEM and the rest is >> decoded in HIGHMEM. >> >>> >>> 2) As documents at many places why is the limit of 896MB for ZONE_NORMAL? >>> >> Since this 896 MB of physical address space is directly mapped to >> the Kernel linear virtual address space i.e from (0xC0000000 to 0xF8000000). >> Also, there is a Fixed constant offset relation between VA to PA i.e. VA = >> PA + 0xC000000. This has been done to avoid any page table walk for >> translating kernel virtual address to physical address. >> Thus when kernel virtual address is generated for execution, PA is >> calculated by MMU directly, thus making kernel code execution faster. >> > > Does this mean MMU doesnt look into TLB or pagetable when the kernel > virtual address is referenced? how does the MMU know the range of direct > mapping ( i.e offset-ed mapping)? > Ideally yes, MMU should hold the range information. I do not know about Intel architecture but I have learnt that in PowerPC architecture there is a BAT register which will hold the offset information. Any comments ? > >> All the above explaination strictly holds good for Intel architecture on >> Desktop machines. >> >> Regards, >> Prabhunath >> >>> >>> >>> Regards, >>> Piyush >>> >>> _______________________________________________ >>> Kernelnewbies mailing list >>> Kernelnewbies at kernelnewbies.org >>> http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies >>> >>> >> >> _______________________________________________ >> Kernelnewbies mailing list >> Kernelnewbies at kernelnewbies.org >> http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies >> >> > > > -- > Regards, > Paraneetharan C > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.kernelnewbies.org/pipermail/kernelnewbies/attachments/20110627/c0d79ab8/attachment.html