memory barrier in UP

memory barrier in UP

[subin gangadharan]

Hi All,

I am reading about the barrier from linux kernel development.In this
books, he says
"On SMP kernels they are defined only as usual memory barriers.where
as on UP kernels they are
defined only as a compiler barrier"

Does this mean in UP, processor won't reorder the instructions ?

Could please give any idea on this.

-- 
With Regards
Subin Gangadharan

I am not afraid and I am also not afraid of being afraid.

memory barrier in UP

[Mulyadi Santosa]

Hi...

On Mon, Dec 12, 2011 at 01:11, subin gangadharan
<subingangadharan@gmail.com> wrote:
> Hi All,
>
> I am reading about the barrier from linux kernel development.In this
> books, he says
> "On SMP kernels they are defined only as usual memory barriers.where
> as on UP kernels they are
> defined only as a compiler barrier"
>
> Does this mean in UP, processor won't reorder the instructions ?

In some arch like Alpha, loosely reordering even in UP could happen at
any time. But in x86 UP, IIRC there's only strict re-ordering, meaning
that every read is always fetching latest write etc.

-- 
regards,

Mulyadi Santosa
Freelance Linux trainer and consultant

blog: the-hydra.blogspot.com
training: mulyaditraining.blogspot.com

memory barrier in UP

[subin gangadharan]

Hi Mulyadi,

Thanks for the answer.

On Mon, Dec 12, 2011 at 11:16 AM, Mulyadi Santosa
<mulyadi.santosa@gmail.com> wrote:
> Hi...
>
> On Mon, Dec 12, 2011 at 01:11, subin gangadharan
> <subingangadharan@gmail.com> wrote:
>> Hi All,
>>
>> I am reading about the barrier from linux kernel development.In this
>> books, he says
>> "On SMP kernels they are defined only as usual memory barriers.where
>> as on UP kernels they are
>> defined only as a compiler barrier"
>>
>> Does this mean in UP, processor won't reorder the instructions ?
>
> In some arch like Alpha, loosely reordering even in UP could happen at
> any time. But in x86 UP, IIRC there's only strict re-ordering, meaning
> that every read is always fetching latest write etc.

In that case (ALPHA), is compiler barrier sufficient enough to prevent
the re ordering done by the processor.
What I was thinking,compiler barrier is to instruct the compiler to
not do any re ordering.

Please correct me if I am wrong.

> --
> regards,
>
> Mulyadi Santosa
> Freelance Linux trainer and consultant
>
> blog: the-hydra.blogspot.com
> training: mulyaditraining.blogspot.com



-- 
With Regards
Subin Gangadharan

I am not afraid and I am also not afraid of being afraid.

memory barrier in UP

[Mulyadi Santosa]

Hi Subin....

On Tue, Dec 13, 2011 at 01:57, subin gangadharan
<subingangadharan@gmail.com> wrote:
> Hi Mulyadi,
>
> Thanks for the answer.

You welcome...I just shared what I know :)

> In that case (ALPHA), is compiler barrier sufficient enough to prevent
> the re ordering done by the processor.
> What I was thinking,compiler barrier is to instruct the compiler to
> not do any re ordering.

Again this is architecture problem. I am not sure about Alpha, since I
only know about one compiler barrier that is "volatile". What I guess
is that in Alpha, it could be something else....maybe it is assembly
instruction like "lock" or something.

I remember there's an old Linuxjournal article that explains about it.
So to avoid further misunderstandings that I might bring, please
kindly read this article:
http://www.linuxjournal.com/article/8212

Hope that helps...

-- 
regards,

Mulyadi Santosa
Freelance Linux trainer and consultant

blog: the-hydra.blogspot.com
training: mulyaditraining.blogspot.com