From: chris@basementcode.com (Christopher Harvey)
To: kernelnewbies@lists.kernelnewbies.org
Subject: IRQs and memory consistency
Date: Wed, 11 Apr 2012 06:59:28 -0500 [thread overview]
Message-ID: <a47a749b9165d01a18b7a4aeb8f28f7c@basementcode.com> (raw)
In-Reply-To: <CAKk8iso9+aV5s8shc3Pde9PQRe78bgC-80J2cc4OoaD=T2ai+w@mail.gmail.com>
On 10.04.2012 19:58, Wink Saville wrote:
> Sounds to me like there needs to be a flush of the processor cache
> by using memory barriers.
I used a wmb(); right after I set the value I wanted.
> I'm guessing that the IRQ is taken on a different thread and possibly
> a different processor and the value needs to be flushed. You might
> try having devid be an atomic_t and then use atomic_set
> and atomic_read so that the "proper" memory barriers are used.
should I use atomic ops instead of a wmb?
The interrupt can't happen until the value is assigned completely in
one thread. I'm sure.
next prev parent reply other threads:[~2012-04-11 11:59 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-04-10 20:22 IRQs and memory consistency Christopher Harvey
2012-04-11 0:58 ` Wink Saville
2012-04-11 11:59 ` Christopher Harvey [this message]
2012-04-11 15:35 ` Wink Saville
2012-04-11 20:14 ` Christopher Harvey
2012-04-11 3:18 ` Mulyadi Santosa
2012-04-11 11:53 ` Christopher Harvey
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