From mboxrd@z Thu Jan 1 00:00:00 1970 From: chris@basementcode.com (Christopher Harvey) Date: Wed, 11 Apr 2012 06:59:28 -0500 Subject: IRQs and memory consistency In-Reply-To: References: <18680507ce5fe185f8355a813376bd26@basementcode.com> Message-ID: To: kernelnewbies@lists.kernelnewbies.org List-Id: kernelnewbies.lists.kernelnewbies.org On 10.04.2012 19:58, Wink Saville wrote: > Sounds to me like there needs to be a flush of the processor cache > by using memory barriers. I used a wmb(); right after I set the value I wanted. > I'm guessing that the IRQ is taken on a different thread and possibly > a different processor and the value needs to be flushed. You might > try having devid be an atomic_t and then use atomic_set > and atomic_read so that the "proper" memory barriers are used. should I use atomic ops instead of a wmb? The interrupt can't happen until the value is assigned completely in one thread. I'm sure.