From mboxrd@z Thu Jan 1 00:00:00 1970 Return-path: Date: Fri, 21 Aug 2015 01:18:16 +0200 From: Peter Zijlstra Subject: Re: [V3 PATCH 2/4] panic/x86: Allow cpus to save registers even if they are looping in NMI context Message-ID: <20150820231816.GH3161@worktop.event.rightround.com> References: <20150806054543.25766.29590.stgit@softrs> <20150806054543.25766.5526.stgit@softrs> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20150806054543.25766.5526.stgit@softrs> List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "kexec" Errors-To: kexec-bounces+dwmw2=infradead.org@lists.infradead.org To: Hidehiro Kawai Cc: x86@kernel.org, Jonathan Corbet , linux-doc@vger.kernel.org, kexec@lists.infradead.org, linux-kernel@vger.kernel.org, Michal Hocko , Ingo Molnar , Thomas Gleixner , "Eric W. Biederman" , "H. Peter Anvin" , Masami Hiramatsu , Andrew Morton , Ingo Molnar , Vivek Goyal On Thu, Aug 06, 2015 at 02:45:43PM +0900, Hidehiro Kawai wrote: > When cpu-A panics on NMI just after cpu-B has panicked, cpu-A loops > infinitely in NMI context. Especially for x86, cpu-B issues NMI IPI > to other cpus to save their register states and do some cleanups if > kdump is enabled, but cpu-A can't handle the NMI and fails to save > register states. > > To solve thie issue, we wait for the timing of the NMI IPI, then > call the NMI handler which saves register states. Sorry, I don't follow, what? _______________________________________________ kexec mailing list kexec@lists.infradead.org http://lists.infradead.org/mailman/listinfo/kexec