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Fri, 15 May 2026 14:15:23 -0700 (PDT) Received: from mimas.lan ([2603:8000:df01:38f7:a6bb:6dff:fecf:e71a]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-134cbcb9ef5sm10736508c88.2.2026.05.15.14.15.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 May 2026 14:15:23 -0700 (PDT) From: Ross Philipson To: linux-kernel@vger.kernel.org, x86@kernel.org, linux-integrity@vger.kernel.org, linux-doc@vger.kernel.org, linux-crypto@vger.kernel.org, kexec@lists.infradead.org, linux-efi@vger.kernel.org, iommu@lists.linux.dev Cc: ross.philipson@gmail.com, dpsmith@apertussolutions.com, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, dave.hansen@linux.intel.com, ardb@kernel.org, mjg59@srcf.ucam.org, James.Bottomley@hansenpartnership.com, peterhuewe@gmx.de, jarkko@kernel.org, jgg@ziepe.ca, luto@amacapital.net, nivedita@alum.mit.edu, herbert@gondor.apana.org.au, davem@davemloft.net, corbet@lwn.net, ebiederm@xmission.com, dwmw2@infradead.org, baolu.lu@linux.intel.com, kanth.ghatraju@oracle.com, daniel.kiper@oracle.com, andrew.cooper3@citrix.com, trenchboot-devel@googlegroups.com Subject: [PATCH v16 25/38] x86/boot: Slight refactor of the 5 level paging logic Date: Fri, 15 May 2026 14:13:57 -0700 Message-ID: <20260515211410.31440-26-ross.philipson@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260515211410.31440-1-ross.philipson@gmail.com> References: <20260515211410.31440-1-ross.philipson@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260515_141524_534368_62A786CE X-CRM114-Status: GOOD ( 13.22 ) X-BeenThere: kexec@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "kexec" Errors-To: kexec-bounces+kexec=archiver.kernel.org@lists.infradead.org From: Ard Biesheuvel In preparation for adding Secure Launch support, which will require that the number of paging levels remains untouched, tweak the logic slightly so that the slaunch check can be inserted easily. No functional change intended. Signed-off-by: Ard Biesheuvel Signed-off-by: Ross Philipson --- arch/x86/boot/compressed/pgtable_64.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/x86/boot/compressed/pgtable_64.c b/arch/x86/boot/compressed/pgtable_64.c index 0e89e197e112..3e9d651da73e 100644 --- a/arch/x86/boot/compressed/pgtable_64.c +++ b/arch/x86/boot/compressed/pgtable_64.c @@ -102,6 +102,7 @@ static unsigned long find_trampoline_placement(void) asmlinkage void configure_5level_paging(struct boot_params *bp, void *pgtable) { + bool l5_enabled = native_read_cr4() & X86_CR4_LA57; void (*toggle_la57)(void *cr3); bool l5_required = false; @@ -118,10 +119,12 @@ asmlinkage void configure_5level_paging(struct boot_params *bp, void *pgtable) * + CPUID leaf 7 is supported * + the leaf has the feature bit set */ - if (!cmdline_find_option_bool("no5lvl") && - native_cpuid_eax(0) >= 7 && (native_cpuid_ecx(7) & BIT(16))) { - l5_required = true; + if (native_cpuid_eax(0) < 7 || !(native_cpuid_ecx(7) & BIT(16))) + return; + + l5_required = !cmdline_find_option_bool("no5lvl"); + if (l5_required) { /* Initialize variables for 5-level paging */ __pgtable_l5_enabled = 1; pgdir_shift = 48; @@ -132,7 +135,7 @@ asmlinkage void configure_5level_paging(struct boot_params *bp, void *pgtable) * The trampoline will not be used if the paging mode is already set to * the desired one. */ - if (l5_required == !!(native_read_cr4() & X86_CR4_LA57)) + if (l5_required == l5_enabled) return; trampoline_32bit = (unsigned long *)find_trampoline_placement(); -- 2.47.3