Re: QNS: ARM64: Cache coherency while doing Kexec for KHO

[Jason Gunthorpe <jgg@nvidia.com>]

On Tue, Aug 11, 2026 at 07:19:11PM +0000, tarunsahu@google.com wrote:
> 
> Hi,
> 
> I have a question regarding cache maintenance for Kernel Handover (KHO)
> preserved memory across kexec reboots on arm64.
> 
> During kexec, all other CPUs gets hot-unplugged where they flush all
> of their caches so there will be no issues with any KHO data preserved
> having caches on these CPUs.
> 
> But CPU0 still has not been flushed its D-cache (Is this correct?) and
> it will only do flushing for specific area by kexec_segment_flush().
> 
> So for KHO preserved memory, if its caches still marked dirty on CPU0
> they will not be flushed?
> 
> Is my understanding correct? or AM I missing something?
> Also if this true, This will be a problem?
> 
> PS: Pardon my less knowledge on ARM64 cache coherency.

Yes, I think what you outline is correct, but I don't think it is a
problem.

As long as the CPU cache implementation is physically tagged and
everything kexec runs during boot with paging and caching disabled is
flushed it should be fine.

Once the new kernel comes up and installs a page table with cachable
attributes everything will still be consistent from the CPU's
perspective.

Anything in the new kernel that needs forced coherence, like DMA, will
be doing flushes anyhow.

Jason