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[2a03:2880:31ff::face:b00c]) by smtp.gmail.com with ESMTPSA id jt12-20020a170906ca0c00b007aec44edcfcsm6148933ejb.75.2022.11.22.07.55.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Nov 2022 07:55:38 -0800 (PST) Date: Tue, 22 Nov 2022 07:55:36 -0800 From: Breno Leitao To: Pawan Gupta Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, leit@meta.com, cascardo@canonical.com, hpa@zytor.com, jpoimboe@kernel.org, peterz@infradead.org, x86@kernel.org, kexec@lists.infradead.org Subject: Re: [PATCH] x86/bugs: Explicitly clear speculative MSR bits Message-ID: References: <20221118194602.vpo4xjm4s7knm7ja@desk> <20221120120255.13054-1-leitao@debian.org> <20221121222031.uo2n7fv7ojusxvr4@desk> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221121222031.uo2n7fv7ojusxvr4@desk> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221122_075543_971252_2455EA60 X-CRM114-Status: GOOD ( 15.33 ) X-BeenThere: kexec@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "kexec" Errors-To: kexec-bounces+kexec=archiver.kernel.org@lists.infradead.org On Mon, Nov 21, 2022 at 02:20:31PM -0800, Pawan Gupta wrote: > On Sun, Nov 20, 2022 at 12:02:55PM +0000, Breno Leitao wrote: ... > > diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c > > index 3e3230cccaa7..970b277d02a6 100644 > > --- a/arch/x86/kernel/cpu/bugs.c > > +++ b/arch/x86/kernel/cpu/bugs.c > > @@ -137,8 +137,16 @@ void __init check_bugs(void) > > * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD > > * init code as it is not enumerated and depends on the family. > > */ > > - if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) > > + if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) { > > rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); > > + /* > > + * Previously running software may have some controls turned ON. > > + * Clear them and let kernel decide which controls to use. > > + */ > > + x86_spec_ctrl_base &= ~SPEC_CTRL_MASK; > > + wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); > > + } > > + > > Nit, extra newline. Thanks. If no other comment about the diff come until tomorrow, I will send a v2 without this extra line. _______________________________________________ kexec mailing list kexec@lists.infradead.org http://lists.infradead.org/mailman/listinfo/kexec