Re: [PATCH v5 0/4] arm64: cross-CPU NMI via SDEI

[YinFengwei <fengwei_yin@linux.alibaba.com>]

Hi Kirill,

On Mon, Jun 29, 2026 at 04:07:14PM +0100, Kiryl Shutsemau wrote:
> From: "Kiryl Shutsemau (Meta)" <kas@kernel.org>
> 
> A class of debug/observability features needs to interrupt a CPU that has
> its interrupts locally masked: the all-CPU backtrace behind sysrq-l /
> RCU-stall / hung-task / hard-lockup dumps, and crash_smp_send_stop()
> capturing a stuck CPU's state into the vmcore. On arm64 these need a
> mechanism that reaches a CPU spinning with DAIF masked, which a normal IPI
> cannot.
> 
V> arm64 has two such mechanisms today:
> 
>   - GICv3 pseudo-NMI (interrupt priority masking). The cost lands on the
>     interrupt mask/unmask hot path: local_irq_enable() becomes an
>     ICC_PMR_EL1 write, and exception entry/exit save and restore the PMR,
>     paid on every CPU whether or not an NMI is ever delivered.
> 
>     Measured on Grace (Neoverse V2; ICC_CTLR_EL1.PMHE=0, so the PMR-sync
>     DSB is already patched to a NOP), pseudo_nmi=0 vs pseudo_nmi=1:
> 
>         gettid() loop:              178 -> 253 ns/call  (+42%, ~74 ns)
>         will-it-scale sched_yield:  0.705x throughput, flat from 1 to 72 cores
>         will-it-scale page_fault1:  within ~5%
> 
>     The ~74 ns is a fixed per-syscall entry/exit tax -- it reproduces at
>     +73.5 ns on Neoverse N2 -- so the hit tracks syscall/exception density
>     and is unacceptable on syscall-bound fleet workloads, which therefore
>     run with pseudo-NMI disabled.
> 
This patchset works perfectly on our Neoverse N2 ARM64 platform. So
 Tested-by: Yin Fengwei <fengwei_yin@linux.alibaba.com>

Regards
Yin, Fengwei