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([27.60.19.161]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-314bc548e29sm918244eec.15.2026.07.24.09.47.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jul 2026 09:47:24 -0700 (PDT) From: Atharva Tiwari To: Cc: Atharva Tiwari , Andre Eikmeyer , Bjorn Helgaas , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andreas Noever , Mika Westerberg , Yehezkel Bernat , Hans de Goede , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Jarkko Sakkinen , Mimi Zohar , Roberto Sassu , Dmitry Kasatkin , Eric Snowberg , Paul Moore , James Morris , "Serge E. Hallyn" , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-integrity@vger.kernel.org, keyrings@vger.kernel.org, linux-security-module@vger.kernel.org Subject: [PATCH v4 2/2] thunderbolt: Add device links for Apple T2 NHI Date: Fri, 24 Jul 2026 12:46:37 -0400 Message-ID: <20260724164641.2239-3-atharvatiwarilinuxdev@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260724164641.2239-1-atharvatiwarilinuxdev@gmail.com> References: <20260724164641.2239-1-atharvatiwarilinuxdev@gmail.com> Precedence: bulk X-Mailing-List: keyrings@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Andre Eikmeyer Icelake Thunderbolt NHI on T2 Macs (2018-2020). The NHI and its associated PCIe root ports all sit directly on the root complex with no upstream port. Apple's ACPI tables name Thunderbolt root ports as TRP0, TRP1, etc. Find them and create device links back to the NHI so that PCIe tunnels can be re-established after sleep. And on other Thunderbolt NHI's, like Titan Ridge, the default method is used to add device links. Co-developed-by: Atharva Tiwari Signed-off-by: Atharva Tiwari Signed-off-by: Andre Eikmeyer --- drivers/thunderbolt/tb.c | 58 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 56 insertions(+), 2 deletions(-) diff --git a/drivers/thunderbolt/tb.c b/drivers/thunderbolt/tb.c index c69c323e6952..625451ff3ea0 100644 --- a/drivers/thunderbolt/tb.c +++ b/drivers/thunderbolt/tb.c @@ -6,9 +6,11 @@ * Copyright (C) 2019, Intel Corporation */ +#include #include #include #include +#include #include #include @@ -3305,21 +3307,73 @@ static const struct tb_cm_ops tb_cm_ops = { static bool tb_apple_add_links(struct tb_nhi *nhi) { struct pci_dev *upstream, *pdev; - bool ret; + bool ret = false; if (!x86_apple_machine) return false; + /* On T2 Macs with Icelake thunderbolt NHI's. + * the root ports are stored in ACPI as TRP0, + * TRP1, etc. Find them and create device links + * so that PCIe tunnels can be re-established after + * sleep. + */ +#if IS_ENABLED(CONFIG_ACPI) + if (has_apple_t2_chip && (nhi->pdev->device == PCI_DEVICE_ID_INTEL_ICL_NHI0 || + nhi->pdev->device == PCI_DEVICE_ID_INTEL_ICL_NHI1)) { + struct acpi_device *adev; + unsigned int slot, func; + const struct device_link *link; + const char *bid; + + for (slot = 0; slot < 32; slot++) { + for (func = 0; func < 8; func++) { + struct pci_dev *current_pdev __free(pci_dev_put) = + pci_get_slot(nhi->pdev->bus, PCI_DEVFN(slot, func)); + if (!current_pdev) + continue; + + if (!pci_is_pcie(current_pdev) || pci_pcie_type(current_pdev) != + PCI_EXP_TYPE_ROOT_PORT) + continue; + + adev = ACPI_COMPANION(¤t_pdev->dev); + if (!adev) + continue; + + bid = acpi_device_bid(adev); + if (strncmp(bid, "TRP", 3) != 0) + continue; + + link = device_link_add(¤t_pdev->dev, &nhi->pdev->dev, + DL_FLAG_AUTOREMOVE_SUPPLIER | + DL_FLAG_PM_RUNTIME); + if (link) { + dev_dbg(&nhi->pdev->dev, "created link from %s\n", + dev_name(¤t_pdev->dev)); + ret = true; + } else { + dev_warn(&nhi->pdev->dev, + "device link creation from %s failed\n", + dev_name(¤t_pdev->dev)); + } + } + } + return ret; + } +#endif + switch (nhi->pdev->device) { case PCI_DEVICE_ID_INTEL_LIGHT_RIDGE: case PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C: case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI: case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI: + case PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_NHI: + case PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_NHI: break; default: return false; } - upstream = pci_upstream_bridge(nhi->pdev); while (upstream) { if (!pci_is_pcie(upstream)) -- 2.43.0