From: Hollis Blanchard <hollisb@us.ibm.com>
To: kvm-ppc@vger.kernel.org
Subject: Re: [kvm-ppc-devel] [PATCH] [3/4] Add userpace tlb access
Date: Wed, 30 Jan 2008 21:29:22 +0000 [thread overview]
Message-ID: <1201728563.10632.20.camel@basalt> (raw)
In-Reply-To: <12016963202210-git-send-email-ehrhardt@linux.vnet.ibm.com>
On Wed, 2008-01-30 at 13:31 +0100, ehrhardt@linux.vnet.ibm.com wrote:
> This version of the userspace tlb access has some changes out of discussions
> with Zhang Wei responsible for the e500 work and Hollis for ppc440. It now
> transports only a single tlb entry per get/set and uses an index specifier
> that every architecture can interpret as needed e.g. e500 could map tlb0/tlb1
> in the high bits and the array index in them in the low bits while ppc440 only
> needs a linear index. The right vcpu is already selected since this is a vcpu
> ioctl.
> Internally the selction of the right tlb layout in kernel e.g. for set/get_tlb
> or in userspace for kvm_dump_tlb is now based on the pvr that selects the
> defines the guest type.
>
> Subject: [PATCH] [3/4] Add userpace tlb access
> From: Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
>
> This adds userspace tlb access transporting a single tlb entry to/from
> userspace. It has an index variable passed with the call to specify the tlb
> entry to get/set. For the guest tlb get&set is supported while the shadow
> tlb can only be read from userspace.
Didn't we agree not to export the shadow TLB?
...
> diff --git a/include/asm-powerpc/kvm.h b/include/asm-powerpc/kvm.h
> --- a/include/asm-powerpc/kvm.h
> +++ b/include/asm-powerpc/kvm.h
> @@ -21,6 +21,7 @@
> #define __POWERPC_KVM_H__
>
> #include <asm/types.h>
> +#include <asm/mmu-44x.h>
>
> struct kvm_regs {
> __u32 pc;
> @@ -53,6 +54,22 @@ struct kvm_fpu {
> struct kvm_fpu {
> };
>
> +struct tlbe {
> + __u32 tid; /* Only the low 8 bits are used. */
> + __u32 word0;
> + __u32 word1;
> + __u32 word2;
> +};
This definitely must be renamed.
> +struct kvm_tlbe {
> + __u32 index;
> + union {
> + struct tlbe tlbe_ppc440;
> + /* Fix the size of the union (hopefully) */
> + char padding[32];
> + };
> +};
Are you sure 32 bytes will be large enough? I think Freescale uses a ton
of MAS registers for TLB insertion.
--
Hollis Blanchard
IBM Linux Technology Center
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next prev parent reply other threads:[~2008-01-30 21:29 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-01-30 12:31 [kvm-ppc-devel] [PATCH] [3/4] Add userpace tlb access ehrhardt
2008-01-30 21:29 ` Hollis Blanchard [this message]
2008-01-31 8:32 ` Christian Ehrhardt
2008-01-31 14:56 ` ehrhardt
2008-01-31 15:00 ` Christian Ehrhardt
2008-01-31 22:52 ` Hollis Blanchard
2008-02-01 3:16 ` Zhang Wei
2008-02-01 13:32 ` Zhang Wei
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